Systems and methods for extending pulsing of a top LF RF generator

Abstract

A system for pulsing a top low frequency (LF) radio frequency (RF) generator is described. The system includes a main LF RF generator that generates a first RF signal and is coupled to a lower electrode of a plasma chamber. The top LF RF generator generates a second RF signal and is coupled to a top electrode of the plasma chamber. The system includes a waveform controller coupled to the main LF RF generator and the top LF RF generator. The waveform controller receives a pulse repetition rate and a first duty cycle of the first RF signal, controls the top LF RF generator to apply the pulse repetition rate to the second RF signal, and controls the top LF RF generator to have a second duty cycle that is greater than the first duty cycle.

Description

SYSTEMS AND METHODS FOR EXTENDING PULSING OF A TOP LF RF GENERATORFIELD

[0001] The embodiments described in the present disclosure relate to systems and methods for extending pulsing of a top low frequency (LF) radio frequency (RF) generator.BACKGROUND

[0002] The background description provided herein is for the purposes of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.

[0003] With each successive semiconductor technology generation, wafer diameters tend to increase and transistor sizes decrease, resulting in the need for an ever higher degree of accuracy and repeatability in wafer processes. Semiconductor substrate materials, such as silicon wafers, are processed by techniques, which include the use of plasma chambers. These techniques include plasma applications, such as deposition and plasma etch.

[0004] Plasma processing systems available today are among those semiconductor fabrication tools, which are subject to an increasing need for increased accuracy and repeatability. An important success metric for plasma processing systems is increased uniformity, which includes uniformity of process results on a semiconductor substrate surface. Continuous increase of on-wafer uniformity is desirable.

[0005] It is in this context that embodiments described in the present disclosure arise.SUMMARY

[0006] Embodiments of the disclosure provide systems and methods for extending pulsing of a top low frequency (LF) radio frequency (RF) generator. It should be appreciated that the present embodiments can be implemented in numerous ways, e.g., a process, an apparatus, a system, a piece of hardware, or a method on a computer-readable medium. Several embodiments are described below.

[0007] In an embodiment, a system for pulsing a top LF RF generator is described. The system includes a main LF RF generator that generates a first RF signal and is coupled to a lower electrode of a plasma chamber. The top LF RF generator generates a second RF signal and is coupled to a top electrode of the plasma chamber. The system includes a waveform controller coupled to the main LF RF generator and the top LF RF generator. The waveform controller receives a pulse repetition rate and a first duty cycle of the first RF signal, controls the top LFRF generator to apply the pulse repetition rate to the second RF signal, and controls the top LF RF generator to have a second duty cycle that is greater than the first duty cycle. The top LF RF generator is controlled to have the second duty cycle to reduce an irregularity in a feature of a substrate.

[0008] In an embodiment, a system for pulsing a top LF RF generator is described. The system includes a main LF RF generator that generates a first LF RF signal and is coupled to a lower electrode of a plasma chamber. The top LF RF generator generates a second RF signal and is coupled to a top electrode of the plasma chamber. The top LF RF generator includes a waveform controller coupled to the main LF RF generator. The waveform controller receives a pulse repetition rate and a first duty cycle of the first RF signal from the main LF RF generator, controls a power supply of the top LF RF generator to apply the pulse repetition rate to the second RF signal, and controls the power supply of the top LF RF generator to achieve a second duty cycle of the second RF signal. The second duty cycle is greater than the first duty cycle and the power supply of the top LF RF generator is controlled to have the second duty cycle to reduce an irregularity in a feature of a substrate.

[0009] In an embodiment, a waveform controller for pulsing a top LF RF generator is described. The waveform controller includes a processor and a memory device coupled to the processor. The processor receives a pulse repetition rate and a first duty cycle of a first RF signal generated by a main LF RF generator, controls the top LF RF generator to apply the pulse repetition rate to a second RF signal generated by the top LF RF generator, and controls the top LF RF generator to have a second duty cycle that is greater than the first duty cycle. The top LF RF generator is controlled to have the second duty cycle to reduce an irregularity in a feature of a substrate.

[0010] Some advantages of the herein described systems and methods for extending pulsing of the top LF RF generator include reducing chances of formation of irregularities in features of a substrate. The irregularities are created by positive ions of plasma deposited on side walls of features formed within the substrate. A duty cycle of a state of a top RF signal generated by the top LF RF generator is extended compared to a duty cycle of a state of a main RF signal. RF power of the top RF signal is supplied to a top electrode and RF power of the main RF signal is supplied to a lower electrode of a substrate support. By extending the duty cycle, electrons are able to penetrate a bottom plasma sheath to neutralize the positive ions. When the positive ions are neutralized, chances of formation of the irregularities are reduced. Additional advantages include increasing a number of states of the top RF signal compared to a number of states of the main RF signal to reduce chances of formation of the irregularities.

[0011] Some other aspects will become apparent from the following detailed description, taken in conjunction with the accompanying drawings.BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The embodiments are understood by reference to the following description taken in conjunction with the accompanying drawings.

[0013] Figure 1A is a diagram of an embodiment of a system to illustrate use of a waveform controller.

[0014] Figure IB is a diagram of an embodiment of the waveform controller.

[0015] Figure 2A is an embodiment of a graph to illustrate an increase in a duty cycle of a state of a top low frequency (LF) radio frequency (RF) signal compared to a duty cycle of the same state of a main RF signal.

[0016] Figure 2B is an embodiment of a graph to illustrate an increase in a number of states of the top RF signal compared to a number of states of the main RF signal.

[0017] Figure 3A is an embodiment of a graph to illustrate an overlap of a voltage level of a top RF signal with a voltage level of a main RF signal.

[0018] Figure 3B is a zoom-in view of a portion of the graph of Figure 3A.

[0019] Figure 3C is a zoom-in view of a portion of the graph of Figure 3A.

[0020] Figure 3D is a zoom-in view of a portion of the graph of Figure 3A.

[0021] Figure 3E is a zoom-in view of a portion of the graph of Figure 3A.

[0022] Figure 4 is an embodiment of a graph to illustrate that a voltage level of a top RF signal reaches across a quasi steady-state after an overshoot state.

[0023] Figure 5A is a cross section view of a feature formed within a substrate that is placed on an electrostatic chuck (ESC) to illustrate that a positive charge is accumulated asymmetrically near a bottom of the feature.

[0024] Figure 5B illustrates a top down view of a feature having an irregularity or a deformity during a high aspect ratio etch due to asymmetric positive charge accumulation illustrated in Figure 5A.

[0025] Figure 5C illustrates a top down view of a feature formed within a substrate after reduction of the positive charge that is accumulated.

[0026] Figure 6 is a block diagram of an embodiment of a main LF RF generator to illustrate details of the main LF RF generator.

[0027] Figure 7 is a block diagram of an embodiment of a top LF RF generator to illustrate details of the top LF RF generator.DETAILED DESCRIPTION

[0028] The following embodiments describe systems and methods for extending pulsing of a top low frequency (LF) radio frequency (RF) generator (RFG). It will be apparent that the present embodiments may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present embodiments.

[0029] Figure 1 A is a diagram of an embodiment of a system 100 to illustrate use of a waveform controller 102. Figure IB is a diagram of an embodiment of the waveform controller 102. The system 100 includes a host computer 104, a main LF RF generator 106, a main match 108, a plasma chamber 110, a top LF RF generator 112, a high frequency (HF) RF generator 114, and a top match 116. Examples of the host computer 104 include a controller, a desktop computer, a laptop computer, a smart phone, and a tablet.

[0030] The host computer 104 includes a processor 118 and a memory device 120. Examples of a processor, as used herein, include a central processing unit (CPU), an application specific integrated circuit (ASIC), a microcontroller, a microprocessor, and a programmable logic device (PLD). Examples of a memory device, as used herein, include a read-only memory or a random access memory or a combination thereof. To illustrate, the memory device is a flash memory.

[0031] Referring to Figure 1A, an example of an LF RFG generator, such as the main LF RFG 106 or the top LF RFG 1 12, include a radiofrequency generator that operates at a low frequency from and including one hundred kilohertz (kHz) to 2 megahertz (MHz). An example of the HF RFG 114 includes a radiofrequency generator that operates at a high frequency of 60 MHz. To illustrate, the HF RFG 114 operates at a frequency ranging from and including 57 MHz to 63 MHz.

[0032] The plasma chamber 110 includes a substrate support 122, an upper electrode 124, and an upper electrode extension 126. The upper electrode 124 is sometimes referred to herein as a top electrode. The plasma chamber 110 further includes an insulator ring 128. An example of the substrate support 122 includes an electrostatic chuck (ESC). To illustrate, the electrostatic chuck includes a bottom electrode, which is sometimes referred to herein as a lower electrode. As an example, each of the upper electrode 124, the upper electrode extension 126, and the bottom electrode is fabricated from a metal, such as aluminum or an alloy of aluminum. Further, as an example, the insulator ring 128 is fabricated from a dielectric material and, such as quartz.

[0033] The upper electrode 124 is located above the substrate support 122 to form a gap 154 therebetween. Also, the upper electrode extension 126 surrounds the insulator ring 128, which surrounds the upper electrode 124.

[0034] Referring to Figure IB, the waveform controller 102 includes a processor 101 and a memory device 103. Examples of a controller, such as the waveform controller 102, as used herein, include a combination of a processor and a memory device, and the processor and the memory device are coupled to each other. To illustrate, the processor 101 of the waveform controller 102 is coupled to the memory device 103 of the waveform controller 102.

[0035] Referring back to Figure 1A, the processor 118 is coupled to the memory device 120. Also, the processor 118 is coupled via a transfer cable 130 to the HF RFG 114 and is coupled via a transfer cable 105 to the top LF RFG 112. Examples of a transfer cable, as used herein, include a cable that enables a parallel transfer of data, or a cable that enables a serial transfer of data, or a cable that enables a transfer of data via a universal serial bus (USB) protocol. Also, the processor 118 is coupled via a transfer cable 132 to the main LF RFG 106.

[0036] The main LF RFG 106 is coupled via an RF cable 134 to an input 136 of the main match 108. An output 138 of the main match 108 is coupled via an RF transmission line 140 to the bottom electrode. Also, the main LF RFG 106 is coupled via a transfer cable 142 to the waveform controller 102 and the waveform controller 102 is coupled via a transfer cable 144 to the top LF RFG 112.

[0037] The top LF RFG 1 12 is coupled via an RF cable 146 to an input 148 of the top match 116 and an output 150 of the top match is coupled via an RF transmission line 152 to the upper electrode 124. The upper electrode extension 126 is grounded, such as is coupled to a ground potential. The HF RFG 114 is coupled via an RF cable 154 to an input 156 of the top match 116.

[0038] A processor, such as a digital signal processor (DSP), of the top LF RFG 112 stores, coupled to a memory device of the top LF RFG 112, controls a phase difference between a phase of a top RF signal 166, such as a top LF RF signal, to be generated by the top LF RFG 112 and a phase of a main RF signal 164, such as a main LF RF signal, generated by the main LF RF generator 106. For example, the processor of the top LF RFG 112 receives a recipe signal indicating the phase difference from the processor 118 via the transfer cable 105. In the example, the transfer cable 105 couples the processor of the top LF RFG 112 with the processor 118.

[0039] The processor 118 generates and sends a main recipe signal 162 via the transfer cable 132 to the main LF RFG 106. As an example, the main recipe signal 162 includes frequency and voltage information for generating the main RF signal 164. To illustrate, the frequency and voltage information for generating the main RF signal 164 includes the lowfrequency of the main RF signal 164, state information, such as two or more voltage levels, of the main RF signal 164, a pulse repetition rate at the two or more voltage levels repeat, and a duty cycle of occurrence of a respective one of the voltage levels. As an example, the pulse repetition rate indicates a time period, such as a time interval, of each occurrence of the two or more voltage levels that repeat periodically.

[0040] Each voltage level represents a state of an RF signal generated by an RF generator and a number of voltage levels of the RF signal during each time period of the pulse repetition rate represents a number of states of the RF signal. For example, a first main voltage level of the main RF signal 164 represents a first state of the main RF signal 164 and a second main voltage level of the main RF signal 164 represents a second state of the main RF signal 164. In the example, the two main voltage levels represent the two states of the main RF signal 164 and the first state of the main RF signal 164 occurs immediately before, such as precedes, the second state of the of the main RF signal 164. Further in the example, a first top voltage level of the top RF signal 166 represents a first state of the top RF signal 166 and a second top voltage level of the top RF signal 166 represents a second state of the top RF signal 166. In the example, the two top voltage levels represent the two states of the top RF signal 166 and the first state of the top RF signal 166 occurs immediately before, such as precedes, the second state of the of the top RF signal 166. Upon receiving the frequency and voltage information within the main recipe signal 162, a processor, such as DSP, of the main LF RFG 106 stores the frequency and voltage information within a memory device of the main LF RFG 106. As an example, the terms state and pulsing state are used herein interchangeably.

[0041] As an example, a duty cycle of occurrence of a voltage level from multiple voltage levels of an RF signal during each time period of the pulse repetition rate is an amount of time period of occurrence of the voltage level as a percentage of a total amount of time period of occurrence of the voltage levels. To illustrate, the top RF signal 166 has three voltage levels including a first voltage level, a second voltage level, and a third voltage level, during a time period of the pulse repetition rate. The first voltage level occurs for 5 microseconds, the second voltage level occurs for 3 microseconds, and the third voltage level occurs for 2 microseconds. In the illustration, a duty cycle of the first voltage level is 50 percent, which is 5 microseconds as a percentage of 10 microseconds. Ten microseconds is an example of the total amount of time period of occurrence of the three voltage levels. Further, in the illustration, a duty cycle of occurrence of the second voltage level is 30 percent and a duty cycle of occurrence of the third voltage level is 20 percent. Further, in the illustration, the three voltage levels repeat with each time period of the pulse repetition rate. In the illustration, the duty cycles of 50%, 30%, and 20% are included within the frequency and voltage information.

[0042] The waveform controller 102 accesses, such as receives or reads, the frequency and voltage information from the memory device of the main LF RFG 106 and generates a waveform control signal 168, such as a synchronization signal or a transistor-transistor logic (TTL) signal, based on the frequency and voltage information. For example, the processor 101 of the waveform controller 102 modifies, such as increases, a duty cycle of a voltage level indicated within the frequency and voltage information to output a modified duty cycle. To illustrate, the processor 101 extends a time period of a voltage level of a state, of the main RF signal 164, indicated within the frequency and voltage information to calculate an extended time period. The processor 101 controls the top LF RF generator 112 to output a voltage level for the extended time period instead of for the time period received within the frequency and voltage information. The voltage level output for the extended time period is of the top RF signal 166. The extended time period is greater than the time period received within the frequency and voltage information. To further illustrate, when the time period received within the frequency and voltage information is 3 microseconds, the extended time period is 5 microseconds. Also, in the illustration, there is some overlap between the time period and the extended time period. Continuing with the example, the modified duty cycle is indicated within the waveform control signal 168.

[0043] As another example, the processor 101 of the waveform controller 102 holds constant a duty cycle of a voltage level indicated within the frequency and voltage information to output an unmodified duty cycle of a voltage level of the top RF signal 166. To illustrate, there is no extension of a time period of the voltage level indicated within the frequency and voltage information to output the unmodified duty cycle. In the example, the unmodified duty cycle is indicated within the waveform control signal 168. Moreover, as another example, the processor 101 of the waveform controller 102 modifies, such as increases or decreases, a number of states indicated within the frequency and voltage information to output a modified number of states of the top RF signal 166 during each time period of the pulse repetition rate. In the example, the modified number of states is indicated within the waveform control signal 168.

[0044] Also, as another example, the processor 101 of the waveform controller 102 modifies, such as increases and decreases, a voltage level that represents a state of the main RF signal 164 and that is indicated within the frequency and voltage information to output a modified voltage level of the top RF signal 166. The voltage level that is modified is within each occurrence of the two or more voltage levels at the pulse repetition rate of the main RF signal 164. Also, the modified voltage level occurs during each time period of the pulse repetition rate of the two or more voltage levels of the top RF signal 166. The modified voltage level represents the same state, such as a first state or a second state, as that represented by the voltage level ofthe main RF signal 164. To illustrate, the processor 101 modifies a first main voltage level of a first state of the main RF signal 164 to output a first top voltage level of a first state of the top RF signal 166 or modifies a second main voltage level of a second state of the main RF signal 164 to output a second top voltage level of a second state of the top RF signal 166. In the illustration, the second state of any RF signal occurs after the first state of the RF signal during each time period of the pulse repetition rate.

[0045] As another example, the processor 101 of the waveform controller 102 does not modify, such as holds constant, a voltage level that represents a state of the main RF signal 164 and that is indicated within the frequency and voltage information to output an unmodified voltage level of the top RF signal 166. The voltage level that is unmodified occurs during each time period of the pulse repetition rate of the two or more voltage levels of the main RF signal 164. Also, the unmodified voltage level occurs during each time period of the pulse repetition rate of the two or more voltage levels of the top RF signal 166. The unmodified voltage level represents the same state, such as a first state or a second state, as that represented by the voltage level of the main RF signal 164. As an illustration, the second state of any RF signal occurs after the first state of the RF signal during each time period of the pulse repetition rate.

[0046] As another example, the processor 101 of the waveform controller 102 holds constant the number of states, of the main RF signal 166, indicated within the frequency and voltage information to output an unmodified number of states of the top RF signal 166. In the example, the unmodified number of states is indicated within the waveform control signal 168.

[0047] As yet another example, the processor 101 of the waveform controller 102 modifies, such as adds a delay to or subtracts a time interval from, a time of start of generation of the main RF signal 164 to output a modified time of start of generation of the top RF signal 166. To illustrate, the time of start is a time at which a trigger signal is received from the processor 118 by the RF generators 106 and 112. As another illustration, the time of start is received by the RF generators 106 and 112 from the processor 118 and the trigger signal is not generated or is ignored by the RF generators 106 and 112. Continuing with the example, the modified time of start is indicated within the waveform control signal 168. It should be noted that when the time interval is subtracted from the time of start, the modified time of start is earlier compared to the time of start.

[0048] As yet another example, the processor 101 of the waveform controller 102 holds constant the time of start of generation of the main RF signal 164 to output an unmodified time of start of generation of the top RF signal 166. In the example, the unmodified time of start is indicated within the waveform control signal 168. As another example, the processor 101 of the waveform controller 102 indicates, within the waveform control signal 168, that the pulserepetition rate of two or more voltage levels of the top RF signal 166 is equal to the pulse repetition rate indicated within the frequency and voltage information.

[0049] As another example, the processor 101 of the waveform controller 102 includes, within the waveform control signal 168, the low frequency received within the frequency and voltage information. The low frequency is of the main RF signal 164.

[0050] The waveform controller 102 sends the waveform control signal 168 via the transfer cable 144 to the processor of the top LF RFG 1 12. Upon receiving the waveform control signal 168, the processor of the top LF RFG 112 stores, within the memory device of the top LF RFG 112, information indicated by the waveform control signal 168. Examples of the information indicated by the waveform control signal 168 includes the modified duty cycle or the unmodified duty cycle of the top RF signal 166, the modified number of states or the unmodified number of states of the top RF signal 166, the modified voltage level or the unmodified voltage level of the top RF signal 166, the modified time of start or the unmodified time of start of the top RF signal 166, the pulse repetition rate of the top RF signal 166, and the frequency of the top RF signal 166. The frequency of the top RF signal 166 is the same as, such as is equal to, the frequency of the main RF signal 164.

[0051] The processor 118 sends the trigger signal via the transfer cable 132 to the main LF RFG 106, via the transfer cable 130 to the HF RFG 114, and via the transfer cable 105 to the top LF RFG 112. Upon receiving the trigger signal, the HF RFG 114 generates an HF RF signal 160 and sends the HF RF signal 160 via the RF cable 154 to the input 156. Also, in response to receiving the trigger signal, the main LF RFG 106 generates the main RF signal 164 based on the frequency and voltage information received within the recipe signal 162. For example, the processor of the main LF RFG 106 controls a power supply of the main LF RFG 106 to generate the main RF signal 164 having the pulse repetition rate indicated within the frequency and voltage information, the two or more voltage levels indicated within the frequency and voltage information, and the low frequency, of the main RF signal 164, indicated within the frequency and voltage information.

[0052] Moreover, the top LF RFG 112 generates the top RF signal 166 based on the information indicated within the waveform control signal 168 and based on the phase difference to be achieved between the RF signals 166 and 164. For example, after the waveform control signal 168 indicating the modified time of start is received and in response to receiving the trigger signal, the processor of the top LF RFG 112 accesses, such as reads, the information received within the waveform control signal 168 from the memory device of the top LF RFG 112 and generates the top RF signal 166 according to the information. To illustrate, the processor of the top LF RFG 112 controls a power supply of the top LF RF generator 112 togenerate the top RF signal 166. In the illustration, the top RF signal 166 is generated to have the modified duty cycle during each time period of the pulse repetition rate compared to the duty cycle of the main RF signal 164 during the time period of the pulse repetition rate. To further illustrate, the modified duty cycle is of a voltage level of a first state from among multiple states of the top RF signal 166 and modified duty cycle is greater than the duty cycle of a voltage level of the first state from among multiple states of the main RF signal 164. The first state occurs before remaining of the multiple states of the top RF signal 166 and before remaining of the multiple states of the main RF signal 164.

[0053] As another illustration, the processor of the top LF RFG 112 controls the power supply of the top LF RF generator 112 to generate the top RF signal 166. In the illustration, the top RF signal 166 is generated to have the unmodified duty cycle during each time period of the pulse repetition rate compared to the duty cycle of the main RF signal 164 during the time period of the pulse repetition rate. To further illustrate, the unmodified duty cycle is of a voltage level of a first state from among multiple states of the top RF signal 166 and the unmodified duty cycle is equal to the duty cycle is of a voltage level of the first state from among multiple states of the main RF signal 164. The first state occurs before remaining of the multiple states of the top RF signal 166 and before remaining of the multiple states of the main RF signal 164.

[0054] As another illustration, the processor of the top LF RFG 112 controls the power supply of the top LF RF generator 112 to generate the top RF signal 166 having the modified number of states compared to the number of states of the main RF signal 164. To further illustrate, the modified number of states is greater than the number of states of the main RF signal 164. As another further illustration, the top RF signal 166 has three states during each time period of the pulse repetition rate and the main RF signal 164 has two states during the time period of the pulse repetition rate. As yet another further illustration, the top RF signal 166 has four states during each time period of the pulse repetition rate and the main RF signal 164 has two or three states during the time period of the pulse repetition rate.

[0055] As yet another illustration, the processor of the top LF RFG 112 controls the power supply of the top LF RF generator 112 to generate the top RF signal 166 having the unmodified number of states compared to the number of states of the main RF signal 164. To further illustrate, the unmodified number of states is equal to the number of states of the main RF signal 164. As another further illustration, the top RF signal 166 has three states during each time period of the pulse repetition rate and the main RF signal 164 also has three states during the time period of the pulse repetition rate. As yet another further illustration, the top RF signal 166 has four states during each time period of the pulse repetition rate and the main RF signal 164 has four states during the time period of the pulse repetition rate.

[0056] As yet another illustration, the processor of the top LF RFG 112 controls the power supply of the top LF RF generator 112 to generate the top RF signal 166 having the modified voltage level representing a state compared to a voltage level of the main RF signal 164 representing the state during each time period of the pulse repetition rate. To further illustrate, the processor of the top LF RFG 112 increases a voltage level representing a second state of the main RF signal 164 to output the modified voltage level representing a second state of the top RF signal 166. The second state of the main RF signal 164 occurs after a first state of the main RF signal 164 and the second state of the top RF signal 166 occurs after a first state of the top RF signal 166 and before a third state of the top RF signal 166.

[0057] As still another illustration, the processor of the top LF RFG 112 controls the power supply of the top LF RF generator 112 to generate the top RF signal 166 having the unmodified voltage level representing a state compared to a voltage level of the main RF signal 164 representing the state during each time period of the pulse repetition rate. To further illustrate, the processor of the top LF RFG 112 holds constant a voltage level representing a second state of the main RF signal 164 to output the unmodified voltage level representing a second state of the top RF signal 166. The second state of the main RF signal 164 occurs after a first state of the main RF signal 164 and the second state of the top RF signal 166 occurs after a first state of the top RF signal 166 and before a third state of the top RF signal 166.

[0058] As another illustration, the processor of the top LF RFG 112 controls the power supply of the top LF RF generator 1 12 to generate the top RF signal 166 having the modified time of start compared to the time of start of the main RF signal 164. To further illustrate, the processor of the top LF RFG 112 controls the power supply of the top LF RF generator 112 to delay or start early compared to the time of start at which the main RF signal 164 is generated by the main LF RFG 106.

[0059] As yet another illustration, the processor of the top LF RFG 112 controls the power supply of the top LF RF generator 112 to generate the top RF signal 166 at the same time of start as that of the main RF signal 164. To further illustrate, the processor of the top LF RFG 112 controls the power supply of the top LF RF generator 112 to generate the start top RF signal 166 at the same time of start at which the main RF signal 164 is generated by the main LF RFG 106.

[0060] As an example, the processor of the top LF RFG 112 controls the power supply of the top LF RFG 112 to achieve the phase difference between the top RF signal 166 and the main RF signal 164. To illustrate, the processor of the top LF RFG 112 receives from the processor 118 via the transfer cable 105, a phase identification signal identifying a first voltage amplitude, such as a peak voltage, at which the main RF signal 164 is to be generated uponreceiving the trigger signal. The first voltage amplitude is to occur during an RF cycle of the main RF signal 164. The processor of the top LF RFG 112 determines a second voltage amplitude at which the top RF signal 166 is to be generated after receiving the trigger signal to achieve the phase difference with respect to the first voltage amplitude of the main RF signal 164. The second voltage amplitude is to occur during an RF cycle of the top RF signal 166. The RF cycle of the top RF signal 166 is the same as the RF cycle of the main RF signal 164. After receiving the trigger signal, the processor of the top LF RFG 1 12 controls the power supply of the top LF RFG 112 to generate the second voltage amplitude of the top RF signal 166 to achieve the phase difference during an RF cycle of the top RF signal 166. As an example, each RF cycle of an RF signal is a cycle of oscillation, such as a sinusoidal oscillation, of the RF signal. To illustrate, each RF cycle of an RF signal is an occurrence of one sinusoidal waveform of the RF signal.

[0061] In one embodiment, the processor 118 is not coupled to the top LF RFG 112 via a transfer cable.

[0062] In one embodiment, the waveform controller 102 is located within the top LF RFG 112. For example, the processor of the top LF RFG 112 is the processor 101 of the waveform controller 102 and the memory device of the top LF RFG 112 is the memory device 103 of the waveform controller 102.

[0063] Figure 2A is an embodiment of a graph 200 to illustrate an increase in a duty cycle of a state, such as a q* state, of the top RF signal 166 (Figure 1 A) compared to a duty cycle of the same state, such as the q,hstate, of the main RF signal 164 (Figure 1A), where q is an integer. The graph 200 plots voltage on a y-axis and time t on an x-axis. For example, the graph 200 plots voltage levels, such as voltage amplitudes, including V0, VI, V2, V3, V4, V5, V6, V7, V8, V9, V10, Vll, V12, and V13 in an increasing order. To illustrate, the voltage level VI is greater than the voltage level V0, the voltage level V2 is greater than the voltage level VI, and so on until the voltage level V13 is greater than the voltage level V12. Also, in the example, the graph 200 includes times tO, t5, t7, t8, tlO, tl5, tl8, t20, and t25 on an x-axis. To illustrate, the time t5 occurs after the time tO, the time t8 occurs after the time t5 and so on until the time t25 occurs after the time t20. Examples of a voltage amplitude of an RF signal include a peak-to- peak amplitude and a zero-to-peak amplitude of the RF signal.

[0064] The graph 200 includes a plot 202 of voltage levels of a main RF signal 206, and includes a plot 204 of voltage levels of a top RF signal 208. The main RF signal 206 is an example of the main RF signal 164 and the top RF signal 208 is an example of the top RF signal 166. During a first pulse cycle, such as a pulse cycle 1, the main RF signal 206 has the voltage level VI 3 from the time t5 to the time t8 and transitions from the voltage level VI 3 to thevoltage level V5 at the time t8. As an example, a pulse cycle is a clock cycle of a clock signal. In the example, the clock signal is generated by the processor 118 (Figure 1A) and sent from the processor 118 to the main and top LF RF generators 106 and 112 and to the HF RF generator 114 to synchronize operation of the RF generators 106, 112, and 114.

[0065] Further, during the first pulse cycle, the main RF signal 206 has the voltage level V5 from the time t8 to the time tl5. During a second pulse cycle, such as a pulse cycle 2, the main RF signal 206 repeats the voltage levels VI 3 and V5 that occur during the first pulse cycle in the same manner as that during the first pulse cycle. For example, at the time 115 , the main RF signal 206 transitions from the voltage level V5 to the voltage level VI 3, has the voltage level V13 from the time tl5 to the time tl8, transitions from the voltage level V13 to the voltage level V5 at the time tl8, and has the voltage level V5 from the time tl 8 to the time t25. The second pulse cycle occurs consecutive to the first pulse cycle. In this manner, the voltage levels VI 3 and V5 of the main RF signal 206 repeat during additional pulse cycles.

[0066] The voltage level VI 3 is a portion of a state Sim of the main RF signal 164, and the voltage level V5 is a portion of a state SOm of the main RF signal 206 and the states Sim and SOm indicate an order of occurrence of the voltage levels VI 3 and V5. For example, the state Sim includes the voltage level V13 and the state SOm includes the voltage level V5, and the voltage level VI 3 occurs before the voltage level V5 during each pulse cycle.

[0067] The states Sim and SOm repeat with each pulse cycle. For example, an instance of the states Sim and SOm occur during the pulse cycle 1 and another instance of the states Sim and SOm occur during the pulse cycle 2.

[0068] Also, during the first pulse cycle, the top RF signal 208 has the voltage level V9 from the time t5 to the time tlO and transitions from the voltage level V9 to the voltage level V2 at the time tlO. Further, during the first pulse cycle, the top RF signal 208 has the voltage level V2 from the time tlO to the time tl5. During the second pulse cycle, the top RF signal 208 repeats the voltage levels V9 and V2 that occur during the first pulse cycle in the same manner as that during the first pulse cycle. For example, at the time tl5, the top RF signal 208 transitions from the voltage level V2 to the voltage level V9, has the voltage level V9 from the time tl 5 to the time t20, transitions from the voltage level V9 to the voltage level V2 at the time t20, and has the voltage level V2 from the time t20 to the time t25. In this manner, the voltage levels V9 and V2 of the top RF signal 208 repeat during the additional pulse cycles.

[0069] The voltage level V9 is a portion of a state Sit of the top RF signal 208, and the voltage level V2 is a portion of a state SOt of the top RF signal 208 and the states Sit and SOt indicate an order of occurrence of the voltage levels V9 and V2. For example, the state Sitincludes the voltage level V9 and the state SOt includes the voltage level V2, and the voltage level V9 occurs before the voltage level V2 during each pulse cycle.

[0070] The states Sit and SOt repeat with each pulse cycle. For example, an instance of the states Sit and SOt occur during the pulse cycle 1 and another instance of the states Sit and SOt occur during the pulse cycle 2.

[0071] It should be noted that during each pulse cycle, a duty cycle of the plot 204 is greater than a duty cycle of the plot 202. For example, during each pulse cycle, the duty cycle of the plot 204 is 50% and the duty cycle of the plot 202 is 35%. To illustrate, during each pulse cycle, the state Sit occurs for a greater time interval than the state Sim while overlapping with a time interval of occurrence of the state Sim. To further illustrate, a first time interval between the times t5 and tlO is greater than a second time interval between the times t5 and t8. In the illustration, the state Sit occurs during the first time interval and the state Sim occurs during the second time interval. There is an overlap time interval, between the times t5 and t8, during which both the states Sit and Sim occur. As another example, the duty cycle of the plot 204 is between 1% and 99% and the duty cycle of the plot 202 is less than the duty cycle of the plot 204. The duty cycle of the plot 204 is an example of the modified duty cycle of the top RF signal 208, and the duty cycle of the plot 202 is an example of the duty cycle of the main RF signal 206.

[0072] The duty cycle of the plot 204 is greater than the duty cycle of the plot 202 during each pulse cycle to create an overlap time interval. An example of the overlap time interval during the pulse cycle 1 is a time interval between the times t8 and tlO. During the overlap time interval, the voltage level V5 of the main RF signal 206 is low, such as lower compared to the voltage level V9 of the top RF signal 136, and a bottom sheath of the plasma is thin. Also, during the overlap time interval, the top RF signal 208 has a high voltage level, such as the voltage level V9 that is greater than the voltage level V5 of the main RF signal 206. When the top RF signal 208 has the high voltage level during the overlap time interval, electrons penetrate the bottom sheath to neutralize positive ions of the plasma. The neutralization reduces, such as removes, chances of irregularities, such as kinks, occurring in features of the substrate S (Figure 1A). The terms irregularities and deformities are used herein interchangeably.

[0073] It should further be noted that, as an example, the states Sit and Sim are the same states and the states SOt and SOm are the same states when the state Sit occurs before the state SOt and the state Sim occurs before the state SOm.

[0074] Figure 2B is an embodiment of a graph 250 to illustrate an increase in a number of states of the top RF signal 166 (Figure 1A) compared to a number of states of the main RF signal 164 (Figure 1A). The graph 250 plots voltage on a y-axis and time t on an x-axis. The x-axis of the graph 250 is the same as the x-axis of the graph 200 (Figure 2A) and the y-axis of the graph 250 is the same as the y-axis of the graph 200.

[0075] The graph 250 includes the plot 202 of voltage levels of the main RF signal 208 (Figure 2B), and includes a plot 254 of voltage levels of a top RF signal 252, which is an example of the top RF signal 166 (Figure 1A). During the first pulse cycle, the top RF signal 252 has the voltage level V9 from the time t5 to the time t8 and transitions from the voltage level V9 to the voltage level VI 1 at the time t8. Further, during the first pulse cycle, the top RF signal 252 has the voltage level VI 1 from the time t8 to the time tlO. During the first pulse cycle, the top RF signal 252 transitions from the voltage level Vl l to the voltage level V7 at the time tlO and remains at the voltage level V7 from the time tlO to the time tl5. During the second pulse cycle, the top RF signal 252 repeats the voltage levels V9, Vl l, and V7 that occur during the first pulse cycle in the same manner as that during the first pulse cycle. For example, at the time tl 5, the top RF signal 252 transitions from the voltage level V7 to the voltage level V9, has the voltage level V9 from the time tl5 to the time tl8, transitions from the voltage level V9 to the voltage level Vl l at the time tl8, has the voltage level Vl l from the time tl8 to the time t20, transitions from the voltage level Vl l to the voltage level V7 at the time t20, and remains at the voltage level V7 from the time t20 to the time t25. In this manner, the voltage levels V9, Vll, and V7 of the top RF signal 252 repeat during the additional pulse cycles.

[0076] The voltage level V9 is a portion of the state Sit of the top RF signal 252, the voltage level Vl l is a portion of a state S2t of the top RF signal 252, and the voltage level V7 is a portion of the state SOt of the top RF signal 252 and the states Sit, S2t, and SOt indicate an order of occurrence of the voltage levels V9, Vl l, and V7. For example, the state Sit includes the voltage level V9, the state S2t includes the voltage level Vl l, and the state SOt includes the voltage level V7. The voltage level V9 occurs before the voltage level Vl l during each pulse cycle, and the voltage level Vll occurs before the voltage level V7 during each pulse cycle.

[0077] The states Sit, S2t, and SOt repeat with each pulse cycle. For example, an instance of the states Sit, S2t, and SOt occur during the pulse cycle 1 and another instance of the states Sit, S2t, and SOt occur during the pulse cycle 2.

[0078] It should be noted that during each pulse cycle, a number of states of the plot 254 is greater than a number of states of the plot 202. For example, the plot 245 has the three states Sit, S2t, and SOt and the plot 202 has the two states Sim and SOm.

[0079] The number of states of the plot 254 is greater than the number of states of the plot 204 during each pulse cycle to create an overshoot state, such as the state S2t. During the overshoot state S25, the voltage level V5 of the main RF signal 208 is low, such as lower compared to the voltage level Vll of the overshoot state of the top RF signal 252, and thebottom sheath of the plasma is thin. Also, during the overshoot state, the top RF signal 252 has a high voltage level, such as the voltage level VI 1 that is greater than the voltage level V5 of the main RF signal 208. When the top RF signal 252 has the high voltage level during the overlap time interval, the electrons penetrate the bottom sheath to neutralize the positive ions of the plasma. The neutralization reduces, such as removes, chances of the deformities occurring in features of the substrate S (Figure 1A).

[0080] In an embodiment, instead of transitioning from a first main voltage level to a second main voltage level at a time, the main RF signal 164 transitions from the first main voltage level to the second main voltage level during a time period, such as a time interval. For example, instead of transitioning from the voltage level V13 to the voltage level V5 at the time t8, the main RF signal 206 transitions from the voltage level V13 to the voltage level V5 during a time period between the times t7 and t8.

[0081] In one embodiment, instead of transitioning from a first top voltage level to a second top voltage level at a time, the top RF signal 166 transitions from the first main voltage level to the second main voltage level during a time period, such as a time interval. For example, instead of transitioning from the voltage level V9 to the voltage level Vll at the time t8, the top RF signal 254 transitions from the voltage level V9 to the voltage level Vll during a time period between the times t7 and t8.

[0082] Figure 3A is an embodiment of a graph 300 to illustrate an overlap of a voltage level 302 of a top RF signal 304 with a voltage level 306 of a main RF signal 308. The top RF signal 304 is an example of the top RF signal 166 (Figure 1A) and the main RF signal 308 is an example of the main RF signal 164 (Figure 1A).

[0083] The graph 300 plots a voltage on a y-axis and the time t, measured in microseconds, on an x-axis. During each pulse cycle, the voltage of the main RF signal 308 transitions between voltage levels 310 and 306. The voltage levels 310 and 306 periodically repeat with each pulse cycle. The voltage level 310 represents a main high state of the main RF signal 308 and the voltage level 306 represents a main low state of the main RF signal 308. The voltage level 310 is greater than the voltage level 306.

[0084] Also, during each pulse cycle, the voltage of the top RF signal 304 transitions among three voltage levels including a voltage level 312, the voltage level 302, and a voltage level 314. The voltage levels 312, 302, and 314 periodically repeat with each pulse cycle. The voltage level 312 represents a top medium state of the top RF signal 304, the voltage level 302 represents a top high state of the top RF signal 304, and the voltage level 314 represents a top low state of the top RF signal 304. For example, the voltage level 312 is lower than the voltagelevel 302 and greater than the voltage level 314. Also, the voltage level 302 is less than the voltage level 310 and greater than the voltage level 306.

[0085] During a time period, such as a transition time period, in which the main RF signal 308 transitions from the main high state to the main low state, the top RF signal 304 transitions from the top medium state to the top high state. Also, during a time period in which the main RF signal 308 has the main low state, the top RF signal 304 has the top high state and transitions from the top high state to the top low state.

[0086] Figure 3B is a zoom-in view of a portion 320 of the graph 300. The portion 320 illustrates the voltage level 312 of the top RF signal 304 during the top medium state and the voltage level 310 of the main RF signal 308 during the main high state. The voltage level 310 is greater than the voltage level 312. During each pulse cycle, the main RF signal 308 has the voltage level 310 and the top RF signal 304 has the voltage level 312.

[0087] Also, as shown in the portion 320, there is a phase difference between the voltages of the main RF signal 308 and the top RF signal 304. For example, the top RF signal 304 is out of phase with the main RF signal 308. To illustrate, the phase difference between the voltages of the main RF signal 308 and the top RF signal 304 ranges from and including 120° to 180°. To further illustrate, during each RF cycle of the main RF signal 308 and the RF cycle of the top RF signal 304, an occurrence of the voltage level 312 lags an occurrence of the voltage level 310 by 120°.

[0088] Figure 3C a zoom-in view of a portion 330 of the graph 300 (Figure 3A). The portion 330 illustrates a transition, during each pulse cycle, of the main RF signal 308 and a transition, during the pulse cycle, of the top RF signal 304. For example, within each pulse cycle, during a time period in which the main RF signal 308 transitions from the voltage level 310 to the voltage level 306, the top RF signal 304 transitions from the voltage level 312 to the voltage level 302. Also, as illustrated in the portion 330, the phase difference between the voltages of the main RF signal 308 and the top RF signal 304 continues to exist.

[0089] Figure 3D is a zoom-in view of a portion 340 of the graph 300 (Figure 3A). The portion 340 depicts the voltage level 306 of the top RF signal 304 and the voltage level 302 of the main RF signal 308. As illustrated in the portion 340, the phase difference between the voltages of the main RF signal 308 and the top RF signal 304 continues to exist.

[0090] Figure 3E is a zoom-in view of a portion 350 of the graph 300 (Figure 3A). The portion 350 depicts the voltage level 314 of the top RF signal 304 and the voltage level 306 of the main RF signal 308. As illustrated in the portion 350, the phase difference between the voltages of the main RF signal 308 and the top RF signal 304 continues to exist.

[0091] Figure 4 is an embodiment of a graph 400 to illustrate that a voltage level VI 1 of a top RF signal 404 reaches a quasi steady-state S3t after an overshoot state S2t. The top RF signal 404 is an example of the top RF signal 166 (Figure 1A). The graph 400 plots voltages of the top RF signal 404 and the main RF signal 208 on a y-axis and the time t on an x-axis. The x- axis of the graph 400 is the same as the x-axis of the graph 200 (Figure 2A) and the y-axis of the graph 400 is the same as the y-axis of the graph 200.

[0092] The graph 400 includes the plot 402 of voltage levels of the top RF signal 404, and includes the plot 202 of voltage levels of the main RF signal 208. During the pulse cycle 1, the top RF signal 404 has the voltage level V9 from the time t5 to the time t8 and transitions from the voltage level V9 to the voltage level V 12 at the time t8. Further, during the pulse cycle 1, the top RF signal 404 has the voltage level V12 from the time t8 to the time tlO and transitions from the voltage level V12 to the voltage level Vll at the time tlO. Also, during the pulse cycle 1, the top RF signal 404 has the voltage level Vl l from the time tlO to the time tl2 and transitions from the voltage level Vll to the voltage level V7 at the time tl2. During the pulse cycle 1, the top RF signal 404 has the voltage level V7 from the time tl2 to the time tl5 and transitions from the voltage level V7 to the voltage level V9 at the time tl5. Between the times tl5 and t25 of the pulse cycle 2, the top RF signal 404 repeat the voltage levels V9, V12, Vl l, and V7 in the same manner in which the V9, V12, Vl l, and V7 occur during the pulse cycle 1. In this manner, the V9, V12, Vl l, and V7 are repeated during additional pulse cycles following the pulse cycle 2. The voltage level V9 forms a state Si t of the top RF signal 404, the voltage level V12 forms the state S2t of the top RF signal 404, the voltage level Vl l forms the state S31 of the top RF signal 404, and the voltage level V7 forms another state S4t of the top RF signal 404.

[0093] Figure 5A is a cross section view of an embodiment of a feature 500, such as a slit channel, formed within a substrate 502 that is placed on an ESC 504. The feature 500 is formed during a high aspect ratio etch of the substrate 502. The electrostatic chuck 504 is an example of the substrate support 122 (Figure 1A) on which the substrate 502 is placed for processing. When the method, described herein, of generating the top RF signal 166 (Figure 1A) is not applied to the substrate 502, positive ions, such as positive charges, accumulate asymmetrically on side walls of the feature 500.

[0094] Figure 5B illustrates a top down view of an embodiment of a feature 510 formed within a substrate 512 during a high aspect ratio etch. The substrate 512 is an example of the substrate 502 (Figure 5 A). Because of the accumulation of the positive ions, an irregularity 514, such as a kink, is introduced within the feature 510.

[0095] Figure 5C illustrates a top down view of an embodiment of a feature 520 formed within a substrate 522. The substrate 522 is an example of the substrate S (Figure 1A). When the substrate 522 is processed by applying the method in which the top RF signal 166 (Figure 1A) is generated, chances of occurrence of the irregularity 514 are reduced, such as eliminated, during a high aspect ratio etch of the substrate 522. When the top RF signal 166 has a high voltage level during an overlap time interval, electrons penetrate the bottom sheath to neutralize the positive ions on the sidewalls of feature 500 (Figure 5A). When the positive ions are neutralized, chances of occurrence of the irregularity 514 are reduced.

[0096] Figure 6 is a block diagram of an embodiment of a main LF RF generator 600 to illustrate details of the main LF RF generator 600. The main LF RF generator 600 is an example of the main LF RF generator 106 (Figure 1A). The main LF RF generator 600 includes a digital signal processor (DSP) 602. The main LF RF generator 600 further includes multiple voltage controllers VSOm and so on until a voltage controller VSpm, where p is an integer greater than zero. Also, the main LF RF generator 600 includes a frequency controller Fm, a driver and amplifier 604, and a main power supply 606.

[0097] As an example, a driver and amplifier, as used herein, includes a driver and an amplifier, and the driver is coupled to the amplifier. An example of a driver includes one or more transistors. An example of a power supply, as used herein, includes an electronic oscillator. To illustrate, the power supply is an RF oscillator that produces sine waves at a radio frequency.

[0098] The DSP 602 is coupled to the voltage controllers VSOm and VSpm, and to the frequency controller Fm. The DSP 602 is also coupled to the transfer cable 132. The voltage controllers VSOm and VSpm and the frequency controller Fm are coupled to the driver of the driver and amplifier 604. The amplifier of the driver and amplifier 604 is coupled to the main power supply 606. The main power supply 606 is coupled to the RF cable 134.

[0099] Upon receiving the main recipe signal 162 via the transfer cable 132, the DSP 602 identifies a voltage level for the state SOm and so on until a voltage level for the state Spm is identified from the frequency and voltage information within the main recipe signal 162. Also, the DSP 602 identifies the low frequency of the main RF signal 164 from the frequency and voltage information received within the main recipe signal 162. Upon identifying the voltage levels for the states SOm through Spm, the DSP 602 sends the voltage level for the state SOm to the voltage controller VSOm and so on until the voltage level for the state Spm is sent to the voltage controller VSpm. Also, in response to identifying the frequency of the main RF signal 164, the DSP 602 sends the frequency to the frequency controller Fm.

[0100] When the voltage level for the state SOm is received from the DSP 602, a processor of the voltage controller VSOm stores the voltage level for the state SOm within amemory device of the voltage controller VSOm. Similarly, in response to receiving the voltage level for the state Spm from the DSP 602, a processor of the voltage controller VSpm stores the voltage level for the state Spm within a memory device of the voltage controller VSpm. Also, upon receiving the frequency of the main RF signal 164 from the DSP 602, a processor of the frequency controller Fm stores the frequency within a memory device of the frequency controller Fm.

[0101] In response to receiving the trigger signal from the processor 1 18 (Figure 1 A) via the transfer cable 132, the DSP 602 controls the main power supply 606 via one or more of the voltage controllers VSOm through VSpm, the frequency controller Fm, and the driver and amplifier 604 to generate the main RF signal 164. For example, in response to receiving the trigger signal, the DSP 602 sends a voltage control signal for the state Spm to the voltage controller VSpm. Upon receiving the voltage control signal for the state Spm, the processor of the voltage controller VSpm generates a drive signal for the state Spm and sends the drive signal to the driver of the driver and amplifier 604. Also, upon receiving the voltage control signal for the state Spm, the processor of the voltage controller VSpm accesses the voltage level for the state Spm from the memory device of the voltage controller VSpm to control the amplifier of the driver and amplifier 604 based on the voltage level for the state Spm. In response to receiving the drive signal for the state Spm, the driver of the driver and amplifier 604 generates a current signal for the state Spm. Also, the voltage controller VSpm controls the amplifier of the driver and amplifier 604 to amplify the current signal to output an amplified current signal for the state Spm to achieve the voltage level of the state Spm. The amplified current signal for achieving the voltage level of the state Spm is sent from the amplifier to the main power supply 606.

[0102] Continuing with the example, upon receiving the trigger signal, the DSP 602 sends a frequency control signal to the frequency controller Fm. In response receiving the frequency control signal, the processor of the frequency controller Fm accesses the frequency of the main RF signal 164 from the memory device of the frequency controller Fm and controls the driver of the driver and amplifier 604 to output the current signal at the frequency. When the current signal is output of the frequency, the amplified current signal from the amplifier of the driver and amplifier 604 is provided at the frequency to the main power supply 606.

[0103] In response to receiving the amplified current signal for achieving the voltage level of the state Spm and having the frequency of the main RF signal 164, the main power supply 606 generates the main RF signal 164 having the voltage level of the state Spm and the frequency. The power supply 606 sends the main RF signal 164 via the RF cable 134 to the main match 108 (Figure 1A).

[0104] Further, in the example, the DSP 602 determines whether a time period indicated by the duty cycle of occurrence of the voltage level of the state Spm is complete. For example, the DSP 602 uses a clock signal to determine whether a predetermined amount of time of the duty cycle of the state Spm has passed since the receipt of the trigger signal. In response to determining that the predetermined amount of time has passed, the DSP 602 determines the time period indicated by the duty cycle of occurrence of the voltage level of the state Spm is complete.

[0105] Continuing with the example, upon determining that the time period indicated by the duty cycle of occurrence of the voltage level of the state Spm is complete, the DSP 602 sends a voltage control signal for the state SOm to the voltage controller VSOm. Upon receiving the voltage control signal for the state SOm, the processor of the voltage controller VSOm generates a drive signal for the state SOm and sends the drive signal to the driver of the driver and amplifier 604. Also, upon receiving the voltage control signal for the state SOm, the processor of the voltage controller VSOm access the voltage level for the state SOm from the memory device of the voltage controller VSOm to control the amplifier of the driver and amplifier 604 based on the voltage level for the state SOm. In response to receiving the drive signal for the state Sim, the driver of the driver and amplifier 604 generates a current signal for the state SOm. Also, the voltage controller VSOm controls the amplifier of the driver and amplifier 604 to amplify the current signal to output an amplified current signal for the state SOm to achieve the voltage level of the state SOm. The amplified current signal for achieving the voltage level of the state SOm is sent from the amplifier to the main power supply 606. In response receiving the amplified current signal for achieving the voltage level of the state SOm and having the frequency of the main RF signal 164, the main power supply 606 modifies the main RF signal 164 to have the voltage level of the state SOm and the frequency.

[0106] Further, in the example, the DSP 602 determines whether a time period indicated by the duty cycle of occurrence of the voltage level of the state SOm is complete. For example, the DSP 602 uses the clock signal to determine whether a predetermined amount of time of the duty cycle of the state SOm has passed since the voltage control signal for the state SOm is sent to the voltage controller VSOm. In response to determining that the predetermined amount of time has passed, the DSP 602 determines the time period indicated by the duty cycle of occurrence of the voltage level of the state SOm is complete.

[0107] In the example, the DSP 602 determines whether a time period indicated by the pulse repetition rate of occurrence of the voltage levels of the states Spm through SOm is complete. For example, the DSP 602 uses the clock signal to determine whether a predetermined amount of time of occurrence of the voltage levels of the states Spm through SOm has passedsince the voltage control signal for the state Spm is sent to the voltage controller VSpm. In response to determining that the predetermined amount of time has passed, the DSP 602 determines the time period indicated by the pulse repetition rate of occurrence of the voltage levels of the states Spm through SOm is complete and the pulse cycle 1 of occurrence of the voltage level of the states Spm through SOm is complete.

[0108] In the example, upon determining that the time period indicated by the pulse repetition rate of occurrence of the voltage levels of the states Spm through SOm is complete, the DSP 602 sends the voltage control signals during the pulse cycle 2 to control the voltage controllers VSpm through VSOm in the same manner in which the voltage control signals are sent to the voltage controllers VSpm through VSOm to complete the pulse cycle 1. In this manner, the DSP 602 controls the main power supply 606 to generate additional pulse cycles, following the pulse cycle 2, of the main RF signal 164.

[0109] In one embodiment, instead of a DSP, an ASIC, a microcontroller, a microprocessor, or a PLD is used.

[0110] Figure 7 is a block diagram of an embodiment of a top LF RF generator 700 to illustrate details of the top LF RF generator 700. The top LF RF generator 700 is an example of the top LF RF generator 112 (Figure 1 A). The top LF RF generator 700 includes a DSP 702. The top LF RF generator 700 further includes multiple voltage controllers VSOt, VS It, VS2t and so on until a voltage controller VSnt, where n is an integer greater than zero. Also, the top LF RF generator 700 includes a frequency controller Ft, a driver and amplifier 704, and a top power supply 706.

[0111] The DSP 702 is coupled to the voltage controllers VSOt, VSlt, VS2t and VSnt, and to the frequency controller Ft. The DSP 702 is also coupled to the transfer cables 105 and 144. The voltage controllers VSOt, VSlt, VS2t and VSnt and the frequency controller Ft are coupled to the driver of the driver and amplifier 704. The amplifier of the driver and amplifier 704 is coupled to the top power supply 706. The top power supply 706 is coupled to the RF cable 146.

[0112] Upon receiving the waveform control signal 168 via the transfer cable 144, the DSP 702 identifies a number of states of the top RF signal 166 to be generated from the information indicated by the waveform control signal 168. For example, the DSP 702 identifies the number of states of the top RF signal 166 to be the modified number of states or the unmodified number of states.

[0113] Moreover, upon identifying the number of states of the top RF signal 166 to be the states SOt, Sit, S2t and so on until the state Snt, the DSP 702 identifies a voltage level for the state SOt, a voltage level for the state Sit, a voltage level for the state S2t, and so on until avoltage level for the state Snt is identified from the information indicated by the waveform control signal 168. For example, the DSP 702 identifies the voltage level for the state SOt to be the modified voltage level compared to the voltage level of the state SOm or the unmodified voltage level compared to the voltage level of the state SOm. As another example, the DSP 702 identifies the voltage level for the state Snt to be the modified voltage level compared to the voltage level of the state Spm or the unmodified voltage level compared to the voltage level of the state Spm.

[0114] Also, upon identifying the voltage levels for the states SOt through Snt, the DSP 702 identifies a duty cycle, such as the modified duty cycle or the unmodified duty cycle, for each of the voltage levels for the states SOt through Snt from the information indicated by the waveform control signal 168. For example, the DSP 702 identifies that the duty cycle of the voltage level of the state SOt is modified or unmodified compared to the duty cycle of the voltage level of the state SOm. The DSP 702 also identifies that the duty cycle of the voltage level of the state Snt is modified or unmodified compared to the duty cycle of the voltage level of the state Spm.

[0115] The DSP 702 identifies a time of start of generation of the top RF signal 166 from the information indicated by the waveform control signal 168. For example, the DSP 702 identifies that the time of start of generation of the top RF signal 166 is the modified time of start or the unmodified time of start. Also, the DSP 702 identifies a frequency of the top RF signal 166 and the pulse repetition rate of the voltage levels of the top RF signal 166 from the information indicated by the waveform control signal 168.

[0116] Upon identifying the voltage levels for the states SOt through Snt, the DSP 702 sends the voltage level for the state SOt to the voltage controller VSOt, sends the voltage level for the state Sit to the voltage controller VS It, sends the voltage level for the state S2t to the voltage controller VS2t, and so on until the voltage level for the state Snt is sent to the voltage controller VSnt. Also, in response to identifying the frequency of the top RF signal 166, the DSP 602 sends the frequency to the frequency controller Ft.

[0117] When the voltage level for the state SOt is received from the DSP 702, a processor of the voltage controller VSOt stores the voltage level for the state SOt within a memory device of the voltage controller VSOt. Similarly, in response to receiving the voltage level for the state Sit from the DSP 702, a processor of the voltage controller VSlt stores the voltage level for the state Sit within a memory device of the voltage controller VSlt, in response to receiving the voltage level for the state S2t from the DSP 702, a processor of the voltage controller VS2t stores the voltage level for the state S2t within a memory device of the voltage controller VS2t, and in response to receiving the voltage level for the state Snt from the DSP702, a processor of the voltage controller VSnt stores the voltage level for the state Snt within a memory device of the voltage controller VSnt. Also, upon receiving the frequency of the top RF signal 166 from the DSP 602, a processor of the frequency controller Ft stores the frequency within a memory device of the frequency controller Ft.

[0118] Before or in response to receiving the trigger signal from the processor 118 (Figure 1A) via the transfer cable 105, the DSP 702 controls the top power supply 706 via one or more of the voltage controllers VSOt through Vsnt, the frequency controller Ft, and the driver and amplifier 704 to generate the top RF signal 166 based on the phase difference to be achieved between the RF signals 166 and 164 and the time of start of generation of the top RF signal 166. For example, upon receiving the trigger signal, the DSP 702 sends a voltage control signal for the state Sit to the voltage controller VSlt. To illustrate, the DSP 702 sends the voltage control signal for the state Sit to the voltage controller VSlt at the modified time of start or at the unmodified time of start compared to a time at which the trigger signal is received. Further, in the illustration, the DSP 702 indicates, within the voltage control signal for the state Sit, a starting voltage amplitude, such as the second voltage amplitude, within an RF cycle, such as a sinusoidal cycle, of the top RF signal 166 to achieve the phase difference. In the illustration, the RF cycle is a period of time that has a start time and an end time. At the end time, the top RF signal 166 has the same voltage amplitude as that during the start time after the sinusoidal cycle of the RF signal 166. As another illustration, the DSP 702 sends the voltage control signal for the state Sit to the voltage controller VS11 at the modified time of start or at the unmodified time of start.

[0119] Upon receiving the voltage control signal for the state Sit, the processor of the voltage controller VSlt generates a drive signal for the state Sit and sends the drive signal to the driver of the driver and amplifier 704. Also, upon receiving the voltage control signal for the state Sit, the processor of the voltage controller VSlt accesses the voltage level for the state Sit from the memory device of the voltage controller VSlt to control the amplifier of the driver and amplifier 704 based on the voltage level for the state Sit and the starting voltage amplitude indicated within the voltage control signal. In response to receiving the drive signal for the state Sit, the driver of the driver and amplifier 704 generates a current signal for the state Sit. Also, the voltage controller VSlt controls the amplifier of the driver and amplifier 704 to amplify the current signal to output an amplified current signal for the state Sit to achieve the voltage level of the state Sit and the starting voltage amplitude. The amplified current signal for achieving the voltage level of the state Sit and the starting voltage amplitude is sent from the amplifier to the top power supply 706.

[0120] Continuing with the example, before or in response to receiving the trigger signal, the DSP 702 sends a frequency control signal to the frequency controller Ft. In response receiving the frequency control signal, the processor of the frequency controller Ft accesses the frequency of the top RF signal 166 from the memory device of the frequency controller Ft and controls the driver of the driver and amplifier 704 to output the current signal at the frequency. When the current signal is output of the frequency, the amplified current signal from the amplifier of the driver and amplifier 704 is provided at the frequency to the power supply 706.

[0121] In response receiving the amplified current signal for achieving the voltage level of the state Sit and having the frequency of the top RF signal 166, the top power supply 706 generates the top RF signal 166 having the voltage level of the state Sit and the starting voltage amplitude and the frequency. The power supply 706 sends the top RF signal 166 via the RF cable 146 to the input 148 of the top match 116 (Figure 1A).

[0122] Further, in the example, the DSP 702 determines whether a time period indicated by the duty cycle of occurrence of the voltage level of the state Sit is complete. For example, the DSP 702 uses a clock signal to determine whether a predetermined amount of time of the duty cycle of the state Sit has passed since the voltage control signal for the state Snt is sent to the voltage controller VS It. In response to determining that the predetermined amount of time has passed, the DSP 702 determines the time period indicated by the duty cycle of occurrence of the voltage level of the state Sit is complete.

[0123] Continuing the example, upon determining that the time period indicated by the duty cycle of occurrence of the voltage level of the state Sit is complete, the DSP 702 sends a voltage control signal for the state S2t to the voltage controller VS2t. Upon receiving the voltage control signal for the state S2t, the processor of the voltage controller VS2t generates a drive signal for the state S2t and sends the drive signal to the driver of the driver and amplifier 704. Also, upon receiving the voltage control signal for the state S2t, the processor of the voltage controller VS2t access the voltage level for the state S2t from the memory device of the voltage controller VS2t to control the amplifier of the driver and amplifier 704 based on the voltage level for the state S2t. In response to receiving the drive signal for the state S2t, the driver of the driver and amplifier 704 generates a current signal for the state S2t. Also, the voltage controller VS2t controls the amplifier of the driver and amplifier 704 to amplify the current signal to output an amplified current signal for the state S2t to achieve the voltage level of the state S2t. The amplified current signal for achieving the voltage level of the state S2t is sent from the amplifier to the main power supply 706. In response receiving the amplified current signal for achieving the voltage level of the state S2t and having the frequency of the top RF signal 166,the top power supply 706 modifies the top RF signal 166 to have the voltage level of the state S2t and the frequency.

[0124] Further, in the example, the DSP 702 determines whether a time period indicated by the duty cycle of occurrence of the voltage level of the state S2t is complete. For example, the DSP 702 uses the clock signal to determine whether a predetermined amount of time of the duty cycle of the state S2t has passed since the voltage control signal for the state Sit is sent to the voltage controller VS It. Tn response to determining that the predetermined amount of time has passed, the DSP 702 determines the time period indicated by the duty cycle of occurrence of the voltage level of the state S2t is complete.

[0125] Also, in the example, in response to determining that the time period indicated by the duty cycle of occurrence of the voltage level of the state S2t is complete, the DSP 702 sends a voltage control signal for the state Snt to the voltage controller VSnt. Upon receiving the voltage control signal for the state Snt, the processor of the voltage controller VSnt generates a drive signal for the state Snt and sends the drive signal to the driver of the driver and amplifier 704. Upon receiving the voltage control signal for the state Snt, the processor of the voltage controller VSnt access the voltage level for the state Snt from the memory device of the voltage controller VSnt to control the amplifier of the driver and amplifier 704 based on the voltage level for the state Snt. In response to receiving the drive signal for the state Snt, the driver of the driver and amplifier 704 generates a current signal for the state Snt. Also, the voltage controller VSnt controls the amplifier of the driver and amplifier 704 to amplify the current signal to output an amplified current signal for the state Snt to achieve the voltage level of the state Snt. The amplified current signal for achieving the voltage level of the state Snt is sent from the amplifier to the top power supply 706. In response receiving the amplified current signal for achieving the voltage level of the state Snt and having the frequency of the top RF signal 166, the top power supply 706 modifies the top RF signal 166 to have the voltage level of the state Snt and the frequency.

[0126] In the example, the DSP 702 determines whether a time period indicated by the duty cycle of occurrence of the voltage level of the state Snt is complete. For example, the DSP 702 uses the clock signal to determine whether a predetermined amount of time of the duty cycle of the state Snt has passed since the voltage control signal for the state S2nt is sent to the voltage controller VS2t. In response to determining that the predetermined amount of time has passed, the DSP 702 determines the time period indicated by the duty cycle of occurrence of the voltage level of the state Snt is complete.

[0127] Also, in the example, in response to determining that the time period indicated by the duty cycle of occurrence of the voltage level of the state Snt is complete, the DSP 702sends a voltage control signal for the state SOt to the voltage controller VSOt. Upon receiving the voltage control signal for the state SOt, the processor of the voltage controller VSOt generates a drive signal for the state SOt and sends the drive signal to the driver of the driver and amplifier 704. Upon receiving the voltage control signal for the state SOt, the processor of the voltage controller VSOt access the voltage level for the state SOt from the memory device of the voltage controller VSOt to control the amplifier of the driver and amplifier 704 based on the voltage level for the state SOt. In response to receiving the drive signal for the state SOt, the driver of the driver and amplifier 704 generates a current signal for the state SOt. Also, the voltage controller VSOt controls the amplifier of the driver and amplifier 704 to amplify the current signal to output an amplified current signal for the state SOt to achieve the voltage level of the state SOt. The amplified current signal for achieving the voltage level of the state SOt is sent from the amplifier to the top power supply 706. In response receiving the amplified current signal for achieving the voltage level of the state SOt and having the frequency of the top RF signal 166, the top power supply 706 modifies the top RF signal 166 to have the voltage level of the state SOt and the frequency.

[0128] Further, in the example, the DSP 602 determines whether a time period indicated by the pulse repetition rate of occurrence of the voltage levels of the states Sit, S2t, Spt, and SOt is complete. For example, the DSP 702 uses the clock signal to determine whether a predetermined amount of time of occurrence of the voltage levels of the states Sit, S2t, Spt, and SOt is complete has passed since the voltage control signal for the state Sit is sent to the voltage controller VS It. In response to determining that the predetermined amount of time has passed, the DSP 702 determines the time period indicated by the pulse repetition rate of occurrence of the voltage levels of the states Sit, S2t, Spt, and SOt is complete and the pulse cycle 1 of occurrence of the voltage level of the states Sit, S2t, Spt, and SOt is complete.

[0129] In the example, upon determining that the time period indicated by the pulse repetition rate of occurrence of the voltage levels of the states Sit, S2t, Spt, and SOt is complete, the DSP 702 sends the voltage control signals during the pulse cycle 2 to control the voltage controllers VS It, VS2t, VSpt, and VSOt in the same manner in which the voltage control signals are sent to the voltage controllers VS It, VS2t, VSpt, and VSOt to complete the pulse cycle 1. In this manner, the DSP 702 controls the top power supply 706 to generate additional pulse cycles, following the pulse cycle 2, of the top RF signal 166.

[0130] In an embodiment, the functions, described herein, as being performed, such as executed, by the waveform controller 102 are performed by the DSP 702. For example, the DSP 702 is coupled via the transfer cable 142 to the DSP 602 instead of the waveform controller 102 and executes the same functions as described herein as being performed by the waveformcontroller 102. As another example, the waveform controller 102 is included within, such as integrated within, the DSP 702 to form a controller, and the controller is coupled via the transfer cable 142 to the DSP 602. The controller is included within the top LF RF generator 700.

[0131] Embodiments, described herein, may be practiced with various computer system configurations including hand-held hardware units, microprocessor systems, microprocessorbased or programmable consumer electronics, minicomputers, mainframe computers and the like. The embodiments, described herein, can also be practiced in distributed computing environments where tasks are performed by remote processing hardware units that are linked through a computer network.

[0132] In some embodiments, a controller is part of a system, which may be part of the above-described examples. The system includes semiconductor processing equipment, including a processing tool or tools, chamber or chambers, a platform or platforms for processing, and / or specific processing components (a wafer pedestal, a gas flow system, etc.). The system is integrated with electronics for controlling its operation before, during, and after processing of a semiconductor wafer or substrate. The electronics is referred to as the “controller,” which may control various components or subparts of the system. The controller, depending on processing requirements and / or a type of the system, is programmed to control any process disclosed herein, including a delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, positional and operation settings, wafer transfers into and out of a tool and other transfer tools and / or load locks connected to or interfaced with the system.

[0133] Broadly speaking, in a variety of embodiments, the controller is defined as electronics having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operation, enable cleaning operations, enable endpoint measurements, and the like. The integrated circuits include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as ASICs, PLDs, one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). The program instructions are instructions communicated to the controller in the form of various individual settings (or program files), defining operational parameters for carrying out a process on or for a semiconductor wafer. The operational parameters are, in some embodiments, a part of a recipe defined by process engineers to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0134] The controller, in some embodiments, is a part of or coupled to a computer that is integrated with, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller is in a “cloud” or all or a part of a fab host computer system, which allows for remote access for wafer processing. The controller enables remote access to the system to monitor current progress of fabrication operations, examines a history of past fabrication operations, examines trends or performance metrics from a plurality of fabrication operations, to change parameters of current processing, to set processing steps to follow a current processing, or to start a new process.

[0135] In some embodiments, a remote computer (e.g. a server) provides process recipes to the system over a computer network, which includes a local network or the Internet. The remote computer includes a user interface that enables entry or programming of parameters and / or settings, which are then communicated to the system from the remote computer. In some examples, the controller receives instructions in the form of settings for processing a wafer. It should be understood that the settings are specific to a type of process to be performed on a wafer and a type of tool that the controller interfaces with or controls. Thus as described above, the controller is distributed, such as by including one or more discrete controllers that are networked together and working towards a common purpose, such as the fulfilling processes described herein. An example of a distributed controller for such purposes includes one or more integrated circuits on a chamber in communication with one or more integrated circuits located remotely (such as at a platform level or as part of a remote computer) that combine to control a process in a chamber.

[0136] Without limitation, in various embodiments, a plasma system, described herein, includes a plasma etch chamber, a deposition chamber, a spin-rinse chamber, a metal plating chamber, a clean chamber, a bevel edge etch chamber, a physical vapor deposition (PVD) chamber, a chemical vapor deposition (CVD) chamber, an atomic layer deposition (ALD) chamber, an atomic layer etch (ALE) chamber, an ion implantation chamber, a track chamber, or any other semiconductor processing chamber that is associated or used in fabrication and / or manufacturing of semiconductor wafers.

[0137] It is further noted that although the above-described operations are described with reference to a parallel plate plasma chamber, e.g., a capacitively-coupled plasma (CCP) chamber, etc., in some embodiments, the above-described operations apply to other types of plasma chambers, e.g., a plasma chamber including an inductively coupled plasma (ICP) reactor, a transformer coupled plasma (TCP) reactor, conductor tools, dielectric tools, a plasma chamber including an electron cyclotron resonance (ECR) reactor, etc. For example, a pulsed DC source is coupled to an RF coil within the ICP plasma chamber.

[0138] As noted above, depending on a process operation to be performed by the tool, the controller communicates with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout a factory, a main computer, another controller, or tools used in material transport that bring containers of wafers to and from tool locations and / or load ports in a semiconductor manufacturing factory.

[0139] With the above embodiments in mind, it should be understood that some of the embodiments employ various computer-implemented operations involving data stored in computer systems. These computer-implemented operations are those that manipulate physical quantities.

[0140] Some of the embodiments also relate to a hardware unit or an apparatus for performing these operations. The apparatus is specially constructed for a special purpose computer. When defined as a special purpose computer, the computer performs other processing, program execution or routines that are not part of the special purpose, while still being capable of operating for the special purpose.

[0141] In some embodiments, the operations, described herein, are performed by a computer selectively activated, or are configured by one or more computer programs stored in a computer memory, or are obtained over a computer network. When data is obtained over the computer network, the data may be processed by other computers on the computer network, e.g., a cloud of computing resources.

[0142] One or more embodiments, described herein, can also be fabricated as computer- readable code on a non-transitory computer-readable medium. The non-transitory computer- readable medium is any data storage hardware unit, e.g., a memory device, etc., that stores data, which is thereafter read by a computer system. Examples of the non-transitory computer- readable medium include hard drives, network attached storage (NAS), ROM, RAM, compact disc-ROMs (CD-ROMs), CD-recordables (CD-Rs), CD-rewritables (CD-RWs), magnetic tapes and other optical and non-optical data storage hardware units. In some embodiments, the non- transitory computer-readable medium includes a computer-readable tangible medium distributed over a network-coupled computer system so that the computer-readable code is stored and executed in a distributed fashion.

[0143] Although some method operations, described above, were presented in a specific order, it should be understood that in various embodiments, other housekeeping operations are performed in between the method operations, or the method operations are adjusted so that they occur at slightly different times, or are distributed in a system which allows the occurrence of themethod operations at various intervals, or are performed in a different order than that described above.

[0144] It should further be noted that in an embodiment, one or more features from any embodiment described above are combined with one or more features of any other embodiment without departing from a scope described in various embodiments described in the present disclosure.

[0145] Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications can be practiced within the scope of appended claims. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the embodiments are not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.

Claims

CLAIMS1. A system for pulsing a top low frequency (LF) radio frequency (RF) generator, comprising: a main LF RF generator configured to generate a first RF signal, wherein the main LF RF generator is configured to be coupled to a lower electrode of a plasma chamber; the top LF RF generator configured to generate a second RF signal, wherein the top LF RF generator is configured to be coupled to a top electrode of the plasma chamber; a waveform controller coupled to the main LF RF generator and the top LF RF generator, wherein the waveform controller is configured to: receive a pulse repetition rate and a first duty cycle of the first RF signal; control the top LF RF generator to apply the pulse repetition rate to the second RF signal; control the top LF RF generator to have a second duty cycle that is greater than the first duty cycle, wherein the top LF RF generator is controlled to have the second duty cycle to reduce an irregularity in a feature of a substrate.

2. The system of claim 1, wherein the second RF signal and the first RF signal has a phase difference that is maintained during a time period in which the second duty cycle is greater than the first duty cycle.

3. The system of claim 2, wherein the phase difference ranges from and including 120 degrees to 180 degrees.

4. The system of claim 1, wherein the waveform controller is configured to control the top LF RF generator to extend a time period for which a voltage level of the second duty cycle is generated by the top LF RF generator, wherein the time period is extended compared to a time period for which a voltage level of the first duty cycle is generated by the main LF RF generator.

5. The system of claim 1, wherein the waveform controller is configured to modify a number of states of the second RF signal compared to a number of states of the first RF signal.

6. The system of claim 5, wherein the waveform controller is configured to increase the number of states of the second RF signal compared to the number of states of the first RF signal to modify the number of states of the second RF signal.

7. The system of claim 5, wherein the states of the first RF signal include a first state having a first main voltage level and a second state having a second main voltage level and the first RF signal transitions from the first state to the second state during a time period, wherein the second main voltage level is lower than the first main voltage level, wherein the waveform controller is configured to control the top LF RF generator to transition, during the time period,the second RF signal from a first state having a first top voltage level to a second state having a second top voltage level, wherein the second top voltage level is greater than the first top voltage level.

8. The system of claim 7, wherein the waveform controller is configured to control the top LF RF generator to transition the second RF signal from the second state having the second top voltage level to a third state having a third top voltage level.

9. The system of claim 8, wherein the first and second states of the first RF signal occur during a pulse cycle, and the first through third states of the second RF signal occur during the pulse cycle to achieve the pulse repetition rate.

10. The system of claim 5, wherein the states of the first RF signal include a first state having a first main voltage level and a second state having a second main voltage level and the first RF signal transitions from the first state to the second state during a time period, wherein the second main voltage level is lower than the first main voltage level, wherein the waveform controller is configured to control the top LF RF generator to transition, during the time period, the second RF signal from a first state having a first top voltage level to a second state having a second top voltage level, wherein the second top voltage level is greater than the first top voltage level, wherein the waveform controller is configured to control the top LF RF generator to transition the second RF signal from the second state to a third state having a third top voltage level, wherein the third top voltage level is lower than the second top voltage level.1 1 . The system of claim 10, wherein the waveform controller is configured to control the top LF RF generator to transition the second RF signal from the third state having the third top voltage level to a fourth state having a fourth top voltage level.

12. The system of claim 11, wherein the first and second states of the first RF signal occur during a pulse cycle, and the first through fourth states of the second RF signal occur during the pulse cycle to achieve the pulse repetition rate.

13. A system for pulsing a top low frequency (LF) radio frequency (RF) generator, comprising: a main LF RF generator configured to generate a first RF signal, wherein the main LF RF generator is configured to be coupled to a lower electrode of a plasma chamber; the top LF RF generator configured to generate a second RF signal, wherein the top LF RF generator is configured to be coupled to a top electrode of the plasma chamber, wherein the top LF RF generator includes a waveform controller coupled to the main LF RF generator, wherein the waveform controller is configured to: receive a pulse repetition rate and a first duty cycle of the first RF signal from the main LF RF generator;control a power supply of the top LF RF generator to apply the pulse repetition rate to the second RF signal; control the power supply of the top LF RF generator to achieve a second duty cycle of the second RF signal, wherein the second duty cycle is greater than the first duty cycle, wherein the power supply of the top LF RF generator is controlled to have the second duty cycle to reduce an irregularity in a feature of a substrate.

14. The system of claim 13, wherein the second RF signal and the first RF signal has a phase difference that is maintained during a time period in which the second duty cycle is greater than the first duty cycle.

15. The system of claim 14, wherein the phase difference ranges from and including 120 degrees to 180 degrees.

16. The system of claim 13, wherein the waveform controller is configured to control the top LF RF generator to extend a time period for which a voltage level of the second duty cycle is generated by the power supply of the top LF RF generator, wherein the time period is extended compared to a time period for which a voltage level of the first duty cycle is generated by a power supply of the main LF RF generator.

17. The system of claim 13, wherein the waveform controller is configured to modify a number of states of the second RF signal compared to a number of states of the first RF signal.

18. The system of claim 17, wherein the waveform controller is configured to increase the number of states of the second RF signal compared to the number of states of the first RF signal to modify the number of states of the second RF signal.

19. The system of claim 17, wherein the states of the first RF signal include a first state having a first main voltage level and a second state having a second main voltage level and the first RF signal transitions from the first state to the second state during a time period, wherein the second main voltage level is lower than the first main voltage level, wherein the waveform controller is configured to control the top LF RF generator to transition, during the time period, the second RF signal from a first state having a first top voltage level to a second state having a second top voltage level, wherein the second top voltage level is greater than the first top voltage level.

20. The system of claim 19, wherein the waveform controller is configured to control the power supply of the top LF RF generator to transition the second RF signal from the second state having the second top voltage level to a third state having a third top voltage level.

21. The system of claim 20, wherein the first and second states of the first RF signal occur during a pulse cycle, and the first through third states of the second RF signal occur during the pulse cycle to achieve the pulse repetition rate.

22. The system of claim 17, wherein the states of the first RF signal include a first state having a first main voltage level and a second state having a second main voltage level and the first RF signal transitions from the first state to the second state during a time period, wherein the second main voltage level is lower than the first main voltage level, wherein the waveform controller is configured to control the top LF RF generator to transition, during the time period, the second RF signal from a first state having a first top voltage level to a second state having a second top voltage level, wherein the second top voltage level is greater than the first top voltage level, wherein the waveform controller is configured to control the top LF RF generator to transition the second RF signal from the second state to a third state having a third top voltage level, wherein the third top voltage level is lower than the second top voltage level.

23. The system of claim 22, wherein the waveform controller is configured to control the power supply of the top LF RF generator to transition the second RF signal from the third state having the third top voltage level to a fourth state having a fourth top voltage level.

24. The system of claim 23, wherein the first and second states of the first RF signal occur during a pulse cycle, and the first through fourth states of the second RF signal occur during the pulse cycle to achieve the pulse repetition rate.

25. A waveform controller for pulsing a top low frequency (LF) radio frequency (RF) generator, comprising: a processor configured to: receive a pulse repetition rate and a first duty cycle of a first RF signal generated by a main LF RF generator; control the top LF RF generator to apply the pulse repetition rate to a second RF signal generated by the top LF RF generator; control the top LF RF generator to have a second duty cycle that is greater than the first duty cycle, wherein the top LF RF generator is controlled to have the second duty cycle to reduce an irregularity in a feature of a substrate; and a memory device coupled to the processor.

26. The waveform controller of claim 25, wherein the second RF signal and the first RF signal has a phase difference that is maintained during a time period in which the second duty cycle is greater than the first duty cycle.

27. The waveform controller of claim 26, wherein the phase difference ranges from and including 120 degrees to 180 degrees.

28. The waveform controller of claim 25, wherein the waveform controller is configured to control the top LF RF generator to extend a time period for which a voltage level of the second duty cycle is generated by the top LF RF generator, wherein the time period is extended compared to a time period for which a voltage level of the first duty cycle is generated by the main LF RF generator.

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