Erasure method for flash memory cell

By employing voltage configuration of substrate and well structure in flash memory cells and channel hot electron-induced hot hole injection method, the problems of limited process size and large cell area of ​​existing flash memory are solved, achieving higher erase speed and higher integration density.

WO2026092227A1 Publication Date: 2026-05-07BEIJING PANXIN MICROELECTRONICS TECHNOLOGY CO LTD
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Patent Information

Application Number
PCT/CN2025/128932
Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
Priority Date
2024-11-01
Filing Date
2025-10-21
Publication Date
2026-05-07

AI Technical Summary

Technical Problem

Existing floating-gate and SONOS type flash memories suffer from problems such as limited process size, large cell area, high write power consumption, and large array area overhead, making it impossible to achieve high-density integration with gigabit capacity or higher.

Method used

The flash memory cell employs a substrate and well structure, and achieves the series connection of the storage transistor and the gate transistor through a specific voltage configuration. Combined with the channel hot electron-induced hot hole injection erasure method, the gate electrode operating voltage is reduced and the charge density of the storage medium layer is increased.

Benefits of technology

It achieves higher erase speed, larger erase window, less hot carrier damage, lower leakage current and higher durability and reliability, and supports smaller process feature size and higher integration density.

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Abstract

Provided in the present disclosure is an erasure method for a flash memory cell. The flash memory cell comprises storage transistors and a gating transistor that are connected in series. The erasure method in the present disclosure comprises: applying erasure voltages to electrodes of a flash memory cell and gate electrodes of transistors, wherein the erasure voltage applied to a gate electrode of a storage transistor to be subjected to erasure is lower than a second power source voltage, such that the physical effect of channel hot-electron induced hot hole injection occurs, and thus hot holes in a channel are attracted into a storage medium layer for erasing. Compared with existing band-to-band hot-hole (BBHH) erasure methods, the erasure method for a flash memory cell in the present disclosure provides wider hole distribution and higher injection efficiency, such that the erasure method in the present disclosure achieves a higher erasure speed, a larger erasure window, reduced hot-carrier damage, a lower leakage current and improved endurance reliability.
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