Semiconductor device and display device

Abstract

Provided is a novel semiconductor device. In this semiconductor device, a first terminal of a first transistor is connected to a first terminal of a second transistor, a gate of a third transistor, and a first terminal of a first capacitive element. A first terminal of the third transistor is connected to a first terminal of a fourth transistor. A second terminal of the first transistor is connected to a first terminal of a fifth transistor. The channel length of the first transistor is greater than the channel length of the third transistor. The channel length of the third transistor is greater than the channel length of the second transistor. Signals of mutually inverted logic are applied to a gate of the second transistor and a gate of the fifth transistor.

Description

Semiconductor device and display device

[0001] One aspect of the present invention relates to a semiconductor device and a display device.

[0002] One aspect of the present invention is not limited to the above-mentioned technical field. Examples of technical fields of one aspect of the present invention include semiconductor devices, display devices, light-emitting devices, projection devices, illumination devices, optical devices, electro-optical devices, imaging devices, light-receiving devices, detection devices, power supply devices, energy storage devices, communication devices, computing devices, control devices, computing processing devices, memory devices, input devices, output devices, input / output devices, signal processing devices, information processing devices, computers, electronic devices, systems having the same, methods for driving them, or methods for manufacturing them.

[0003] Display devices are used in a variety of applications. Large-scale display devices are used in home television systems and PID (Public Information Display) for digital signage. Small-scale display devices are used in mobile information terminals such as smartphones and tablets, and wearable devices such as VR (Virtual Reality) devices and AR (Augmented Reality) devices. Furthermore, display devices are being enhanced and given higher value by adding functions other than display. For example, display devices with touch panel functionality and display devices with in-screen fingerprint authentication functionality have been developed.

[0004] Furthermore, circuits for driving display devices have been developed. Patent Document 1 discloses an example of a driving circuit that can be used in a display device.

[0005] Japanese Patent Publication No. 2008-122939

[0006] One aspect of the present invention aims to provide a semiconductor device that can improve the display quality of a display device. Alternatively, one aspect of the present invention aims to provide a semiconductor device that can improve the reliability of a display device. Alternatively, one aspect of the present invention aims to provide a semiconductor device that can reduce the power consumption of a display device. Alternatively, one aspect of the present invention aims to provide a semiconductor device that can lower the manufacturing cost of a display device. Alternatively, one aspect of the present invention aims to provide a semiconductor device that can shorten the manufacturing period of a display device. Alternatively, one aspect of the present invention aims to provide a semiconductor device that can increase the screen size of a display device. Alternatively, one aspect of the present invention aims to provide a semiconductor device that can narrow the bezel width of a display device. Alternatively, one aspect of the present invention aims to provide a semiconductor device that can increase the operating speed of a display device. Alternatively, one aspect of the present invention aims to provide a semiconductor device that can improve the performance of a display device. Alternatively, one aspect of the present invention aims to provide a drive circuit to which the above semiconductor device is applied. Alternatively, one aspect of the present invention aims to provide a display device to which the above semiconductor device is applied. Alternatively, one aspect of the present invention aims to provide a method for driving the above semiconductor device. Alternatively, one aspect of the present invention aims to provide a method for driving the above-mentioned drive circuit. Alternatively, one aspect of the present invention aims to provide a method for driving the above-mentioned display device. Alternatively, one aspect of the present invention aims to provide a novel semiconductor device. Alternatively, one aspect of the present invention aims to provide a novel drive circuit. Alternatively, one aspect of the present invention aims to provide a novel display device.

[0007] Furthermore, the above-mentioned problems do not preclude the existence of other problems. Those skilled in the art can naturally derive other problems from the description in this specification, drawings, claims, etc., and it is possible to extract other problems from the description in this specification, drawings, claims, etc. Furthermore, one aspect of the present invention does not need to solve all of these problems (the above-mentioned problems and other problems).

[0008] (1) One aspect of the present invention is a semiconductor device comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a first capacitance element, wherein the first terminal of the first transistor is electrically connected to the first terminal of the second transistor, the gate of the third transistor, and the first terminal of the first capacitance element, the first terminal of the third transistor is electrically connected to the first terminal of the fourth transistor, the second terminal of the first transistor is electrically connected to the first terminal of the fifth transistor, the channel length of the first transistor is greater than the channel length of the third transistor, and the channel length of the third transistor is greater than the channel length of the second transistor.

[0009] (2) In addition, in (1) above, the gates of the second transistor and the fifth transistor may be supplied with signals whose logic is inverted relative to each other.

[0010] (3) In addition, in (1) or (2) above, each of the first to fifth transistors is an n-channel transistor, a first potential is applied to the gate of the first transistor, a second potential is applied to either the second terminal of the second transistor or the second terminal of the fifth transistor, a third potential is applied to the other of the second terminal of the second transistor or the second terminal of the fifth transistor, and a first potential, a second potential, or a third potential is applied to the second terminal of the first capacitive element, and the first potential may be greater than the second potential and less than the third potential.

[0011] (4) In addition, in (3) above, a fourth potential may be applied to the second terminal of the third transistor, a fifth potential may be applied to the second terminal of the fourth transistor, and a sixth potential may be applied to the gate of the fourth transistor, where the fourth potential is greater than the third potential, the fifth potential is less than the second potential, and the sixth potential is greater than the fifth potential and less than the fourth potential.

[0012] (5) In addition, in any one of (1) to (4) above, the channel width of the first transistor may be smaller than the channel width of the second transistor, and the channel width of the second transistor may be smaller than the channel width of the third transistor.

[0013] (6) In addition, in any one of (1) to (5) above, each of the first to fifth transistors may include an oxide semiconductor in the channel formation region.

[0014] (7) Another aspect of the present invention is a display device comprising a semiconductor device according to any one of (1) to (6) above, and a pixel, wherein the pixel comprises a sixth transistor and a second capacitance element, the first terminal of the third transistor is electrically connected to the first terminal of the sixth transistor or the first terminal of the second capacitance element, and the gate of the sixth transistor is electrically connected to the second terminal of the second capacitance element.

[0015] (8) In addition, in (7) above, the pixel may have a seventh transistor and a light-emitting element, the second terminal of the sixth transistor being electrically connected to the gate of the seventh transistor, and the first terminal of the seventh transistor being electrically connected to the first terminal of the light-emitting element.

[0016] According to one aspect of the present invention, a semiconductor device capable of improving the display quality of a display device can be provided. Or, according to one aspect of the present invention, a semiconductor device capable of enhancing the reliability of a display device can be provided. Or, according to one aspect of the present invention, a semiconductor device capable of reducing the power consumption of a display device can be provided. Or, according to one aspect of the present invention, a semiconductor device capable of lowering the manufacturing cost of a display device can be provided. Or, according to one aspect of the present invention, a semiconductor device capable of shortening the manufacturing period of a display device can be provided. Or, according to one aspect of the present invention, a semiconductor device capable of increasing the screen size of a display device can be provided. Or, according to one aspect of the present invention, a semiconductor device capable of narrowing the frame width of a display device can be provided. Or, according to one aspect of the present invention, a semiconductor device capable of increasing the operating speed of a display device can be provided. Or, according to one aspect of the present invention, a semiconductor device capable of enhancing the performance of a display device can be provided. Or, according to one aspect of the present invention, a driving circuit applying the above semiconductor device can be provided. Or, according to one aspect of the present invention, a display device applying the above semiconductor device can be provided. Or, according to one aspect of the present invention, a driving method of the above semiconductor device can be provided. Or, according to one aspect of the present invention, a driving method of the above driving circuit can be provided. Or, according to one aspect of the present invention, a driving method of the above display device can be provided. Or, according to one aspect of the present invention, a novel semiconductor device can be provided. Or, according to one aspect of the present invention, a novel driving circuit can be provided. Or, according to one aspect of the present invention, a novel display device can be provided.

[0017] Note that the above effects do not prevent the existence of other effects. A person skilled in the art can naturally derive other effects from the descriptions in this specification, drawings, claims, etc., and it is possible to extract other effects from the descriptions in this specification, drawings, claims, etc. Note that one aspect of the present invention does not necessarily have all of these effects (the above effects and other effects).

[0018] Figure 1A is a circuit diagram illustrating an example configuration of a semiconductor device. Figure 1B is a timing chart illustrating an example operation of a semiconductor device. Figures 2A and 2B are circuit diagrams illustrating an example operation of a semiconductor device. Figures 3A and 3B are circuit diagrams illustrating an example configuration of a semiconductor device. Figures 4A and 4B are circuit diagrams illustrating an example configuration of a semiconductor device. Figures 5A and 5B are circuit diagrams illustrating an example configuration of a semiconductor device. Figures 6A and 6B are circuit diagrams illustrating an example configuration of a semiconductor device. Figures 7A and 7B are circuit diagrams illustrating an example configuration of a semiconductor device. Figures 8A and 8B are circuit diagrams illustrating an example configuration of a semiconductor device. Figures 9A and 9B are circuit diagrams illustrating an example configuration of a semiconductor device. Figures 10A and 10B are circuit diagrams illustrating an example configuration of a drive circuit. Figures 11A and 11B are block diagrams illustrating an example configuration of a display device. Figures 12A and 12B are circuit diagrams illustrating an example configuration of a display device. Figure 13 is a timing chart illustrating an example operation of a display device. Figures 14A and 14B are circuit diagrams illustrating an example configuration of a display device. Figure 15A is a top view illustrating an example of a transistor configuration. Figures 15B and 15C are cross-sectional views illustrating an example of a transistor configuration. Figure 16A is a top view illustrating an example of a transistor configuration. Figures 16B and 16C are cross-sectional views illustrating an example of a transistor configuration. Figure 17 is a top view illustrating an example of a semiconductor device configuration. Figure 18 is a top view illustrating an example of a semiconductor device configuration. Figures 19A, 19B, 19C, 19D, and 19E are cross-sectional views illustrating an example of a semiconductor device configuration. Figure 20A is a perspective view illustrating an example of a display device configuration. Figures 20B, 20C, 20D, 20E, and 20F are top views illustrating an example of a pixel arrangement. Figure 21 is a cross-sectional view illustrating an example of a display device configuration. Figures 22A, 22B, 22C, 22D, 22E, 22F, 22G, and 22H are diagrams illustrating an example of an electronic device. Figures 23A1, 23A2, 23A3, 23A4, 23A5, 23A6, 23A7 and 23B1, 23B2, 23B3, 23B4, 23B5, and 23B6 illustrate the electrical connections.

[0019] Embodiments of the present invention will be described. However, those skilled in the art can easily understand that the embodiments and their details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not to be construed as being limited to the description of the following embodiments.

[0020] In addition, the contents described in the embodiments can be appropriately combined to form an aspect of the present invention.

[0021] In this specification and the like, the components of the present invention may be classified by function and shown as independent elements. However, it may be difficult to separate the components by function, and in some cases, a single element may involve multiple functions, or a single function may involve multiple elements. Therefore, it is not limited to that description and may be appropriately rephrased in some cases.

[0022] Also, when using the same reference numerals for multiple elements and distinguishing them in the description, they may be described with identification symbols such as "A", "b", "_1", "[n]", "[m, n]", etc. Also, when explaining matters common to multiple elements with identification symbols, or when explaining them without distinguishing them, they may be described without identification symbols.

[0023] Also, in the drawings, the same reference numerals may be used for the same elements, elements having the same function, elements of the same material, elements formed simultaneously, etc. to omit the repeated description. Also, the hatching pattern and the like may be the same so that no reference numeral is attached.

[0024] Also, the drawings are schematically shown to assist in understanding the present invention. Therefore, they are not limited to their size, aspect ratio, shape, etc. Also, some elements may be omitted.

[0025] (Embodiment 1) A semiconductor device according to an aspect of the present invention will be described with reference to the drawings. At least a part of the semiconductor device according to an aspect of the present invention can be used, for example, in a display device. In particular, it can be used in a driving circuit included in a display device.

[0026] Furthermore, a semiconductor device according to one aspect of the present invention is capable of outputting a ramp wave. Examples of ramp waves include sawtooth waves and triangular waves. Therefore, in a display device using this semiconductor device, pulse width modulation (PWM) control using sawtooth waves or triangular waves can be performed to drive the pixels of the display device. In particular, when using micro-LEDs (Light Emitting Diodes) or the like as light-emitting elements in the pixels, PWM control is preferable. By performing PWM control, the emission wavelength of the light-emitting elements can be stabilized, thereby improving display quality. In addition, since the light-emitting elements can be made to emit light at a current density that is efficient in terms of luminescence, power consumption can be reduced. Furthermore, since the light-emitting elements can emit light at a constant current density regardless of their luminescence intensity, reliability can be improved.

[0027] <Example of Semiconductor Device Configuration> Figure 1 is a circuit diagram illustrating a semiconductor device 100 according to one aspect of the present invention.

[0028] The semiconductor device 100 includes transistor M11, transistor M12, transistor M13, transistor M14, transistor M15, and a capacitive element C11.

[0029] One source or drain of transistor M11 is connected to one source or drain of transistor M12, the gate of transistor M13, and one terminal of capacitive element C11. One source or drain of transistor M13 is connected to one source or drain of transistor M14 and wiring OL. The other source or drain of transistor M11 is connected to one source or drain of transistor M15. The gate of transistor M11 is connected to wiring VLB1. The other source or drain of transistor M12 is connected to wiring VLS1. The other source or drain of transistor M13 is connected to wiring VLD2. The other source or drain of transistor M14 is connected to wiring VLS2. The other source or drain of transistor M15 is connected to wiring VLD1. The gate of transistor M14 is connected to wiring VLB2. The other terminal of capacitive element C11 is connected to wiring VLC.

[0030] The wiring connected to the gate of transistor M15 may be referred to as node ND11. The wiring connected to the gate of transistor M12 may be referred to as node ND12. The wiring connected to the source or the other drain of transistor M11 may be referred to as node ND13. The wiring connected to one of the source or drain of transistor M11 and one terminal of the capacitive element C11 may be referred to as node ND14.

[0031] Each of the wires VLS1, VLD1, VLB1, VLS2, VLD2, VLB2, and VLC functions as a power line. These wires have the function of transmitting a constant potential output from a circuit (e.g., a power supply circuit) located outside the semiconductor device 100 to the semiconductor device 100. Therefore, each of the wires VLS1, VLD1, VLB1, VLS2, VLD2, VLB2, and VLC is supplied with a constant potential, for example. At least one of the wires VLS1, VLD1, VLB1, VLS2, VLD2, VLB2, and VLC may also function as a signal line. Each of the nodes ND11 and ND12 functions as a signal line. Nodes ND11 and ND12 are each supplied with a signal from register 111 in the drive circuit 110, which will be described later.

[0032] An n-channel transistor can be used as the transistor constituting the semiconductor device 100.

[0033] Furthermore, a p-channel transistor may be used as at least one of the transistors constituting the semiconductor device 100. In that case, the descriptions relating to the positive and negative relationship of voltage, the magnitude relationship of electric potential, and the positive and negative relationship of current (also known as the direction of current flow) in the explanation of the semiconductor device 100 may be appropriately reinterpreted. For example, "high electric potential" and "low electric potential" may be appropriately reinterpreted as mutual. Also, for example, "raise the electric potential" and "lower the electric potential" may be appropriately reinterpreted as mutual.

[0034] The semiconductor device 100 is a circuit capable of outputting ramp waves such as sawtooth waves or triangular waves, and can be constructed using transistors of all the same conductivity type (either only n-channel transistors or only p-channel transistors). Therefore, compared to a configuration using both n-channel and p-channel transistors (such as a CMOS circuit), at least one of the following can be achieved: reduced manufacturing costs and shortened manufacturing time.

[0035] In the semiconductor device 100, a sawtooth wave can be generated by repeatedly and alternately initializing the potential of node ND14 and slowly changing the potential of node ND14 at a constant period.

[0036] In the semiconductor device 100, a filter 101 is formed by a transistor M11 and a capacitive element C11. The filter 101 has its input to node ND13 and its output to node ND14, and functions as a low-pass filter with a cutoff frequency of "1 / (2 × π × on-resistance of transistor M11 × capacitance of capacitive element C11)". It can also be said that the filter 101 functions as an integrating circuit with a time constant of "on-resistance of transistor M11 × capacitance of capacitive element C11". As a result, the semiconductor device 100 can gradually change the potential of node ND14 in response to abrupt changes in the potential of node ND13. Note that, for the sake of clarity, the effects of parasitic capacitance, parasitic resistance, etc., may not be considered in this explanation.

[0037] Furthermore, in the semiconductor device 100, an amplifier 102 is formed by transistors M13 and M14. The amplifier 102 functions as a source follower (also called a common-drain amplifier circuit), taking node ND14 as an input and wiring OL as an output. The amplifier 102 may also function as a common-source amplifier circuit. As a result, the semiconductor device 100 can supply a signal to a load connected to wiring OL (such as a pixel of a display device) that follows the change in the potential of node ND14.

[0038] In the semiconductor device 100, transistors M15 and M12 can be operated complementaryly by applying signals to nodes ND11 and ND12 that have their logic inverted relative to each other (these signals can also have a period of logic inversion). At this time, by setting transistor M15 to the OFF state and transistor M12 to the ON state, the potential of wiring VLS1 is supplied to node ND14 via transistor M12. This allows the potential of node ND14 to be initialized to the potential of wiring VLS1. Also, by setting transistor M15 to the ON state and transistor M12 to the OFF state, the potential of wiring VLD1 is supplied to node ND14 via transistors M15 and M11. This allows the potential of node ND14 to be gradually changed toward the potential of wiring VLD1.

[0039] Therefore, the semiconductor device 100 can generate a signal in which the initialization of the potential of node ND14 and the gradual change of the potential of node ND14 alternate and are repeated at a constant period by supplying node ND11 and node ND12 with periodic signals whose logic is inverted relative to each other (or periodic signals that have a period of logic inversion). Furthermore, this signal can be output to wiring OL via amplifier 102. At this time, the period for gradually changing the potential of node ND14 can be made sufficiently longer than the period for initializing the potential of node ND14.

[0040] Here, in the semiconductor device 100, by increasing the "on-resistance of transistor M11 × capacitance of capacitive element C11," which corresponds to the time constant of filter 101, the period during which the potential of node ND14 can be considered linear when it changes slowly becomes longer. Therefore, by making the time constant of filter 101 sufficiently large compared to the period of the periodic signal supplied to node ND11 and node ND12, the change in the potential of node ND14 can be considered as a sawtooth wave. Thus, the semiconductor device 100 can generate a sawtooth wave and output it to wiring OL.

[0041] To increase the "on-resistance of transistor M11 × capacitance of capacitive element C11," which corresponds to the time constant of filter 101, it is preferable to increase the on-resistance of transistor M11. It is also preferable to increase the capacitance of capacitive element C11.

[0042] To increase the on-resistance of transistor M11, the channel length of transistor M11 can be increased. For example, the channel length of transistor M11 may be made larger than the channel lengths of transistors M12 to M15. Alternatively, to increase the on-resistance of transistor M11, the channel width of transistor M11 can be reduced. For example, the channel width of transistor M11 may be made smaller than the channel widths of transistors M12 to M15.

[0043] Furthermore, reliability can be improved by increasing the channel length of transistor M11.

[0044] To increase the capacitance of the capacitive element C11, the relative permittivity of the dielectric of the capacitive element C11 can be increased. For example, the relative permittivity of the dielectric of the capacitive element C11 may be higher than the relative permittivity of the gate insulating films of transistors M12 to M15. Also, to increase the capacitance of the capacitive element C11, the film thickness of the dielectric of the capacitive element C11 (corresponding to the distance between the pair of electrodes) can be decreased. For example, the film thickness of the dielectric of the capacitive element C11 may be smaller than the film thickness of the gate insulating films of transistors M12 to M15. Furthermore, to increase the capacitance of the capacitive element C11, the area of ​​the capacitive element C11 (corresponding to the area of ​​the region where the pair of electrodes overlap) may be increased. For example, the area of ​​the capacitive element C11 may be larger than the channel area (corresponding to channel length × channel width) of transistors M12 to M15.

[0045] For the sake of simplicity, the time constant of the filter 101 was given as "on-resistance of transistor M11 × capacitance of capacitive element C11," but it can also be given as "on-resistance of transistor M11 × (capacitance of capacitive element C11 + gate capacitance of transistor M11)." Therefore, by making "on-resistance of transistor M11 × gate capacitance of transistor M11" sufficiently large, it may be possible to generate a sawtooth wave. In this case, the semiconductor device 100 does not need to have a capacitive element C11.

[0046] Furthermore, in the semiconductor device 100, it is preferable that the transistors constituting the amplifier 102 (transistors M13 and M14) have a large on-current in order to drive the load connected to the wiring OL. To increase the on-current of the transistors, for example, the channel width of the transistors can be increased. Alternatively, the channel length of the transistors can be decreased. On the other hand, it is preferable that the transistors constituting the amplifier 102 have high saturation (the change in drain current with respect to drain voltage is small in the saturation region of the transistors). To increase the saturation of the transistors, the channel length of the transistors can be increased.

[0047] For example, the channel lengths of transistors M13 and M14 may be made larger than the channel lengths of transistors M12 and M15. Also, for example, the channel widths of transistors M13 and M14 may be made larger than the channel widths of transistors M12 and M15.

[0048] Furthermore, reliability can be improved by increasing the channel lengths of transistors M13 and M14.

[0049] In one aspect of the present invention, OS transistors (transistors containing an oxide semiconductor in the channel formation region) can be used as transistors (transistors M11 to M15) constituting the semiconductor device 100. OS transistors are easy to fabricate, for example, on large substrates. Therefore, by using OS transistors, for example, when the semiconductor device 100 is used as a display device, the screen size of the display device can be increased.

[0050] Various oxide semiconductors can be used for the OS transistor. Furthermore, oxide semiconductors with different elements or compositions may be used for each transistor constituting the semiconductor device 100. For example, an oxide semiconductor that has a higher on-resistance than transistors M12 to M15 can be used for transistor M11. Also, for example, an oxide semiconductor that has a higher on-current than transistor M11 can be used for each of transistors M12 to M15. Here, for example, a transistor using indium oxide tends to have a higher on-current than a transistor using an oxide containing at least indium and zinc (such as indium gallium zinc oxide (IGZO) described later). Therefore, for example, an oxide containing at least indium and zinc may be used for transistor M11, and indium oxide may be used for each of transistors M12 to M15.

[0051] [Operation Example] Next, an operation example of the semiconductor device 100 will be described.

[0052] Figure 1B is a timing chart illustrating an example of the operation of the semiconductor device 100. Figures 2A and 2B are circuit diagrams illustrating an example of the operation of the semiconductor device 100.

[0053] In the semiconductor device 100, wiring VLS1 is given a potential L (sometimes simply written as "L"). Wiring VLD1 is given a potential H (sometimes simply written as "H") which is greater than potential L. Wiring VLB1 is given a potential VB which is greater than potential L and less than potential H. In addition, nodes ND11 and ND12 are each given a signal that is either potential L or potential H.

[0054] Potential L is set to a potential that, when supplied to the gates of transistors M12 and M15, can turn them off. Potential H is set to a potential that, when supplied to the gates of transistors M12 and M15, can turn them on. The difference between potential L and potential H is set to be greater than the threshold voltage of transistors M12 and M15. Potential L or potential H may, for example, be the ground potential.

[0055] The potential VB is set to a potential that, when supplied to the gate of transistor M11, allows the transistor to operate in the ON state. As described above, it is preferable to increase the on-resistance of transistor M11. To this end, the on-resistance of transistor M11 may be increased by decreasing the potential VB within the range in which transistor M11 operates in the ON state.

[0056] Furthermore, in the semiconductor device 100, the wiring VLS2, wiring VLD2, and wiring VLB2 are each provided with a potential that allows the amplifier 102 to operate as a source follower. For example, wiring VLS2 is provided with a potential SFVSS that is smaller than potential L. Wiring VLD2 is provided with a potential SFVDD that is larger than potential H. Wiring VLB2 is provided with a potential SFVB that is larger than potential SFVSS and smaller than potential SFVDD. At this time, potential SFVB is set to a potential that allows transistor M14 to operate in the saturation region. Therefore, it can be said that transistor M14 functions as a constant current source. As a result, wiring OL outputs a potential that follows the change in potential of node ND14 and is smaller than the potential of node ND14 by the threshold voltage of transistor M13.

[0057] Furthermore, in the semiconductor device 100, a constant potential is supplied to the wiring VLC. For example, a potential L, a potential H, a potential VB, a potential SFVSS, a potential SFVDD, a potential SFVB, or a ground potential is supplied. Therefore, the wiring VLC may be connected to wiring VLS1, wiring VLD1, wiring VLB1, wiring VLS2, wiring VLD2, or wiring VLB2.

[0058] In the description of operation, rise and fall times may occur when the potential changes, for example, due to loads such as wiring (parasitic capacitance and resistance). Also, even if two different operations are shown to occur at the same time, this does not necessarily mean that they are strictly at the same time. For example, even if there is a slight time difference due to signal delay in the wiring, they may still be considered to occur at the same time.

[0059] Furthermore, in timing charts, even if each period is depicted as having the same length on the diagram for the sake of clarity, the actual duration of each period may differ.

[0060] The timing chart shown in Figure 1B illustrates the potential applied to each wire during each period of operation. It also shows the change in potential at each node.

[0061] Furthermore, Figures 2A and 2B show the state of the circuit at each point in time during operation (potential of each wire and node, state of each transistor, current flowing through each wire and node, etc.). In these cases, a symbol indicating potential, such as "H" or "L" (also called a potential symbol), may be written adjacent to each wire and node, enclosed in a line. In addition, an "×" symbol may be superimposed on an off-state transistor. Furthermore, a dashed arrow may be used to indicate the direction of current flow (which can also be said to be the direction of positive charge movement) or the way potential is supplied along each wire and node.

[0062] Furthermore, in order to simplify the explanation, the effects of parasitic capacity, parasitic resistance, etc., may be omitted from the explanation.

[0063] Furthermore, for the sake of clarity, the potential applied to wiring VLS1 is denoted as potential L, the potential applied to wiring VLD1 is denoted as potential H, and the potentials applied to nodes ND11 and ND12 are denoted as potential L or potential H, respectively. However, different potentials may be applied to each wiring and node. For example, wiring VLD1 may be given a potential different from potential H (for example, a potential smaller than potential H). Also, for example, wiring VLS1 may be given a potential different from potential L (for example, a potential larger than potential L).

[0064] During period T11, the potential of node ND11 becomes "L" and the potential of node ND12 becomes "H" (see Figure 2A). As a result, transistor M15 turns off and transistor M12 turns on. Then, the potential of wiring VLS1 is supplied to node ND14 via transistor M12, and further supplied to node ND13 via transistor M11. Thus, the potentials of node ND14 and node ND13 are initialized to "L". Also, since the potential of node ND14 is output to wiring OL via amplifier 102, the potential of wiring OL is also initialized.

[0065] During period T12, the potential of node ND11 becomes "H" and the potential of node ND12 becomes "L" (see Figure 2B). As a result, transistor M15 turns on and transistor M12 turns off. Then, the potential of wiring VLD1 is supplied to node ND13 via transistor M15. Thus, the potentials of each node ND13 become "H". Furthermore, the potential of node ND13 is supplied to node ND14 via filter 101. Thus, the potential of node ND14 gradually rises. In addition, since the potential of node ND14 is output to wiring OL via amplifier 102, the potential of wiring OL also gradually rises.

[0066] In the operation of the semiconductor device 100, the operation during period T11 and the operation during period T12 are performed alternately and repeatedly. In this case, it is preferable to make period T12 sufficiently longer than period T11.

[0067] Here, in the semiconductor device 100, it is preferable to make the "on-resistance of transistor M11 × capacitance of capacitive element C11," which corresponds to the time constant of the filter 101, sufficiently large relative to the length of the period T12. This allows the potential of node ND14 to be considered linear as it gradually rises during the period T12. Therefore, the change in the potential of node ND14 can be considered as a sawtooth wave.

[0068] In the above example of operation, a potential H may be applied to wiring VLS1 and a potential L to wiring VLD1. As a result, the potential of node ND14 is initialized to "H" during period T11, and the potential of node ND14 gradually decreases during period T12. Such a change in the potential of node ND14 can also be considered a sawtooth wave (also called an inverse sawtooth wave in this context).

[0069] Furthermore, although not shown in the figures, the semiconductor device 100 may be configured such that one source or drain of transistor M12 is connected to the other source or drain of transistor M11. In this case, in the above example of operation, the lengths of period T11 and period T12 may be the same. As a result, the potential of node ND14 gradually decreases during period T11, and the potential of node ND14 gradually increases during period T12. Such a change in the potential of node ND14 can be considered as a triangular wave.

[0070] Furthermore, different potentials may be applied to the wiring VLB1 during period T11 and period T12. For example, the potential applied to the wiring VLB1 during period T11 may be greater than the potential applied to the wiring VLB1 during period T12. This allows the on-current of transistor M11 to be increased during period T11, thereby accelerating the fall time of the potential of node ND13 and shortening the time required for initialization.

[0071] [Modification 1] One aspect of the present invention is not limited to the above-described configuration example.

[0072] Figure 3A is a circuit diagram illustrating a modified example of the semiconductor device 100 shown in Figure 1A. The semiconductor device 100 shown in Figure 3A differs from the semiconductor device 100 shown in Figure 1A in terms of the connections between transistors M13 and M14. Here, the other end of either the source or drain of transistor M13 is connected to wiring VLD1, and the other end of either the source or drain of transistor M14 is connected to wiring VLS1.

[0073] In the semiconductor device 100 shown in Figure 3A, the potential of node ND14 is initialized to "L" during period T11, and the potential of node ND14 gradually increases during period T12.

[0074] For example, a potential L may be applied to the wiring VLS1 during period T11, and a potential SFVSS may be applied to the wiring VLS1 during period T12. This allows the amplifier 102 to operate as a source follower even if the potential of node ND14 is near "L" in the early stages of period T12.

[0075] This configuration eliminates the need for wiring VLS2 and wiring VLD2, thus reducing the layout area. Consequently, the bezel width of the display device can be reduced.

[0076] [Modification 2] Figure 3B is a circuit diagram illustrating a modified version of the semiconductor device 100 shown in Figure 1A. The semiconductor device 100 shown in Figure 3B differs from the semiconductor device 100 shown in Figure 1A in terms of the connection of transistors M12 to M15. Here, the other end of either the source or drain of transistor M12 is connected to the wiring VLD1, the other end of either the source or drain of transistor M13 is connected to the wiring VLD1, the other end of either the source or drain of transistor M14 is connected to the wiring VLS1, and the other end of either the source or drain of transistor M15 is connected to the wiring VLS1.

[0077] In the semiconductor device 100 shown in Figure 3B, the potential of node ND14 is initialized to "H" during period T11, and the potential of node ND14 gradually decreases during period T12.

[0078] This configuration eliminates the need for wiring VLS2 and wiring VLD2, thus reducing the layout area. Consequently, the bezel width of the display device can be reduced.

[0079] [Modification 3] Figure 4A is a circuit diagram illustrating a modified version of the semiconductor device 100 shown in Figure 1A. The semiconductor device 100 shown in Figure 4A differs from the semiconductor device 100 shown in Figure 1A in that it includes a transistor M16 and a capacitive element C12. In this case, the gate of transistor M15 is connected to either the source or drain of transistor M16 and to one terminal of the capacitive element C12. The other terminal of the capacitive element C12 is connected to either the source or drain of transistor M15. The gate of transistor M16 is connected to wiring VLD1a.

[0080] Here, the wiring connected to the gate of transistor M15, either the source or drain of transistor M16, and one terminal of the capacitive element C12 may be referred to as node ND15. The wiring connected to the other source or drain of transistor M16 may be referred to as node ND11.

[0081] A constant potential is applied to the VLD1a wiring, for example. For example, the VLD1a wiring may be given the same potential as the VLD1 wiring, or it may be given a different potential (for example, a potential lower than that of the VLD1 wiring). Also, the VLD1a wiring may be connected to the VLD1 wiring.

[0082] With this configuration, during period T12, when potential is supplied from wiring VLD1 to node ND13 via transistor M15, a bootstrap effect occurs due to the capacitive coupling of capacitive element C12, and the gate voltage of transistor M15 (here, this corresponds to the potential difference between the gate and either the source or drain (corresponding to node ND13) as the reference) is maintained. This suppresses the decrease in the potential supplied to node ND13 due to the threshold voltage of transistor M15, and also speeds up the rise time of the potential at node ND13.

[0083] Furthermore, the potential applied to wiring VLD1a may be less than the potential applied to wiring VLD1. For example, a potential H may be applied to wiring VLD1, and a potential less than H may be applied to wiring VLD1a. In this case, even if the potential of node ND11 is set to a potential less than "H" during period T12, the bootstrap effect can make the potential of node ND13 "H". Therefore, the amplitude of the signal applied to node ND11 can be reduced. In this case, the amplitude of the signal applied to node ND12 can also be reduced in the same way. This makes it possible to lower the power supply voltage for operating the circuits that apply signals to node ND11 and node ND12, respectively (for example, the register 111 described later). Therefore, at least one of the following can be achieved: reduced power consumption and improved reliability.

[0084] Note that the semiconductor device 100 shown in Figure 4A does not necessarily have to have a capacitive element C12. In this case, the bootstrap effect can be generated by the parasitic capacitance between the gate of transistor M15 and either the source or the drain. This reduces the layout area and allows for a reduction in the bezel width of the display device. On the other hand, having a capacitive element C12 can enhance the bootstrap effect. Therefore, it is possible to suppress the decrease in the potential supplied to node ND13 and to accelerate the rise time of the potential at node ND13.

[0085] [Modification 4] Figure 4B is a circuit diagram illustrating a modified version of the semiconductor device 100 shown in Figure 1A. The semiconductor device 100 shown in Figure 4B differs from the semiconductor device 100 shown in Figure 1A in that it has a transistor M17. In this case, one of the sources or drains of transistor M17 is connected to the other of the source or drain of transistor M11. The other of the source or drain of transistor M17 is connected to wiring VLS1a. The gate of transistor M17 is connected to the gate of transistor M12.

[0086] For example, a constant potential is supplied to the wiring VLS1a. For example, the wiring VLS1a may be supplied with the same potential as the wiring VLS1, or it may be supplied with a different potential. Also, the wiring VLS1a may be connected to the wiring VLS1.

[0087] With this configuration, during period T11, the potential of the wiring VLS1a is supplied to node ND13 via transistor M17. This speeds up the fall time of the potential at node ND13, thereby shortening the time required for initialization.

[0088] [Modification 5] Figure 5A is a circuit diagram illustrating a modified version of the semiconductor device 100 shown in Figure 1A. The semiconductor device 100 shown in Figure 5A differs from the semiconductor device 100 shown in Figure 1A in that it has a transistor M18. In this case, one of the source or drain of transistor M18 is connected to wiring OL. The other of the source or drain of transistor M18 is connected to wiring VLS1b. The gate of transistor M18 is connected to the gate of transistor M12.

[0089] A constant potential is supplied to wiring VLS1b, for example. For example, wiring VLS1b may be supplied with the same potential as wiring VLS1, the same potential as wiring VLS2, or a different potential. Also, wiring VLS1b may be connected to wiring VLS1 or to wiring VLS2.

[0090] With this configuration, during period T11, the potential of wiring VLS1b is supplied to wiring OL via transistor M18. This makes it possible to speed up the fall time of the potential of wiring OL.

[0091] Furthermore, by providing transistor M18, the fall time of the potential of wiring OL can be accelerated, so for example, in amplifier 102, the current flowing through transistor M14, which functions as a constant current source, can be reduced. As a result, in amplifier 102, the current that flows steadily from wiring VLD2 through transistors M13 and M14 to wiring VLS2 can be reduced. Thus, power consumption can be reduced.

[0092] [Modification 6] Figure 5B is a circuit diagram illustrating a modified version of the semiconductor device 100 shown in Figure 1A. The semiconductor device 100 shown in Figure 5B differs from the semiconductor device 100 shown in Figure 1A in that it has a transistor M18 and does not have a transistor M14 in the amplifier 102. In this case, one of the sources or drains of transistor M18 is connected to wiring OL. The other of the sources or drains of transistor M18 is connected to wiring VLS1b. The gate of transistor M18 is connected to the gate of transistor M12.

[0093] The semiconductor device 100 shown in Figure 5B can be described as having the same configuration as the semiconductor device 100 shown in Figure 5A, but without the transistor M14. Therefore, the current that flows steadily through the amplifier 102 can be eliminated. Thus, power consumption can be reduced.

[0094] [Modification 7] Figure 6A is a circuit diagram illustrating a modified version of the semiconductor device 100 shown in Figure 1A. The semiconductor device 100 shown in Figure 6A differs from the semiconductor device 100 shown in Figure 1A in terms of the configuration of the filter 101. Here, the filter 101 includes a transistor M11, P (where P is an integer of 2 or more) capacitive elements C11 (capacitive elements C11_1 to C11_P), and P transistors MS11 (transistors MS11_1 to MS11_P).

[0095] One source or drain of transistor MS11_p (where p is an integer between 1 and P) is connected to one source or drain of transistor M11, one source or drain of transistor M12, and the gate (not shown) of transistor M13. The other source or drain of transistor MS11_p is connected to one terminal of capacitive element C11_p. The other terminal of capacitive element C11_p is connected to wiring VLC.

[0096] Each gate of transistors MS11_1 through MS11_P is connected to a different wire. As a result, each gate of transistors MS11_1 through MS11_P is supplied with an independent signal. Therefore, the on or off state of each transistor MS11_1 through MS11_P can be selected individually.

[0097] With this configuration, the time constant of the filter 101, which is calculated as "on-resistance of transistor M11 × capacitance of capacitance element C11", can be adjusted by selecting at least one of the capacitance elements C11_1 to C11_P, and the combined capacitance of the selected capacitance elements can be used as the capacitance of capacitance element C11. Therefore, the time constant of the filter 101 can be varied. This makes it possible to vary the period of the sawtooth wave generated by the semiconductor device 100. Thus, for example, the refresh rate can be varied in a display device using the semiconductor device 100.

[0098] Although not shown in the diagram, the other terminal of the capacitive element C11_p may be connected to either the source or drain of transistor M11, either the source or drain of transistor M12, and the gate of transistor M13, while either the source or drain of transistor MS11_p may be connected to wiring VLC.

[0099] [Modification 8] Figure 6B is a circuit diagram illustrating a modified version of the semiconductor device 100 shown in Figure 1A. The semiconductor device 100 shown in Figure 6B differs from the semiconductor device 100 shown in Figure 1A in terms of the configuration of the filter 101. Here, the filter 101 has Q transistors M11 (transistors M11_1 to M11_Q) (where Q is an integer of 2 or more) and a capacitive element C11.

[0100] One of the sources or drains of transistor M11_q (where q is an integer between 1 and Q) is connected to one terminal of capacitive element C11, one of the sources or drains of transistor M12, and the gate (not shown) of transistor M13. The other of the sources or drains of transistor M11_q is connected to one of the sources or drains of transistor M15.

[0101] Each gate of transistors M11_1 through M11_Q is connected to a different wiring. As a result, each gate of transistors M11_1 through M11_Q is supplied with an independent signal. Therefore, the on or off state of each transistor M11_1 through M11_Q can be selected individually.

[0102] With this configuration, the time constant of the filter 101 is calculated as "on-resistance of transistor M11 × capacitance of capacitive element C11". At least one of transistors M11_1 to M11_Q can be selected, and the combined resistance of the on-resistances of the selected transistors can be used as the on-resistance of transistor M11. Therefore, the time constant of the filter 101 can be varied. This makes it possible to vary the period of the sawtooth wave generated by the semiconductor device 100. Thus, for example, the refresh rate can be varied in a display device using the semiconductor device 100.

[0103] [Modification 9] Figure 7A is a circuit diagram illustrating a modified version of the semiconductor device 100 shown in Figure 1A. The semiconductor device 100 shown in Figure 7A differs from the semiconductor device 100 shown in Figure 1A in that, in the filter 101, transistor M11a is replaced with transistor M11a and transistor M11b. In this case, one source or drain of transistor M11a is connected to one source or drain of transistor M12, the gate of transistor M13, and one terminal of capacitive element C11. The other source or drain of transistor M11a is connected to one source or drain of transistor M11b. The other source or drain of transistor M11b is connected to one source or drain of transistor M15. The gates of transistor M11a and transistor M11b are each connected to wiring VLB1.

[0104] The semiconductor device 100 shown in Figure 7A can also be described as having a configuration in which transistors M11a and M11b are connected in series instead of transistor M11. Alternatively, a configuration with three or more transistors connected in series may be used instead of transistor M11. By using this configuration in which multiple transistors are connected in series, the channel length can be substantially increased. Therefore, the on-resistance of transistor M11 can be increased in the "on-resistance of transistor M11 × capacitance of capacitive element C11" which corresponds to the time constant of the filter 101.

[0105] When the semiconductor device 100 is used as a display device, the area in which each component of the semiconductor device 100 can be laid out may be limited by the size of the pixels of the display device. In this case, by configuring the transistor M11 as a series of multiple transistors connected in series, the channel length of each transistor can be reduced. Therefore, it may be possible to efficiently lay out the transistor M11 within the area limited by the size of the pixels.

[0106] [Modification 10] Figure 7B is a circuit diagram illustrating a modified version of the semiconductor device 100 shown in Figure 1A. In the filter 101 of the semiconductor device 100 shown in Figure 7B, transistor M11 has a back gate. The back gate of transistor M11 is connected to wiring BGL.

[0107] Transistor M11 can change its threshold voltage depending on the potential applied to its back gate. For example, by decreasing the potential applied to the back gate, the threshold voltage of transistor M11 can be increased. By increasing the threshold voltage of transistor M11, the on-resistance of transistor M11 can be effectively increased. Therefore, the "on-resistance of transistor M11 × capacitance of capacitive element C11," which corresponds to the time constant of filter 101, can be increased.

[0108] This configuration allows the time constant of the filter 101 to be made sufficiently large relative to the length of the period T12. In this case, the channel length of the transistor M11 can be reduced. Also, the area of ​​the capacitive element C11 can be reduced. As a result, the layout area of ​​the semiconductor device 100 can be reduced, and the bezel width of the display device can be reduced.

[0109] The wiring BGL may be given a constant potential, or it may be given different potentials in period T11 and period T12. For example, the potential given to the wiring BGL in period T11 may be greater than the potential given to the wiring BGL in period T12. Also, for example, the back gate of transistor M11 may be connected to wiring VLS1, wiring VLS2, or wiring VLB2. By making the potential given to the wiring BGL in period T11 greater than the potential given to the wiring BGL in period T12, the on-resistance of transistor M11 can be increased in period T12 while the on-current of transistor M11 can be increased in period T11. Therefore, in period T11, the fall time of the potential of node ND13 can be accelerated, and the time required for initialization can be shortened.

[0110] [Modification 11] Figure 8A is a circuit diagram illustrating a modified version of the semiconductor device 100 shown in Figure 1A. The semiconductor device 100 shown in Figure 8A differs from the semiconductor device 100 shown in Figure 1A in the connection of transistor M11 in the filter 101. Here, the gate of transistor M11 is connected to the other side of the source or drain of transistor M11 (corresponding to node ND13).

[0111] Although not shown in the diagram, the gate of transistor M11 may be connected to either the source or the drain of transistor M11 (corresponding to node ND14).

[0112] The configuration in which the gate of transistor M11 is connected to node ND13 is applicable when the potential of node ND14 is gradually increased during period T12. On the other hand, the configuration in which the gate of transistor M11 is connected to node ND14 is applicable when the potential of node ND14 is gradually decreased during period T12.

[0113] This configuration eliminates the need for wiring VLB1, thus reducing the layout area. Consequently, the bezel width of the display device can be reduced.

[0114] [Modification 12] Figure 8B is a circuit diagram illustrating a modified version of the semiconductor device 100 shown in Figure 1A. The semiconductor device 100 shown in Figure 8B differs from the semiconductor device 100 shown in Figure 1A in that the filter 101 has a transistor MC11 instead of a capacitive element C11. In this case, the gate of transistor MC11 is connected to either the source or the drain of transistor M11. One of the sources or drains of transistor MC11 and the other of the sources or drains of transistor MC11 are each connected to wiring VLC. In this case, wiring VLC is given a potential smaller than, for example, wiring VLS1.

[0115] With this configuration, a channel is formed in the channel formation region of transistor MC11 during period T12, so that the gate capacitance of transistor MC11 can function as a capacitive element instead of the capacitive element C11.

[0116] Here, in order to increase the "on-resistance of transistor M11 × capacitance of capacitive element C11" which corresponds to the time constant of filter 101, it is preferable to increase the capacitance of capacitive element C11. To increase the capacitance of capacitive element C11, for example, the area of ​​capacitive element C11 can be increased. Alternatively, in order to increase the capacitance while suppressing the increase in the area of ​​capacitive element C11, for example, a conductive layer can be added to reduce the thickness of the dielectric film, or a dielectric with a high relative permittivity can be used. On the other hand, these increase process costs. Therefore, the gate capacitance of transistor MC11 may be used as the capacitive element instead of capacitive element C11. As a result, the gate insulating film of transistor MC11 functions as the dielectric of the capacitive element, making it easier to increase the capacitance per unit area. This makes it possible to reduce the layout area of ​​semiconductor device 100. Thus, the bezel width of the display device can be reduced.

[0117] Although not shown in the diagram, one source or drain of transistor MC11 and the other source or drain of transistor MC11 may be connected to one source or drain of transistor M11, and the gate of transistor MC11 may be connected to wiring VLC. In this case, wiring VLC is given a potential greater than, for example, wiring VLS1, wiring VLB1, or wiring VLD1.

[0118] [Modification 13] Figure 9A is a circuit diagram illustrating a modified version of the semiconductor device 100 shown in Figure 1A. The semiconductor device 100 shown in Figure 9A differs from the semiconductor device 100 shown in Figure 1A in that the filter 101 has a resistor R11 instead of a transistor M11. In this case, one terminal of the resistor R11 (sometimes called one of a pair of terminals, the first terminal, etc.) is connected to one of the source or drain of the transistor M12, the gate of the transistor M13, and one terminal of the capacitive element C11. The other terminal of the resistor R11 (sometimes called the other of a pair of terminals, the second terminal, etc.) is connected to one of the source or drain of the transistor M15.

[0119] In this case, the time constant of the filter 101 is "electrical resistance of the resistive element R11 × capacitance of the capacitive element C11".

[0120] Furthermore, various types of resistive elements can be used as the resistive element R11. For example, a resistive element containing silicon (such as a diffusion resistor or polysilicon resistor) can be used. Alternatively, a resistive element containing a conductive material (such as a wiring resistor) can be used. In particular, a conductive material with high resistivity (also known as low conductivity) can be used. Alternatively, a resistive element containing a metal oxide may be used. The metal oxide may contain, for example, indium oxide.

[0121] [Modification 14] Figure 9B is a circuit diagram illustrating a modified version of the semiconductor device 100 shown in Figure 1A. The semiconductor device 100 shown in Figure 9B differs from the semiconductor device 100 shown in Figure 1A in that it has a switch S12 instead of transistor M12 and a switch S15 instead of transistor M15.

[0122] Thus, one aspect of the present invention may have a configuration in which at least a portion of the transistors constituting the semiconductor device 100 are replaced with other elements that function as switches.

[0123] Furthermore, one aspect of the present invention includes a configuration in which at least one of the gate, source, and drain of one or more transistors is either not connected to anything or connected to any wiring. Also, one aspect of the present invention includes a configuration in which one or more wirings are either not input to anything or are input to any signal or potential.

[0124] Furthermore, two or more of the modified examples described above, whether illustrated or not illustrated, can be applied to the semiconductor device 100 shown in Figure 1A. In addition, the semiconductor device 100 described above, whether illustrated or not illustrated, can solve the problem of providing at least a novel semiconductor device simply by its circuit configuration.

[0125] Furthermore, one aspect of the present invention is all or part of the circuit configuration described herein. Therefore, one aspect of the present invention does not have to include all or part of the operations described herein. Moreover, one aspect of the present invention is not limited to the operations described herein, and it is possible to appropriately change the potential applied to each wire, the timing of the change in that potential, etc.

[0126] <Example of Drive Circuit Configuration> Next, a drive circuit according to one aspect of the present invention will be described with reference to the drawings. At least a part of the semiconductor device according to one aspect of the present invention can be used in this drive circuit. Furthermore, this drive circuit can be used in a display device. In particular, it can be used in a gate driver of a display device.

[0127] Figure 10A is a circuit diagram illustrating an example configuration of a drive circuit having the semiconductor device described above.

[0128] As shown in Figure 10A, the drive circuit 110 includes a register 111 and a semiconductor device 100.

[0129] Figure 10A illustrates a configuration of semiconductor device 100 that combines the semiconductor device 100 shown in Figure 4A, the semiconductor device 100 shown in Figure 4B, and the semiconductor device 100 shown in Figure 5A, as an example of a semiconductor device 100. Furthermore, the other source or drain of transistor M17, the other source or drain of transistor M18, and the other terminal of capacitive element C11 are each connected to VLS1 as an example. Also, the gate of transistor M16 is connected to VLD1 as an example.

[0130] Furthermore, the semiconductor device 100 of the drive circuit 110 is not limited to the configuration shown in Figure 10A, but can be configured in various ways as described above.

[0131] Register 111 has the function of providing nodes ND11 and ND12 with signals whose logic is inverted relative to each other. Various configurations can be applied to register 111.

[0132] Figure 10B is a circuit diagram illustrating a specific configuration example of register 111.

[0133] As shown in Figure 10B, the register 111 includes, for example, transistors M21, M22, M23, M24, M25, and M26. The register 111 may also include at least one of transistor M27 and a capacitive element C21.

[0134] One source or drain of transistor M21 is connected to one source or drain of transistor M23, one source or drain of transistor M27, and node ND12 in semiconductor device 100. One source or drain of transistor M22 is connected to the gate of transistor M23, one source or drain of transistor M24, the gate of transistor M26, and node ND11 in semiconductor device 100. The other source or drain of transistor M27 is connected to the gate of transistor M25 and one terminal of capacitive element C21. One source or drain of transistor M25 is connected to one source or drain of transistor M26, the other terminal of capacitive element C21, and wiring SRL. The gates of transistor M21 and transistor M24 are each connected to wiring IL1. The gate of transistor M22 is connected to wiring IL2. The other source or drain of transistor M25 is connected to wiring CKL. The other source or drain of transistor M21, the other source or drain of transistor M22, and the gate of transistor M27 are each connected to wiring VLD3. The other source or drain of transistor M23, the other source or drain of transistor M24, and the other source or drain of transistor M26 are each connected to wiring VLS3.

[0135] In the register 111 shown in Figure 10B, the presence of transistor M27 and capacitive element C21 creates a bootstrap effect due to capacitive coupling of the capacitive element C21 when outputting a signal from wiring CKL to wiring SRL. This maintains the gate voltage of transistor M25 (which here corresponds to the potential difference between the gate and either the source or drain (corresponding to wiring SRL) as the reference). Therefore, the threshold voltage of transistor M25 suppresses a drop in the signal potential output to wiring SRL, and also speeds up the rise and fall times of the signal.

[0136] Note that register 111 does not necessarily have to have at least one of transistor M27 and capacitive element C21.

[0137] If register 111 does not have transistor M27, the gate of transistor M25 and one terminal of capacitive element C21 are connected to node ND12. This allows the capacitive element C21 to generate a bootstrap effect when transistors M21 and M23 are both in the off state. By omitting transistor M27 from register 111, the layout area of ​​register 111 can be reduced, thereby reducing the bezel width of the display device. On the other hand, if register 111 has transistor M27, when the potential of node ND12 rises due to the bootstrap effect, the voltage applied between the terminals of transistors M21 and M23 connected to node ND12 can be reduced. Therefore, transistor failure and degradation can be suppressed, and the reliability of the display device can be improved.

[0138] Furthermore, if the register 111 does not have a capacitive element C21, a bootstrap effect can be generated by the parasitic capacitance between the gate of transistor M25 and either the source or the drain. By omitting the capacitive element C21 from the register 111, the layout area of ​​the register 111 can be reduced, thereby reducing the bezel width of the display device. On the other hand, by having the capacitive element C21 in the register 111, the bootstrap effect can be enhanced. Therefore, the effect of suppressing a drop in the potential of the signal output to the wiring SRL and speeding up the rise and fall times of the signal can be enhanced.

[0139] Multiple drive circuits 110 can be applied, for example, to a shift register in a gate driver. In this case, one drive circuit 110 is provided for each stage of the shift register. At this time, the wiring IL1 of a register 111 provided in a certain stage is connected to the wiring SRL of a register 111 provided in the previous stage, or two or more stages prior. The wiring IL1 of a register 111 provided in the first stage is connected to the wiring to which a trigger signal (also called a start pulse signal) that starts the operation of the shift register is supplied. In addition, the wiring IL2 of a register 111 provided in a certain stage is connected to the wiring SRL of a register 111 provided in the next stage, or two or more stages prior.

[0140] Furthermore, a clock signal is supplied to the wiring CKL. At this time, the wiring CKL of a register 111 located in a certain stage is supplied with a clock signal that has a different phase from the clock signal supplied to the wiring CKL of a register 111 located in, for example, the stage immediately preceding or following it.

[0141] Furthermore, a constant potential is supplied to each of the wiring VLS3 and VLD3, for example. Note that the same potential as wiring VLS1 may be supplied to wiring VLS3, or a different potential (for example, a potential lower than wiring VLS1). Also, wiring VLS3 may be connected to wiring VLS1. The same potential as wiring VLD3 may be supplied to wiring VLD1, or a different potential (for example, a potential lower than wiring VLD1). Also, wiring VLD3 may be connected to wiring VLD1.

[0142] With this configuration, a shift register having multiple drive circuits 110 can sequentially output signals to the wiring SRL of each register 111 based on the clock signal. Therefore, in a shift register having multiple drive circuits 110, sawtooth waves are sequentially generated in each semiconductor device 100 and output to their respective wiring OLs.

[0143] Furthermore, as a drive circuit according to one aspect of the present invention, it is possible to apply various configurations using the semiconductor device 100, not limited to the drive circuit 110 described above.

[0144] <Example of Display Device Configuration> Next, a display device according to one aspect of the present invention will be described with reference to the drawings. At least a part of the semiconductor device according to one aspect of the present invention can be used in the display device. Furthermore, at least a part of the drive circuit according to one aspect of the present invention can be used in the display device.

[0145] Figure 11A is a block diagram illustrating an example of the configuration of a display device 160 according to one embodiment of the present invention.

[0146] As shown in Figure 11A, the display device 160 includes a pixel unit 162, a gate driver unit 163, a source driver unit 164, and a control unit 167. The pixel unit 162 has, for example, a plurality of pixels 161 arranged in a matrix of m rows and n columns (where m is an integer of 2 or more, and n is an integer of 2 or more).

[0147] Each pixel 161 has a display element such as a liquid crystal element or a light-emitting element. In this case, the display device 160 can also be said to have the function of an output device. Furthermore, each pixel 161 may have a light-receiving element. In this case, the display device 160 can also be said to have the function of an imaging device (sometimes called an input device). Also, each pixel 161 may have both a display element and a light-receiving element. In this case, the display device 160 can also be said to have the function of both a display device and an imaging device (sometimes called an input / output device).

[0148] In Figure 11A, the pixel 161 located in the first row and first column is shown as pixel 161[1,1], the pixel 161 located in the first row and nth column is shown as pixel 161[1,n], the pixel 161 located in the m row and first column is shown as pixel 161[m,1], and the pixel 161 located in the m row and nth column is shown as pixel 161[m,n]. In some cases, the pixel 161 located in the u row and v column (where u is an integer between 1 and m, and v is an integer between 1 and n) is shown as pixel 161[u,v]. When describing matters common to multiple pixels 161, they may not be described with identification codes such as "[u,v]".

[0149] Furthermore, the display device 160 has m gate lines 165, each arranged in parallel, and whose potential is controlled by a circuit included in the gate driver unit 163. The potential of one gate line 165 is supplied to n pixels 161 arranged in the row direction. Depending on the configuration of the pixels 161, a configuration in which multiple wires are included per gate line 165 is also possible.

[0150] Furthermore, the display device 160 has n source lines 166, each arranged in parallel, and whose potential is controlled by a circuit included in the source driver unit 164. The potential of one source line 166 is supplied to m pixels 161 arranged in the column direction. Depending on the configuration of the pixels 161, each source line 166 may be configured to include multiple wires.

[0151] The circuit included in the gate driver unit 163 functions, for example, as a scan line drive circuit (sometimes called a gate line drive circuit, gate driver, scan driver, or low driver).

[0152] The circuit included in the source driver unit 164 functions, for example, as a signal line drive circuit (sometimes called a source line drive circuit, source driver, data driver, or column driver).

[0153] One of the circuits included in the control unit 167 functions, for example, as a power supply circuit. Another circuit included in the control unit 167 functions, for example, as a signal generation circuit.

[0154] The display device 160 does not necessarily have to have one or both of the source driver unit 164 and the control unit 167. For example, one or both of the source driver unit 164 and the control unit 167 may be provided on an IC (Integrated Circuit) chip located outside the display device 160. In this case, a part of the source driver unit 164 and the control unit 167 may be provided on the display device 160.

[0155] Figure 11B is a block diagram illustrating a modified example of the display device 160. The display device 160 shown in Figure 11B differs from the display device 160 shown in Figure 11A in that it has two gate driver units 163 arranged to face each other via a pixel unit 162. In the configuration shown in Figure 11B, the potential of m gate lines 165 is controlled by the two gate driver units 163. With this configuration, for example, the actual wiring load (parasitic capacitance and parasitic resistance) can be reduced to 1 / 4 of the wiring load in the display device 160 shown in Figure 11A. Therefore, at least one of the following can be achieved for the display device 160: higher speed, higher resolution, higher resolution, narrower bezel, and larger screen.

[0156] In one aspect of the present invention, various transistors can be used as the transistors constituting the display device 160. For example, a Si transistor (a transistor containing silicon in its channel formation region) may be used, an OS transistor (a transistor containing oxide semiconductor in its channel formation region) may be used, or both a Si transistor and an OS transistor may be used.

[0157] OS transistors can be freely arranged on a silicon substrate, for example, on which Si transistors are mounted, making integration easy. Furthermore, since OS transistors can be manufactured using the same manufacturing equipment as Si transistors, they can be produced at low cost.

[0158] Therefore, in the display device 160, for example, Si transistors containing part of a silicon substrate may be used for the transistors constituting the source driver unit 164, and OS transistors provided on a silicon substrate may be used for the transistors constituting the gate driver unit 163 and the pixel unit 162, respectively. Furthermore, OS transistors may be used for at least a portion of the transistors constituting the source driver unit 164, and Si transistors may be used for at least a portion of the transistors constituting the gate driver unit 163 and the pixel unit 162, respectively.

[0159] Furthermore, various circuits (which may include arithmetic circuits, memory circuits, etc.) for controlling the operation of the display device 160 may be provided using Si transistors that include a portion of the silicon substrate. Thus, in one aspect of the present invention, for example, an OS transistor is arranged on a silicon substrate on which Si transistors are provided, and a display element or light-receiving element is arranged on the layer on which the OS transistors are provided.

[0160] In one aspect of the present invention, the gate driver unit 163 can use at least a portion of the various semiconductor devices 100 described above and the drive circuits (such as the drive circuit 110) having said semiconductor devices. Furthermore, the control unit 167 can be provided with a power supply circuit that generates a constant potential supplied to each of the wiring VLS1, wiring VLD1, wiring VLB1, wiring VLS2, wiring VLD2, wiring VLB2, wiring VLC, wiring VLS3, and wiring VLD3. Furthermore, the control unit 167 can be provided with a signal generation circuit that generates a signal supplied to wiring CKL, etc.

[0161] [Gate Driver] Figures 12A and 12B are circuit diagrams illustrating an example configuration of a shift register in the gate driver unit 163.

[0162] The shift register of the gate driver unit 163 has at least m drive circuits 110 to drive each row of pixels 161 arranged in an m x n matrix. Figure 12A shows, as a representative, the drive circuit 110[u-1] for row u, the drive circuit 110[u] for row u, and the drive circuit 110[u+1] for row u+1. The semiconductor device 100[u-1] and register 111[u-1] of the drive circuit 110[u], the semiconductor device 100[u] and register 111[u] of the drive circuit 110[u], and the semiconductor device 100[u+1] and register 111[u+1] of the drive circuit 110[u+1] are shown as circuit blocks. Figure 12B shows the semiconductor device 100 and register 111 of the drive circuit 110 as circuit blocks. Furthermore, when describing matters common to each of the m drive circuits 110, m semiconductor devices 100, and m registers 111, etc., the identification code such as "[u]" may be omitted.

[0163] Register 111[u-1] is connected to semiconductor device 100[u-1] via nodes ND11[u-1] and ND12[u-1]. Register 111[u] is connected to semiconductor device 100[u] via nodes ND11[u] and ND12[u]. Register 111[u+1] is connected to semiconductor device 100[u+1] via nodes ND11[u+1] and ND12[u+1].

[0164] The wiring IL1 (wiring IL1[u]) of register 111[u] is connected to the wiring SRL (wiring SRL[u-1]) of register 111[u-1]. The wiring IL2 (wiring IL2[u]) of register 111[u] is connected to the wiring SRL (wiring SRL[u+1]) of register 111[u+1]. The wiring SRL (wiring SRL[u]) of register 111[u] is connected to the wiring IL2 (wiring IL2[u-1]) of register 111[u-1], and to the wiring IL1 (wiring IL1[u+1]) of register 111[u+1].

[0165] The wiring CKL of register 111[u-1] is connected to wiring CKL2. The wiring CKL of register 111[u] is connected to wiring CKL1. The wiring CKL of register 111[u+1] is connected to wiring CKL2.

[0166] Although not shown in the diagram, the wiring OL (wiring OL[u-1]) of semiconductor device 100[u-1] is connected to n pixels 161 (pixels 161[u-1,1] to 161[u-1,n]) located in row u-1. The wiring OL (wiring OL[u]) of semiconductor device 100[u] is connected to n pixels 161 (pixels 161[u,1] to 161[u,n]) located in row u. The wiring OL (wiring OL[u+1]) of semiconductor device 100[u+1] is connected to n pixels 161 (pixels 161[u+1,1] to 161[u+1,n]) located in row u+1.

[0167] Figure 13 is a timing chart illustrating an example of the operation of the shift register shown in Figures 12A and 12B.

[0168] Figure 13 shows the potentials of wiring CKL1 and wiring CKL2. It also shows the potentials of wiring SRL[u-1], wiring SRL[u], and wiring SRL[u+1] as representatives of m wiring SRL. Furthermore, it shows the potentials of node ND11[u-1], node ND11[u], and node ND11[u+1] as representatives of m node ND11. It also shows the potentials of node ND12[u-1], node ND12[u], and node ND12[u+1] as representatives of m node ND12. Finally, it shows the potentials of wiring OL[u-1], wiring OL[u], and wiring OL[u+1] as representatives of m wiring OL.

[0169] Furthermore, Figure 13 shows the periods corresponding to periods T11 and T12 of the timing chart shown in Figure 1B above, respectively, for the sawtooth wave output to wiring [u].

[0170] As shown in Figure 13, clock signals are supplied to wiring CKL1 and wiring CKL2, with each having a phase difference of half the period. Although not shown in the figure, a start pulse signal is supplied to wiring IL1[1] at a constant period (here, the period is Tsr).

[0171] As a result, in the m registers 111, signals are sequentially output to m wirings SRL at half the period of the clock signal. Furthermore, signals are sequentially output to m nodes ND11 and m nodes ND12. At this time, nodes ND11 and ND12 output signals with their logic inverted relative to each other. Therefore, sawtooth waves are sequentially generated in the m semiconductor devices 100 and output to m wirings OL. Figure 13 illustrates the period Tsr, which corresponds to one period of the sawtooth wave.

[0172] [Pixel] An example configuration applicable to pixel 161 will be described.

[0173] Figure 14A is a circuit diagram illustrating an example configuration of a pixel 161 having a light-emitting element LD. As an example, Figure 14A shows a semiconductor device 100[u] provided in the gate driver unit 163 and a pixel 161[u,v] in the u row and v column provided in the pixel unit 162.

[0174] Pixel 161[u,v] is connected to wiring SWPL[u], wiring GLa[u], wiring GLb[u], wiring SLa[v], and wiring SLb[v]. Wiring SWPL[u] in pixel section 162 is connected to wiring OL[u] in gate driver section 163. As a result, pixel 161[u,v] is connected to semiconductor device 100[u] via wiring SWPL[u] and wiring OL[u].

[0175] In addition, pixels 161[u,v] may be simply referred to as pixels 161, wiring SWPL[u] as wiring SWPL, wiring GLa[u] as wiring GLa, wiring GLb[u] as wiring GLb, wiring SLa[v] as wiring SLa, wiring SLb[v] as wiring SLb, semiconductor device 100[u] as semiconductor device 100, and wiring OL[u] as wiring OL.

[0176] Pixel 161, as an example, includes transistor M31, transistor M32, transistor M33, transistor M34, capacitive element C31, and light-emitting element LD.

[0177] A light-emitting element (LD) emits light with an intensity corresponding to the amount of current flowing through it. As the light-emitting element (LD), for example, an electroluminescent element (especially an injection-type electroluminescent element) such as a light-emitting diode (LED) can be used. As the LED, for example, an LED using an inorganic material as the light-emitting substance, or an LED using an organic material as the light-emitting substance (also called an organic EL (Electroluminescence) element or OLED (Organic LED)) can be used. As an LED using an inorganic material as the light-emitting substance, for example, a mini-LED or micro-LED can be used.

[0178] In this specification, a mini-LED refers to an LED with an emitting surface area of ​​10,000 μm². ２ Larger by 1 mm ２ The following refers to the following. Furthermore, a micro-LED is defined as having an emitting surface area of ​​10,000 μm². ２ This refers to the following:

[0179] In the pixel 161 shown in Figure 14A, one terminal of the capacitive element C31 is connected to the wiring SWPL. One of the source or drain of transistor M34 is connected to the wiring VL31. The other terminal of the capacitive element C31 is connected to one of the source or drain of transistor M33 and to the gate of transistor M34. The other source or drain of transistor M34 is connected to the gate of transistor M32 and to one of the source or drain of transistor M31. One of the source or drain of transistor M32 is connected to one terminal (e.g., anode) of the light-emitting element LD. The other source or drain of transistor M31 is connected to the wiring SLa. The gate of transistor M31 is connected to the wiring GLa. The other source or drain of transistor M32 is connected to the wiring ANO. The other source or drain of transistor M33 is connected to the wiring SLb. The gate of transistor M33 is connected to the wiring SLb. The other terminal of the light-emitting element LD (e.g., the cathode) is connected to the wiring CATH.

[0180] Although not shown in the diagram, one of the sources or drains of transistor M32 may be connected to the other terminal (e.g., cathode) of the light-emitting element LD, the other of the sources or drains of transistor M32 may be connected to wiring CATH, and one terminal (e.g., anode) of the light-emitting element LD may be connected to wiring ANO.

[0181] Transistor M31 functions as a switch that controls whether or not to write the image signal Da provided from wiring SLa to the pixel 161. For example, transistor M31 functions as a switch that controls whether or not to supply a potential corresponding to the image signal Da provided from wiring SLa to the gate of transistor M32.

[0182] Transistor M32 is provided in the current path from wiring ANO through the light-emitting element LD to wiring CATH, and has the function of controlling the amount of current supplied to the light-emitting element LD. A potential corresponding to the image signal Da is applied to the gate of transistor M32. Therefore, a gate voltage corresponding to the image signal Da is applied to transistor M32, a drain current based on the gate voltage flows, and this drain current is supplied to the light-emitting element LD.

[0183] Transistor M33 functions as a switch that controls whether or not to write the image signal Db provided from wiring SLb to the pixel 161. For example, transistor M33 functions as a switch that controls whether or not to supply a potential corresponding to the image signal Db provided from wiring SLb to the gate of transistor M34.

[0184] Transistor M34 functions as a switch that controls whether or not the potential of wiring VL31 is supplied to the gate of transistor M32. Wiring VL31 is supplied with a potential that can turn transistor M32 off. Transistor M32 can also be said to have the function of controlling whether or not the light-emitting element LD is de-illuminated. A potential corresponding to the image signal Db is supplied to the gate of transistor M34. Therefore, a gate voltage corresponding to the image signal Db is applied to transistor M34.

[0185] Capacitive element C31 has the function of controlling the gate potential of transistor M34. As described above, the semiconductor device 100 in the gate driver unit 163 can generate a sawtooth wave and output it to the wiring OL. As a result, a sawtooth wave is supplied to the wiring SWPL. Furthermore, a sawtooth wave is supplied to one terminal of capacitive element C31. Therefore, the capacitive coupling of capacitive element C31 makes it possible to gradually raise or lower the gate potential of transistor M34.

[0186] Furthermore, for example, another transistor may be provided between the capacitive element C31 and the wiring SWPL. This allows a sawtooth wave to be applied from the wiring SWPL to one terminal of the capacitive element C31 via the transistor.

[0187] Although not shown in the diagram, one terminal of a capacitive element that has the function of stabilizing the gate voltage of transistor M32 may also be connected to the gate of transistor M32.

[0188] Furthermore, in addition to the above configuration, the pixel 161 may also have a transistor and a capacitive element. This makes it possible to realize a pixel with various functions, such as a function to fix the source potential when applying a potential to the gate of the transistor, a function to correct the threshold voltage variation of the transistor, a function to suppress the effect of the hysteresis characteristics of the transistor, and a function to initialize the voltage applied to the light-emitting element LD.

[0189] An example of the operation of pixel 161 will be explained.

[0190] First, with the potential of wiring SWPL initialized, the image signal Db is written to the gate of transistor M34. At this time, transistor M34 is in the off state. Next, the image signal Da is written to the gate of transistor M32. As a result, a current corresponding to the image signal Da is supplied to the light-emitting element LD, causing the light-emitting element LD to emit light. Next, the potential of wiring SWPL is gradually increased. This causes the potential of the gate of transistor M34 to gradually increase. As a result, the gate voltage of transistor M34 gradually increases. After that, when the gate voltage of transistor M34 exceeds the threshold voltage, transistor M34 turns on. Then, the potential of wiring VL31 is supplied to the gate of transistor M32, causing transistor M32 to turn off, and the light-emitting element LD stops emitting light.

[0191] Here, the light emission intensity of the light-emitting element (LD) is controlled by the image signal Da. This type of control can be called pulse amplitude modulation (PAM) control. Furthermore, the light emission time from when the light-emitting element (LD) emits light until it stops emitting light is controlled by the image signal Db. This type of control can be called PWM control.

[0192] Therefore, in a display device 160 having pixels 161, the light emission intensity of the light-emitting element LD can be controlled by combining PAM control and PWM control. This makes it possible to improve at least one of the following: improved gradation expression and improved dynamic range.

[0193] As a method of controlling the light emission intensity of a light-emitting element (LD) by combining PWM control and PAM control, for example, if the light emission intensity of the light-emitting element (LD) is low, PAM control can be performed, and if the light emission intensity of the light-emitting element (LD) is high, PWM control can be performed. Alternatively, for example, if the light emission intensity of the light-emitting element (LD) is low, PAM control can be performed, and if the light emission intensity of the light-emitting element (LD) is high, PWM control and PAM control can be combined. Alternatively, for example, if the light emission intensity of the light-emitting element (LD) is low, PAM control can be performed, if the light emission intensity of the light-emitting element (LD) is medium, PWM control can be performed, and if the light emission intensity of the light-emitting element (LD) is high, PAM control can be performed. Alternatively, for example, if the light emission intensity of the light-emitting element (LD) is low, PAM control can be performed, if the light emission intensity of the light-emitting element (LD) is medium, PWM control and PAM control can be combined, and if the light emission intensity of the light-emitting element (LD) is high, PAM control can be performed. Note that PWM control alone may be performed without PAM control.

[0194] Furthermore, when using micro-LEDs or similar devices as light-emitting diodes (LDs), PWM control can be used to stabilize the emission wavelength of the LDs, thereby improving display quality.

[0195] Figure 14B is a circuit diagram illustrating a modified version of the pixel 161 shown in Figure 14A. In the pixel 161 shown in Figure 14B, one terminal of the capacitive element C31 is connected to the wiring VL31. One of the sources or drains of the transistor M34 is connected to the wiring SWPL.

[0196] In this case, as an example of the operation of pixel 161, first, with the potential of the wiring SWPL initialized, the image signal Db is written to the gate of transistor M34. At this time, transistor M34 is in the off state. Next, the image signal Da is written to the gate of transistor M32. As a result, a current corresponding to the image signal Da is supplied to the light-emitting element LD, and the light-emitting element LD emits light. Next, the potential of the wiring SWPL is gradually decreased. Then, the potential of either the source or drain of transistor M34 gradually decreases. As a result, the gate voltage of transistor M34 gradually increases. After that, when the gate voltage of transistor M34 exceeds the threshold voltage, transistor M34 turns on. Then, the potential of the wiring SWPL is supplied to the gate of transistor M32, transistor M32 turns off, and the light-emitting element LD stops emitting light.

[0197] Furthermore, the pixel configuration applicable to the display device 160 is not limited to the pixel 161 described above. Various configurations that use sawtooth waves or triangular waves for PWM control can be applied to the pixels of the display device 160.

[0198] [Transistors] In one aspect of the present invention, n-channel transistors can be used as transistors constituting the display device 160. Furthermore, p-channel transistors may be used as at least a portion of the transistors constituting the display device 160.

[0199] Furthermore, as transistors constituting the display device 160, for example, transistors containing a single-crystal semiconductor, polycrystalline semiconductor, microcrystalline semiconductor, or amorphous semiconductor in the channel formation region can be used. In addition, the semiconductor is not limited to a single-element semiconductor whose main component is a single element (such as silicon or germanium), but can also be a compound semiconductor (such as silicon germanium or gallium arsenide), or an oxide semiconductor.

[0200] For example, as the transistors constituting the display device 160, a transistor containing silicon in the channel formation region (Si transistor) may be used, a transistor containing oxide semiconductor in the channel formation region (OS transistor) may be used, or both Si transistors and OS transistors may be used.

[0201] Furthermore, various types of transistors can be used as the transistors that make up the display device 160. For example, MOS field-effect transistors, junction field-effect transistors, or bipolar transistors can be used.

[0202] Furthermore, transistors of various structures can be used as the transistors constituting the display device 160. For example, transistors of various structures can be used, such as top-gate type (planar type, staggered type, etc.), bottom-gate type (inverse planar type, inverse staggered type, etc.), dual-gate type (a structure in which gates are arranged on both sides (e.g., top and bottom) of the channel formation region), FIN type, TRI-GATE type, or GAA type (gate all-around type). In addition, for example, vertical transistors (transistors in which the channel length direction has a component in the vertical direction (also called the height direction or the direction perpendicular to the surface to which it is formed)) can be used.

[0203] In the pixels 161 shown in Figures 14A and 14B, it is preferable to use transistors with low off-currents for transistors M31, M33, and M34, respectively. For example, OS transistors can be used as transistors with low off-currents. This allows the image signals Da and Db written to the pixels 161 to be retained for a long period of time. Therefore, for example, the display device 160 can be operated at a low refresh rate, and power consumption can be reduced.

[0204] Furthermore, in the pixels 161 shown in Figures 14A and 14B, it is preferable to use a transistor with a small hysteresis width for the transistor M32. For example, an OS transistor can be used as a transistor with a small hysteresis width. This can improve the display quality of the display device 160. In addition, the pixel 161 may not need to have a function to suppress the effects of the hysteresis characteristics of the transistor, and the configuration of the pixel 161 can be simplified. This can reduce the layout area of ​​the pixel 161 and improve the resolution of the display device 160.

[0205] Furthermore, the contents of this embodiment can be combined as appropriate. Also, the contents of this embodiment can be combined as appropriate with the contents of other embodiments, etc.

[0206] (Embodiment 2) This embodiment describes a transistor according to one aspect of the present invention. At least a part of the transistor shown in this embodiment can be applied to the semiconductor device shown in Embodiment 1 described above, a drive circuit having said semiconductor device, and a display device, etc.

[0207] <Transistor Configuration Example 1> Figure 15A is a top view of a semiconductor device having a transistor 200A. Figure 15B is a cross-sectional view between A1 and A2, shown by a dashed line in Figure 15A. Figure 15C is a cross-sectional view between A3 and A4, shown by a dashed line in Figure 15A. Note that some elements have been omitted from the top view of Figure 15A for clarity. Some elements may also be omitted in other top views.

[0208] In the semiconductor device shown in Figures 15A to 15C, an insulating layer 202 is provided on a substrate 201, and a semiconductor layer 203 is provided on the insulating layer 202. Furthermore, an insulating layer 204 is provided on the insulating layer 202 and the semiconductor layer 203. In addition, a conductive layer 205 is provided on the insulating layer 204. In this case, the semiconductor layer 203 and the conductive layer 205 are provided such that they have overlapping regions with respect to the insulating layer 204.

[0209] The semiconductor layer 203 has a region 203a that functions as either the source region or the drain region of the transistor 200A, a channel-forming region 203c, and a region 203b that functions as the other of the source region or the drain region. In the semiconductor layer 203, the region that overlaps with the conductive layer 205 functions as the channel-forming region 203c. Therefore, the region of the conductive layer 205 that overlaps with the channel-forming region 203c functions as the gate electrode of the transistor 200A. Also, the region of the insulating layer 204 that overlaps with the channel-forming region 203c functions as the gate insulating film of the transistor 200A.

[0210] Furthermore, in the semiconductor layer 203, the shortest distance between region 203a and region 203b in the channel formation region 203c can be set to the channel length Lch of the transistor 200A (see Figures 15A and 15B). Also, in the semiconductor layer 203, the length of the portion where region 203a and region 203b face each other in the channel formation region 203c can be set to the channel width Wch of the transistor 200A (see Figures 15A and 15C).

[0211] Furthermore, in the semiconductor device shown in Figures 15A to 15C, an insulating layer 206 is provided on top of the insulating layer 204 and the conductive layer 205. In addition, an opening 207a is provided in the insulating layer 204 and the insulating layer 206 in the region overlapping with region 203a of the semiconductor layer 203. In addition, an opening 207b is provided in the insulating layer 204 and the insulating layer 206 in the region overlapping with region 203b of the semiconductor layer 203. Furthermore, a conductive layer 208a is provided on top of the insulating layer 206 and within the opening 207a, and a conductive layer 208b is provided on top of the insulating layer 206 and within the opening 207b. Furthermore, an insulating layer 209 is provided on top of the insulating layer 206 and the conductive layer 208 (conductive layer 208a and conductive layer 208b).

[0212] The conductive layer 208a is in contact with region 203a of the semiconductor layer 203 at the bottom of the opening 207a. Similarly, the conductive layer 208b is in contact with region 203b of the semiconductor layer 203 at the bottom of the opening 207b. Therefore, the conductive layer 208a functions as either the source electrode or the drain electrode of the transistor 200A, and the conductive layer 208b functions as either the source electrode or the drain electrode of the transistor 200A.

[0213] <Transistor Configuration Example 2> Figure 16A is a top view of a semiconductor device having transistor 200B. The semiconductor device having transistor 200B is a modified version of the semiconductor device having transistor 200A described above. To reduce repetition in the explanation, we will mainly explain the differences between the semiconductor device having transistor 200B and the semiconductor device having transistor 200A.

[0214] Figure 16B is a cross-sectional view between A1 and A2, shown by the dashed line in Figure 16A. Figure 16C is a cross-sectional view between A3 and A4, shown by the dashed line in Figure 16A.

[0215] The semiconductor device shown in Figures 16A to 16C differs from the semiconductor device shown in Figures 15A to 15C in that it has a conductive layer 215 between the substrate 201 and the insulating layer 202. The conductive layer 215 overlaps with the channel formation region 203c via the insulating layer 202. Therefore, the region of the insulating layer 202 that overlaps with the channel formation region 203c functions as the back gate insulating film of the transistor 200B, and the region of the conductive layer 215 that overlaps with the channel formation region 203c functions as the back gate electrode of the transistor 200B.

[0216] The insulating layer 202 may have different film thicknesses in the region overlapping with the conductive layer 215 and the region not overlapping with it, or it may have a uniform film thickness. The conductive layer 215 may also extend beyond the edge of the channel-forming region 203c. Although not shown in the figures, an insulating layer may be provided between the substrate 201 and the conductive layer 215.

[0217] In a transistor with a back gate, the transistor's gate and back gate are positioned so as to sandwich the channel formation region of the semiconductor layer. The back gate can function similarly to the gate. When the gate is used to control the on and off states of the transistor, the potential of the back gate can be the same as that of the gate. Alternatively, it can be set to any potential.

[0218] For example, when turning on a transistor, supplying the potential that turns the transistor on to both the gate and the back gate can increase the on-current compared to supplying it to only one. For example, by connecting the gate and the back gate, it is possible to keep the gate and back gate at the same potential at all times. Furthermore, by controlling the potential of the back gate independently of the gate potential, the threshold voltage of the transistor can be adjusted. For example, supplying the potential that turns the transistor on to the back gate can decrease the threshold voltage of the transistor, and supplying the potential that turns the transistor off to the back gate can increase the threshold voltage of the transistor.

[0219] Furthermore, a constant potential, such as ground potential, may be supplied to the back gate. Since the gate and back gate are formed by conductive layers, sandwiching the channel formation region of the semiconductor layer between the gate and back gate makes it difficult for electric fields generated outside the transistor to act on the channel formation region (also known as the "electric field shielding effect"). For this reason, providing a back gate to a transistor stabilizes its operation. In addition, providing a back gate to a transistor reduces the variation in characteristics between multiple transistors. Providing a back gate to a transistor can improve the reliability of the transistor. Therefore, the reliability of the semiconductor device containing the transistor can be improved. Note that the electric field shielding effect can be obtained even if one or both of the gate and back gate are electrically floating (also known as the "floating state"), but the effect can be enhanced by supplying potential to the gate and back gate.

[0220] <Transistor Components> Next, we will describe the components that can be used in transistor 200 (transistor 200A and transistor 200B).

[0221] [Substrate] When a transistor is mounted on a substrate, there are no major restrictions on the material used for the substrate. The material used for the substrate can be determined by considering factors such as whether or not it is translucent and whether it has sufficient heat resistance to withstand heat treatment, depending on the purpose. For example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used as the substrate. As an insulating substrate, for example, glass substrates such as barium borosilicate glass or aluminoborsilicate glass, ceramic substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates) can be used. In addition, semiconductor substrates, flexible substrates, resin substrates, etc. may be used as the substrate.

[0222] Examples of semiconductor substrates include semiconductor substrates made from silicon or germanium, or compound semiconductor substrates made from silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there are semiconductor substrates having insulating regions within the above-mentioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates. In addition, the semiconductor substrate may be a single-crystal semiconductor or a polycrystalline semiconductor.

[0223] Conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. There are also substrates containing metal nitrides and metal oxides. Furthermore, there are substrates with a conductive or semiconductor layer on an insulating substrate, substrates with a conductive or insulating layer on a semiconductor substrate, and substrates with a semiconductor or insulating layer on a conductive substrate.

[0224] Examples of materials that can be used for flexible substrates, resin substrates, etc. include polyesters such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile, acrylic resin, polyimide, polymethyl methacrylate, polycarbonate (PC), polyethersulfone (PES), polyamide (nylon, aramid, etc.), polysiloxane, cycloolefin resin, polystyrene, polyamide-imide, polyurethane, polyvinyl chloride, polyvinylidene chloride, polypropylene, polytetrafluoroethylene (PTFE), ABS resin, cellulose nanofiber, and the like.

[0225] By using the above material as a substrate, a lightweight semiconductor device can be provided. Furthermore, by using the above material as a substrate, a semiconductor device that is resistant to impact can be provided. Furthermore, by using the above material as a substrate, a semiconductor device that is less prone to damage can be provided. In addition, devices on which elements are provided on these substrates may also be used. Elements provided on the substrate include capacitive elements, resistive elements, switch elements, light-emitting elements, and memory elements.

[0226] [Insulating Layer] An inorganic insulating film can be used for the insulating layer (insulating layer 202, insulating layer 204, insulating layer 206, insulating layer 209, etc.). Examples of inorganic insulating films include oxide insulating films, nitride insulating films, oxidative nitride insulating films, and nitride oxide insulating films. Examples of oxide insulating films include silicon oxide film, aluminum oxide film, magnesium oxide film, gallium oxide film, germanium oxide film, yttrium oxide film, zirconium oxide film, lanthanum oxide film, neodymium oxide film, hafnium oxide film, tantalum oxide film, cerium oxide film, gallium zinc oxide film, and hafnium aluminate film. Examples of nitride insulating films include silicon nitride film and aluminum nitride film. Examples of oxidative nitride insulating films include silicon oxide nitride film, aluminum oxide nitride film, gallium oxide nitride film, yttrium oxide nitride film, and hafnium oxide nitride film. Examples of nitride oxide insulating films include silicon oxide nitride film and aluminum oxide nitride film. In addition, an organic insulating film may be used for the insulating layer of the semiconductor device.

[0227] In this specification, "oxide nitride" refers to a material in which the oxygen content is greater than the nitrogen content, and "nitride oxide" refers to a material in which the nitrogen content is greater than the oxygen content. For example, when "silicon oxynitride" is written, it refers to a material in which the oxygen content is greater than the nitrogen content, and when "silicon nitride oxide" is written, it refers to a material in which the nitrogen content is greater than the oxygen content. The content of each element can be measured using methods such as Rutherford backscattering (RBS).

[0228] For example, as transistors become smaller and more integrated, the thinning of the gate insulating film can lead to problems such as gate leakage current. Therefore, by using a material with a high relative permittivity (high-k) for the insulating layer that functions as the gate insulating film, it becomes possible to lower the gate voltage applied during transistor operation while maintaining the physical film thickness. Furthermore, it becomes possible to thin the equivalent oxide thickness (EOT) of the gate insulating film. Additionally, by using a material with a high relative permittivity for the insulating layer that functions as the dielectric of a capacitive element, the capacitance per unit area can be increased. On the other hand, by using a material with a low relative permittivity for the insulating layer that functions as an interlayer film, parasitic capacitance between wiring can be reduced. Therefore, materials can be selected according to the function of the insulating layer. It should be noted that materials with a low relative permittivity also have high dielectric strength.

[0229] Examples of materials with a high dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium-zirconium oxide, oxides containing aluminum and hafnium, oxides containing aluminum and hafnium, oxides containing silicon and hafnium, oxides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0230] Examples of materials with a low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxide-nitride, and silicon nitride-oxide, as well as resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with a low dielectric constant include, for example, silicon oxide with added fluorine, silicon oxide with added carbon, and silicon oxide with added carbon and nitrogen. Also, for example, silicon oxide with vacancies can be used. These silicon oxides may contain nitrogen.

[0231] [Conductive Layers] For the conductive layers used in the transistor 200 (conductive layer 205, conductive layer 208, conductive layer 215, etc.), it is preferable to use metal elements selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., alloys composed of the above metal elements, or alloys combining the above metal elements. As alloys composed of the above metal elements, nitrides of the alloy or oxides of the alloy may be used. For example, it is preferable to use tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Alternatively, highly conductive semiconductors such as polycrystalline silicon containing impurity elements like phosphorus, or silicides such as nickel silicide, may be used.

[0232] Furthermore, it is preferable to use conductive materials that are resistant to oxidation, conductive materials that have a function to suppress oxygen diffusion, or materials that maintain conductivity even when absorbing oxygen. Examples of such materials include nitrogen-containing conductive materials such as tantalum-containing nitrides, titanium-containing nitrides, molybdenum-containing nitrides, tungsten-containing nitrides, ruthenium-containing nitrides, tantalum and aluminum-containing nitrides, and titanium and aluminum-containing nitrides. Examples of oxygen-containing conductive materials include ruthenium oxide, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel. Examples of materials containing metallic elements such as titanium, tantalum, and ruthenium are also included. Examples of oxygen-containing conductive materials include materials containing tungsten oxide and indium oxide, materials containing titanium oxide and indium oxide, indium tin oxide (also known as ITO), indium tin oxide containing titanium oxide, indium tin oxide containing silicon oxide (also known as ITSO), indium zinc oxide (also known as IZO®), and indium zinc oxide containing tungsten oxide. In this specification, a conductive layer formed using an oxygen-containing conductive material may be referred to as an oxide conductive layer.

[0233] Furthermore, it is preferable to use a conductive material with high conductivity, such as one mainly composed of tungsten, copper, or aluminum.

[0234] Furthermore, multiple conductive layers formed from the above materials may be used in a laminated structure. For example, a laminated structure may be formed by combining a material containing the above-mentioned metal element with a conductive material containing oxygen. Alternatively, a laminated structure may be formed by combining a material containing the above-mentioned metal element with a conductive material containing nitrogen. Alternatively, a laminated structure may be formed by combining a material containing the above-mentioned metal element with a conductive material containing oxygen and a conductive material containing nitrogen.

[0235] For example, in transistor 200A or transistor 200B, when an oxide semiconductor, which is a type of metal oxide, is used for the semiconductor layer 203, a laminated structure combining a material containing the aforementioned metal element and a conductive material containing oxygen may be used for conductive layers that function as gate electrodes, such as conductive layer 205 and conductive layer 215. In this case, the conductive material containing oxygen may be provided on the semiconductor layer 203 side. By providing the conductive material containing oxygen on the semiconductor layer 203 side, oxygen detached from the conductive material is more easily supplied to the channel formation region of the semiconductor layer 203.

[0236] Furthermore, when an oxide semiconductor, which is a type of metal oxide, is used as the semiconductor layer 203, the conductive layer 208 in contact with the semiconductor layer 203 may be made of a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a conductive metal oxide (also called an oxide conductor), or a conductive material that has the function of suppressing oxygen diffusion. Examples of such conductive materials include conductive materials containing nitrogen and conductive materials containing oxygen. This makes it possible to suppress a decrease in the conductivity of the conductive layer 208.

[0237] By using an oxygen-containing conductive material as the conductive layer 208, conductivity can be maintained even if the conductive layer 208 absorbs oxygen. For example, even when an insulating layer containing excess oxygen is used as the insulating layer in contact with the conductive layer 208, the conductive layer 208 can maintain its conductivity. Examples of materials that can be used as the conductive layer 208 include ITO, ITSO, and IZO (registered trademarks).

[0238] [Semiconductor layer] As the semiconductor layer (semiconductor layer 203, etc.), single-crystal semiconductors, polycrystalline semiconductors, microcrystalline semiconductors, or amorphous semiconductors can be used individually or in combination.

[0239] As the semiconductor layer, a semiconductor composed of a single element or a compound semiconductor may be used. Examples of semiconductors composed of single elements include silicon and germanium. Examples of compound semiconductors include gallium arsenide, silicon carbide, and silicon germanium. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. Oxide semiconductors are also a type of compound semiconductor. These semiconductor materials may contain impurities as dopants.

[0240] When silicon is used as a semiconductor layer, examples of silicon that can be used for the semiconductor layer include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. As an example of polycrystalline silicon, low-temperature polysilicon (LTPS) is used.

[0241] For example, in transistor 200A or transistor 200B, if silicon is used for the semiconductor layer 203, it is possible to make the transistor function as an n-type transistor by including phosphorus or arsenic as an n-type dopant in regions 203a and 203b of the semiconductor layer 203. Furthermore, it is possible to make the transistor function as a p-type transistor by including boron as a p-type dopant in regions 203a and 203b of the semiconductor layer 203. Note that if both n-type and p-type dopants are present in regions 203a and 203b of the semiconductor layer 203, the conductivity type with the higher dopant concentration is more likely to manifest.

[0242] Furthermore, a two-dimensional material that functions as a semiconductor may be used as the semiconductor layer. Two-dimensional materials are also called layered materials and are a general term for a group of materials that have a layered crystalline structure. Layered materials have high conductivity within a unit layer (also called high two-dimensional conductivity). By using a material that functions as a semiconductor and has high two-dimensional conductivity as the semiconductor layer, it is possible to provide a transistor with a large on-current.

[0243] Examples of the above layer material include graphene, silicene, chalcogenide, etc. A chalcogenide is a compound containing a chalcogen (an element belonging to Group 16). Examples of chalcogenides also include transition metal chalcogenides and Group 13 chalcogenides. Specifically, examples of transition metal chalcogenides applicable as the semiconductor layer include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten telluride (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ), etc.

[0244] Also, an oxide semiconductor which is a kind of metal oxide may be used as the semiconductor layer. At this time, the band gap of the metal oxide is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide having a large band gap as the semiconductor layer, the off-current of the transistor can be significantly reduced. Since the OS transistor has a small off-current, the power consumption of the semiconductor device can be reduced.

[0245] In a transistor using an oxide semiconductor for the semiconductor layer, it is preferable that the channel formation region of the transistor has less oxygen deficiency or a lower impurity concentration (for example, the concentration of hydrogen, nitrogen, metal elements, etc.) than the source region and the drain region. Also, since VH (a defect in which hydrogen enters an oxygen deficiency) may be formed by hydrogen near the oxygen deficiency and electrons serving as carriers may be generated, V Ｏ H (a defect in which hydrogen enters an oxygen deficiency) is formed and electrons serving as carriers may be generated. Therefore, V ＯIt is also preferable that H is low. Thus, the channel formation region of the transistor is a high-resistance region with a low carrier concentration. Therefore, the channel formation region of the transistor can be said to be type i (intrinsic) or substantially type i.

[0246] Furthermore, the source and drain regions of the transistor have more oxygen vacancies than the channel formation region. Ｏ It is preferable that there is a high concentration of H or a high impurity concentration. Thus, the source region and drain region of the transistor have a higher carrier concentration and are low-resistance n-type regions than the channel formation region.

[0247] <Oxide Semiconductor Layer> Next, an oxide semiconductor layer that can be used as a semiconductor layer of a transistor according to one aspect of the present invention will be described.

[0248] The oxide semiconductor layer preferably contains a crystalline metal oxide. Examples of crystalline metal oxide structures include CAAC (c-axis aligned crystal) structure, polycrystalline structure, microcrystalline structure, and nanocrystalline (nc: nano-crystal) structure. By using a crystalline metal oxide in the oxide semiconductor layer, the defect level density in the oxide semiconductor layer can be reduced. Therefore, the reliability of transistors using oxide semiconductor layers can be improved, and the reliability of semiconductor devices on which such transistors are mounted can be improved.

[0249] The oxide semiconductor layer is preferably a metal oxide having a CAAC structure. A CAAC structure is a crystalline structure in which multiple nanocrystals (typically multiple nanocrystals having a hexagonal crystal structure) are oriented along the c axis, and in the a-b plane, the multiple nanocrystals are linked together without orientation. Furthermore, when a cross-section of an oxide semiconductor layer having a CAAC structure is observed using a high-resolution transmission electron microscope (TEM), it can be confirmed that metal atoms are arranged in layers in the crystalline portion. Therefore, an oxide semiconductor layer having a CAAC structure can also be said to have a structure with layered crystalline portions.

[0250] The crystallinity of an oxide semiconductor layer can be analyzed, for example, by X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0251] The crystallinity of the semiconductor material in the oxide semiconductor layer is not particularly limited. For example, the oxide semiconductor layer may include one or more amorphous semiconductors (semiconductors with an amorphous structure), single-crystal semiconductors (semiconductors with a single-crystal structure), or semiconductors with crystalline properties other than single crystals (microcrystalline semiconductors, polycrystalline semiconductors, or semiconductors with crystalline regions in part). The crystallinity of the oxide semiconductor layer may suppress the degradation of transistor characteristics.

[0252] Examples of metal oxides include indium oxide, gallium oxide, and zinc oxide. Preferably, the metal oxide contains at least indium (In). Preferably, the metal oxide contains at least indium (In) or zinc (Zn). Preferably, the metal oxide contains two or three elements selected from indium, element M, and zinc. Element M is a metallic or metalloid element with a high bond energy to oxygen; for example, a metallic or metalloid element with a higher bond energy to oxygen than indium. Specific examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M present in the metal oxide is preferably one or more selected from the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. When element M is gallium, the metal oxide preferably has one or more selected from indium, gallium, and zinc. In this specification, metal elements and metalloid elements are sometimes collectively referred to as "metal elements," and the "metal elements" described in this specification may include metalloid elements.

[0253] Examples of metal oxides include indium oxide. Other examples of metal oxides include indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also written as IGTO), indium tungsten oxide (In-W oxide), gallium zinc oxide (Ga-Zn oxide, also written as GZO), and aluminum zinc oxide (Al-Zn oxide, A Examples include indium aluminum zinc oxide (also written as ZO), indium aluminum zinc oxide (In-Al-Zn oxide, also written as IAZO), indium tin zinc oxide (also written as In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also written as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also written as IGAZO or IAGZO). In addition, examples of metal oxides include indium tin oxide containing silicon oxide (also called ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide).

[0254] By increasing the ratio of indium atoms to the sum of all metal element atoms contained in the metal oxide (also called the indium (In) content), the transistor can obtain at least one of a large on-current and high frequency characteristics.

[0255] The metal oxide may contain one or more metal elements with higher periodic numbers in the periodic table, instead of indium. Alternatively, the metal oxide may contain one or more metal elements with higher periodic numbers in the periodic table, in addition to indium. The greater the overlap of the metal element orbitals, the greater the carrier conduction in the metal oxide tends to be. Therefore, including metal elements with higher periodic numbers in the periodic table can sometimes increase the field-effect mobility of the transistor. Examples of metal elements with higher periodic numbers in the periodic table include metal elements belonging to the 5th period and metal elements belonging to the 6th period. Specifically, examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0256] Furthermore, metal oxides may contain one or more nonmetallic elements. The presence of nonmetallic elements in metal oxides can sometimes increase the field-effect mobility of transistors. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0257] Furthermore, by increasing the ratio of zinc atoms to the sum of the total number of atoms of all metal elements contained in the metal oxide, a highly crystalline metal oxide is obtained, which suppresses the diffusion of impurities in the metal oxide. Therefore, fluctuations in the electrical properties of the transistor are suppressed, and reliability can be improved.

[0258] Furthermore, by increasing the ratio of element M atoms to the sum of the total number of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation caused by oxygen vacancies is suppressed, resulting in a transistor with low off-current. In addition, fluctuations in the electrical characteristics of the transistor are suppressed, and reliability can be improved.

[0259] Furthermore, the contents of this embodiment can be combined as appropriate. Also, the contents of this embodiment can be combined as appropriate with the contents of other embodiments, etc.

[0260] (Embodiment 3) In this embodiment, an example of a layout when the transistor shown in Embodiment 2 is applied to the semiconductor device shown in Embodiment 1 described above will be explained. Here, as an example, an example of the layout of the semiconductor device 100 shown in Figure 10A will be explained.

[0261] <Layout Example> Figures 17 and 18 are top views showing an example of a layout when the transistor 200A shown in Figure 15 is applied as the transistor constituting the semiconductor device 100 shown in Figure 10A. Figure 19A is a cross-sectional view between A1 and A2 shown by the dashed line in Figure 17. Figure 19B is a cross-sectional view between A3 and A4 shown by the dashed line in Figure 17. Figure 19C is a cross-sectional view between A5 and A6 shown by the dashed line in Figure 17. Figure 19D is a cross-sectional view between A7 and A8 shown by the dashed line in Figure 18. Figure 19E is a cross-sectional view between A9 and A10 shown by the dashed line in Figure 18.

[0262] Figures 17 and 18 illustrate semiconductor layers ac01, ac02, ac03, ac04, ac05, ac06, ac07, and ac08, which correspond to the semiconductor layer 203 on the insulating layer 202. Also, conductive layers ge01, ge02, ge03, ge04, ge05, ge06, ge07, ge08, ge09, ge10, and ge11, which correspond to the conductive layer 205 on the insulating layer 204. Furthermore, the conductive layers me01, me02, me03, me04, me05, me06, me07, me08, me09, me10, me11, me12, me13, and me14, which correspond to the conductive layer 208 on the insulating layer 206, are also shown in the diagram.

[0263] Semiconductor layer ac01 has a channel formation region for transistor M11. Semiconductor layer ac02 has a channel formation region for transistor M12. Semiconductor layer ac03 has a channel formation region for transistor M15 and a channel formation region for transistor M17. Semiconductor layer ac04 has a channel formation region for transistor M16. Semiconductor layer ac05 has a channel formation region for transistor M13 and a channel formation region for transistor M14. Semiconductor layer ac06 has a channel formation region for transistor M13 and a channel formation region for transistor M14. Semiconductor layer ac07 has a channel formation region for transistor M13 and a channel formation region for transistor M18. Semiconductor layer ac08 has a channel formation region for transistor M13 and a channel formation region for transistor M18.

[0264] Conductive layer ge01 has a region that functions as the gate of transistor M11 and a region that functions as wiring VLB1. Conductive layer ge02 has a region that functions as one terminal of capacitive element C11 and a region that functions as node ND14. Conductive layer ge03 has a region that functions as the gate of transistor M13 and a region that functions as node ND14. Conductive layer ge04 has a region that functions as the gate of transistor M12, a region that functions as the gate of transistor M17, a region that functions as the gate of transistor M18, and a region that functions as node ND12. Conductive layer ge05 has a region that functions as wiring VLS1_1, which corresponds to wiring VLS1. Conductive layer ge06 has a region that functions as the gate of transistor M15, a region that functions as one terminal of capacitive element C12, and a region that functions as node ND15. Conductive layer ge07 has a region that functions as the gate of transistor M16 and a region that functions as wiring VLD1. Conductive layer ge08 has a region that functions as node ND11. Conductive layer ge09 has a region that functions as wiring VLS1_2, corresponding to wiring VLS1. Conductive layer ge10 has a region that functions as wiring VLS2. Conductive layer ge11 has a region that functions as the gate of transistor M14 and a region that functions as wiring VLB2.

[0265] Conductive layer me01 has a region that functions as wiring VLB1. Conductive layer me02 has a region that functions as the other source or drain of transistor M12, a region that functions as the other terminal of capacitive element C11, and a region that functions as wiring VLS1_1 corresponding to wiring VLS1. Conductive layer me03 has a region that functions as one source or drain of transistor M11, a region that functions as one source or drain of transistor M12, and a region that functions as node ND14. Conductive layer me04 has a region that functions as the other source or drain of transistor M11, a region that functions as one source or drain of transistor M15, a region that functions as one source or drain of transistor M17, a region that functions as the other terminal of capacitive element C12, and a region that functions as node ND13. Conductive layer me05 has a region that functions as the other source or drain of transistor M15, and a region that functions as wiring VLSD1. Conductive layer me06 has a region that functions as either the source or the drain of transistor M16, and a region that functions as node ND15. Conductive layer me07 has a region that functions as the other source or drain of transistor M16, and a region that functions as node ND11. Conductive layer me08 has a region that functions as the other source or drain of transistor M17, and a region that functions as wiring VLS1_2 corresponding to wiring VLS1. Conductive layer me09 has a region that functions as wiring VLS1_2 corresponding to wiring VLS1. Conductive layer me10 has a region that functions as either the source or the drain of transistor M13, a region that functions as either the source or the drain of transistor M14, a region that functions as either the source or the drain of transistor M18, and a region that functions as wiring OL. Conductive layer me11 has a region that functions as the other source or drain of transistor M13, and a region that functions as wiring VLD2. The conductive layer me12 has a region that functions as either the source or the drain of the transistor M14, and a region that functions as the VLS2 wiring. The conductive layer me13 has a region that functions as the VLS2 wiring.The conductive layer me14 has a region that functions as a wiring VLB2.

[0266] Conductive layer me01 is connected to conductive layer ge01 through an opening in the insulating layer 206. Conductive layer me02 is connected to conductive layer ge05 through an opening in the insulating layer 206. Conductive layer me03 is connected to conductive layer ge02 through an opening in the insulating layer 206. Conductive layer me03 is also connected to conductive layer ge03 through an opening in the insulating layer 206. Conductive layer me05 is connected to conductive layer ge07 through an opening in the insulating layer 206. Conductive layer me06 is connected to conductive layer ge06 through an opening in the insulating layer 206. Conductive layer me07 is connected to conductive layer ge08 through an opening in the insulating layer 206. Conductive layer me08 is connected to conductive layer ge09 through an opening in the insulating layer 206. Conductive layer me09 is connected to conductive layer ge09 through an opening in the insulating layer 206. Conductive layer me12 is connected to conductive layer ge10 through an opening in the insulating layer 206. Conductive layer me13 is connected to conductive layer ge10 through an opening in the insulating layer 206. Conductive layer me14 is connected to conductive layer ge11 through an opening in the insulating layer 206. Figure 19C illustrates how conductive layer me03 and conductive layer ge03 are connected to each other through an opening in the insulating layer 206.

[0267] In Figures 17 and 18, the conductive layer 205 (conductive layers ge01 to ge11) and the conductive layer 208 (conductive layers me01 to me14) are connected to each other at two openings. By configuring the conductive layer 205 and the conductive layer 208 to be connected to each other at multiple openings in this way, the yield of the semiconductor device 100 can be improved.

[0268] As shown in Figures 17 and 18, the region where the semiconductor layer 203 (semiconductor layer ac01 to semiconductor layer ac08) overlaps with the conductive layer 205 (conductive layer ge01 to conductive layer ge11) functions as the channel formation region of the transistor (corresponding to the channel formation region 203c in Figures 15A to 15C). Therefore, the channel length of the transistor (corresponding to the channel length Lch in Figure 15B) corresponds to the width of the conductive layer 205 in the direction in which the semiconductor layer 203 extends, in the region where the semiconductor layer 203 and the conductive layer 205 overlap each other. Figure 19A shows the channel length Lch11 of transistor M11. Figure 19C shows the channel length Lch12 of transistor M12. Figure 19D shows the channel length Lch13 of transistor M13 and the channel length Lch14 of transistor M14. Furthermore, the channel width of the transistor (corresponding to the channel width Wch in Figure 15C) corresponds to the width of the semiconductor layer 203 in the direction in which the conductive layer 205 extends, in the region where the semiconductor layer 203 and the conductive layer 205 overlap each other. Also, the area of ​​the channel formation region of the transistor (corresponding to channel length × channel width) corresponds to the area of ​​the region where the semiconductor layer 203 and the conductive layer 205 overlap each other.

[0269] In a transistor 200A applied to each transistor constituting the semiconductor device 100, multiple transistors 200A may share a semiconductor layer 203 that is provided in a continuous manner. Figures 17 and 18 illustrate how two transistors 200A share semiconductor layer ac02, six transistors 200A share semiconductor layer ac03, two transistors 200A share semiconductor layer ac05, two transistors 200A share semiconductor layer ac06, two transistors 200A share semiconductor layer ac07, and two transistors 200A share semiconductor layer ac08.

[0270] Furthermore, in Figures 17 and 18, transistors M13 and M14 share semiconductor layers ac05 and ac06, respectively, as an example. For instance, of the two transistors 200A provided in semiconductor layer ac05, one is designated as transistor M13 and the other as transistor M14. Of the two transistors 200A provided in semiconductor layer ac06, one is designated as transistor M13 and the other as transistor M14. Also, transistors M13 and M18 share semiconductor layers ac07 and ac08, respectively, as an example. For instance, of the two transistors 200A provided in semiconductor layer ac07, one is designated as transistor M13 and the other as transistor M18. Of the two transistors 200A provided in semiconductor layer ac08, one is designated as transistor M13 and the other as transistor M18. Furthermore, transistors M15 and M17 share the semiconductor layer ac03, for example. For instance, of the six transistors 200A provided on the semiconductor layer ac03, four are designated as transistors M15 and the remaining two as transistors M17. Figure 19D illustrates how transistors M13 and M14 share a continuous semiconductor layer ac06. In this way, by having multiple transistors 200A share a continuous semiconductor layer 203, the layout area of ​​the transistors can be reduced. Therefore, the layout area of ​​the semiconductor device 100 can be reduced, and the bezel width of the display device can be reduced.

[0271] However, this is not limited to this configuration; two or more transistors may share a single semiconductor layer 203. For example, although not shown, transistors M11, M12, M15, and M17 may share a single semiconductor layer 203. This allows for a reasonable reduction in conductive layers and vias used to connect the semiconductor layers 203 to each other. As a result, the layout area of ​​the semiconductor device 100 can be reduced, and the bezel width of the display device can be narrowed.

[0272] Furthermore, in the transistors 200A applied to each transistor constituting the semiconductor device 100, a configuration in which multiple transistors 200A are connected in parallel may be used. In Figures 17 and 18, transistor M12, as an example, has a configuration in which two transistors 200A are connected in parallel. Transistor M13, as an example, has a configuration in which four transistors 200A are connected in parallel. Transistor M14, as an example, has a configuration in which two transistors 200A are connected in parallel. Transistor M15, as an example, has a configuration in which four transistors 200A are connected in parallel. Transistor M17, as an example, has a configuration in which two transistors 200A are connected in parallel. Transistor M18, as an example, has a configuration in which two transistors 200A are connected in parallel. Figure 19C illustrates two transistors 200A in transistor M12. Figure 19E illustrates two transistors 200A in transistor M14. In this configuration, multiple transistors 200A are connected in parallel, which effectively increases the channel width and thus the on-current.

[0273] As described in Embodiment 1 above, it is preferable to increase the on-resistance of transistor M11, and for this purpose, the channel length of transistor M11 may be made larger than the channel lengths of transistors M12 to M18. For example, the channel length of transistor M11 (corresponding to Lch11 shown in Figure 19A) may be made larger than the channel length of transistor M12 (corresponding to Lch12 shown in Figure 19C) and the channel length of transistor M13 (corresponding to Lch13 shown in Figure 19D).

[0274] Furthermore, in order to increase the channel length of transistor M11, the channel formation region of transistor M11 may have a bent shape in one or more places (for example, an L-shape, a U-shape, an S-shape, a meandering shape, etc.). For example, in the channel formation region of transistor M11, one or both of the semiconductor layer ac01 and the conductive layer ge01 may have a bent shape in one or more places. This increases the channel length of transistor M11 and allows for efficient arrangement of transistor M11. Figure 17 shows an example in which the channel formation region of transistor M11 has a U-shape due to having multiple bent shapes.

[0275] Furthermore, in order to increase the on-resistance of transistor M11, the channel width of transistor M11 may be made smaller than the channel widths of transistors M12 to M18.

[0276] Furthermore, as described in Embodiment 1 above, it is preferable to increase the saturation of transistors M13 and M14, and for this purpose, the channel lengths of transistors M13 and M14 may be made larger than the channel lengths of transistors M12 and M15 to M18. For example, the channel length of transistor M13 (corresponding to Lch13 shown in Figure 19D) may be made larger than the channel length of transistor M12 (corresponding to Lch12 shown in Figure 19C).

[0277] Furthermore, as described in Embodiment 1 above, it is preferable to increase the on-current of transistors M13 and M14, and for this purpose, the channel widths of transistors M13 and M14 may be made larger than the channel widths of transistors M12 and M15. In this case, as shown in Figures 17 and 18, the channel width of each transistor 200A in transistors M13 and M14 may be made larger than the channel width of each transistor 200A in transistors M12 and M15. This makes it possible to reduce the number of transistors connected in parallel when obtaining the same on-current, and to reduce the layout area of ​​the transistors. Thus, the bezel width of the display device can be reduced.

[0278] As shown in Figures 17 and 18, the capacitive element C11 can be configured such that a portion of the insulating layer 206 functions as a dielectric in the region where the conductive layer ge02 and the conductive layer me02 overlap each other. The capacitive element C12 can be configured such that a portion of the insulating layer 206 functions as a dielectric in the region where the conductive layer ge06 and the conductive layer me04 overlap each other. Figure 19C illustrates, as an example, the capacitive element C11 in which a portion of the insulating layer 206 functions as a dielectric, and portions of the conductive layer ge02 and the conductive layer me02 each function as a pair of terminals.

[0279] In Figure 17, in the capacitive element C11, the conductive layer ge02 is positioned inside the outer edge of the conductive layer me02, except for the lead-out portion (in some cases, the conductive layer me02 is positioned to encompass the conductive layer ge02). For example, in the capacitive element C11, the outer edge of the region of the conductive layer me02 that overlaps with the conductive layer ge02 has a portion that is inscribed with the outer edge of the conductive layer me02 and a portion that is not inscribed with the outer edge of the conductive layer me02, and the sum of the lengths of the portions that are not inscribed with the outer edge of the conductive layer me02 is greater than the sum of the lengths of the portions that are inscribed with the outer edge of the conductive layer me02. Alternatively, although not shown, for example, the entire outer edge of the region may be positioned inside the outer edge of the conductive layer me02 without being inscribed with the outer edge of the conductive layer me02. This allows the insulating layer between the end of the conductive layer ge02 and the conductive layer me02 covering it to also be used as a dielectric of the capacitive element C11. Therefore, it becomes easier to increase the capacitance per unit area of ​​the capacitive element C11, and the layout area can be reduced. Thus, the bezel width of the display device can be reduced.

[0280] Furthermore, in Figure 17, in the capacitive element C12, the conductive layer me04 is positioned inside the outer edge of the conductive layer ge06, except for the lead-out portion (in some cases, the conductive layer ge06 is positioned to encompass the conductive layer me04). For example, in the capacitive element C12, the outer edge of the region of the conductive layer ge06 that overlaps with the conductive layer me04 has a portion that is inscribed with the outer edge of the conductive layer ge06 and a portion that is not inscribed with the outer edge of the conductive layer ge06, and the total length of the portion that is not inscribed with the outer edge of the conductive layer ge06 is greater than the total length of the portion that is inscribed with the outer edge of the conductive layer ge06. Alternatively, although not shown, for example, the entire outer edge of the region may be positioned inside the outer edge of the conductive layer ge06 without being inscribed with the outer edge of the conductive layer ge06. As a result, the region that functions as a dielectric of the capacitive element C12 is composed of an insulating layer 206 with a uniform thickness. Therefore, it is possible to reduce either or both the capacitance error (here, the difference between the design value and the actual value) and the variation (here, the degree of dispersion of the actual value) of the capacitance element C12.

[0281] In addition, in the capacitive element C11, similar to the capacitive element C12, the conductive layer me02 may be arranged inside the outer edge of the conductive layer ge02, excluding the lead-out portion (in some cases, the conductive layer ge02 may be arranged to encompass the conductive layer me02). Also, in the capacitive element C12, similar to the capacitive element C11, the conductive layer ge06 may be arranged inside the outer edge of the conductive layer me04, excluding the lead-out portion (in some cases, the conductive layer me04 may be arranged to encompass the conductive layer ge06).

[0282] Furthermore, in the capacitive element C11, when the conductive layer me02 is positioned inside the outer edge of the conductive layer ge02, excluding the lead-out portion, the area in which the conductive layer me02 covers the edge of the conductive layer ge02 can be reduced compared to when the conductive layer ge02 is positioned inside the outer edge of the conductive layer me02, excluding the lead-out portion. Therefore, the concern that dielectric breakdown of the insulating layer 206 may occur due to electric field concentration on the insulating layer 206 at the edge of the conductive layer ge02 can be reduced. Thus, reliability can be improved. The same applies to the capacitive element C12.

[0283] Outside the regions where the capacitive elements C11 and C12 are located, the regions where conductive layers overlap each other via an insulating layer (for example, the region where conductive layer 205 (conductive layers ge01 to ge11) and conductive layer 208 (conductive layers me01 to me14) overlap each other) become parasitic capacitances where a part of the insulating layer (for example, insulating layer 206) functions as a dielectric. Therefore, it is preferable that the area of ​​the region where the conductive layers that form the parasitic capacitance overlap each other is smaller than the area of ​​the capacitive element C11 (here, this corresponds to the area where conductive layer ge02 and conductive layer me02 overlap each other). Furthermore, it is preferable that the area of ​​the region where the conductive layers that form the parasitic capacitance overlap each other is smaller than the area of ​​the capacitive element C12 (here, this corresponds to the area where conductive layer ge06 and conductive layer me04 overlap each other).

[0284] Therefore, in Figures 17 and 18, for example, it is preferable that the area of ​​the capacitive element C11 is larger than the area of ​​the region where the conductive layer ge02 and the conductive layer 208 other than the conductive layer me02 overlap each other. Also, it is preferable that the area of ​​the capacitive element C11 is larger than the area of ​​the region where the conductive layer 205 other than the conductive layer ge02 and the conductive layer me02 overlap each other. For example, it is preferable that the area of ​​the capacitive element C11 is larger than the area where the conductive layer ge04 and the conductive layer me02 overlap each other. Also, it is preferable that the area of ​​the capacitive element C12 is larger than the area of ​​the region where the conductive layer ge06 and the conductive layer 208 other than the conductive layer me04 overlap each other. Also, it is preferable that the area of ​​the capacitive element C12 is larger than the area of ​​the region where the conductive layer 205 other than the conductive layer ge06 and the conductive layer me04 overlap each other. For example, it is preferable that the area of ​​the capacitive element C12 is larger than the area where the conductive layer ge04 and the conductive layer me04 overlap each other.

[0285] As described in Embodiment 1 above, it is preferable to increase the capacitance of the capacitive element C11, and for this purpose, for example, the area of ​​the conductive layer ge02 may be increased. In this case, as shown in Figure 17, at node ND14, the conductive layer ge02 having a region that functions as one terminal of the capacitive element C11 and the conductive layer ge03 having a region that functions as the gate of the transistor M13 may be connected to each other via the conductive layer me03. This makes it possible to suppress damage to the gate insulating film (corresponding to the insulating layer 204) of the transistor M11 due to the charge charged in the conductive layer ge02 during the manufacturing process of the semiconductor device 100 (also known as the antenna effect). Thus, at least one of the following can be achieved: improved yield and improved reliability.

[0286] Although not shown in the figures, a configuration may be used in which, for example, a part of the insulating layer 204 functions as a dielectric, and a part of the semiconductor layer 203 and the conductive layer 205 each functions as a pair of terminals. Alternatively, for example, a configuration may be used in which a part of the insulating layer 204 and the insulating layer 206 each functions as a dielectric, and a part of the semiconductor layer 203 and the conductive layer 208 each functions as a pair of terminals. Alternatively, for example, a conductive layer (not shown) may be provided between the substrate 201 and the insulating layer 202, and a part of the insulating layer 202 and the insulating layer 204 each functions as a dielectric, and a part of the conductive layer (not shown) and the conductive layer 205 each functions as a pair of terminals. Alternatively, for example, a conductive layer (not shown) may be provided between the substrate 201 and the insulating layer 202, and a part of the insulating layer 202 functions as a dielectric, and a part of the conductive layer (not shown) and the semiconductor layer 203 each functions as a pair of terminals.

[0287] As shown in Figures 17 and 18, the wiring VLS1 may be provided as two separate connections: wiring VLS1_1 connected to the other source or drain of transistor M12 and the other source or drain of transistor M18, and wiring VLS1_2 connected to the other source or drain of transistor M17. In this case, wiring VLS1_1 and wiring VLS1_2 are connected to each other, for example, outside the semiconductor device 100. This arrangement allows for efficient placement of transistors M12, M17, M18, and wiring VLS1 (wiring VLS1_1 and wiring VLS1_2).

[0288] As shown in Figures 17 and 18, the width of wiring VLD2 (corresponding here to the wiring width of conductive layer me11) and the width of wiring VLS2 (corresponding here to the wiring width of conductive layer me13) are made larger than the width of wiring VLD1 (corresponding here to the wiring width of conductive layer me05), wiring VLS1_1 (corresponding here to the wiring width of conductive layer me02), wiring VLS1_2 (corresponding here to the wiring width of conductive layer me09), wiring VLB1 (corresponding here to the wiring width of conductive layer me01), and wiring VLB2 (corresponding here to the wiring width of conductive layer me14). In addition, the widths of wiring VLD1, wiring VLS1_1, and wiring VLS1_2 are made larger than the widths of wiring VLB1 and wiring VLB2.

[0289] Current flows steadily through wiring VLD2 and wiring VLS2 to drive amplifier 102. In addition, the current flowing through wiring VLD2 and wiring VLS2 becomes large in order to drive one row of pixels connected to wiring OL. As a result, the voltage drop in wiring VLD2 and wiring VLS2 becomes large, raising concerns about its impact on circuit operation. Therefore, in order to suppress the effects of the voltage drop in wiring VLD2 and wiring VLS2, it is preferable to increase the width of wiring VLD2 and wiring VLS2. However, since large currents may flow instantaneously through wiring VLD1, wiring VLS1_1, and wiring VLS1_2, it is also preferable to increase the width of wiring VLD1, wiring VLS1_1, and wiring VLS1_2. Note that almost no current flows through wiring VLB1 and wiring VLB2. In this case, increasing the width of any of the above wirings will increase the layout area. Therefore, by prioritizing and increasing the width of wiring with high current flow, it is possible to suppress the increase in layout area while suppressing the effects of voltage drop. In addition, by prioritizing and increasing the width of wiring with high current flow, the current density within the wiring can be reduced. As a result, wiring breakage or short circuits due to electromigration become less likely, thus improving reliability.

[0290] Therefore, the widths of wiring VLD2 and VLS2 may be made larger than the widths of wiring VLD1, wiring VLS1_1, wiring VLS1_2, wiring VLB1, and wiring VLB2. Also, the widths of wiring VLD1, wiring VLS1_1, and wiring VLS1_2 may be made larger than the widths of wiring VLB1 and wiring VLB2. This makes it possible to suppress the effects of voltage drop in each wiring while suppressing an increase in the layout area.

[0291] Here, in Figures 17 and 18, for example, if the wiring width of conductive layer me11 having a region that functions as wiring VLD2 is increased, the overlap between conductive layer me11 and conductive layer ge03 having a region that functions as node ND14, and conductive layer ge04 having a region that functions as node ND12, increases. Therefore, there is concern that the increase in parasitic capacitance due to the overlap of the two conductive layers may affect the circuit operation. Accordingly, although not shown in the figures, in order to suppress this increase in parasitic capacitance, for example, the wiring width of conductive layer me11 may be selectively reduced in the region where conductive layer me11, conductive layer ge03, and conductive layer ge04 overlap each other, or an opening may be formed in conductive layer me11. The same applies to wiring VLS2, wiring VLD1, wiring VLS1_1, and wiring VLS1_2. The same also applies to the overlap of other conductive layers where parasitic capacitance may be formed.

[0292] Furthermore, the technical concepts, configurations, operations, and effects described in this embodiment are not limited to the semiconductor device 100 shown in Figure 10A, but can be applied to various semiconductor devices 100 as described in Embodiment 1 above.

[0293] Furthermore, the contents of this embodiment can be combined as appropriate. Also, the contents of this embodiment can be combined as appropriate with the contents of other embodiments, etc.

[0294] (Embodiment 4) This embodiment describes a display device according to one aspect of the present invention.

[0295] Furthermore, at least a portion of the semiconductor device, the drive circuit having the semiconductor device, and the display device described in Embodiment 1 above can be applied to the display device shown in this embodiment and the module having the display device.

[0296] Here, examples of modules having the display device include modules to which a connector such as a flexible printed circuit board (FPC) or a TCP (Tape Carrier Package) is attached, or modules on which an integrated circuit (IC) is mounted using a COG (Chip On Glass) method or a COF (Chip On Film) method.

[0297] <Example of Display Device Configuration> Figure 20A is a perspective view showing an example of the configuration of a display device 400 according to one aspect of the present invention.

[0298] The display device 400 has a configuration in which substrate 409 and substrate 401 are bonded together. In Figure 20A, substrate 409 is shown with a dashed line.

[0299] The display device 400 includes a display unit 402, a circuit unit 403, a circuit unit 404, a connection unit 405, and a wiring unit 406. Figure 20A shows an example in which an IC chip 407 and an FPC 408 are mounted on the display device 400. Therefore, the configuration shown in Figure 20A can also be described as a display module having a display device 400, an IC chip, and an FPC.

[0300] Furthermore, at least a portion of the semiconductor device 100, drive circuit 110, and display device 160 shown in Embodiment 1 above can be applied to the display device 400. For example, at least a portion of the gate driver unit 163, source driver unit 164, and control unit 167 shown in Embodiment 1 above can be applied to the circuit unit 403 and circuit unit 404. Also, for example, at least a portion of the pixel unit 162 shown in Embodiment 1 above can be applied to the display unit 402. Also, for example, at least a portion of the semiconductor device 100 and drive circuit 110 shown in Embodiment 1 above can be applied to the circuit unit 403 and circuit unit 404. Also, for example, at least a portion of the gate driver unit 163, source driver unit 164, and control unit 167 shown in Embodiment 1 above can be applied to the IC chip 407.

[0301] Circuit section 403 includes, for example, a scan line drive circuit (also called a gate driver or scan driver). Circuit section 404 also includes, for example, a signal line drive circuit (also called a source driver or data driver).

[0302] The wiring section 406 has the function of supplying signals and power to the display section 402, the circuit section 403, and the circuit section 404. These signals and power are input to the wiring section 406 from outside the display device 400 via the FPC 408, or from the IC chip 407 to the wiring section 406.

[0303] Figure 20A shows an example in which an IC chip 407 is provided on the substrate 401 using a COG (Camera-Owned Gauge) or COF (Camera-Owned Frame) method. The IC chip 407 can be, for example, an IC chip having one or both of a scan line drive circuit and a signal line drive circuit. The IC chip may also have a power supply circuit, a signal generation circuit, etc. The display device 400 and the display module may be configured without an IC chip. The IC chip may also be mounted on an FPC (Flexible Printed Circuit) using a COF method or the like.

[0304] Furthermore, a scan line driving circuit may be configured in either or both of the IC chip 407 and the circuit section 403. In this case, the IC chip 407 may be referred to as a gate driver IC. Alternatively, a signal line driving circuit may be configured in either or both of the IC chip 407 and the circuit section 404. In this case, the IC chip 407 may be referred to as a source driver IC.

[0305] The display unit 402 is the area in the display device 400 that displays an image, and has a plurality of pixels 411 arranged periodically. Figure 20A shows a magnified view of one pixel 411.

[0306] The pixel 411 shown in Figure 20A has a pixel 412R that emits red (R) light, a pixel 412G that emits green (G) light, and a pixel 412B that emits blue (B) light. Full-color display can be achieved by configuring one pixel 411 with pixels 412R, 412G, and 412B. Pixels 412R, 412G, and 412B each function as sub-pixels. The display device 400 shown in Figure 20A shows an example in which the sub-pixels 412R, 412B, and 412G are arranged in a stripe pattern. Note that the number of sub-pixels constituting one pixel 411 is not limited to three, but may be four or more. For example, there may be four sub-pixels that emit R, G, B, and white (W) light, respectively. Alternatively, there may be four sub-pixels that emit R, G, B, and yellow (Y) light, respectively.

[0307] In this specification, elements related to red light may be denoted with the identification code "R," elements related to green light with the identification code "G," and elements related to blue light with the identification code "B" to explain each respective matter. In addition, common matters may be explained by not assigning these identification codes. For example, when it is necessary to distinguish between multiple pixels 412, they may be indicated as pixel 412R, pixel 412G, or pixel 412B. Also, when it is not necessary to distinguish between pixels 412R, pixel 412G, and pixel 412B, they may simply be indicated as pixel 412.

[0308] Each pixel 412R, pixel 412G, and pixel 412B includes a display element and a circuit (pixel circuit) that controls the driving of the display element.

[0309] The connection portion 405 is provided on the outside of the display portion 402. The connection portion 405 can be provided along one or more sides of the display portion 402. There may be one or more connection portions 405. Figure 20A shows an example in which the connection portion 405 is provided so as to surround all four sides of the display portion. At the connection portion 405, one of the pair of electrodes of the display element is connected to the wiring portion 406, and a potential can be supplied to one of the pair of electrodes.

[0310] The substrates 401 and 409 can be made of glass, quartz, ceramics, sapphire, resin, metal, alloy, or semiconductor, respectively. It is preferable to use a light-transmitting material for the substrate that extracts light from the display element (in this case, substrate 409). A polarizing plate may also be used as at least one of the substrates 401 and 409. Furthermore, flexible materials can be used for substrates 401 and 409. This increases the flexibility of the display device, enabling the creation of flexible displays (bendable displays, foldable displays, rollable displays, slidable displays, stretchable displays, etc.).

[0311] Furthermore, a display device according to one aspect of the present invention may also function as a touch panel. For example, various detection elements (also called sensor elements) capable of detecting the proximity or contact of an object to be detected, such as a finger, can be applied to the display device.

[0312] Examples of sensor types include capacitive, resistive, surface acoustic wave, infrared, optical, and pressure-sensitive sensors.

[0313] Examples of capacitance methods include surface capacitance and projected capacitance. Examples of projected capacitance methods include self-capacitance and mutual capacitance. Mutual capacitance is preferred because it enables simultaneous multi-point detection.

[0314] Examples of touch panels include out-cell, on-cell, and in-cell types. An in-cell touch panel refers to a configuration in which electrodes constituting a sensing element are provided on one or both of the substrate supporting the display element (also called a display device) and the opposing substrate.

[0315] [Pixel Arrangement] Figures 20B to 20F are top views illustrating the pixel arrangement. In a display device according to one embodiment of the present invention, there are no particular limitations on the pixel arrangement, and various arrangements can be applied. Examples of pixel arrangements include stripe arrangement (see Figure 20B), S-stripe arrangement (see Figure 20C), delta arrangement (see Figure 20D), zigzag arrangement (see Figure 20E), and pentile arrangement (see Figure 20F). Other examples include mosaic arrangement, diamond arrangement, and Bayer arrangement. The pentile arrangement shown in Figure 20F includes a pixel 411 composed of pixels 412R and 412G, and a pixel 411 composed of pixels 412B and 412G.

[0316] Furthermore, in Figures 20B to 20F, the top surface shape of each sub-pixel (pixel 412R, pixel 412G, and pixel 412B) can be, for example, a triangle, a quadrilateral (including rectangles and squares), a pentagon, a polygon with rounded corners, an ellipse, or a circle. Here, the top surface shape of each sub-pixel corresponds to the top surface shape of the display area of ​​the display element that each sub-pixel possesses. The top surface shape and size of each sub-pixel can be determined independently. Note that the arrangement of pixels 412R, 412G, and 412B may be changed as appropriate. Also, the display elements and the pixel circuits may be arranged in the same way or in different ways.

[0317] [Display Elements] Various elements can be used as display elements, for example, liquid crystal elements and light-emitting elements. In addition, display elements using shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems), microcapsule-type, electrophoretic-type, electrowetting-type, or electronic powder fluid (registered trademark)-type may also be used. Furthermore, QLED (Quantum-dot LED) using a light source and color conversion technology using quantum dot materials may also be used.

[0318] Examples of display devices using liquid crystal elements include transmissive liquid crystal display devices, reflective liquid crystal display devices, and semi-transmissive liquid crystal display devices.

[0319] Modes that can be used in display devices using liquid crystal elements include, for example, Vertical Alignment (VA) mode, FFS (Fringe Field Switching) mode, IPS (In-Plane-Switching) mode, TN (Twisted Nematic) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, and ECB (Electrically Examples of VA modes include Controlled Birefringence mode and guest host mode. Examples of VA modes include MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode, and ASV (Advanced Super View) mode.

[0320] Examples of liquid crystal materials that can be used in liquid crystal elements include thermotropic liquid crystals, low molecular weight liquid crystals, polymer liquid crystals, polymer dispersed liquid crystals (PDLC), polymer network liquid crystals (PNLC), ferroelectric liquid crystals, and antiferroelectric liquid crystals. Depending on the conditions, these liquid crystal materials exhibit a cholesteric phase, smectic phase, cubic phase, chiral nematic phase, isotropic phase, or blue phase. Furthermore, either positive-type or negative-type liquid crystals may be used as the liquid crystal material.

[0321] As light-emitting elements, for example, field-emitting elements (such as injection-type field-emitting elements) such as LEDs using inorganic materials as the light-emitting material, organic EL elements (also called OLEDs), or semiconductor lasers (also called laser diodes) can be used. As LEDs using inorganic materials as the light-emitting material, for example, mini-LEDs or micro-LEDs can be used.

[0322] Examples of light-emitting materials for light-emitting devices include fluorescent materials, phosphorescent materials, thermally activated delayed fluorescence (TADF) materials, and inorganic compounds (such as quantum dot materials).

[0323] The light-emitting element can emit light of colors such as red, green, blue, blue-green, reddish-purple, yellow, or white. It may also emit ultraviolet or infrared light. Furthermore, the color purity can be improved by adding a microcavity structure to the light-emitting element.

[0324] Of the pair of electrodes in a light-emitting element, one electrode functions as the anode (also called the positive electrode), and the other electrode functions as the cathode (also called the negative electrode).

[0325] In addition, in a display device using liquid crystal elements, the above-mentioned light-emitting elements may be used as the light source of the display device (backlight, edge light, side light, front light, etc.). For example, a light-emitting element such as a mini-LED may be used as the backlight of the display device. In one aspect of the present invention, at least a part of the semiconductor device 100 shown in Embodiment 1 described above can be applied to the drive circuit of the light-emitting element.

[0326] <Example of Cross-Sectional Structure of a Display Device> Figure 21 is a cross-sectional view illustrating an example of the cross-sectional structure of a display device according to one embodiment of the present invention.

[0327] In the display device 490 shown in Figure 21, the configurations shown in regions 490a, 490b, and 490c can be used in the display device 400, respectively. For example, the configuration shown in region 490a can be used in the region where the pixels 412 are provided. The configuration shown in region 490b can be used in the region where the circuit sections 403 and 404 are provided. The configuration shown in region 490c can be used in the region where the FPC 408 is provided.

[0328] Region 490a corresponds to the region where the pixel 161 shown in Embodiment 1 described above is provided. Therefore, the transistors provided in region 490a correspond to the transistors (transistors M31 to M34, etc.) that the pixel 161 shown in Embodiment 1 described above has. Region 490b corresponds to the region where the gate driver unit 163 (corresponding to the semiconductor device 100 and drive circuit 110, etc.), source driver unit 164, and control unit 167, etc., shown in Embodiment 1 described above are provided. Therefore, the transistors provided in region 490b correspond to the transistors (transistors M11 to M15, etc.) that the semiconductor device 100 etc. shown in Embodiment 1 described above has.

[0329] The display device 490 has a substrate 310 (corresponding to the substrate 401 described above) and a substrate 350 (corresponding to the substrate 409 described above). A resin layer 340 is also present between the substrates 310 and 350. The substrate 350 faces the substrate 310 via the resin layer 340. In region 490c, there is no substrate 350 and no resin layer 340.

[0330] An insulating layer 312 is provided on the substrate 350 side of the substrate 310. Transistors and light-emitting elements are provided on the insulating layer 312.

[0331] Here, as an example, a configuration is shown in which the transistor 200A shown in Embodiment 2 above is provided in both region 490a and region 490b. Furthermore, a configuration is shown in which the transistor 200B shown in Embodiment 2 above is provided in region 490a.

[0332] Furthermore, the transistors provided in regions 490a and 490b are not limited to structures like transistor 200A and transistor 200B. Various transistor structures can be provided in regions 490a and 490b. In this case, one type of transistor structure may be provided, or two or more different transistor structures may be provided.

[0333] Furthermore, a conductive layer 364 is provided in region 490c. The conductive layer 364 can be formed using the same process as the conductive layer 208 (conductive layer 208a, conductive layer 208b, etc.) in transistors 200A and 200B.

[0334] An insulating layer 218 is provided so as to cover transistors 200A and 200B.

[0335] In region 490a, a pixel electrode 321 (pixel electrode 321a and pixel electrode 321b) is provided on the insulating layer 218. The pixel electrode 321a is in contact with the conductive layer 208b at openings provided in the insulating layer 218 and the insulating layer 209. In addition, an insulating layer 322 is provided on the insulating layer 218. The insulating layer 322 has a region that covers the end of the pixel electrode 321.

[0336] A light-emitting element 370 is provided on top of the pixel electrode 321.

[0337] The light-emitting element 370 corresponds to the light-emitting element LD found in the pixel 161, etc., as shown in Embodiment 1 described above.

[0338] The light-emitting element 370 has a configuration in which a semiconductor layer 371, an emissive layer 372, and a semiconductor layer 373 are provided in this order. An opening is provided in part of the emissive layer 372 and the semiconductor layer 373 that reaches the semiconductor layer 371. An insulating layer 374 is provided so as to cover the semiconductor layer 371, the emissive layer 372, and the semiconductor layer 373. A conductive layer 375a is provided in the opening provided in the insulating layer 374 that is in contact with the semiconductor layer 373. A conductive layer 375b is provided in the opening provided in the insulating layer 374 that is in contact with the semiconductor layer 371. The conductive layer 375a is connected to a conductive layer 377a provided on the pixel electrode 321a via a connecting layer 376a. The conductive layer 375b is connected to a conductive layer 377b provided on the pixel electrode 321b via a connecting layer 376b.

[0339] For the conductive layer 375 (conductive layer 375a and conductive layer 375b) and conductive layer 377 (conductive layer 377a and conductive layer 377b), for example, metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, tin, zinc, silver, platinum, gold, molybdenum, tantalum, or tungsten, or alloys mainly composed of these metals (such as an alloy of silver, palladium, and copper), can be used. Alternatively, oxides such as tin oxide or zinc oxide may be used. For the connecting layer 376 (connecting layer 376a and connecting layer 376b), for example, solder bumps or gold bumps can be used.

[0340] The light-emitting layer 372 is provided between the semiconductor layer 371 and the semiconductor layer 373. In the light-emitting layer 372, electrons and holes combine to emit light. One of the semiconductor layers 371 and 373 can be an n-type semiconductor layer, and the other can be a p-type semiconductor layer. Furthermore, the light-emitting layer 372 can be an n-type, i-type, or p-type semiconductor layer.

[0341] The laminated structure, comprising a semiconductor layer 371, a light-emitting layer 372, and a semiconductor layer 373, is formed to emit light such as infrared, red, green, blue, blue-violet, violet, or ultraviolet light. For example, compounds containing group 13 and group 15 elements (also called group 3-5 compounds) can be used in the laminated structure. Examples of group 13 elements include aluminum, gallium, and indium. Examples of group 15 elements include nitrogen, phosphorus, arsenic, and antimony.

[0342] In a laminated structure including a semiconductor layer 371, a light-emitting layer 372, and a semiconductor layer 373, a light-emitting element 370 that emits desired light can be fabricated by forming a pn junction or pin junction using, for example, a compound of gallium and phosphorus, a compound of gallium and arsenic, a compound of gallium, aluminum and arsenic, a compound of aluminum, gallium, indium and phosphorus, gallium nitride, a compound of indium and gallium nitride, or a compound of selenium and zinc. The pn junction or pin junction formed in the laminated structure may be a homojunction, a heterojunction, or a double heterojunction. Furthermore, a quantum well structure may be used in the laminated structure. Furthermore, nanocolumns may be used in the laminated structure.

[0343] As materials that can be used in a laminated structure including a semiconductor layer 371, an emissive layer 372, and a semiconductor layer 373, for example, gallium nitride can be used for light-emitting elements that emit light in the ultraviolet to blue wavelength range. For light-emitting elements that emit light in the ultraviolet to green wavelength range, a compound of indium and gallium nitride can be used. For light-emitting elements that emit light in the green to red wavelength range, a compound of aluminum, gallium, indium, and phosphorus, or a compound of gallium and arsenic can be used. For light-emitting elements that emit light in the infrared wavelength range, a compound of gallium and arsenic can be used.

[0344] Here, when the display device 490 has a plurality of light-emitting elements 370, adjacent light-emitting elements 370 can be configured to emit light of different colors, such as red, green, and blue.

[0345] For example, a pixel emitting blue light may have a light-emitting element 370 that emits blue light, a pixel emitting green light may have a light-emitting element 370 that emits green light, and a pixel emitting red light may have a light-emitting element 370 that emits red light. This makes it possible to display a color image. In this case, for example, a pixel emitting blue light may have a colored layer that enhances the color purity of the blue light, a pixel emitting green light may have a colored layer that enhances the color purity of the green light, and a pixel emitting red light may have a colored layer that enhances the color purity of the red light.

[0346] Furthermore, when the display device 490 has a plurality of light-emitting elements 370, adjacent light-emitting elements 370 may be configured to emit light of the same color. In this case, the light emitted from each light-emitting element 370 is emitted to the outside of the display device 490, for example, through one or both of the color conversion layer and the coloring layer.

[0347] For example, a pixel emitting blue light may have a light-emitting element 370 that emits blue light; a pixel emitting green light may have a light-emitting element 370 that emits blue light and a color conversion layer that converts blue light to green light; and a pixel emitting red light may have a light-emitting element 370 that emits blue light and a color conversion layer that converts blue light to red light. This makes it possible to display a color image. In this case, for example, a pixel emitting blue light may have a coloring layer that enhances the color purity of the blue light; a pixel emitting green light may have a coloring layer that enhances the color purity of the green light; and a pixel emitting red light may have a coloring layer that enhances the color purity of the red light.

[0348] Furthermore, for example, a pixel emitting blue light may have a light-emitting element 370 that emits ultraviolet light and a color conversion layer that converts ultraviolet light to blue light; a pixel emitting green light may have a light-emitting element 370 that emits ultraviolet light and a color conversion layer that converts ultraviolet light to green light; and a pixel emitting red light may have a light-emitting element 370 that emits ultraviolet light and a color conversion layer that converts ultraviolet light to red light. This makes it possible to display a color image. In this case, for example, a pixel emitting blue light may have a coloring layer that enhances the color purity of the blue light, a pixel emitting green light may have a coloring layer that enhances the color purity of the green light, and a pixel emitting red light may have a coloring layer that enhances the color purity of the red light.

[0349] A light-shielding layer 352 is provided on the substrate 310 side of the substrate 350.

[0350] In region 490a, the light-shielding layer 352 is provided with an opening that overlaps with the light-emitting element 370. Therefore, the light emitted from the light-emitting element 370 is emitted to the outside of the display device 490 through the opening in the light-shielding layer 352. In Figure 21, this is represented by a dashed arrow and the label "Light".

[0351] An optical functional layer 354 may be provided in the openings in the light-shielding layer 352. For example, one or both of a color conversion layer and a coloring layer may be applied as the optical functional layer 354. By applying a coloring layer to the optical functional layer 354, the color purity of the light emitted from the light-emitting element 370 can be increased. Also, by applying a color conversion layer to the optical functional layer 354, the wavelength of the light emitted from the light-emitting element 370 can be converted.

[0352] Furthermore, although not shown in the figures, for example, one or both of the color conversion layer and the coloring layer may be provided on the substrate 350 side of the light-emitting element 370 so as to be in contact with the semiconductor layer 371.

[0353] Furthermore, for example, a light-shielding layer 353 may be provided between adjacent light-emitting elements 370. This suppresses light leakage (stray light) to adjacent light-emitting elements 370. Thus, the display quality of the display device can be improved.

[0354] Furthermore, at least a portion of the insulating layer 374, insulating layer 322, pixel electrode 321, and light-shielding layer 353 may have the function of reflecting light emitted from the light-emitting element 370. Also, at least a portion of the insulating layer 374 on the substrate 350 side, the insulating layer 322 on the substrate 350 side, the pixel electrode 321 on the substrate 350 side, and the light-shielding layer 353 on the light-emitting element 370 side may be provided with a reflective layer that has the function of reflecting light emitted from the light-emitting element 370. In this case, at least a portion of the insulating layer 374, insulating layer 322, pixel electrode 321, and light-shielding layer 353, or the reflective layer provided thereon, may be appropriately tilted or otherwise provided so that the amount of reflected light emitted to the outside of the display device 490 is increased. This makes it possible to increase the amount of light emitted to the outside of the display device 490. Therefore, the brightness of the display device can be increased.

[0355] Although not shown in the figures, as an example, the pixel electrode 321a or pixel electrode 321b may be provided so as to cover the region of the insulating layer 218 that overlaps with the light-emitting element 370. In this case, the pixel electrode 321a or pixel electrode 321b may have the function of reflecting light emitted from the light-emitting element 370. Alternatively, a reflective layer having the function of reflecting light emitted from the light-emitting element 370 may be provided on the substrate 350 side of the pixel electrode 321a or pixel electrode 321b. This increases the amount of light emitted to the outside of the display device 490. Therefore, the brightness of the display device can be increased. Furthermore, it is possible to suppress the irradiation of transistors 200A and 200B, etc., by light emitted from the light-emitting element 370. This suppresses changes in the electrical characteristics of transistors 200A and 200B, etc. Therefore, reliability can be improved.

[0356] Furthermore, in the display device 490 shown in Figure 21, as an example, a region 490a is provided between the light-emitting element 370 and the substrate 350 where the resin layer 340 is not present. However, a resin layer 340 may be present between the light-emitting element 370 and the substrate 350. Although not shown, for example, another resin layer with a different refractive index may be provided in the region where the resin layer 340 is not present, thereby increasing the amount of light emitted to the outside of the display device 490. Also, although not shown, for example, a microlens may be provided between the light-emitting element 370 and the substrate 350, thereby increasing the amount of light emitted to the outside of the display device 490. Also, although not shown, for example, a fine shape may be provided on the surface of the semiconductor layer 371 on the substrate 350 side of the light-emitting element 370, thereby increasing the amount of light emitted to the outside of the display device 490.

[0357] Furthermore, the method of mounting the light-emitting element 370 is not limited to a specific mounting method. For example, methods using flip-chip bonding or methods using bonding of metal layers can be applied. In addition, for example, a method of monolithically stacking semiconductor layers 371, light-emitting layer 372, and semiconductor layer 373 with pixel electrodes 321 can be applied.

[0358] The above configuration of the light-emitting element 370 and its surroundings is merely an example and is not limited thereto. Therefore, it is not necessary to have at least a part of the above configuration. Furthermore, at least a part of the above configuration can be combined as appropriate.

[0359] In region 490c, a conductive layer 366 is provided on a portion of the insulating layer 218. The conductive layer 366 is in contact with the conductive layer 364 at openings provided in the insulating layer 218 and the insulating layer 209.

[0360] The conductive layer 364 can be provided in the same layer as the conductive layer 208. Therefore, the conductive layer 364 can have the same material as the conductive layer 208 and can be formed in the same process. For example, the conductive layer 208 and the conductive layer 364 can be formed by processing the same conductive film. Also, the conductive layer 366 can be provided in the same layer as the pixel electrode 321. Therefore, the conductive layer 366 can have the same material as the pixel electrode 321 and can be formed in the same process. For example, the pixel electrode 321 and the conductive layer 366 can be formed by processing the same conductive film. In region 490c, the conductive layer 366 is exposed. This allows the conductive layer 366 and the FPC 408 to be connected via the connecting layer 368.

[0361] As the connecting layer 368, an anisotropic conductive film (ACF) or an anisotropic conductive paste (ACP) can be used.

[0362] Furthermore, the contents of this embodiment can be combined as appropriate. Also, the contents of this embodiment can be combined as appropriate with the contents of other embodiments, etc.

[0363] (Embodiment 5) This embodiment describes an indium oxide film that can be used in the semiconductor layer of a transistor according to one aspect of the present invention.

[0364] In this specification, indium oxide having at least a crystalline portion or crystalline region in the film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystal IO or crystalline IO include single-crystal indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0365] Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0366] This paper describes the carrier concentration dependence of the hole mobility of indium oxide, silicon, and IGZO.

[0367] IGZO tends to exhibit higher hole mobility as the carrier concentration increases. On the other hand, single-crystal indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases. This trend is similar to that of silicon, where lower dopant (impurity) concentrations in the material reduce impurity scattering and increase hole mobility. In other words, the higher the purity and intrinsic nature of single-crystal indium oxide, the higher its hole mobility. From these results, it can be said that single-crystal indium oxide, unlike IGZO, is a material with physical properties similar to silicon. Note that when indium oxide is not single-crystal (e.g., polycrystalline), the trend may differ from that of single crystals.

[0368] The range of carrier concentrations suitable for the channel formation region of a transistor is 1 × 10⁻⁶. １５ cm −３ This range includes, for example, 1 × 10 １４ cm −３ The above is 1 x 10 １８ cm −３ The range is as follows: By sufficiently reducing the carrier concentration, the hole mobility value can be increased to 270 cm⁻¹. ２ It can be expected to be raised to the level of / (V・s).

[0369] Indium oxide can contain elements that lower the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. These elements can lower the carrier concentration by substituting for indium. Other examples include nitrogen, phosphorus, arsenic, and antimony. These elements can lower the carrier concentration by substituting for oxygen.

[0370] On the other hand, electrical resistance can be reduced by increasing the carrier concentration. For example, the suitable carrier concentration range for the source and drain regions of a transistor, or for a resistor or transparent conductive film, is when the carrier concentration value is 1 × 10⁻⁶ ２０ cm −３ This range includes, for example, 1 × 10 １９cm −３ The above is 1 x 10 ２２ cm −３ The range is as follows: By making the carrier concentration sufficiently high, the resistivity can be increased to 1 × 10⁻⁶. −４ It is expected that the level can be reduced to below Ω·cm.

[0371] Indium oxide may contain elements that increase the carrier concentration. For example, it is preferable to include elements common to the source and drain electrodes of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use elements in which the oxide is conductive or semiconducting.

[0372] Because indium oxide is an oxide whose valence electrons can be controlled, the region with a low carrier concentration can be used for the channel formation region of the transistor, and the region with a high carrier concentration can be used for the source and drain regions of the transistor. This makes it possible to create a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region). Valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technological concept that would not normally be conceived. By using this technological concept, it is possible to realize a transistor with high mobility, low off-current, normally-off capability, and high reliability.

[0373] The indium oxide film is preferably crystalline. In particular, the indium oxide film is preferably polycrystalline, and more preferably single-crystal. A single-crystal film does not have grain boundaries. By using a single-crystal film, carrier scattering at grain boundaries can be suppressed, enabling the realization of transistors that exhibit high field-effect mobility. Furthermore, it has the excellent effect of suppressing variations in transistor characteristics caused by these grain boundaries.

[0374] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using polycrystalline films, it is preferable to use films with the largest possible grain size and few grain boundaries. In a transistor to which a polycrystalline film is applied, if there are no grain boundaries in the channel formation region, or if no grain boundaries are observed, the channel formation region is located within the single-crystal region contained in the polycrystalline film, and therefore it can be considered a transistor to which a single-crystal film is applied.

[0375] The crystallinity of indium oxide can be analyzed, for example, by XRD, TEM, or ED. Alternatively, a combination of these methods may be used for analysis.

[0376] Furthermore, in this specification, a semiconductor layer in which no grain boundaries are observed in the channel formation region, a semiconductor layer in which the channel formation region is contained within a single crystal grain, or a semiconductor layer in which the crystal axis directions are the same in at least two regions within the channel formation region can be considered as a single crystal film.

[0377] Unless otherwise specified, the channel formation region refers to the region of the semiconductor layer that overlaps with (or faces) the gate electrode via the gate insulating film, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The crystal grains, grain boundaries, crystal axes, and crystal orientation in the channel formation region can be confirmed by cross-sectional observation including the semiconductor layer, source electrode, and drain electrode.

[0378] Impurities in the indium oxide film can act as a source of carrier scattering, thus potentially causing a decrease in field-effect mobility and inhibiting crystal growth. Examples of impurities in the indium oxide film include boron and silicon. In the channel-forming region of the indium oxide film, lower concentrations of these impurities are preferable. For example, the concentration of each of the above impurity elements should be 0.1% or less, more preferably 0.01% (100 ppm) or less. Note that elements such as carbon and hydrogen may be present in the deposition gas or precursor during film formation, and may remain in the indium oxide film in higher concentrations than the above impurities.

[0379] Furthermore, the indium oxide film may contain elements that can become trivalent cations like indium, as long as their crystals maintain a cubic crystal structure (Bixbite type). Examples include Group 13 elements of the periodic table such as gallium and aluminum, and Group 3 elements of the periodic table. Since these elements mainly exist as trivalent cations in the oxide, the carrier concentration of indium oxide can be kept low.

[0380] By using such an indium oxide film in a transistor, the field-effect mobility of the transistor can be increased to 50 cm². ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ It can be set to (V・s) or more.

[0381] One of the characteristics of indium oxide films is their higher oxygen permeability (diffusivity) compared to IGZO films. For example, oxygen diffusing into an indium oxide film permeates the film and is released as oxygen molecules. In some cases, it may also be released as water molecules by reacting with hydrogen contained in the film. Furthermore, if there is an oxygen deficiency in the film, diffusing oxygen atoms will fill the deficiency. Because oxygen diffuses easily through indium oxide films, it can be said that oxygen deficiencies are more easily filled in compared to IGZO films.

[0382] Thus, because indium oxide films are more likely to reduce oxygen vacancies in the film compared to IGZO films, applying such indium oxide films to transistors makes it possible to realize transistors with extremely high reliability.

[0383] Furthermore, the indium oxide film diffuses hydrogen. Hydrogen diffusing into the indium oxide film from the outside permeates the film and is released as hydrogen molecules. Alternatively, it reacts with oxygen contained in the film and is released as water molecules.

[0384] Indium oxide is characterized by a small effective electron mass and a large effective hole mass. Furthermore, the effective electron mass of indium oxide is largely independent of the crystal orientation. Therefore, using crystalline indium oxide in transistors allows for the realization of transistors with high field-effect mobility and high frequency characteristics (also known as f-response). Moreover, due to the large effective hole mass, transistors with extremely low off-currents can be realized. For example, by applying an indium oxide film to a transistor, the off-current per 1 μm of channel width is 1 fA (1 × 10⁻¹⁶) at 125°C. −１５ A) Less than or equal to, or 1aA (1 × 10 −１８ A) Less than or equal to 1aA (1 × 10) in a room temperature (25°C) environment. −１８ A) Less than or equal to, or 1zA (1 × 10⁻¹⁰ −２１ A) The following is possible. Furthermore, because indium oxide has a smaller effective electron mass and a larger effective hole mass than silicon, it may be possible to realize transistors with higher field-effect mobility and lower off-current than Si transistors.

[0385] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. It is preferable to use a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with the indium oxide for the seed layer. This improves the crystallinity of the indium oxide film. A substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0386] One method for evaluating the degree of lattice mismatch is to use the following lattice mismatch value. The lattice mismatch Δa [%] of the crystals in the formed film (in this case, the indium oxide film) relative to the crystals in the seed layer is given by Δa = ((L １ -L ２ ) / L ２ It is calculated as ) × 100. Here L １ L is the length of the unit cell vector of the crystals in the formed film, or the lattice constant. ２is the length of the unit cell vector of the crystal in the seed layer, or the lattice constant.

[0387] The lattice mismatch Δa between the seed layer and the indium oxide film is preferably small in absolute value, and most preferably zero. For example, Δa can be -5% or more and 5% or less, preferably -4% or more and 4% or less, more preferably -3% or more and 3% or less, and even more preferably -2% or more and 2% or less.

[0388] Here, the indium oxide crystal has a cubic structure (bixbite type). For example, yttria-stabilized zirconia (YSZ) crystals can have a cubic structure (fluorite type). The lattice mismatch of the indium oxide crystal with respect to the cubic YSZ crystal is in the range of -2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on a YSZ substrate.

[0389] Furthermore, the crystal structure of the seed layer and the crystal structure of the indium oxide film do not necessarily have to be the same in terms of crystal system or crystal orientation. For example, a film with a hexagonal or trigonal crystal structure can be used beneath an indium oxide film with a cubic crystal structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to crystal orientation necessary for epitaxial growth can be met. Examples of hexagonal or trigonal crystals include wurtzite-type structures and YbFe. ２ O ４ Type structure, Yb ２ Fe ３ O ７ These include type structures and their modified type structures. YbFe ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a type structure is IGZO.

[0390] Furthermore, the contents of this embodiment can be combined as appropriate. Also, the contents of this embodiment can be combined as appropriate with the contents of other embodiments, etc.

[0391] (Embodiment 6) This embodiment describes an electronic device according to one aspect of the present invention.

[0392] The electronic device shown in this embodiment has a display unit that uses a display device according to one aspect of the present invention, or a semiconductor device according to one aspect of the present invention. The display device according to one aspect of the present invention facilitates either or both high resolution and high definition. Therefore, it can be used in the display units of various electronic devices.

[0393] Furthermore, a semiconductor device according to one aspect of the present invention can be applied to devices other than the display unit of an electronic device. For example, using a semiconductor device according to one aspect of the present invention in the control unit of an electronic device is preferable because it enables lower power consumption.

[0394] Examples of electronic devices include those with relatively large screens, such as television sets, desktop or notebook computers, computer monitors, digital signage, and large game machines like pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, personal digital assistants, and audio playback devices.

[0395] In particular, a display device according to one aspect of the present invention can be used in electronic devices having a relatively small display area because it can increase the resolution. Examples of such electronic devices include wearable devices that can be worn on the wrist (watch-type information terminals, bracelet-type information terminals, etc.), wearable devices that can be worn on the head (VR devices such as head-mounted displays, AR devices such as glasses, SR (Substitutional Reality) devices, MR (Mixed Reality) devices, devices that implement spatial computing such as spatial computers, etc.).

[0396] A display device according to one aspect of the present invention preferably has an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels). In particular, a resolution of 4K, 8K, or higher is preferred. Furthermore, the pixel density (resolution) of the display device according to one aspect of the present invention is preferably 100 ppi or more, preferably 300 ppi or more, more preferably 500 ppi or more, more preferably 1000 ppi or more, more preferably 2000 ppi or more, more preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 7000 ppi or more. By using a display device having high resolution and / or high detail, it is possible to enhance at least one of the following: a sense of presence and a sense of depth. Furthermore, there are no particular limitations on the aspect ratio of the display device according to one embodiment of the present invention, and various aspect ratios such as 1:1 (square), 4:3, 16:9, or 16:10 can be used.

[0397] The electronic device shown in this embodiment may have sensors (including functions for detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation).

[0398] The electronic device shown in this embodiment may include a processing unit, a memory device, an input device, an output device, a control device, and the like. A semiconductor device according to one aspect of the present invention may be applied to the processing unit, memory device, input device, output device, control device, and the like of the electronic device.

[0399] The electronic device shown in this embodiment can have a variety of functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, time, etc., a function to control processing by various software (programs), a wireless communication function, a function to read and process programs or data recorded on a recording medium, etc. However, the functions of the electronic device are not limited to these and can have a variety of functions. The electronic device may have multiple display units. The electronic device may also have a camera and may have a function to take still images or videos with the camera, a function to save the captured images to a recording medium provided outside or inside the camera, a function to display the captured images on a display unit, etc.

[0400] Figure 22A shows an example of an electronic device that can be used as a portable information terminal, such as a smartphone.

[0401] The electronic device 8100 includes a housing 8101, a display unit 8102, a power button 8103, operation buttons 8104, a speaker 8105, a microphone 8106, a camera 8107, and a light source 8108. The display unit 8102 may also function as a touch panel.

[0402] A display device according to one embodiment of the present invention can be applied to the display unit 8102.

[0403] Figure 22B shows an example of an electronic device that can be used as a smartwatch or other wristwatch-type information terminal.

[0404] The electronic device 8200 includes a housing 8201, a display unit 8202, a power key 8203, operation keys 8204, a speaker 8205, a microphone 8206, a sensor 8207, and connection terminals 8208. The display unit 8202 is curved.

[0405] A display device according to one embodiment of the present invention can be applied to the display unit 8202.

[0406] Furthermore, the electronic device 8200 can communicate with a wireless headset to enable hands-free calling. The electronic device 8200 can also transmit data to other electronic devices and be charged via its connection terminal 8208. Charging may be performed via wireless power supply.

[0407] Figure 22C shows an example of an electronic device that can be used as a television system, etc.

[0408] The electronic device 8300 includes a housing 8301 and a display unit 8302, etc. The housing 8301 is supported by a stand 8303.

[0409] A display device according to one aspect of the present invention can be applied to the display unit 8302.

[0410] The electronic device 8300 can be operated using the operation switches on the housing 8301 or a separate remote control. The display unit 8302 may also function as a touch panel, and the electronic device 8300 can be operated by touching the display unit 8302 with a finger or other object.

[0411] The electronic device 8300 may also include a receiver and a modem. The receiver can receive general television broadcasts. Furthermore, by connecting to a wired or wireless communication network via the modem, it is possible to perform one-way (from sender to receiver only) or two-way (between sender and receiver, or between receivers, etc.) information communication.

[0412] Figure 22D shows an example of an electronic device that can be used as a notebook computer or the like.

[0413] The electronic device 8400 includes a housing 8401, a display unit 8402, a keyboard 8403, a pointing device 8404, and an external connection port 8405.

[0414] A display device according to one embodiment of the present invention can be applied to the display unit 8402.

[0415] Figure 22E shows an example of an electronic device that can be used as digital signage, etc.

[0416] The electronic device 8500 has a display unit 8501 and the like. The electronic device 8500 is attached along the curved surface of a columnar pillar 8509.

[0417] The display device according to one aspect of the present invention can be applied to the display unit 8501.

[0418] In the electronic device 8500, the display unit 8501 may have a function as a touch panel. Thereby, the electronic device 8500 can be intuitively operated. For example, when the electronic device 8500 is used for applications such as providing route information or traffic information, the usability can be enhanced by intuitive operation.

[0419] Further, the electronic device 8500 may be capable of wireless communication and cooperation with an information terminal device 8508 such as a smartphone possessed by a user. For example, the advertisement information displayed on the display unit 8501 can be displayed on the screen of the information terminal device 8508. Also, the display of the display unit 8501 can be switched by operating the information terminal device 8508. Further, a game using the screen of the information terminal device 8508 as an operation means (controller) can be executed on the electronic device 8500. Thereby, a plurality of users can participate in the game simultaneously and enjoy it.

[0420] FIG. 22F shows an example of an electronic device attached to the periphery of a windshield in an automobile interior.

[0421] The electronic device 8600 has display units 8601, 8602, and 8603 attached to the dashboard, a display unit 8604 attached to a pillar, and a main body 8605.

[0422] The display device according to one aspect of the present invention can be applied to each of the display units 8601, 8602, 8603, and 8604.

[0423] Note that each of display units 8601 to 8604 can display various information transmitted from the main body 8605 by wired communication or wireless communication. For example, each of display units 8601 to 8603 can display various information such as navigation information, speedometer, tachometer, driving distance, fuel gauge, gear state, air conditioning settings, and the like. The display unit 8604 can display an image from imaging means provided outside the vehicle in order to enhance safety by complementing the field of view (blind spot) blocked by the pillar.

[0424] FIG. 22G shows an example of a glasses-type electronic device that can be used for AR devices and the like.

[0425] The electronic device 8700 includes a main body 8701, a display unit 8702, a mounting unit 8703, a lens 8704, and the like. A battery 8705 is provided in the mounting unit 8703. The battery 8705 is connected to the main body via a cable 8706.

[0426] The display device according to an aspect of the present invention can be applied to the display unit 8702.

[0427] In the electronic device 8700, for example, since the main body 8701 has a wireless receiver or the like, video information such as received image data can be displayed on the display unit 8702. Also, for example, since the main body 8701 has a camera, it is possible to capture the movement of the user's eyeball or eyelid, etc., and calculate the user's line of sight based on that information, so that the user's line of sight can be used as an input means.

[0428] In the electronic device 8700, a plurality of electrodes may be provided at positions where the user touches in the mounting unit 8703. Thereby, the electronic device 8700 may have a function of recognizing the user's line of sight by detecting the current flowing through the electrodes as the user's eyeball moves. Also, it may have a function of monitoring the user's pulse by detecting the current flowing through the electrodes.

[0429] Furthermore, the electronic device 8700 may have various sensors to display the user's biometric information on the display unit 8702. It may also have a function to detect the user's head movements and change the image displayed on the display unit 8702 in accordance with those movements.

[0430] Figure 22H shows an example of a head-mounted display type electronic device that can be used for VR equipment and the like.

[0431] The electronic device 8800 includes a housing 8801, a display unit 8802, operation buttons 8803, and a fixing device 8804. A battery 8805 is provided in the fixing device 8804.

[0432] A display device according to one embodiment of the present invention can be applied to the display unit 8802.

[0433] Furthermore, since the electronic device 8800 has two display units 8802, the user can view one display unit with each eye. This allows for the display of high-resolution images even when performing 3D displays using parallax.

[0434] Furthermore, the contents of this embodiment can be combined as appropriate. Also, the contents of this embodiment can be combined as appropriate with the contents of other embodiments, etc.

[0435] (Notes regarding the description in this specification, etc.) The above embodiments and descriptions of each component in the embodiments are provided below.

[0436] In this specification, a semiconductor device refers to any device that can function by utilizing semiconductor properties. For example, semiconductor elements such as transistors, electronic circuits containing semiconductor elements, chips with electronic circuits formed on a substrate, electronic components with chips housed in a package, and electronic devices on which electronic components are mounted are examples of semiconductor devices. In addition, display devices, light-emitting devices, projection devices, illumination devices, optical devices, electro-optical devices, imaging devices, light-receiving devices, detection devices, power supply devices, energy storage devices, communication devices, arithmetic units, control devices, arithmetic processing units, memory devices, input devices, output devices, input / output devices, signal processing devices, information processing devices, computers, and electronic devices may have semiconductor devices and can be said to be semiconductor devices themselves.

[0437] In this specification, a "transistor" has three terminals called the "gate" (also called the gate terminal, gate region, or gate electrode), the "source" (also called the source terminal, source region, or source electrode), and the "drain" (also called the drain terminal, drain region, or drain electrode). A transistor also has a region where a channel is formed between the drain and the source (also called the channel formation region). A transistor can pass current between the source and the drain through the channel formation region. Furthermore, a transistor can generate electrical signals or potential interactions between the source and the drain through the channel formation region. The channel formation region is the region where current primarily flows. The gate is a control terminal that controls the amount of current flowing through the channel formation region. The two terminals that function as the source or drain are input / output terminals that input or output the current flowing through the channel formation region.

[0438] The two input / output terminals function as either a source or a drain, depending on the transistor's conductivity type (n-channel or p-channel) and the potential applied to its three terminals. Furthermore, the source and drain functions may be reversed when the direction of current changes during circuit operation. Therefore, the terms "source" and "drain" are interchangeable. When describing the connections of a transistor, the expressions "one of the source or drain" (or first electrode, first terminal, etc.) and "the other of the source or drain" (or second electrode, second terminal, etc.) should be used.

[0439] In addition to the three terminals mentioned above, transistors may have a terminal called a "back gate" (also called the back gate terminal, back gate region, or back gate electrode). In this case, one of the gates or back gate of the transistor may be called the first gate, and the other of the gates or back gate may be called the second gate. Also, in the same transistor, the terms "gate" and "back gate" may be interchangeable. Furthermore, if a transistor has three or more gates, each gate may be called the first gate, second gate, third gate, and so on.

[0440] Furthermore, the voltage between the gate and source (gate-source) (unless otherwise specified, the potential of the source is used as the reference) is sometimes called the "gate voltage," the voltage between the drain and source (drain-source) (unless otherwise specified, the potential of the source is used as the reference) is sometimes called the "drain voltage," and the voltage between the back gate and source (back gate-source) (unless otherwise specified, the potential of the source is used as the reference) is sometimes called the "back gate voltage." Also, the current flowing between the drain and source (unless otherwise specified, the direction from drain to source is considered positive) is sometimes called the "drain current." Note that in n-channel transistors, expressions such as high gate voltage, high drain voltage, and high back gate voltage can be appropriately substituted for each other, and in p-channel transistors, expressions such as low gate voltage, low drain voltage, and low back gate voltage can be appropriately substituted for each other. Similarly, in n-channel transistors, expressions such as low gate voltage, low drain voltage, and low back gate voltage can be appropriately substituted for each other, and in p-channel transistors, expressions such as high gate voltage, high drain voltage, and high back gate voltage can be appropriately substituted for each other.

[0441] The "conducting state" or "on state" of a transistor refers to, for example, a state in which the source and drain of the transistor can be considered to be electrically short-circuited, a state in which the gate voltage is higher than the threshold voltage in an n-channel transistor, or a state in which the gate voltage is lower than the threshold voltage in a p-channel transistor. The "non-conducting state" or "off state" of a transistor refers to, for example, a state in which the source and drain of the transistor can be considered to be electrically disconnected, a state in which the gate voltage is lower than the threshold voltage in an n-channel transistor, or a state in which the gate voltage is higher than the threshold voltage in a p-channel transistor.

[0442] Furthermore, unless otherwise specified, the "off-current" of a transistor refers to the drain current when the transistor is in the off state. Note that the off-current and the current flowing between the gate, source, and drain (also called gate leakage current) are sometimes collectively referred to as leakage current.

[0443] In this specification, "capacitive element" refers to a circuit element having a configuration in which a pair of electrodes are provided with a dielectric material in between. However, capacitive elements are not limited to this and may include, for example, parasitic capacitance between two wires, gate capacitance between the source and drain of a transistor and the gate, etc. Furthermore, terms such as "capacitive element," "parasitic capacitance," and "gate capacitance" may be interchangeable with terms such as "capacitance" and "electrostatic capacitance." In addition, terms such as "pair of electrodes," "pair of wires," "pair of terminals," and "pair of conductive layers" of a capacitive element may be interchangeable.

[0444] In this specification, "switch" refers to a circuit element having multiple terminals and having the function of switching (selecting) the conduction or non-conductivity between those terminals. A switch can be said to have the function of controlling whether or not to allow current to flow between multiple terminals, or the function of controlling whether or not to generate the transmission or reception of electrical signals or the interaction of potentials between multiple terminals. For example, if a switch has two terminals, the state in which the two terminals can be considered to be electrically short-circuited is called the "conducting state" or "on state". Conversely, the state in which the two terminals can be considered to be electrically disconnected is called the "non-conducting state" or "off state". Note that electrical switches, mechanical switches, etc., can be used as switches.

[0445] In this specification, a single circuit element shown in a circuit diagram includes cases where multiple such circuit elements are connected in series, parallel, or series-parallel.

[0446] In this specification, a signal line refers to wiring to which a signal is supplied, and a power line refers to wiring to which a constant potential is supplied. Therefore, the terms "signal line" and "power line" can sometimes be replaced with the term "wiring." For example, a signal line can be considered to have a constant potential if the signal supplied to it does not change. Similarly, a power line can be considered to have a signal if the potential supplied to it changes. Therefore, the terms "potential" and "signal" supplied to wiring can sometimes be interchangeable.

[0447] In this specification, voltage refers to the potential difference from a reference potential (such as ground potential). Therefore, the terms "voltage" and "potential" can sometimes be used interchangeably.

[0448] In this specification, the terms "electrode," "wiring," and "terminal" do not functionally limit these components. Therefore, an electrode may be part of wiring or a terminal, wiring may be part of an electrode or a terminal, and a terminal may be part of an electrode or wiring. Furthermore, "electrode or wiring" includes cases where multiple electrodes or multiple wirings are integrated. Similarly, "terminal" includes cases where multiple electrodes, multiple wirings, or multiple terminals are integrated. Additionally, the terms "electrode," "wiring," and "terminal" may be replaced with terms such as "region" or "conductive layer."

[0449] In this specification, the term "node" may be replaced with terms such as "electrode," "wiring," "terminal," "region," or "conductive layer," depending on the circuit configuration, device structure, etc. Conversely, terms such as "electrode," "wiring," and "terminal" may be replaced with the term "node."

[0450] In this specification, terms containing the words "layer" and "film" may be interchangeable. For example, the terms "conductive layer" and "conductive film" may be interchangeable. For example, the terms "insulating layer" and "insulating film" may be interchangeable. For example, the terms "semiconductor layer" and "semiconductor film" may be interchangeable. Furthermore, in terms containing the words "layer" and "film," these terms may be replaced with other terms. For example, the terms "conductive layer" and "conductive film" may be interchangeable with the term "conductor." For example, the terms "insulating layer" and "insulating film" may be interchangeable with the term "insulator."

[0451] In this specification, terms such as "above" and "below" are used for convenience to describe the positional relationships of the constituent elements. Therefore, these terms can be replaced with other terms and the expression can be appropriately modified. For example, the expression "Element B is located above Element A, and Element C is located below Element A" can be changed to "Element B is located below Element A, and Element C is located above Element A." Similarly, the expression "Element B is located above Element A, and Element C is located below Element A" can be changed to "Element B is located to the left (or right) of Element A, and Element C is located to the right (or left) of Element A." It should be noted that when using the terms "above" or "below," the positional relationship of the constituent elements is not limited to directly above or directly below. Therefore, the term "above" can be replaced with terms such as "upper," "upper side," or "upper layer," and the term "below" can be replaced with terms such as "downward," "lower side," or "lower layer." Furthermore, for example, the expression "element B on element A" is not limited to cases where element B is placed in contact with element A, but also includes cases where other elements (including space) are provided between element A and element B.

[0452] In this specification, "parallel" does not mean strictly parallel. Unless otherwise specified, "parallel" may include a state in which two lines or planes are positioned at an angle of -5° to 5°. Alternatively, it may include a state in which two lines or planes are positioned at an angle of -10° to 10°. Or, it may include a state in which two lines or planes are positioned at an angle of -30° to 30°. Therefore, the term "parallel" may be replaced with terms such as "approximately parallel" or "substantially parallel." Also, "parallel" may mean "parallel or approximately parallel."

[0453] In this specification, "perpendicular" does not mean strictly perpendicular. Unless otherwise specified, "perpendicular" may include a state in which two lines or planes are positioned at an angle of 85° to 95°. Alternatively, it may include a state in which two lines or planes are positioned at an angle of 80° to 100°. Or, it may include a state in which two lines or planes are positioned at an angle of 60° to 120°. Therefore, the term "perpendicular" may be replaced with terms such as "approximately perpendicular" or "substantially perpendicular." Also, "perpendicular" may mean "perpendicular or approximately perpendicular."

[0454] In this specification, when terms such as "identical," "same," "equal," "simultaneous," "consistent," and "uniform" (including their synonyms) are used in reference to count values, measured values, etc., these terms shall include errors. Therefore, unless otherwise specified, these terms may include an error of plus or minus 10%, or an error of plus or minus 20%. Thus, "identical" may mean "identical or approximately identical," "same" may mean "same or approximately the same," "equal" may mean "equal or approximately equal," "simultaneous" may mean "simultaneous or approximately simultaneous," "consistent" may mean "consistent or approximately consistent," and "uniform" may mean "uniform or approximately uniform."

[0455] In this specification, ordinal numbers such as "first," "second," etc., are used to avoid confusion of components and do not limit the number of components, their order, etc. For example, a component referred to as "first" in one embodiment may be referred to as "second" in other embodiments, claims, etc. Also, for example, a component referred to as "first" in one embodiment may be omitted in other embodiments, claims, etc. Furthermore, even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims. Also, even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Furthermore, even if a term has an ordinal number in this specification, an ordinal number may be omitted in the claims.

[0456] In this specification, one of the source or drain (also called the two input / output terminals) of a transistor may be referred to as the first terminal, and the other of the source or drain of a transistor may be referred to as the second terminal. Therefore, a transistor has at least a gate (also called the gate terminal), a first terminal, and a second terminal. In addition, one terminal of a capacitive element (also called one of a pair of terminals) may be referred to as the first terminal, and the other terminal of a capacitive element (also called the other of a pair of terminals) may be referred to as the second terminal. In addition, one terminal of a display element may be referred to as the first terminal, and the other terminal of a display element may be referred to as the second terminal. In addition, one terminal of a liquid crystal element may be referred to as the first terminal, and the other terminal of a liquid crystal element may be referred to as the second terminal. In addition, one terminal of a light-emitting element may be referred to as the first terminal, and the other terminal of a light-emitting element may be referred to as the second terminal. In addition, one terminal of a light-receiving element may be referred to as the first terminal, and the other terminal of a light-receiving element may be referred to as the second terminal. In addition, one of the anode or cathode of a diode (also called one of the pair of terminals) is sometimes called the first terminal, and the other of the anode or cathode of a diode (also called the other of the pair of terminals) is sometimes called the second terminal.

[0457] "Connection" as used in this specification includes, for example, "electrical connection". In order to define the connection relationship of circuit elements as a physical entity, when expressing "electrical connection", "electrical connection" includes, for example, "direct connection" and "indirect connection". "A and B are directly connected" means, for example, that A and B are connected without passing through a circuit element (for example, a transistor or a switch, etc. Note that wiring is not a circuit element). On the other hand, "A and B are indirectly connected" means, for example, that A and B are connected through one or more circuit elements. Note that A, B, and C described below represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0458] Here, when defining "A and B are indirectly connected", it means, for example, the connection relationship in the following cases. That is, assuming that the circuit is operating, if there is a timing during the operation period of the circuit when an electrical signal is transmitted or received or a potential interaction occurs between A and B, such a circuit can be defined as "A and B are indirectly connected" as a physical entity. Note that even if there is a timing when no electrical signal is transmitted or received or potential interaction occurs between A and B, if there is a timing during the operation period of the circuit when an electrical signal is transmitted or received or a potential interaction occurs between A and B, it can be defined as "A and B are indirectly connected". Note that "A and B are indirectly connected" is defined as a physical entity for the connection relationship of circuit elements. Therefore, for example, even when the circuit is not supplied with a power supply voltage and the circuit is not operating, the circuit can be defined as "A and B are indirectly connected" as a physical entity (however, for example, only when the circuit is supplied with a power supply voltage and operates, and an electrical signal is transmitted or received or a potential interaction occurs between A and B during the operation period of the circuit).

[0459] The following are specific examples of "indirect connections". First, an example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors, as shown in Figures 23A1 and 23A2. Another example of a case where "A and B are indirectly connected" is when A and B are connected via one or more switches. When "A and B are indirectly connected", assuming the circuit is operating, one transistor between A and B will be in an ON state, conducting state, or a state in which current can flow at least once. Note that when "A and B are indirectly connected", this includes the case where one transistor between A and B is in an OFF state or a non-conducting state. When "A and B are indirectly connected" and multiple transistors are connected between A and B, assuming the circuit is operating, each of the multiple transistors between A and B will be in an ON state, conducting state, or a state in which current can flow at least once. In other words, when "A and B are indirectly connected," it is not necessary for all of the transistors to be in an ON state, a conducting state, or a state in which current can flow simultaneously. Therefore, when "A and B are indirectly connected," it includes cases where the transistors between A and B are in an OFF state or a non-conducting state at the same time or at different times. As another example, as shown in Figure 23A3, when A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected," "B and C are indirectly connected," or "A and B are indirectly connected." However, as will be discussed later, if a constant potential V is supplied to C from a power supply or GND, it can be said that "A and C are indirectly connected," or "B and C are indirectly connected," but it cannot be said that "A and B are indirectly connected."

[0460] Having shown examples of cases where a connection can be considered "indirect" and cases where it cannot, let's look at another example of a case where a connection cannot be considered "indirect." Even if electrical signals are exchanged or potential interactions occur between A and B during the operation of the circuit, there are exceptional cases where it cannot be said that "A and B are indirectly connected." An example of such an exceptional case is when A and B are connected via an insulator. In other words, when A and B are connected via an insulator, it cannot be said that "A and B are indirectly connected." A specific example of when A and B are connected via an insulator is when a capacitive element is connected between A and B, as shown in Figure 23A4. Another example of when A and B are connected via an insulator is when a transistor gate insulating film is interposed between A and B, as shown in Figure 23A5. In this case, it cannot be said that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected."

[0461] Another example of a situation where it cannot be said that "A and B are indirectly connected" is when there is no timing for the exchange of electrical signals or potential interaction between A and B. For example, as shown in Figures 23A6 and 23A7, multiple transistors are connected via source and drain in the path from A to B, and a constant potential V is supplied to the nodes between the transistors from a power source or GND. In this case, it cannot be said that "A and B are indirectly connected," but it can be said that "A and V are indirectly connected," or "B and V are indirectly connected." In Figure 23A3, if A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, and a constant potential V is supplied to C from a power supply or GND, then the connection relationship is the same as in Figures 23A6 and 23A7, so it cannot be said that "A and B are indirectly connected," but it can be said that "A and C are indirectly connected" or "B and C are indirectly connected."

[0462] As shown above, we have provided an example of "indirect connection." As an example, the provisions for "indirect connection" are included in the provisions for "electrical connection," so if "A and B are indirectly connected," then "A and B are electrically connected."

[0463] Next, we will show specific examples of "direct connection." Examples of cases where "A and B are directly connected" include cases where A and B are connected without a circuit element in between, as shown in Figures 23B1, 23B2, and 23B3. Furthermore, as shown in Figures 23B4 and 23B5, when A and B are connected to a power supply that provides a constant potential V, or to GND, without a circuit element in between, we can say that "A and B are directly connected," "A and V are directly connected," or "B and V are directly connected." Furthermore, as shown in Figure 23B6, even when A (or B) is connected to a constant potential V via the source and drain of a transistor, we can say that "A and B are directly connected." Furthermore, since A and V, or B and V, are connected via the source and drain of a transistor, they cannot be said to be directly connected, and we can say that "A and V are indirectly connected," or "B and V are indirectly connected."

[0464] As shown above, an example of "direct connection" has been given, but as an example, since the provisions for "direct connection" are included in the provisions for "electrical connection," if "A and B are directly connected," then "A and B are electrically connected."

[0465] 100: Semiconductor device, 101: Filter, 102: Amplifier, 110: Drive circuit, 111: Register, 160: Display device, 161: Pixel, 162: Pixel section, 163: Gate driver section, 164: Source driver section, 165: Gate line, 166: Source line, 167: Control section, M11: Transistor, M11a: Transistor, M11b: Transistor, M12: Transistor, M13: Transistor, M14: Transistor, M15: Transistor, M 16: Transistor, M17: Transistor, M18: Transistor, M21: Transistor, M22: Transistor, M23: Transistor, M24: Transistor, M25: Transistor, M26: Transistor, M27: Transistor, M31: Transistor, M32: Transistor, M33: Transistor, M34: Transistor, MS11: Transistor, MC11: Transistor, C11: Capacitive element, C12: Capacitive element, C21: Capacitive element Child, C31: Capacitive element, LD: Light-emitting element, VLD1: Wiring, VLD1a: Wiring, VLD2: Wiring, VLD3: Wiring, VLS1: Wiring, VLS1a: Wiring, VLS1b: Wiring, VLS2: Wiring, VLS3: Wiring, VLB1: Wiring, VLB2: Wiring, VLC: Wiring, OL: Wiring, BGL: Wiring, CKL: Wiring, CKL1: Wiring, CKL2: Wiring, IL1: Wiring, IL2: Wiring, SRL: Wiring, ANO: Wiring, CATH: Wiring, VL31: Wiring, SWPL: Wiring, GLa: Wiring, GLb: Wiring, SLa: Wiring, SLb: Wiring, ND11: Node, ND12: Node, ND13: Node, ND14: Node, ND15: Node, R11: Resistor, S12: Switch, S15: Switch, 200: Transistor, 200A: Transistor, 200B: Transistor, 370: Light-emitting element, 400: Display device, 411: Pixel, 412: Pixel, 412R: Pixel, 412G: Pixel, 412B: Pixel, 490: Display device

Claims

It comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a first capacitive element. The first terminal of the first transistor is electrically connected to the first terminal of the second transistor, the gate of the third transistor, and the first terminal of the first capacitive element. The first terminal of the third transistor is electrically connected to the first terminal of the fourth transistor. The second terminal of the first transistor is electrically connected to the first terminal of the fifth transistor. The channel length of the first transistor is greater than the channel length of the third transistor. The channel length of the third transistor is greater than the channel length of the second transistor. Semiconductor equipment. 　 In claim 1, The gates of the second transistor and the fifth transistor are supplied with signals whose logic is inverted relative to each other. Semiconductor equipment. 　 In claim 1, Each of the first to fifth transistors is an n-channel transistor. A first potential is applied to the gate of the first transistor. A second potential is applied to either the second terminal of the second transistor or the second terminal of the fifth transistor. A third potential is applied to the other of the second terminal of the second transistor or the second terminal of the fifth transistor. The second terminal of the first capacitance element is supplied with the first potential, the second potential, or the third potential. The first potential is greater than the second potential and less than the third potential. Semiconductor equipment. 　 In claim 3, A fourth potential is applied to the second terminal of the third transistor. A fifth potential is applied to the second terminal of the fourth transistor. A sixth potential is applied to the gate of the fourth transistor. The aforementioned fourth potential is greater than the aforementioned third potential. The fifth potential is smaller than the second potential. The sixth potential is greater than the fifth potential and less than the fourth potential. Semiconductor equipment. 　 In claim 1, The channel width of the first transistor is smaller than the channel width of the second transistor. The channel width of the second transistor is smaller than the channel width of the third transistor. Semiconductor equipment. 　 In claim 1, Each of the first to fifth transistors includes an oxide semiconductor in its channel formation region. Semiconductor equipment. 　 A semiconductor device according to claim 1, and a pixel, The aforementioned pixel has a sixth transistor and a second capacitance element, The first terminal of the third transistor is electrically connected to the first terminal of the sixth transistor or the first terminal of the second capacitive element. The gate of the sixth transistor is electrically connected to the second terminal of the second capacitive element. Display device. In claim 7, The aforementioned pixel comprises a seventh transistor and a light-emitting element. The second terminal of the sixth transistor is electrically connected to the gate of the seventh transistor. The first terminal of the seventh transistor is electrically connected to the first terminal of the light-emitting element. Display device.

Images