Barrier and liner for interconnects

Abstract

Embodiments herein provide a method for forming an interconnect structure, comprising: depositing a barrier layer over one or more surfaces of a feature formed in a surface of a substrate, wherein the barrier layer comprises manganese, and the one or more surfaces of the feature comprise one or more sidewall surfaces and a bottom surface; depositing a liner layer over the barrier layer, wherein the liner layer comprises ruthenium; and filling the feature with an interconnect material, wherein filling the feature comprises depositing the interconnect material on the deposited liner layer.

Description

PATENTAttorney Docket No.: 44025298WO01BARRIER AND LINER FOR INTERCONNECTSBACKGROUNDField

[0001] Embodiments described herein generally relate to methods for depositing layers on a substrate.Description of the Related Art

[0002] Integrated circuits can include more than one million micro-electronic field effect transistors (e.g., complementary metal-oxide-sem iconductor (CMOS) field effect transistors) that are formed on a substrate (e.g., semiconductor wafer) and cooperate to perform various functions within the circuit. Reliably producing smaller features is one of the key technologies for the next generation of very large scale integration (VLSI) and ultra large-scale integration (ULSI) of semiconductor devices. However, as the limits of integrated circuit technology are pushed, the shrinking dimensions of interconnects in VLSI and ULSI technology have placed additional demands on processing capabilities. Reliable formation of the interconnecting features within a device structure is important to the successful formation of integrated circuits and to the continued effort to increase circuit density and quality of individual substrates and dies.

[0003] Conventional methods of deposition have issues depositing materials in critical dimension (CD) openings associated with VLSI and ULSI technology (e.g., less than about 12 nm) due to pinch off of the deposited films. Poor step coverage, overhang, and voids can be formed within features, such as vias or trenches, when the feature has a CD of less than about 12 nm. Furthermore, insufficient deposition on the bottom and sidewalls of the vias or trenches can result in deposition discontinuity, thereby resulting in device open circuitry or poor interconnect formation. Too much deposition on the bottom wall of vias can also result in increased resistance for interconnect structures due to the presence of materials that have a higher resistivity than the desired interconnect material (e.g., copper (Cu)). Interconnect structures include contact junctions that allow connections between semiconductor device structures and electrical signal transferringPATENTAttorney Docket No.: 44025298WO01 interconnects. Contact junctions, or simply contacts, with a low resistivity are desirable in semiconductor devices. However, when contacts have high resistance, the contacts adversely affect device performance. The need for multiple metal layers within conventional interconnect contacts, such as barrier and liner layers within copper (Cu) containing interconnects, contribute to the resistance within the contact junction.

[0004] Moreover, a metal layer deposited in such features may also have poor adhesion over the underlying material layer(s), resulting in peeling of the metal layer from the substrate and the subsequently deposited conductive metal layer. Deposited metals can also agglomerate under thermal stress, creating weak points in the deposited metal layer.

[0005] There is a need for an apparatus and a method of depositing metal layers in small-width critical dimension features. Moreover, there is a need for improved methods of forming a device contact that has a reduced overall resistance and solves the problems described above.SUMMARY

[0006] The present disclosure generally relates to methods for forming an interconnect structure.

[0007] Embodiments of the disclosure include a method for forming an interconnect structure, comprising: depositing a barrier layer over one or more surfaces of a feature formed in a surface of a substrate, wherein the barrier layer comprises manganese, and the one or more surfaces of the feature comprise one or more sidewall surfaces and a bottom surface; depositing a liner layer over the barrier layer, wherein the liner layer comprises ruthenium; and filling the feature with an interconnect material, wherein filling the feature comprises depositing the interconnect material on the deposited liner layer. The method may further comprise selectively forming a Self-Assembled Monolayer (SAM) layer over the one or more surfaces of the feature before depositing the barrier layer over the one or more surfaces of the feature, wherein the Self-Assembled Monolayer (SAM) layer is formed on the bottom surface, and the bottom surface comprises an interconnect8760359_1 2PATENTAttorney Docket No.: 44025298WO01 material. The method may also further comprise removing the Self-Assembled Monolayer (SAM) layer from the one or more surface of the feature before depositing the liner layer and after depositing the barrier layer over the one or more surfaces of the feature, wherein removing the SAM layer comprises exposing the one or more surfaces of the feature to a direct plasma treatment. The method also further comprise heating the interconnect material, the liner layer, and the barrier layer to a first temperature after filling the feature with the interconnect material. The method may further comprise heating the liner layer and the barrier layer to a second temperature before filling the feature with the interconnect material.

[0008] Embodiments of the disclosure include a method for forming an interconnect structure, comprising: depositing a first barrier layer over one or more surfaces of a feature formed in a surface of a substrate, wherein the barrier layer comprises manganese, and the one or more surfaces of the feature comprise one or more sidewall surfaces and a bottom surface; depositing a second barrier layer over the one or more surfaces of the feature, the second barrier layer comprising tantalum; depositing a liner layer on the second barrier layer, wherein the liner layer comprises ruthenium; and filling the feature with an interconnect material, wherein filling the feature comprises depositing the interconnect material on the deposited liner layer.

[0009] Embodiments of the disclosure include a method for forming an interconnect structure, comprising: selectively forming a Self-Assembled Monolayer (SAM) layer over one or more surfaces of a feature formed in a surface of a substrate, wherein the one or more surfaces of the feature comprise one or more sidewall surfaces and a bottom surface, and the Self-Assembled Monolayer (SAM) layer is formed on at least one surface of the one or more surfaces of the feature, and the at least one surface comprises a first interconnect material. Then depositing a barrier layer over one or more surfaces of a feature after selectively forming the Self-Assembled Monolayer (SAM) layer, wherein the barrier layer comprises manganese, depositing a liner layer over the barrier layer, wherein the liner layer comprises ruthenium; and filling the feature with a second interconnect material, wherein filling the feature comprises depositing the interconnect material on the deposited liner layer.8760359_1 3PATENTAttorney Docket No.: 44025298WO01

[0010] In certain embodiments, a method for forming an interconnect structure includes forming a feature on a substrate, where the feature comprises one or more sidewalls. A barrier layer containing manganese is deposited on one or more sidewalls of the feature. Subsequently, a liner layer comprising a metal, such as ruthenium (Ru), cobalt (Co), titanium (Ti), or tantalum (Ta), is deposited over the barrier layer.

[0011] In certain embodiments, a method for forming an interconnect structure includes forming a feature on a substrate, with the feature comprising one or more sidewalls. A first barrier layer comprising manganese is deposited over the sidewalls, followed by a second barrier layer comprising tantalum, which is also deposited over the sidewalls. A ruthenium liner layer is deposited over both the first and second barrier layers.

[0012] In certain embodiments, a method for forming an interconnect structure includes forming a feature on a substrate, where the feature comprises one or more sidewalls. The method includes exposing the substrate to a Self-Assembled Monolayer (SAM) soak, which deposits a SAM layer on at least one portion of a structure within the interconnect. A first barrier layer containing manganese is then deposited over the sidewalls, and a ruthenium liner layer is deposited on top of the first barrier layer. The SAM layer is removed from the feature.BRIEF DESCRIPTION OF THE DRAWINGS

[0013] So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments.

[0014] FIG. 1 illustrates a schematic side view of a device structure, according to at least one embodiment.8760359_1 4PATENTAttorney Docket No.: 44025298WO01

[0015] FIG. 2 is a flow diagram of a method for depositing a plurality of layers to form a device structure, according to at least one embodiment.

[0016] FIGS. 3A-3G illustrate a schematic side view of a device structure during various blocks of the method of FIG. 2, according to at least one embodiment.

[0017] Figure 4 is a diagram illustrating simplified process flows used to process a substrate according to various embodiments representing different implementations for forming interconnect structures with barrier and liner layers.

[0018] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.DETAILED DESCRIPTION

[0019] Embodiments disclosed herein address deficiencies in conventional deposition techniques for forming conductive interconnects, such as copper interconnects, in high aspect ratio features. Conventional methods often suffer from inadequate step coverage, overhang, void formation, unwanted metal diffusion, metal agglomeration, poor adhesion, and increased bottom stack thickness, which detrimentally impact device yield, reliability, and interconnection integrity. To address these challenges, the present embodiments provide methods that improve deposition characteristics, leading to enhanced device performance and increased reliability. In the present embodiments, conductive and intermediate (e.g., liner and barrier) layers are deposited using chemical vapor deposition (CVD) and / or atomic layer deposition (ALD) techniques to form uniform interconnect structures with optimized thickness profiles. Specific material combinations are utilized to improve interconnect layer flowability (e.g., copper) during a reflow process, deposition selectivity, and deposition uniformity, reducing the occurrence of defects and enhancing overall device performance and reliability. Additionally, the disclosed methods allow for greater scalability in high aspect ratio feature applications, supporting advanced manufacturing requirements.8760359_1 5PATENTAttorney Docket No.: 44025298WO01

[0020] As used herein, the term “about” refers to a + / - 10% variation from the nominal value. It is to be understood that such a variation can be included in any value provided herein.

[0021] The term “substrate” as used herein refers to a layer of material that serves as a basis for subsequent processing operations and includes a surface to be cleaned. The substrate may be a silicon based material, glass based material, or any suitable insulating materials or conductive materials as needed. The substrate may include a material such as crystalline silicon (e.g., Si<100> or Si<111 >), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers and patterned or non-patterned wafers, silicon on insulator (SOI), carbon doped silicon oxides, silicon nitride, doped silicon, germanium, gallium arsenide, glass, or sapphire.

[0022] FIG. 1 illustrates a cross-sectional schematic side view of a portion of an example interconnect structure 100 that can be formed using the methods described herein, according to certain embodiments. It should be understood that FIG. 1 illustrates only a partial view of the interconnect structure 100, and that the interconnect structure 100 can contain any number of features and materials having aspects illustrated in the figures. As shown, the interconnect structure 100 includes a first portion 102 and a second portion 104. In the illustrated embodiments, the first portion 102 is disposed substantially below the second portion 104. As will be discussed further below, the interconnect structure 100 illustrated in FIG. 1 can be formed by use of one or more of the process sequences illustrated and described in relation to FIGS. 2-4. In one example, the interconnect structure 100 illustrated in FIG. 1 can be formed by removing operation 414B from the process sequence 400E.

[0023] The first portion 102 includes a dielectric layer 106, a barrier layer 108, a liner layer 110, an interconnect layer 114, and one or more etch stop layers 128. In certain embodiments, the dielectric layer 106 can be formed of organosilicate glass (SiCOH), silicon dioxide (SiC>2), silicon nitride (SisN4), silicon carbide (SiC), aluminum oxide (AI2O3), aluminum nitride (AIN), or any other dielectric material(s). In certain embodiments, the barrier layer 108 can be formed of tantalum (Ta), tantalum nitride (TaN), ruthenium doped tantalum nitride, manganese (Mn),8760359_1 6PATENTAttorney Docket No.: 44025298WO01 manganese nitride (MnN), titanium (Ti), titanium nitride (TiN), combinations thereof, or any other suitable material(s). The barrier layer 108 can be formed of one or more layers. Where the barrier layer 108 includes a plurality of layers, two or more layers of the barrier layer 108 can be formed of the same or different materials. In certain embodiments, the liner layer 110 can be formed of cobalt (Co), ruthenium (Ru), titanium (Ti), tantalum (Ta), or any other suitable material(s). In certain embodiments, the interconnect layer 114 can be formed of molybdenum (Mo), tungsten (W), ruthenium (Ru), cobalt (Co), copper (Cu), or any other suitable conductive material(s). In certain embodiments, the etch stop layer(s) 128 can be formed of silicon nitride, carbon (C), aluminum oxide (AI2O3), or any other suitable material(s).

[0024] The second portion 104 includes a dielectric layer 116, a barrier layer 118, a liner layer 120, and an interconnect layer 124. In certain embodiments, the second portion 104 further includes one or more etch stop layers 138. In certain embodiments, the dielectric layer 116 can be formed of organosilicate glass (SiCOH), silicon dioxide (SiC>2), silicon nitride (Si3N4), silicon carbide (SiC), aluminum oxide (AI2O3), aluminum nitride (AIN), or any other low-k dielectric material(s). In certain embodiments, the barrier layer 118 can be formed of tantalum (Ta), tantalum nitride (TaN), manganese (Mn), manganese nitride (MnN), titanium (Ti), titanium nitride (TiN), or any other suitable material(s). The barrier layer 118 can be formed of one or more layers. Where the barrier layer 118 includes a plurality of layers, two or more layers of the barrier layer 118 can be formed of the same or different materials. In certain embodiments, the liner layer 120 can be formed of cobalt (Co), ruthenium (Ru), titanium, tantalum, or any other suitable material(s). In certain embodiments, the interconnect layer 124 can be formed of copper (Cu). In certain other embodiments, the interconnect layer 124 can be formed of molybdenum (Mo), tungsten (W), ruthenium, cobalt, or any other suitable conductive material(s). In certain embodiments, the etch stop layer(s) 138 can be formed of silicon nitride, carbon (C), aluminum oxide (AI2O3), or any other suitable material(s).

[0025] FIG. 2 depicts a process flow diagram of an example method 200 for forming at least a portion of an interconnect structure, such as the interconnect8760359_1 7PATENTAttorney Docket No.: 44025298WO01 structure 100, according to certain embodiments. FIGs. 3A-3G illustrate cross- sectional schematic side views of the interconnect structure 100 at various stages during the performance of method 200, according to certain embodiments. It should be understood that FIGs. 3A-3G illustrate only partial views of a configuration of the interconnect structure 100, and that the interconnect structure 100 can contain any number of features and materials having aspects illustrated in the Figures. It should also be noted that although the method 200 illustrated in FIG. 2 is described sequentially, other process sequences that include one or more operations that have been omitted and / or added, and / or have been rearranged in another desirable order, fall within the scope of the embodiments of the disclosure provided herein. For example, the SAM soak process (operation 204) is optional and may be omitted to provide non-selective deposition of the barrier and liner layers. Additionally, where multiple barrier layers are used, such as manganese (Mn) containing and tantalum (Ta) containing barrier layers, these layers may be deposited in any order relative to each other. For instance, the tantalum-containing barrier layer may be deposited before or after the manganese-containing barrier layer, or multiple alternating layers of manganese-containing and tantalum-containing barriers may be deposited. The tantalum-containing barrier layer itself is optional and may be omitted in certain embodiments where only the manganese-containing barrier layer is desired. These variations in process flow enable optimization of the interconnect structure for different applications and requirements. Further, persons skilled in the art will understand that any system configured to perform the method operations, in any order, falls within the scope of the embodiments described herein. Further, the method 200 described in operations 202 through 214, with or without the SAM soak, can be performed using an integrated deposition system comprising multiple chambers, each designed for specific operations in the process.

[0026] With reference now to FIG. 2 and FIG. 3A, at operation 202, a feature 302 is formed in a substrate, such as the dielectric layer 116 of the second portion 104. Generally, the feature 302 can comprise a via or trench having one or more bottom wall 304 and one or more sidewalls 306. In certain embodiments, the bottom wall 304 is at least partially defined by a portion of one or more metal layers of the first portion 102, while an insulating dielectric material of the second portion8760359_1 8PATENTAttorney Docket No.: 44025298WO01104 at least partially defines the sidewalls 306. The feature 302 can have any suitable geometry and dimensions. In certain embodiments, as shown in FIG. 3A, the feature 302 can have non-uniform dimensions along a height H and / or a width W of the feature 302. In certain embodiments, the feature 302 can have uniform dimensions along the height H and / or the width W. The feature 302 can be formed via any suitable methods, including photolithography and etching techniques, laser patterning, and / or the like.

[0027] At operation 204, which is optional, the feature 302 is exposed to a Self- Assembled Monolayer (SAM) soak process, as shown in FIG. 3B, to facilitate selective deposition of liner and / or barrier layers along the sidewalls 306 of the feature 302 at later operations to reduce the resistance of the final interconnect structure 100. During operation 204, a SAM precursor, which includes SAM molecules, is delivered to a surface of the substrate to allow the formation of a SAM layer 310 within the feature 302. In some embodiments, the SAM layer 310 is selectively formed on the bottom wall 304 of the feature 302, due to the SAM layer 310 being selected and configured to exhibit a high affinity for the material(s) positioned within the bottom wall 304, which includes a metal, while exhibiting low affinity for the sidewalls 306, which are made of an insulating dielectric material. The SAM layer 310 selectively adsorbs onto the metal surface(s) of the bottom wall 304, thereby blocking / preventing or substantially minimizing the amount of subsequent deposition onto these surface(s). Accordingly, the SAM layer 310 reduces the overall thickness of the subsequently deposited barrier layer 118 and liner layer 120 at the bottom wall 304, which reduces the electrical resistance formed between the interconnect layer 114 of the first portion 102 and the subsequently formed interconnect layer 124 of the second portion 104 when a current flows through the first and second portions during device operation. In turn, this decreases the resistance of the overall interconnect structure 100.

[0028] In certain embodiments, the SAM layer 310 comprises long-chain organic molecules with unsaturated bonds, which selectively bind to the metal surface(s). In certain embodiments, the SAM soak process is carried out under controlled conditions, including providing the SAM precursor to a surface of the substrate that is maintained at a temperature in a range of about 20°C to 100°C, and is positioned8760359_1 9PATENTAttorney Docket No.: 44025298WO01 in an environment that is at a pressure of about 0.1 to 10 Torr, for a SAM soak process duration of 1 to 5 minutes, ensuring complete coverage of the metal surface. In certain embodiments, the SAM soak is followed by a pump-down to remove excess SAM molecules from the environment, after which the substrate is transferred to a next process chamber. In certain embodiments, the SAM soak is performed in a dedicated chamber within an integrated deposition system, which also contains chambers for subsequent barrier and liner deposition operations.

[0029] FIG. 3B demonstrates the SAM layer 310 formed on the bottom wall 304 while leaving the sidewalls 306 of the feature 302 exposed for subsequent processing. However, in certain embodiments, the SAM soak can be omitted entirely, and the method 200 can proceed directly to operation 206.

[0030] At operation 206, which corresponds to FIG. 3C, the barrier layer 118 is deposited over at least the sidewalls 306 of the feature 302. Where a SAM soak is performed, the SAM layer 310 prevents or reduces deposition of the barrier layer 118 onto the bottom wall 304. In embodiments where operation 204 is not performed, the barrier layer 118 may also be deposited over the bottom wall 304. The barrier layer 118 serves to prevent metal (e.g., copper) diffusion from the subsequent interconnect layer into the surrounding dielectric material and to reduce electromigration effects.

[0031] In certain embodiments, the barrier layer 118 includes one or more materials such as manganese-containing materials (e.g., manganese (Mn), manganese nitride (MnN)), tantalum-containing materials (e.g., tantalum (Ta), tantalum nitride (TaN)), ruthenium doped tantalum nitride, titanium (Ti), or titanium nitride (TiN). Where manganese or manganese nitride is used, the manganese (Mn) or manganese nitride (MnN) material can be caused to diffuse into a subsequently formed liner layer 120, by use of one or more thermal processing steps or elevated temperature liner layer deposition processes, to improve adhesion between the liner layer 120 and the subsequently formed interconnect layer 124.8760359_1 10PATENTAttorney Docket No.: 44025298WO01

[0032] In certain embodiments, the barrier layer 118 includes a plurality of layers, two or more of which can be formed of the same material(s) or different material(s). For example, in certain embodiments, the barrier layer 118 includes a first layer formed of manganese (Mn) or manganese nitride (MnN), and a second layer formed of tantalum (Ta) or tantalum nitride (TaN). In certain embodiments, the barrier layer 118 includes more than two layers; for example, in certain embodiments, the barrier layer 118 includes three or more layers, where the three or more layers are deposited in alternating fashion between manganese-containing and tantalum-containing materials. Generally, where the barrier layer 118 includes a plurality of layers, the multiple layers can be deposited in any sequential order.

[0033] In certain embodiments, the deposition of the barrier layer 118 is performed using techniques such as Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), pulsed CVD, Plasma Enhanced Chemical Vapor Deposition (PECVD), or Physical Vapor Deposition (PVD). Some materials of the barrier layer 118 may provide better conformality with ALD or CVD.

[0034] In certain embodiments, the barrier layer 118 has an overall thickness (e.g., combined thickness where multiple layers are formed) ranging from about 3 angstroms to about 20 angstroms on the sidewalls 306 or bottom wall 304. In embodiments where operation 204 is performed prior to operation 206, deposition of the barrier layer 118 on the bottom wall 304 is minimized due primarily to the presence of the SAM layer, resulting in a thickness of the barrier layer 118 of less than 1 angstrom thereon. In embodiments where operation 204 is not performed, the barrier layer 118 can be deposited directly on both the sidewalls 306 and the bottom wall 304, resulting in a conformal barrier coverage.

[0035] At operation 208, which corresponds to FIG. 3D, a liner layer 120 is deposited over the barrier layer 118. Where a SAM soak is performed (i.e., operation 204), the SAM layer 310 prevents or reduces deposition of the liner layer 120 onto the bottom wall 304. In embodiments where operation 204 is not performed, the liner layer 120 may also be deposited over the bottom wall 304. The liner layer 120 is generally used to promote adhesion of the interconnect layer 124 material with the other materials (e.g., barrier layer 118) disposed within the feature8760359_1 11PATENTAttorney Docket No.: 44025298WO01 and, especially, in cases where reflow of the interconnect layer 124 in the feature 302 is performed during subsequent processing operations.

[0036] In certain embodiments, the liner layer 120 includes at least one of ruthenium (Ru), cobalt (Co), titanium (Ti), tantalum (Ta), or any other suitable material depending on the material of the subsequent interconnect layer 124.

[0037] In certain embodiments, the liner layer 120 is deposited using CVD, pulsed CVD, ALD, PECVD, PVD, Plasma Enhanced ALD (PEALD), depending on the desired conformality and materials of the liner layer 120.

[0038] In certain embodiments, the liner layer 120 has an overall thickness ranging from between about 0.1 nm and about 5 nm. In embodiments where operation 204 is performed prior to operation 208, deposition of the liner layer 120 on the bottom wall 304 is minimized, resulting in a substantially reduced thickness of the liner layer. In embodiments where operation 204 is not performed, the liner layer 120 can be deposited directly onto the barrier layer 118 over both the sidewalls 306 and the bottom wall 304, resulting in a conformal liner coverage.

[0039] In one example of an interconnect structure 100, a liner layer 120 comprises ruthenium and is disposed over a barrier layer 118 that comprises manganese or manganese nitride. In another example, a liner layer 120 comprising tantalum or tantalum nitride is disposed over a barrier layer 118 that comprises manganese or manganese nitride. In another example, a liner layer 120 comprising cobalt is disposed over a barrier layer 118 that comprises manganese or manganese nitride. In yet another example, a liner layer 120 comprising titanium or titanium nitride is disposed over a barrier layer 118 that comprises manganese or manganese nitride.

[0040] At operation 210, which is optional, the SAM layer 310 is removed, as shown in FIG. 3E. In certain embodiments, the removal of the SAM layer 310 is performed using a direct plasma treatment, such as a Capacitively Coupled Plasma (CCP) process utilizing hydrogen and / or argon plasma. However, in some alternate embodiments, the removal of the SAM layer 310 is performed using a non-direct plasma treatment, such as exposing the substrate to a gas provided from a remote8760359_1 12PATENTAttorney Docket No.: 44025298WO01 plasma source (RPS), wherein the provided gas primarily includes hydrogen radicals and / or argon radicals. This treatment can be carried out at temperatures above 200°C to ensure the complete removal of SAM molecules without leaving residues, thereby exposing a clean metal surface at the surface of the bottom wall 304 for the subsequent interconnect deposition process.

[0041] At operation 212, which corresponds to FIG. 3F, the interconnect layer 124 is deposited to substantially fill the remaining volume of the feature 302. In certain embodiments, the interconnect layer 124 is formed of copper (Cu). In certain other embodiments, the interconnect layer 124 is formed of molybdenum, tungsten, ruthenium, cobalt, or any other suitable conductive material(s).

[0042] In certain embodiments, the interconnect layer 124 is deposited using a two-part, iterative process involving Physical Vapor Deposition (PVD) followed by a reflow process. The process includes performing a PVD process to deposit an initial copper layer, followed by a reflow process where the temperature is raised to between about 175°C and 275°C for approximately 1 -2 minutes. During this brief temperature increase, the copper material flows within the interconnect structure 100 to fill gaps and voids within the feature. This deposition-reflow cycle may be repeated multiple times, e.g., 2-4 cycles or more, to ensure complete filling of high- aspect ratio features. After the iterative fill processes are complete, a final thicker copper deposition (e.g., overburden layer) may be performed to ensure complete coverage of the interconnect material. Importantly, the temperature used during these copper reflow steps is lower than the temperature required for significant manganese diffusion through the liner layer 120 (e.g., ruthenium containing liner layer). In this example, this ensures that during the reflow process, the copper material is in contact with a substantially pure ruthenium surface during operation 212, which provides optimal conditions for copper reflow and void-free gap fill. During the reflow process, the deposited material is exposed to elevated temperatures to allow the material to flow and fill any gaps or seams that may have formed during the initial deposition. Generally, the two-part process can be performed iteratively until the feature 302 is completely and uniformly filled by the interconnect layer 124.8760359_1 13PATENTAttorney Docket No.: 44025298WO01

[0043] At operation 214, which corresponds to FIG. 3G, a post-deposition anneal process is performed, where the interconnect structure 100, now with filled feature 302, is exposed to elevated temperatures for a target duration of time. In certain embodiments, the anneal process is performed at a temperature of approximately 400°C for a sufficient duration to ensure uniform diffusion of various materials in the interconnect structure 100. In certain embodiments, the anneal process is performed under inert gas containing (e.g., argon (Ar)) atmosphere.

[0044] Where the barrier layer 118 includes manganese or manganese nitride, the anneal process at operation 214 facilitates the diffusion of manganese into the liner layer 120 to the interface between the liner layer 120 and the interconnect layer 124. During this diffusion process, the manganese preferentially binds to oxygen- rich locations within the ruthenium liner layer, which typically contains impurities such as carbon and oxygen from the CVD deposition process. This binding strengthens the ruthenium liner by forming a mixed layer with improved barrier properties, and thus providing a self-reinforcing effect. The diffused manganese also improves adhesion between the copper and the surrounding layers, as manganese exhibits strong adhesion properties with copper. This improved adhesion helps maintain the copper within the interconnect structure and prevents undesired copper movement or delamination. Additionally, the manganese diffusion enables improved adhesion between the liner layer 120 and the interconnect layer 124, and reduction of agglomeration of the material(s) of the liner layer 120, particularly where the liner layer 120 includes ruthenium. Generally, agglomeration of ruthenium, or other materials, can create weak points in the liner layer 120 and interconnect structure 100, generally. Thus, the migration of manganese at operation 214 facilitates reinforcement (e.g., strengthening) of the liner layer 120.

[0045] Figure 4 is a diagram illustrating simplified process flows 400A-400F used to process a substrate according to various embodiments. Each process flow represents different implementations for forming interconnect structures with barrier and liner layers as described herein. The process flows can be performed using an integrated deposition system comprising multiple chambers, each designed for specific operations in the process.8760359_1 14PATENTAttorney Docket No.: 44025298WO01

[0046] Process flow 400A illustrates the formation of a basic barrier-liner stack that can include manganese (e.g., Mn or MnN) and ruthenium, for example. The process begins at block 402 with providing a substrate having features formed therein, such as the feature 302 shown in FIG. 3A. The feature typically includes one or more sidewalls 306 and bottom wall 304 and may have dimensions corresponding to critical dimensions of less than about 12 nm. At block 404, a manganese nitride barrier layer is deposited using atomic layer ALD or CVD techniques to form a conformal layer over the sidewalls and bottom wall of the feature. Forming the barrier layer can include exposing the surfaces of the feature 302 to precursor gases that include a manganese-containing precursor (e.g., Mn(CO)s, Mn(N(CH3)2)2), a nitrogen source (e.g., NH3, N2, N2H4), and optional carrier gases (e.g., Ar, He). The manganese nitride barrier layer typically can have a thickness between about 3 angstroms and about 20 angstroms and serves to prevent copper diffusion into surrounding dielectric materials. The barrier layer may be deposited at temperatures between about 20°C and 400°C using precursors containing manganese and nitrogen.

[0047] During block 404, exposing the feature to the precursor gases can include co-flowing the manganese precursor and nitrogen source in combination for CVD mode or alternating their delivery when used in an ALD mode. For example, the manganese precursor and nitrogen source may be co-flowed simultaneously. Alternatively, the manganese precursor is flowed first, followed by a purge step, then the nitrogen source is flowed, followed by another purge step. The substrate temperature is maintained at about 20°C to about 400°C, such as about 100°C to about 300°C. The manganese precursor is flowed at a rate of about 10 seem to about 500 seem. The nitrogen source is flowed at a rate of about 100 seem to about 2000 seem. In some embodiments, the precursor gases are combined with an inert carrier gas, such as Ar, He, or a combination thereof. The flow rate of the precursors is controlled and may be pulsed by control valves to provide precise control of film composition and thickness.

[0048] Following barrier layer formation, at block 406, a ruthenium liner layer is deposited over the manganese nitride barrier layer using ALD or CVD techniques. The ruthenium liner layer typically has a thickness between about 0.1 nm and about8760359_1 15PATENTAttorney Docket No.: 44025298WO015 nm and serves as a surface to promote copper reflow and adhesion. The ruthenium may be deposited using precursors such as ruthenium organometallic compounds at temperatures between about 150°C and 400°C. At block 408, the feature is filled with copper using techniques such as physical vapor deposition, electroplating, or reflow, as illustrated in FIG. 3F. The copper fill may be performed using a two-part, iterative process involving physical vapor deposition followed by reflow. The material forming the copper layer may be heated to a reflow temperature between about 175°C and 275°C in an inert gas and / or vacuum environment before, during, or after depositing the copper layer.

[0049] Optionally, at block 410, a thermal anneal is performed, as illustrated in FIG. 3G, to drive manganese diffusion from the barrier layer through the ruthenium liner and to the ruthenium / copper interface. This anneal is typically performed at temperatures of approximately 400°C under an argon gas containing atmosphere. The manganese diffusion reduces ruthenium agglomeration by healing defect sites in the ruthenium layer, strengthens adhesion between the ruthenium and copper layers, and reduces interface scattering to lower the overall formed interconnect resistance. Block 410 can be conducted at temperatures between about 350°C and 450°C for about 1 -5 minutes under inert atmosphere, with a controlled ramp rate of 10-50°C / second to enable the manganese diffusion through the ruthenium liner.

[0050] Process flow 400B demonstrates formation of a multi-layer barrier-liner stack that can include tantalum (e.g., Ta or TaN), manganese (e.g., Mn or MnN), and ruthenium, such as a TaN / MnN / Ru or TaN / Mn / Ru stack, to at least provide enhanced barrier properties. Following substrate preparation at block 402 as described above, block 404 comprises depositing a composite barrier layer.

[0051] First, a tantalum nitride layer is deposited using ALD or CVD at temperatures between about 200°C and 400°C to a thickness of about 3-10 angstroms. The first step of block 404 includes depositing tantalum nitride using ALD or CVD processes. The tantalum nitride deposition includes exposing the feature to a tantalum precursor (e.g., TBTDET, PDMAT, TaCIs) and a nitrogen source (e.g., NH3, N2). The chamber temperature is maintained between about 200°C and 400°C during tantalum nitride deposition. The tantalum precursor is8760359_1 16PATENTAttorney Docket No.: 44025298WO01 flowed at rates between about 50 seem and 1000 seem, while the nitrogen source flows at rates between about 100 seem and 2000 seem. This first barrier component typically has a thickness between about 3 angstroms and 10 angstroms.

[0052] Subsequently, without breaking vacuum, a manganese nitride layer is deposited over the tantalum nitride using similar techniques as described for process flow 400A, or alternatively, manganese may be co-deposited during tantalum nitride formation to create a gradient composition barrier layer. Without breaking vacuum, the second step of block 404 proceeds with manganese nitride deposition using process conditions similar to those described in process 400A. The two-layer barrier structure combines the copper diffusion barrier properties of tantalum nitride with the beneficial diffusion properties of manganese nitride. The total barrier stack thickness typically ranges from about 6 angstroms to about 30 angstroms.

[0053] A conformal ruthenium liner is then deposited at block 406 using ALD or CVD techniques as previously described. The multi-layer barrier structure combines the superior copper barrier properties of tantalum nitride with the beneficial diffusion and interface engineering properties of manganese nitride.

[0054] Copper fill is performed at block 408 where the material forming the copper layer may be heated to a reflow temperature between about 175°C and 275°C in an inert gas and / or vacuum environment before, during, or after deposition. The copper fill typically uses a two-part process involving physical vapor deposition followed by reflow. This process is followed by an optional anneal at block 410 performed at temperatures of approximately 400°C under argon atmosphere to drive manganese diffusion from the barrier layer through the ruthenium liner and to the ruthenium / copper interface.

[0055] Process flow 400C illustrates a self-reinforced repair flow incorporating an additional manganese doping process. After substrate preparation at block 402 and initial barrier layer deposition at block 404 as described in either process flow 400A or 400B, a ruthenium liner is deposited at block 406.8760359_1 17PATENTAttorney Docket No.: 44025298WO01

[0056] At block 412, an additional manganese "re-dose" block is performed to enrich the ruthenium layer with manganese. This re-dose may be implemented via manganese soak at temperatures between about 100°C and 300°C, manganese- containing plasma treatment at powers between about 50W and 500W, or thermal co-evaporation of manganese. The re-dose step ensures sufficient manganese is available for subsequent diffusion and repair processes. In one example, block 412 can include a manganese re-dose step that can be implemented through several techniques: (a) manganese soak at temperatures between about 100°C and 300°C with manganese precursor partial pressures between 0.1 -5 Torr, (b) manganese- containing plasma treatment at powers between about 50W and 500W with manganese precursor flow rates of 50-500 seem, or (c) thermal co-evaporation of manganese at temperatures between 300°C and 500°C. The re-dose step typically continues for durations between about 30 seconds and 5 minutes to ensure sufficient manganese incorporation.

[0057] Following the re-dose step, copper fill at block 408 proceeds with the material forming the copper layer being heated to a reflow temperature between about 175°C and 275°C in an inert gas and / or vacuum environment before, during, or after deposition. A high-temperature anneal is then performed at block 410, typically at temperatures between about 350°C and 450°C for about 1-5 minutes under inert atmosphere. This anneal drives the additional manganese throughout the ruthenium layer to heal defects and reduce interface resistance. The higher manganese concentration from the re-dose step results in more complete defect repair and interface modification compared to process flows 400A and 400B.

[0058] Process flow 400D demonstrates a selective manganese (e.g., Mn or MnN) deposition process with conformal ruthenium coverage. After substrate preparation at block 402 as previously described, a first Self-Assembled Monolayer (SAM) is applied at block 414A through a controlled SAM soak process performed at temperatures between about 20°C and 100°C and pressures between about 0.1 and 10 Torr for approximately 1 -5 minutes. The SAM molecules selectively bind to metal surfaces at feature bottoms, as illustrated in FIG. 3B, blocking subsequent manganese deposition (e.g., Mn or MnN) in these regions.8760359_1 18PATENTAttorney Docket No.: 44025298WO01

[0059] A selective manganese-containing (e.g., MnN) barrier deposition process occurs at block 404 using ALD or pulsed CVD techniques. Due to the presence of the SAM blocking layer, MnN deposits primarily on feature sidewalls while minimal deposition occurs at the feature’s bottom wall. The selective deposition results in a barrier layer thickness of about 3-20 angstroms on sidewalls and less than 1 angstrom at bottom surfaces. At block 416, the SAM is removed using direct plasma treatment, such as a capacitively coupled plasma process utilizing hydrogen and / or argon plasma at temperatures above 200°C to ensure complete removal without leaving residues. Conformal ruthenium liner deposition follows at block 406 using previously described ALD or CVD techniques, followed by a copper fill process at block 408 as illustrated in FIG. 3F.

[0060] Process flow 400E illustrates fully selective barrier and liner deposition for ultra-low via resistance. Following substrate preparation at block 402, a first SAM layer is applied at block 414A under conditions described above to block MnN deposition at via bottoms. Next, the processes of block 404 are performed, which comprises depositing a barrier layer, such as a manganese containing layer, a tantalum nitride containing layer, or a titanium or titanium nitride containing layer by use of an ALD or CVD process at temperatures between about 200°C and 400°C to a thickness of about 3-10 angstroms. In one example, block 404 comprises a selective MnN barrier deposition process using ALD or pulsed CVD, resulting in sidewall coverage while maintaining minimal bottom deposition due to the first SAM. Next at block 416, the SAM formed during block 414A is removed using direct plasma treatment, such as a capacitively coupled plasma process utilizing hydrogen and / or argon plasma at temperatures above 200°C to ensure complete removal without leaving residues. Next, a second SAM application follows at block 414B, performed under similar controlled conditions, to block ruthenium deposition at via bottoms. Next, at block 406 will include a selective ruthenium liner deposition, which deposits primarily on feature sidewalls due to the second SAM blocking layer. This dual-SAM approach minimizes both barrier and liner thickness at via bottoms, significantly reducing via resistance in the final structure. At block 416, the SAM layers are removed SAM is removed using direct plasma treatment, such as a capacitively coupled plasma process utilizing hydrogen and / or argon plasma at8760359_1 19PATENTAttorney Docket No.: 44025298WO01 temperatures above 200°C to ensure complete removal without leaving residues, ensuring complete removal of all organic residues. The feature is then filled with copper at block 408 using the previously detailed copper fill process. The dual- selective nature of this process flow results in direct copper-to-copper contact at via bottoms while maintaining sufficient barrier and liner coverage on sidewalls for reliable interconnect performance.

[0061] Process flow 400F demonstrates a barrier-liner co-deposition and doping approach. After substrate preparation at block 402, blocks 404 and 406 are combined into a single deposition step where MnN and ruthenium precursors are either alternately pulsed or co-flowed in an ALD or CVD process. Process temperatures typically range from 200°C to 400°C, with partial pressures of the respective precursors controlled to achieve desired compositions. This technique creates either a graded composition where manganese concentration gradually decreases from the dielectric interface to the copper interface, or a nano-layered structure with alternating MnN-rich and Ru-rich regions. An optional in-situ plasma or thermal treatment follows at block 412, performed at temperatures between 300°C and 400°C, which encourages manganese migration to ruthenium defect sites, forming a "self-healing" structure. The process concludes with copper fill at block 408 and an optional post-fill anneal at block 410, typically performed at 400°C within an inert gas (e.g., argon) containing atmosphere, which drives remaining manganese to the ruthenium / copper interface for enhanced adhesion and reduced resistance. This co-deposition approach allows for precise control of manganese distribution throughout the barrier-liner stack while maintaining the benefits of manganese diffusion and interface engineering.

[0062] In some embodiments of the process flow 400F, after performing the substrate preparation process at block 402 as previously described, a Self- Assembled Monolayer (SAM) is applied at block 414A through a controlled SAM soak process performed at temperatures between about 20°C and 100°C and pressures between about 0.1 and 10 Torr for approximately 1 -5 minutes. The SAM molecules selectively bind to metal surfaces at the feature bottoms, as illustrated in FIG. 3B, blocking subsequent MnN deposition in these regions. Then, blocks 404 and 406 are combined into a single deposition step where MnN and ruthenium8760359_1 20PATENTAttorney Docket No.: 44025298WO01 precursors are either alternately pulsed or co-flowed in an ALD or CVD process. An optional in-situ plasma or thermal treatment can then follow at block 412 to encourage manganese migration to ruthenium defect sites, forming a "self-healing" structure. The process concludes with copper fill at block 408 and an optional postfill anneal at block 410, typically performed at 400°C under argon atmosphere, which drives the remaining manganese to the ruthenium / copper interface for enhanced adhesion and reduced resistance.

[0063] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.8760359_1 21

Claims

PATENTAttorney Docket No.: 44025298WO01Claims:1 . A method for forming an interconnect structure, comprising: depositing a barrier layer over one or more surfaces of a feature formed in a surface of a substrate, wherein the barrier layer comprises manganese, and the one or more surfaces of the feature comprise one or more sidewall surfaces and a bottom surface; depositing a liner layer over the barrier layer, wherein the liner layer comprises a metal selected from a group consisting of ruthenium (Ru), cobalt (Co), titanium (Ti), and tantalum (Ta); and filling the feature with an interconnect material, wherein filling the feature comprises depositing the interconnect material on the deposited liner layer.

2. The method of claim 1 , wherein the interconnect material comprises copper.

3. The method of claim 2, wherein the barrier layer comprises manganese nitride, and the liner layer comprises ruthenium (Ru).

4. The method of claim 1 , further comprising: selectively forming a Self-Assembled Monolayer (SAM) layer over the one or more surfaces of the feature before depositing the barrier layer over the one or more surfaces of the feature, wherein the Self-Assembled Monolayer (SAM) layer is formed on the bottom surface, and the bottom surface comprises a metal.

5. The method of claim 4, further comprising: removing the Self-Assembled Monolayer (SAM) layer from the one or more surface of the feature before depositing the liner layer and after depositing the barrier layer over the one or more surfaces of the feature, wherein removing the SAM layer comprises exposing the one or more surfaces of the feature to a direct plasma treatment.8760359_1 22PATENTAttorney Docket No.: 44025298WO016. The method of claim 4, wherein depositing the barrier layer over the one or more surfaces of the feature causes the barrier layer to selectively form on the one or more sidewall surfaces versus on the Self-Assembled Monolayer (SAM) layer.

7. The method of claim 6, wherein the barrier layer comprises manganese nitride.

8. The method of claim 1 , further comprising: heating the interconnect material, the liner layer, and the barrier layer to a first temperature after filling the feature with the interconnect material.

9. The method of claim 8, further comprising: heating the liner layer and the barrier layer to a second temperature before filling the feature with the interconnect material.

10. The method of claim 8, wherein filling the feature with the interconnect material comprises: depositing a first portion of the deposited interconnect material on the deposited liner layer; heating the substrate and the first portion of the deposited interconnect material to a temperature between about 175°C and 275°C; and depositing a second portion of the deposited interconnect material on the first portion of the deposited interconnect material.

11. A method for forming an interconnect structure, comprising: depositing a first barrier layer over one or more surfaces of a feature formed in a surface of a substrate, wherein the barrier layer comprises manganese, and the one or more surfaces of the feature comprise one or more sidewall surfaces and a bottom surface; depositing a second barrier layer over the one or more surfaces of the feature, the second barrier layer comprising tantalum; depositing a liner layer on the second barrier layer, wherein the liner layer comprises ruthenium; and8760359_1 23PATENTAttorney Docket No.: 44025298WO01 filling the feature with an interconnect material, wherein filling the feature comprises depositing the interconnect material on the deposited liner layer.

12. The method of claim 11 , wherein the first barrier layer comprises manganese nitride.

13. The method of claim 12, wherein the second barrier layer comprises tantalum nitride.

14. The method of claim 11 , further comprising: selectively forming a Self-Assembled Monolayer (SAM) layer over the one or more surfaces of the feature before depositing the first barrier layer over the one or more surfaces of the feature, wherein the Self-Assembled Monolayer (SAM) layer is formed on the bottom surface, and the bottom surface comprises an interconnect material.

15. The method of claim 14, further comprising: removing the Self-Assembled Monolayer (SAM) layer from the one or more surface of the feature before depositing the liner layer and after depositing the second barrier layer over the one or more surfaces of the feature.

16. The method of claim 14, wherein depositing the first barrier layer over the one or more surfaces of the feature causes the first barrier layer to selectively form on the one or more sidewall surfaces versus on the Self-Assembled Monolayer (SAM) layer.

17. The method of claim 11 , further comprising: heating the interconnect material, the liner layer, and the barrier layer to a first temperature after filling the feature with the interconnect material.

18. A method for forming an interconnect structure, comprising: selectively forming a Self-Assembled Monolayer (SAM) layer over one or more surfaces of a feature formed in a surface of a substrate, wherein8760359_1 24PATENTAttorney Docket No.: 44025298WO01 the one or more surfaces of the feature comprise one or more sidewall surfaces and a bottom surface, and the Self-Assembled Monolayer (SAM) layer is formed on at least one surface of the one or more surfaces of the feature, and the at least one surface comprises a first interconnect material; depositing a barrier layer over one or more surfaces of a feature after selectively forming the Self-Assembled Monolayer (SAM) layer, wherein the barrier layer comprises manganese, and depositing a liner layer over the barrier layer, wherein the liner layer comprises ruthenium; and filling the feature with a second interconnect material, wherein filling the feature comprises depositing the interconnect material on the deposited liner layer.

19. The method of claim 18, wherein the first and second interconnect materials each comprises copper, and the barrier layer comprises manganese nitride.

20. The method of claim 19, further comprising: removing the Self-Assembled Monolayer (SAM) layer from the one or more surface of the feature before depositing the liner layer and after depositing the barrier layer over the one or more surfaces of the feature, wherein removing the SAM layer comprises exposing the one or more surfaces of the feature to a direct plasma treatment.8760359_1 25

Images