Three-dimensional architectures for large-scale quantum procesors

Abstract

There is described herein a superconducting quantum processor package comprising: a package substrate having an external connector port; an interposer having first and second opposing sur¬ faces, the first surface of the interposer facing the package substrate, the interposer carrying a first quantum readout device coupled to the external connector port; a first qubit substrate having top and bottom opposing surfaces, the bottom surface of the first qubit substrate facing the second surface of the interposer, the first qubit substrate carrying a first qubit circuit with interleaved qubits and couplers, the first qubit circuit coupled to the first quantum readout device, wherein the first qubit circuit, the first quantum readout device, and the external connector port form a first readout communication path; and a first amplifying device in the first readout communication path, coupled between the first quantum readout device and the external connector port, to amplify readout sig¬ nals from the first quantum readout device.

Description

THREE-DIMENSIONAL ARCHITECTURES FOR LARGE-SCALE QUANTUM PROCESORSCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present application claims the benefit of United States Provisional Patent Application No. 63 / 621 ,143 filed January 16, 2024, the contents of which are hereby incorporated by reference in their entirety.TECHNICAL FIELD

[0002] The present disclosure generally relates to three-dimensional architectures for superconducting quantum processors.BACKGROUND OF THE ART

[0003] Superconducting qubit technology is the leading platform to develop large scale quantum processors. A superconducting quantum processor is an electronics device fabricated using advanced nanofabrication processes on specialized substrates such as high resistivity silicon or sapphire. The fabrication process involves lithography, deposition, and etching steps that are widely used in the semiconducting industry.

[0004] Currently, the most advanced quantum processors typically have a few 10s to a few 100s of superconducting qubits using academic / prototyping nanofabrication facilities with little reproducibility and relatively low yield. Moreover, until recently, quantum chips for superconducting qubits were manufactured mainly in planar geometries where the qubits and other components found on quantum chips were laid out on a single substrate. As the number of qubits increases, more realestate is needed and the limits of 2D architectures have already been reached. There is a need to expand into integrated 3D architectures to accommodate more qubits. It should be noted that a useful quantum processor would require the fabrication of tens of thousands to millions of qubits with high yield and reliability.

[0005] Therefore, improvements are needed.SUMMARY

[0006] There are described herein advanced nanofabrication and 3D packaging architectures for large scale superconducting quantum processors. As used herein, large-scale is understood to mean quantum processors comprising 100 or more qubits, such as but not limited to 500 qubits, 1000 qubits, 10,000 qubits, 100,000 qubits, etc.

[0007] In general, in some aspects, the subject matter of the present disclosure can be embodied in a superconducting quantum processor package comprising: a package substrate having an external connector port; an interposer having first and second opposing surfaces, the first surface of the interposer facing the package substrate, the interposer carrying a first quantum readout device coupled to the external connector port; a first qubit substrate having top and bottom opposing surfaces, the bottom surface of the first qubit substrate facing the second surface of the interposer, the first qubit substrate carrying a first qubit circuit with interleaved qubits and couplers, the first qubit circuit coupled to the first quantum readout device, wherein the first qubit circuit, the first quantum readout device, and the external connector port form a first readout communication path; and a first amplifying device in the first readout communication path, coupled between the first quantum readout device and the external connector port, to amplify readout signals from the first quantum readout device.

[0008] Implementations of the superconducting quantum processor package can include one or more of the following features or other features described herein. For example, in some implementations, the first amplifying device is carried by the interposer.

[0009] In some implementations, the package further comprises a first amplifier substrate having top and bottom opposing surfaces, the bottom surface of the first amplifier substrate facing the second surface of the interposer, wherein the first amplifying device is carried by the first amplifier substrate, and wherein the first amplifier substrate is separate from and adjacent to the first qubit substrate.

[0010] In some implementations, the first amplifying device comprises at least one amplifier and at least one circulator coupled thereto.

[0011] In some implementations, the circulator is coupled between the external connector port, the first quantum readout device, and the amplifier.

[0012] In some implementations, the first amplifying device comprises a Josephson Parametric Amplifier (JPA).

[0013] In some implementations, the interposer is bonded to the package substrate through a Ball Grid Array (BGA).

[0014] In some implementations, the first qubit substrate is bonded to the interposer through a first grid of superconducting microspheres.

[0015] In some implementations, the first quantum readout device comprises a plurality of resonators associated with a transmission line.

[0016] In some implementations, the resonators are arranged in a curved pattern and align with the qubits in the first qubit circuit also aligned in the curved pattern.

[0017] In some implementations, the first quantum readout device comprises at least one filter.

[0018] In some implementations, the external connector port is by-directional and performs readout and input.

[0019] In some implementations, the external connector port is configured for a plurality of output lines, and the first amplifying device comprises a plurality of amplifiers each corresponding to one of the plurality of output lines.

[0020] In some implementations, the package further comprises a second quantum readout device carried in the interposer; a second qubit substrate separate from the first qubit substrate and having top and bottom opposing surfaces, the bottom surface of the second qubit substrate facing the second surface of the interposer, the second qubit substrate carrying a second qubit circuit with interleaved qubits and couplers, the second qubit circuit coupled to the second quantum readout device; and a coupling substrate facing and overlapping with the top surfaces of the first qubit substrate and the second qubit substrate, the coupling substrate comprising at least one coupler configured for selectively coupling at least one qubit from the first qubit circuit with at least one qubit from the second qubit circuit.

[0021] In some implementations, the package further comprises a second amplifying device coupled between the second quantum readout device and the external connector port, to amplify readout signals from the second qubit circuit.

[0022] In some implementations, the package further comprises a second amplifying device coupled between the second quantum readout device and a second external connector port on the package substrate, to amplify readout signals from the second qubit circuit.

[0023] In some implementations, the package further comprises third and fourth quantum readout devices carried in the interposer; and third and fourth qubit substrates separate from thefirst and second qubit substrates, carrying third and fourth qubit circuits, respectively, and coupled to the third and fourth quantum readout devices, respectively. The coupling substrate overlaps with the first, second, third, and fourth qubit substrates, and the at least one coupler is configured for selectively coupling at least one qubit from any one of the first, second, third and fourth qubit circuits with at least one qubit from any other one of the first, second, third and fourth qubit circuits.

[0024] In some implementations, the package further comprises third and fourth amplifying devices coupled to the third and fourth quantum readout devices, respectively.

[0025] In some implementations, the second, third, and fourth amplifying devices are carried in the interposer.

[0026] In some implementations, the second, third, and fourth amplifying devices are carried are carried by second, third and fourth amplifier substrates, respectively, which are separate from the first, second, third and fourth qubit substrates and sit on the interposer.

[0027] The details of the one or more implementations are set forth in the accompanying drawings and the description below. Other features will be apparent from the description, the drawings, and the claims.BRIEF DESCRIPTION OF THE DRAWINGS

[0028] FIG. 1 is an example embodiment of a flip-chip architecture for a superconducting quantum processor package;

[0029] FIG. 2 is an example embodiment of a flip-chip architecture with superconducting vias, for a superconducting quantum processor package;

[0030] FIG. 3 is an example embodiment of a through-silicon via with scallops;

[0031] FIG. 4 is an example embodiment of qubit substrates coupled through a coupler in an interposer;

[0032] FIG. 5 is an example embodiment of qubit substrates coupled through a coupler in a coupling substrate;

[0033] FIG. 6 is an example embodiment of the qubit substrate connecting architecture of Fig. 5 with the interposer wire bonded to a package substrate;

[0034] FIG. 7 is an example embodiment of the qubit substrate connecting architecture of Fig. 4 with the interposer wire bonded to a package substrate;

[0035] FIG. 8 is a top schematic view of an example quantum readout device;

[0036] FIG. 9 is a top schematic view of an example qubit circuit overlaid on the quantum readout device of FIG. 8;

[0037] FIG. 10 is a side schematic view of an example embodiment for a superconducting quantum processor package with an amplifying device in an interposer;

[0038] FIG. 11 is a side schematic view of an example embodiment for a superconducting quantum processor package with an amplifying device in an amplifier substrate;

[0039] FIGS. 12A & 12B are example embodiments of an amplifying device;

[0040] FIGS. 13A & 13B are side schematic views of example embodiments for a superconducting quantum processor package with a bi-directional external connector port;

[0041] FIG. 14 is another example embodiment of an amplifying device; and

[0042] FIGS. 15A-15C are top views of example layouts for a superconducting quantum processor package with multiple qubit substrates and one or more amplifying substrates.DETAILED DESCRIPTION

[0043] The present disclosure is directed to advanced nanofabrication and 3D packaging processes for large scale superconducting quantum processors. This involves fabrication processes and architectures for superconducting multi-chip modules to reduce the impact of defects on yield. It also involves using various vertical strategies such as through-silicon vias, flip-chips, use of multiple interposers, and various combinations of vertical stacking to address the need to increase the qubit count with the limited real estate available on a substrate. These processes are combined with the use of superconducting materials such as aluminum, indium, titanium nitride, and niobium in a series of subtractive patterning, etching, lithography, and deposition processes that result in ultra-low-loss superconducting devices.

[0044] The present disclosure makes reference to qubit circuits, which comprise interleaved qubits and couplers. In some embodiments, the qubits circuit used for some, or all, of the 3D architectures described herein corresponds to the superconducting qubit circuit described in U.S. Patent No. 10,622,998, the contents of which are hereby incorporated by reference in their entirety. The qubits are superconducting qubits, such as but not limited to charge qubits, flux qubits, phase qubits, fluxoniums, transmons, differential transmons, and the like. In other embodiments, the qubits are spin qubits or any quantum object having a plurality of discrete levels out of which at least two levels can be selectively addressed. The qubits may be fixed-frequency or tunable-frequency qubits. The qubits may be configured to represent and operate on information in more thanone state simultaneously. In some implementations, the qubits are formed of quantum circuit elements include circuit elements such as superconducting co-planar waveguides, quantum LC oscillators, superconducting quantum interference devices (SQUIDs) (e.g., RF-SQUID or DC-SQUID), among others. The quantum circuit elements may include circuit elements formed, in part, from superconductor materials (e.g., aluminum, titanium nitride or niobium).

[0045] The qubits are interleaved with couplers, which may also be implemented as qubits. In some embodiments, the couplers have the same architecture as the qubits. However, the qubits and couplers need not be of the same architecture ortype. The couplers may be frequency-tunable, and they may be tuned by applying a frequency-changing signal to a transmission line associated with each coupler.

[0046] The qubits are carried by a qubit substrate, and may be formed on and / or within the substrate. The qubit substrate may be formed from low loss dielectric materials suitable for quantum circuit elements, such as a silicon or sapphire wafer. Other materials may be used for the qubit substrate instead of or in addition to thereto.

[0047] With reference to Fig. 1 , there is illustrated a first example embodiment for a superconducting quantum processor package 100. In this architecture, a qubit substrate 102 is attached to an interposer 104. The interposer 104 may be composed of one or more layers of materials such as low loss dielectric material suitable for quantum circuits, such as single crystalline silicon or sapphire. The interposer 104 may include quantum circuit elements and / or classical circuit elements. The qubit substrate 102 may be joined to the interposer 104 through an array of interconnects 108. In some embodiments, the interconnects 108 are bump bonds arranged to couple data between qubits on the qubit chip 102 and circuit elements on the interposer 104. The bump bonds may include superconductor material to avoid energy loss and decoherence of qubits located on the qubit substrate 102. For instance, suitable superconductor material for use as a bump bond includes, but is not limited to, indium, lead, rhenium, palladium, or niobium having a thin layer of gold. The bump bonds may be formed on interconnect pads on both the qubit substrate 102 and the interposer 104. In some embodiments, the interconnects 108 are microspheres, for example indium microspheres. While indium bump bonds are typically grown via electroplating or evaporation and face-to-face compression bonded using a flip-chip bonder, microspheres may be placed manually on a surface of the interposer 104 or qubit substrate 102 and the two are pressed togetherusing a transfer stage. This eliminates the need for patterning and growing indium micro bumps. Other materials and types of interconnects may also be used.

[0048] The interposer 104 sits on a package substrate 106, inside a cutout. In some embodiments, the package substrate 106 is a printed circuit board (PCB). The interposer 104 is connected to the PCB via wire bonding 110 to pads around the perimeter of the interposer 104.

[0049] With reference to Fig. 2, there is shown another embodiment for a superconducting quantum processor package 202. In this implementation, the interposer 204 is connected to the package substrate 206 from the bottom instead of from the side. To transition to an underside connection between the interposer 204 and the package substrate 206, interconnects 212 are used, for example a Ball Grid Array (BGA) or other types of interconnects. Through-silicon vias 210 are also added to the interposer 204, from a bottom surface to a top surface, to replace the wire-bonding and allow the connection between the package substrate 206 and the qubit substrate 202. Superconducting material must be added inside the vias 210.

[0050] In some embodiments, the interconnects 208 are superconducting bump bonds that are of the order of 5 microns and are fabricated using a deposition system. In some embodiments, the interconnects 212 are of the order of 100 microns and cannot be deposited. Electroplating may be used to fabricate BGAs.

[0051] A deep silicon etch called the Bosch process may be used to create the vias. However, this technique can create scallops 304, as shown in Fig. 3, making it more challenging to deposit superconducting material 306 inside the vias 302. The superconducting material 306 may break off during the depositing process or not reach the bottom of the via 302 if nothing is done to smooth out the inside walls of the vias. The wafers used may vary in dimensions. With a low aspect ratio of the vias 302, shadow evaporation may be used to smooth out the vias 302. In some embodiments, the wafers are 8 inches in diameter and about 750 microns in thickness. The vias 302 may have a diameter of about 10-50 microns. Therefore, the aspect ratio between the diameter and the depth of the via is very large. For large aspect ratios of the vias, and in some embodiments, a liner is placed inside the via to smooth out the sharp scallop edges on the inner walls. In some embodiments, silicon oxide is grown on the inner walls of the vias to smooth out the sharp scallops. In some embodiments, cryogenic etching is used to avoid the scallops altogether. A constant aspect ratio should be maintained throughout the entire depth of the via.

[0052] Qubits are typically fabricated on a single wafer. As the number of qubits increases, the size of the wafer increases. If something falls on the wafer, all qubits may be lost. In order to increase the yield of qubits, large qubit wafers may be broken into multiple chiplets with about 20-50 qubits per chiplet. More or less qubits per chiplet may be used. With the chiplet approach, reduced development timelines and costs can be obtained. As used herein, a chiplet is referred to as a qubit substrate in the superconducting quantum processor package, and a plurality of qubit substrates may be provided in a same package. In some embodiments, qubits in different qubit substrates may be coupled together through the interposer, as shown in the example embodiment of Fig. 4. For example, a first qubit substrate 402A carries a first qubit circuit 404A having a plurality of interleaved qubits and couplers. A second qubit substrate 402B carries a second qubit circuit 404B having a plurality of interleaved qubits and couplers. A coupler 406 is positioned on the interposer 412 and is configured to selectively coupled at least one a qubit in the first qubit circuit 402B of the first qubit substrate 402A with at least one qubit in the second qubit circuit 404B of the second qubit substrate 402B (as per the interleaved architecture of qubits and couplers). The coupler 406 couples to the qubit circuits 404A, 404B through superconducting interconnects 408.

[0053] It will be noted that with this approach, the interposer 412 comprises both vias 410 and coupler(s) 406 (amongst other components). The equipment used to fab the vias 410 may be found in a semiconducting side of a facility, where gold is also found. Couplers that comprise Josephson Junctions are superconducting structures that cannot be exposed to gold. There is a strict rule that a component that has been exposed to gold cannot enter a gold-free quantum facility. This means that the coupler 406 would need to be fabricated first and then the vias 410, and the coupler 406 would need to be protected from a possible gold contamination.

[0054] In some embodiments, a layer of resist is added on top of the coupler (on the interposer) prior to fabricating the vias, and the layer is removed via lift-off at the end of the process. However, there is always a risk that residue from the resist stays on the coupler.

[0055] In some embodiment, a coupling substrate carries the coupler that couples qubits from different qubit circuits of different qubit substrates, as shown in the example embodiment of Fig. 5. The coupling substrate 506 is placed on top of and overlapping with qubit substrates 502A, 502B, each carrying a qubit circuit 504A, 504B, respectively. Interconnects 510 are used to connect the coupling substrate 506 to the qubit substrates 502A, 502B. The interconnects 510 may be the same or different from interconnects 512 used to connect the qubit substrates 502A, 502B, to the interposer 514, provided an electrical connection may be made between the coupler 508 and qubit circuits 504A, 504B. The coupler substrate 506 thus carries the coupler(s) 508, allowing the interposer 514 to be fabricated separately from the coupler substrate 506 and without the challenges arising from having to fabricate the vias 516 and the coupler 508 on the same component. This approach, however, makes the qubit substrates 502A, 504A two sided, which increases complexity as you need a process for double-sided wafers.

[0056] In some embodiments, the qubit substrates 602A, 602B and coupling substrate 604 are used without vias in the interposer 606. In this case, the interposer 606 is provided in a cutout on the package substrate 608 and wire bonding 610 electrically connects the interposer 606 to the package substrate 608, as shown in the example embodiment of Fig. 6.

[0057] In some embodiments, the qubits from the first qubit circuit 704A and second qubit circuit 704B from the first and second qubit substrates 702A, 702B, respectively are connected through a coupler 706 carried by the interposer 708. The interposer 708 is provided in a cutout on the package substrate 710 and wire bonding 712 electrically connects the interposer 708 to the package substrate 710, as shown in the example embodiment of Fig. 7.

[0058] It will be understood that although the examples herein show two qubit substrates and one coupling substrate, more qubit substrates may be provided in a same package, and each pair of qubit substrate may be coupled together with a coupling substrate. In some implementations, a coupling substrate may straddle four qubit substrates and selectively couple a qubit from anyone of the four qubit substrates with another qubit from any other one of the qubit substrates.

[0059] Readout of the qubits in the qubit circuits may be accomplished using a quantum readout device, which may be carried by the interposer. A quantum readout device comprises at least one resonator and at least one transmission line. In some embodiments, the quantum readout device comprises a plurality of readout resonators, and each readout resonator is associated with a respective qubit. In some embodiments, each readout transmission line has an input port for sending an input signal and an output port for receiving an output signal. Note that a single port of the transmission line may be used for both input and output. In such a case, an input signal is applied at a port of the transmission line and a reflection of the input signal is measured as the output signal at the same port. As used herein, the expression “performing a readout” encompasses the steps of applying one or more input signal at a port of a transmission line and subsequently measuring one or more output signal at the same or a different port of the transmission line. Additional processing steps of the raw data as measured may also be included in performing the readout and as such, additional components may be provided in the quantum readout device. In some embodiments, multiple readout resonators are connected to a single transmission line. Alternatively, each readout resonator may be associated with a separate transmission line.

[0060] With reference to Fig. 8, there is illustrated an embodiment of a quantum readout device 800 in accordance with a specific and non-limiting example. A plurality of resonators 802A, 802B, 802C, 802D, 802E are associated with a transmission line 804 having an input port 806A and an output port 806B. In some embodiments, a filter 808 is associated with a resonator 802A to filterthe readout signal. The filter 808 may be a frequency filter (e.g. a bandpass filter, a high pass filter, a low pass filter, a stepped impedance filter, or the like) to impede propagation photons emitted from the qubit at the qubit frequency, and thus prevent energy leakage of a qubit through unwanted decay channels. In some implementations, the filter 808 is a Purcell filter. Although only one filter 808 is illustrated, filters may be provided for each resonator of the quantum readout device 800.

[0061] The quantum readout device 800 may be capacitively or inductively coupled to a qubit circuit. In some implementations, the quantum readout device of the interposer and the qubit circuit of the qubit substrate are aligned for coupling. Fig. 9 is a top view of a qubit circuit overlaid with a quantum readout device. The interposer and qubit substrate are omitted for ease of understanding. The qubit circuit is composed of qubits 902A, 902B, 902C, 902D, 902E interleaved with couplers 904A, 904B, 904C, 904D. Qubits 902A, 902B, 902C, 902D, 902E overlap with resonators 906A, 906B, 906C, 906D, 906E, respectively, to allow for the capacitive or inductive coupling therebetween. In this example, the qubits 902A, 902B, 902C, 902D, 902E and resonators 906A, 906B, 906C, 906D, 906E are arranged in a curved pattern, around the transmission line 908, which is also shaped accordingly. Other arrangements may also be used. Although five qubits and resonators are illustrated in the example, more or less than five may be used.

[0062] The superconducting quantum processor package is maintained at cryogenic temperatures for operation, for example in a dilution refrigerator. A dilution refrigerator is a cryogenic system that provides continuous cooling from ambient temperature all the way down to millikelvin temperatures. The dilution refrigerator is composed of a cryostat, and the superconducting quantum processor package is disposed inside the cryostat. Control and readout of the qubits in the quantum processor package is performed by classical control electronics, which is disposed outside the cryostat while being in communication with the quantum processor housed within a core of the cryostat. It will be understood that some of the components of the classical control electronics involved in the control and readout of the qubits may also be integrated, in part or in whole, inside the cryostat, depending on practical applications. Signals may be transmitted between the quantum processor and the classical control electronics via interconnects, which for example may be a plurality of coaxial lines entering and exiting the cryostat. Other types of cables, such as optical fibers or RF over fiber, may also be used to carry the control signals to and from the cryostat and / or to and from the quantum processor inside the cryostat.

[0063] The superconducting quantum processor package may be coupled to the cables (microwave, optical, or the like) through various types of connectors. The connectors may be coaxial connectors, for example RF connectors, such as SMA connectors, SMP connectors, SMMP connectors, and the like. In some embodiments, the connectors are High Density (HD) connectors,whereby multiple lines are provided within a single connector housing. The superconducting quantum processor package therefore includes one or more external connector port, carried by the package substrate, for connection to one or more cable.

[0064] When performing a readout of a qubit, a probe tone may be generated to sample the frequency of the quantum readout device and measure a phase shift that depends on the state / fre- quency of the qubit. However, important attenuation may occur to the signal obtained from the quantum readout device overthe output line, decreasing the signal to noise ratio and making measurement more difficult. To mitigate attenuation of the readout signal from the quantum readout device, an amplifier may be used. In accordance with the embodiments described herein, the amplifying device may be incorporated inside the superconducting quantum processor package.

[0065] With reference to Fig. 10, an example embodiment is illustrated of a superconducting quantum processor package having an amplifying device. A qubit substrate 1002 carries a qubit circuit 1008 that is aligned with a quantum readout device 1010 carried by an interposer 1004. The interposer 1004 sits above a package substrate 1006, which carries at least one external connector port, in the present case external connector ports 1012 and 1014. In this example a signal comes in through external connector port 1014 and travels through the package substrate 1006 and the interposer 1004 to reach the transmission line in the quantum readout device 1010. Various conductive pathways are provided to allow the signal to travel through the package 1000, such as one or more conductive vias, one or more conductive lines, microspheres, bump bonds, ball grid arrays, or a combination thereof. The conductive pathways may be arranged in various layers of the substrates 1002, 1004, 1006. An amplifying device 1016 is provided in a readout communication path between the quantum readout device 1010 and the external connector port 1012, to amplify readout signals from the quantum readout device 1010.

[0066] As shown in Fig. 10, the amplifying device 1016 may be carried by the interposer 1004 and coupled to the quantum readout device 1010 through a conductive path. In some embodiments, the amplifying device is placed at an opposite surface of the interposer 1004 from the quantum readout device 1010 to minimize its interaction with the qubits in the qubit circuit 1008 in the qubit substrate 1002.

[0067] In some embodiments, the amplifying device is placed in a substrate separate from the substrate carrying the qubit circuit and the substrate carrying the quantum readout device. An example embodiment of such an implementation is shown in Fig. 1 1. A superconducting quantum processor package 1100 comprises a package substrate 1106 and an external connector port 1 112. A qubit substrate 1102 carries a qubit circuit 1108 that is aligned with a quantum readoutdevice 1110 carried by an interposer 1 104. An amplifier substrate 1120 carries an amplifying device 11 16 coupled between the quantum readout device 11 10 and the external connector port 1 112. As such, the amplifying device 1116 is still provided in the readout communication path, as per the example shown in Fig. 10, and may still amplify readout signals from the quantum readout device 1 110.

[0068] With reference to Figs. 12A and 12B, there are shown two example embodiments of an amplifying device. In Fig. 12A, an amplifying device 1202 is shown to comprise at least one amplifier 1204 and at least one circulator 1206. In some embodiments, the amplifier 1204 is a parametric amplifier, such as a Josephson Parametric Amplifier (JPA). The JPA may be a high-gain and broadband cryogenic amplifier designed to amplify low power microwave signals. In this manner, the JPA introduces very low noise to the signal such that its noise temperature approaches the quantum limit. The JPA operates at the lowest temperature of a dilution refrigerator, i.e. below 50 milliKelvin. Although not illustrated, a DC current and an RF signal pump signal are provided to the JPA. In some embodiments, the amplifier 1204 is a Traveling Wave Parametric Amplifier (TWPA). The TWPA may be a Josephson junction TWPA, a kinetic inductance TWPA, and the like. More than one amplifier 1204 may be used to further increase the signal-to-noise ratio. The circulator 1206 may be used to block a reflected signal from the amplifier 1204. In the embodiment of Fig. 12B, another circulator 1212 is also provided in an amplifying device 1222, at the output of the amplifier 1204, to protect the amplifier 1204 from noise passing through the output line in reverse. The embodiments of Figs. 12A and 12B may be used with the superconducting quantum processor packages 1000, 1100. The readout signal coming from the quantum readout device 1010, 1 110, enters the amplifying device 1202, 1222 through input 1208 and exits through output 1210 to continue its path towards the external connector port 1012, 11 12.

[0069] In some embodiments, and as shown in Figs. 13A and 13B, a bi-directional external coupler port 1312 may be used for both input and output transmission of signals. A signal comes in through external connector port 1312 and travels through package substrate 1306 and interposer 1304 to reach a transmission line in quantum readout device 1310. Readout signals measured from qubit circuit 1308 carried by qubit substrate 1302 travel back through the same path, from quantum readout device 1310 to amplifying device 1316 and to external connector port 1312. In Fig. 13A, the amplifying device 1316 is carried by the interposer. In Fig. 13B, the amplifying device 1316 is carried by amplifier substrate 1318.

[0070] In the implementations using a bi-directional external connector port 1312, the amplifying device 1316 may be configured as shown in the example of Fig 14. An incoming signal is received at port 1410 and flows through circulator 1406 towards port 1408, such that it does not flow throughamplifier 1404. Port 1408 is connected to the quantum readout device. A signal received at port 1408 from the quantum readout device flows through circulator 1406 towards amplifier 1404. The amplified signal is reflected back to circulator 1406 and travels out of the amplifying device 1402 through port 1410, which is connected to the external coupler port, for example bi-directional external coupler port 1312. Other embodiments for the amplifying device 1316 may also be used.

[0071] In some embodiments, the superconducting quantum processor package comprises a plurality of qubit substrates and one or more amplifying substrates, each carrying one or more amplifying devices. Example implementations are shown in Figs. 15A-15C. Fig. 15A shows a top view of a first example embodiment. A package 1500 comprises a package substrate 1502 and an interposer 1504. A pair of qubit substrates 1506A, 1506B are disposed on the interposer 1504, and a coupling substrate 1508 overlaps the qubit substrates 1506A, 1506B, to selectively couple at least one qubit from a qubit circuit in qubit substrate 1506A with at least one qubit from a qubit circuit in qubit substrate 1506B. An amplifying substrate 1510 is disposed along an outside edge of the first and second qubit substrates 1506A, 1506B. Amplifying devices 1512A, 1512B are carried by amplifying substrate 1510, and are respectively coupled to quantum readout devices (not shown) in the interposer 1504. Various other embodiments may be used for the superconducting quantum processor package with multiple qubit substrates and amplifying substrates. For example, and as shown in the example of Fig. 15B, there may be four qubit substrates 1056A, 1506B, 1506C, 1506D and one coupling substrate 1508. Amplifying substrates 1510A, 1510B may be provided on each outside edge of pairs of qubit substrates, such that amplifying device 1512A is associated with a quantum readout device coupled with a qubit circuit carried by qubit substrate 1506A, amplifying device 1512B is associated with a quantum readout device coupled with a qubit circuit carried by qubit substrate 1506B, amplifying device 1512C is associated with a quantum readout device coupled with a qubit circuit carried by qubit substrate 1506C, and amplifying device 1512D is associated with a quantum readout device coupled with a qubit circuit carried by qubit substrate 1506D. Alternatively, each pair of qubit substrate may be associated with coupling substrate, such that an implementation with four qubit substrates has two coupling substrates, an implementation with six qubit substrates has three coupling substrates, an implementation with eight qubit substrates has four coupling substrates, etc.

[0072] The amplifying substrates may be placed using various configurations around the perimeter of the qubit substrates. In some embodiments, each amplifying substrate carries a single amplifying device, as shown in the example of Fig. 15C. In this example, amplifying substrates 1522A, 1522B, 1522C, 1522D are provided at the corners of the interposer 1504, and carry amplifying devices 1512A, 1512B, 1512C, 1512D, respectively. A combination of the features shown insuperconducting quantum processor packages 1500, 1520, and 1530 may be used. For example, the amplifying substrates do not need to be disposed symmetrically on the interposer. In addition, there may be a package configuration having one amplifying substrate carrying multiple amplifying devices and another amplifying substrate carrying a single amplifying device. Furthermore, although the embodiments herein have shown each qubit substrate carrying a single qubit circuit, multiple qubit circuits may be provided per qubit substrate. Qubit circuits carried by a same qubit substrate may be electrically independent from each other, and associated with different quantum readout devices in the interposer. As such, various layouts for placement of the amplifying substrates and / or amplifying devices (in the interposer or in the amplifying substrate(s)) may be used to optimize spacing in the package and suitable connection through the various conductive paths provided on the various layers of the package.

[0073] The fabrication process of a superconducting quantum processor comprises steps of lithography, etching, characterization, deposition, and packaging. In addition, to the equipment usually needed to fabricate superconducting quantum processors, the additional equipment needed for the various architectures described herein may include one or more of: an Indium deposition tool; an Indium native oxide etching tool (e.g. atmospheric plasma etch); a CVD or ALD tool to coat sidewalls of the vias with superconducting materials; and a polisher to thin wafers to reveal vias.

[0074] The described embodiments and examples are illustrative and non-limiting. Practical implementation of the features may incorporate a combination of some or all of the aspects, and features described herein should not be taken as indications of future or existing product plans. Applicant partakes in both foundational and applied research, and in some cases, the features described are developed on an exploratory basis.

[0075] The term "connected" or "coupled to" may include both direct coupling (in which two elements that are coupled to each other contact each other) and indirect coupling (in which at least one additional element is located between the two elements).

[0076] Although the embodiments have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the scope. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification.

[0077] As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially thesame result as the corresponding embodiments described herein may be utilized. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

[0078] As can be understood, the examples described above and illustrated are intended to be exemplary only.

Claims

CLAIMS1 . A superconducting quantum processor package comprising: a package substrate having an external connector port; an interposer having first and second opposing surfaces, the first surface of the interposer facing the package substrate, the interposer carrying a first quantum readout device coupled to the external connector port; a first qubit substrate having top and bottom opposing surfaces, the bottom surface of the first qubit substrate facing the second surface of the interposer, the first qubit substrate carrying a first qubit circuit with interleaved qubits and couplers, the first qubit circuit coupled to the first quantum readout device, wherein the first qubit circuit, the first quantum readout device, and the external connector port form a first readout communication path; and a first amplifying device in the first readout communication path, coupled between the first quantum readout device and the external connector port, to amplify readout signals from the first quantum readout device.

2. The superconducting quantum processor package of claim 1 , wherein the first amplifying device is carried by the interposer.

3. The superconducting quantum processor package of claim 1 , further comprising a first amplifier substrate having top and bottom opposing surfaces, the bottom surface of the first amplifier substrate facing the second surface of the interposer, wherein the first amplifying device is carried by the first amplifier substrate, and wherein the first amplifier substrate is separate from and adjacent to the first qubit substrate.

4. The superconducting quantum processor package of any one of claims 1 to 3, wherein the first amplifying device comprises at least one amplifier and at least one circulator coupled thereto.

5. The superconducting quantum processor package of claim 4, wherein the circulator is coupled between the external connector port, the first quantum readout device, and the amplifier.

6. The superconducting quantum processor package of any one of claims 1 to 5, wherein the first amplifying device comprises a Josephson Parametric Amplifier (JPA).

7. The superconducting quantum processor package of any one of claims 1 to 6, wherein the interposer is bonded to the package substrate through a Ball Grid Array (BGA).

8. The superconducting quantum processor package of any one of claims 1 to 7, wherein the first qubit substrate is bonded to the interposer through a first grid of superconducting microspheres.

9. The superconducting quantum processor package of any one of claims 1 to 8, wherein the first quantum readout device comprises a plurality of resonators associated with a transmission line.

10. The superconducting quantum processor package of claim 9, wherein the resonators are arranged in a curved pattern and align with the qubits in the first qubit circuit also aligned in the curved pattern.

11. The superconducting quantum processor package of any one of claims 1 to 10, wherein the first quantum readout device comprises at least one filter.

12. The superconducting quantum processor package of any one of claims 1 to 11 , wherein the external connector port is by-directional and performs readout and input.

13. The superconducting quantum processor package of claim 1 , wherein the external connector port comprises a plurality of output lines, and the first amplifying device comprises a plurality of amplifiers each corresponding to one of the plurality of output lines.

14. The superconducting quantum processor package of any one of claims 1 to 13, further comprising: a second quantum readout device carried in the interposer; a second qubit substrate separate from the first qubit substrate and having top and bottom opposing surfaces, the bottom surface of the second qubit substrate facing the second surface of the interposer, the second qubit substrate carrying a second qubit circuit with interleaved qubits and couplers, the second qubit circuit coupled to the second quantum readout device; and a coupling substrate facing and overlapping with the top surfaces of the first qubit substrate and the second qubit substrate, the coupling substrate carrying at least one coupler configured for selectively coupling at least one qubit from the first qubit circuit with at least one qubit from the second qubit circuit.

15. The superconducting quantum processor package of claim 14, further comprising a second amplifying device coupled between the second quantum readout device and the external connector port, to amplify readout signals from the second qubit circuit.

16. The superconducting quantum processor package of claim 14, further comprising a second amplifying device coupled between the second quantum readout device and a second external connector port on the package substrate, to amplify readout signals from the second qubit circuit.

17. The superconducting quantum processor package of any one of claims 14 to 16, further comprising: third and fourth quantum readout devices carried in the interposer; and third and fourth qubit substrates separate from the first and second qubit substrates, carrying third and fourth qubit circuits, respectively, and coupled to the third and fourth quantum readout devices, respectively; wherein the coupling substrate overlaps with the first, second, third, and fourth qubit substrates, and the at least one coupler is configured for selectively coupling at least one qubit from any one of the first, second, third and fourth qubit circuits with at least one qubit from any other one of the first, second, third and fourth qubit circuits.

18. The superconducting quantum processor package of claim 17, further comprising third and fourth amplifying devices coupled to the third and fourth quantum readout devices, respectively.

19. The superconducting quantum processor package of claim 18, wherein the second, third, and fourth amplifying devices are carried in the interposer.

20. The superconducting quantum processor package of claim 18, wherein the second, third, and fourth amplifying devices are carried are carried by second, third and fourth amplifier substrates, respectively, which are separate from the first, second, third and fourth qubit substrates and sit on the interposer.