Method for forming shallow trench isolation structure

An isolation structure and shallow trench technology, applied in electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve the problem of poor isolation performance of shallow trench isolation structure, semiconductor devices prone to leakage, affecting the stability of semiconductor devices, etc. problems, to achieve the effect of eliminating the Q-time effect, improving the uniformity of film thickness, and being less prone to leakage.

CN103545243AActive Publication Date: 2014-01-29SHANGHAI HUALI MICROELECTRONICS CORP
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Publication Date
2014-01-29

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Abstract

The invention provides a method for forming a shallow trench isolation structure. After a first oxidation layer is formed through the SACVD technology, the dry etching technology is executed to eliminate a fragile face of the first oxidation layer, and then a second oxidation layer is formed through the SACVD technology. The shallow trench isolation structure formed with the method is good in isolation effect, and a semiconductor device comprising the shallow trench isolation structure is good in stability and not prone to electric leakage and breakdown. Besides, the hydrogen passivation technology is added, unsaturated bonds on the surface of a film can be eliminated with the hydrogen passivation technology, and thus the deposition rate of the subsequent technology is stable, and finally the thickness uniformity of the film is improved. Furthermore, the oxygen plasma processing technology is adopted, hydrogen bonds on the surface and the surface layer of the structure are effectively removed through O2 plasma to eliminate the Q-time effect of the deposition rate of the subsequent manufacturing process, and thus the structure is more stable before the deposition of the subsequent manufacturing process.
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Description

Technical field

[0001] The present invention relates to the technical field of integrated circuit manufacturing, in particular to a method for forming a shallow trench isolation structure. Background technique

[0002] As the semiconductor process enters the deep sub-micron era, most of the components below 0.18 microns (for example, between the active areas of CMOS integrated circuits) are made by shallow trench isolation (STI) for lateral isolation. As the feature size of semiconductor devices continues to decrease, the size of the shallow trench isolation structure used for device isolation has also become smaller, and accordingly, the aspect ratio of the isolation trench used for forming the shallow trench isolation structure has increased.

[0003] In the existing advanced manufacturing process, starting from the 45-nanometer technology node, its shallow trench isolation process has begun to use sub-atmospheric chemical vapor deposition (SACVD) technology for trench oxide fill...

Examples

Embodiment Construction

[0030] As described in the background art, as the feature size of semiconductor devices continues to decrease, the size of the shallow trench isolation structure used for device isolation also becomes smaller, and the aspect ratio of the isolation trench used to form the shallow trench isolation structure changes. When the oxide layer is filled and formed in the isolation trench through the SACVD process, fragile surfaces are likely to appear, resulting in poor isolation performance of the shallow trench isolation structure, and semiconductor devices containing the shallow trench isolation structure are prone to leakage and poor stability. For this reason, after the first oxide layer is formed by the SACVD process in the present invention, a dry etching process is performed to eliminate the fragile surface, and then the second oxide layer is formed by the SACVD process, and then the planarization process is performed, thereby forming a shallow trench The isolation effect of the ...