Load-based dynamic frequency compensation method and device

Abstract

The present invention relates to a load-based dynamic frequency compensation method and device. The device comprises: a charge pump unit, the output end of the charge pump unit is connected to a voltage divider module; an error amplification unit, the error amplification unit is connected to the voltage divider module; a dynamic frequency compensation unit, one end of the dynamic frequency compensation unit is connected to the output end of the error amplification unit, and the other end is connected to the charge pump unit, the dynamic frequency compensation unit realizes that the zero point of the device changes with the load and compensates for the change of the secondary pole. In the present invention, a load-based dynamic frequency compensation unit is used to compensate the charge pump unit, and the zero point changes with the change of the load. Therefore, the unit gain bandwidth of the system is increased, which does not affect the stability of the system and improves the response speed.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a load-based dynamic frequency compensation method and device. Background Art

[0002] With the increasing popularity of smart phones, people have put forward higher and higher requirements for the display effect of mobile smart terminal LCD screens, and wide-screen, high-resolution and high-performance display effects have become the mainstream. Therefore, the functions and performance of mobile smart terminal LCD display driver chips have also been increasingly challenged.

[0003] The charge pump is an important power management unit in the LCD driver chip, providing deflection voltage for the liquid crystal molecules. When the liquid crystal molecules in all pixel arrays flip, the transient current of the response will have a large transient overshoot, and the charge pump will not be able to respond in time. Therefore, it takes several clock cycles of charging and discharging to return to a stable state. With the improvement of screen resolution, for high-resolution displays such as WVGA (Wide Video Graphics Array) and HD (High Definition), when the swing amplitude is the heaviest and the load is the heaviest, the voltage drive output for the GAMMA curve correction required for display must reach 95% of the steady-state value within 1 / 3 of the line time. As the number of pixels increases, the time left for transient response becomes shorter and shorter. Therefore, for the power system, a faster transient response speed is required, that is, a shorter power recovery time. Therefore, the stability and fast response capability of the charge pump unit are posed with higher challenges.

[0004] To solve the above technical problems, the following two methods are generally used in the prior art:

[0005] Method 1 is to use feedback control, refer to Figure 1 As shown, the output end of the charge pump circuit is connected to the negative input end of the comparator, the output voltage OUTPUT is compared with the reference voltage Reference Voltage, and the compared Flag signal is output to adjust the charge and discharge process of the charge pump circuit, so that the output voltage OUTPUT is kept near the Reference Voltage, thereby improving the accuracy of the output voltage. However, this method generates large ripples, and the rise time of the transient response of the output voltage is affected by the comparator and the clock cycle, which will produce a certain system delay. Therefore, the improvement of the response time of the large current load is limited.

[0006] The second method is to use the Miller compensation method of resistor Rz and capacitor Cc to achieve smaller ripple. However, the system bandwidth BW=gm1 / 2πCc achieved by this method. If you want to improve the response speed of the system, you need to increase gm1 or reduce the compensation capacitor Cc. The former requires increasing the aspect ratio W / L of the transistor or the bias current, while the latter requires sacrificing the phase margin and causing instability. In addition, under the conditions of widescreen and high-resolution display, such as Figure 2 As shown, when the load current Iload is within a wide range of large load current Imax, the secondary pole of the system will change with the change of the load current. This method generates a zero point Z1=1 / (Rz-1 / gm2)Cc for compensation. The relatively fixed zero point Z1 is difficult to adapt to the change range of the secondary pole P2, thereby affecting the stability of the system.

[0007] Therefore, it is necessary to propose a faster response method for the power system to meet the requirements of wide-band and high-resolution display and large load on the response speed of the power system. Summary of the invention

[0008] The object of the present invention is to provide a load-based dynamic frequency compensation method and device to solve the technical problem in the prior art that the charge pump circuit is difficult to respond quickly and maintain stability.

[0009] In order to solve the above technical problems, the present invention provides a load-based dynamic frequency compensation method, which realizes that the zero point of the device changes with the load and compensates for the change of the secondary pole, thereby achieving stability of the device.

[0010] Optionally, the zero point and the secondary pole of the device increase as the load increases, or decrease as the load decreases.

[0011] Accordingly, the present invention also provides a load-based dynamic frequency compensation device, comprising:

[0012] A charge pump unit, wherein the output end of the charge pump unit is connected to the voltage dividing module;

[0013] an error amplifying unit, wherein the error amplifying unit is connected to the voltage dividing module;

[0014] A dynamic frequency compensation unit, one end of which is connected to the output end of the error amplification unit, and the other end is connected to the charge pump unit. The dynamic frequency compensation unit realizes that the zero point of the device changes with the load and compensates for the change of the secondary pole.

[0015] Optionally, the zero point and the secondary pole increase as the load increases, or decrease as the load decreases.

[0016] Optionally, the dynamic frequency compensation circuit includes:

[0017] A first NMOS transistor, a drain of which is connected to the output end of the error amplifying unit, and a gate of which is connected to a working power supply;

[0018] A first capacitor, wherein one electrode of the first capacitor is connected to the source of the first NMOS transistor, and the other electrode of the first capacitor is connected to the ground;

[0019] The first PMOS transistor has a source connected to the working power supply, a drain connected to the input end of the charge pump unit, and a gate connected to the output end of the error amplification unit.

[0020] Optionally, the dynamic frequency compensation circuit includes:

[0021] A first NMOS transistor, a drain of which is connected to the output end of the error amplifying unit, and a gate of which is connected to a working power supply;

[0022] a first capacitor, wherein one electrode of the first capacitor is connected to the source of the first NMOS transistor, and the other electrode of the first capacitor is connected to the output end of the charge pump unit;

[0023] The first PMOS transistor has a source connected to the working power supply, a drain connected to the input end of the charge pump unit, and a gate connected to the output end of the error amplification unit.

[0024] Optionally, the output end of the charge pump unit is a positive power supply voltage.

[0025] Optionally, the dynamic frequency compensation circuit includes:

[0026] A first PMOS transistor, a source of which is connected to the output end of the error amplifying unit, and a gate of which is connected to the ground end;

[0027] a first capacitor, wherein one electrode of the first capacitor is connected to the drain of the first PMOS transistor, and the other electrode of the first capacitor is connected to the ground;

[0028] The first NMOS transistor has a source connected to the ground, a drain connected to the input end of the charge pump unit, and a gate connected to the output end of the error amplifying unit.

[0029] Optionally, the dynamic frequency compensation circuit includes:

[0030] A first PMOS transistor, a source of which is connected to the output end of the error amplifying unit, and a gate of which is connected to the ground end;

[0031] a first capacitor, wherein one electrode of the first capacitor is connected to the drain of the first PMOS transistor, and the other electrode of the first capacitor is connected to the output end of the charge pump unit;

[0032] The first NMOS transistor has a source connected to the ground, a drain connected to the input end of the charge pump unit, and a gate connected to the output end of the error amplifying unit.

[0033] Optionally, the output end of the charge pump unit is a negative power supply voltage.

[0034] Optionally, the voltage divider unit includes a first resistor and a second resistor connected in series, the first resistor is connected between the output end of the charge pump unit and the input end of the error amplification unit, and the second resistor is connected between the input end of the error amplification unit and a ground end.

[0035] Compared with the prior art, the load-based dynamic frequency compensation method and device of the present invention have the following beneficial effects:

[0036] In the present invention, a dynamic frequency compensation circuit is used to compensate the charge pump unit. As the load current changes, the frequency of the zero point also changes and is used to compensate for the change of the secondary pole, so that the unit gain bandwidth of the system is increased, which does not affect the stability of the system and improves the response speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 It is a circuit diagram of a voltage-stabilizing charge pump device in the prior art;

[0038] Figure 2 is a curve of gain variation under different loads in the second prior art method;

[0039] Figure 3 A circuit diagram of a charge pump device according to an embodiment of the present invention;

[0040] Figure 4 is a circuit diagram of a charge pump device in a first embodiment of the present invention;

[0041] Figure 5 is a circuit diagram of a charge pump device in a second embodiment of the present invention;

[0042] Figure 6 is a circuit diagram of a charge pump device in Embodiment 3 of the present invention;

[0043] Figure 7 is a circuit diagram of a charge pump device in a fourth embodiment of the present invention;

[0044] Figure 8 It is the simulation result of the charge pump device in the second prior art method;

[0045] Fig. 9 FIG. 4 is a simulation result of a charge pump device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0046] Many specific details are set forth in the following description to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways than those described herein, and those skilled in the art can make similar generalizations without violating the connotation of the present invention, so the present invention is not limited to the specific implementation disclosed below.

[0047] Secondly, the present invention is described in detail using schematic diagrams. When describing the embodiments of the present invention in detail, for the convenience of explanation, the schematic diagrams are only examples and should not limit the scope of protection of the present invention.

[0048] In order to make the above-mentioned objects, features and advantages of the present invention more clearly understood, reference is made to Figure 3 As shown in , the load-based dynamic frequency compensation device provided by the present invention includes:

[0049] A charge pump unit 10, wherein the charge pump unit 10 includes an N-stage charge pump circuit, and an output end of the charge pump unit 10 is connected to a voltage dividing unit 20;

[0050] An error amplifying unit 30, wherein an input end of the error amplifying unit 30 is connected to the voltage dividing module 20;

[0051] A dynamic frequency compensation circuit 40 , one end of which is connected to the output end of the operational amplifier 30 , and the other end of which is connected to the charge pump unit 10 .

[0052] In the load-based dynamic frequency compensation method of the present invention, the dynamic frequency compensation circuit 40 can make the zero point and the sub-pole of the device increase simultaneously with the increase of the load, or the zero point and the sub-pole decrease simultaneously with the decrease of the load, so that the zero point can track the change of the compensation sub-pole, and improve the bandwidth and response speed of the charge pump device. The specific implementation of the load-based dynamic frequency compensation method and device of the present invention is described below in conjunction with the accompanying drawings. Embodiment 1

[0053] refer to Figure 4As shown, in this embodiment, the charge pump unit 10 includes a multi-stage charge pump circuit, and the output ends of each charge pump circuit are connected and connected to the voltage divider module 20. The voltage divider module 20 includes a first resistor R1 and a second resistor R2 connected in series, the first resistor R1 is connected between the output end of the charge pump unit 10 and the input end of the operational amplifier 30, and the second resistor R2 is connected between the input end of the operational amplifier 30 and the ground GND. Specifically, the two stages of the first resistor R1 are respectively connected to the output end of the charge pump unit 10 and the positive input end of the operational amplifier 30, and the two poles of the second resistor R2 are respectively connected to the positive input end of the operational amplifier 30 and the ground GND. The voltage divider module 20 is used to divide the output voltage VOUT of the charge pump unit 10 and provide it to the error amplification unit 30, and the error amplification unit compares and amplifies the voltage signal after the voltage division.

[0054] Specifically, the error amplification unit 30 is an operational amplifier, the voltage divider unit 20 is connected to the positive input terminal of the operational amplifier 30, and the negative input terminal of the operational amplifier is connected to a reference voltage VREF. The voltage provided by the voltage divider unit to the operational amplifier is VOUT×(R2 / R1+R2), and the operational amplifier compares and amplifies the voltage with the reference voltage VREF at the negative input terminal, and provides the compared voltage signal to the dynamic frequency compensation circuit 40. Of course, the error amplification unit in the present invention is not limited to an operational amplifier, but can also be other circuits with signal amplification function. In addition, the connection relationship between the positive and negative input terminals of the operational amplifier is not limited to this, and the positive input terminal can also be connected to a reference voltage. This is a setting based on the actual circuit structure, and the present invention is not limited to this.

[0055] Continue to refer Figure 4 As shown, the dynamic frequency compensation circuit 30 in this embodiment includes:

[0056] A first NMOS transistor MT, wherein a drain of the first NMOS transistor MT is connected to the output terminal of the operational amplifier 30, and a gate of the first NMOS transistor MT is connected to a working power supply VDD;

[0057] A first capacitor Cc, wherein one electrode of the first capacitor Cc is connected to the source of the first NMOS transistor MT, and the other electrode of the first capacitor Cc is connected to the ground terminal GND;

[0058] A first PMOS transistor MREG, wherein a source of the first PMOS transistor MREG is connected to a working power supply VDD, a drain of the first PMOS transistor MREG is connected to an input end of the charge pump unit 10 , and a gate of the first PMOS transistor MREG is connected to an output end of the operational amplifier 30 .

[0059] In this embodiment, the voltage at the positive input terminal of the operational amplifier 30 is compared with the reference voltage VREF, and the compared voltage signal is provided to the gate of the first PMOS transistor MREG to control the switch of the first PMOS transistor MREG.

[0060] After the voltage output by the operational amplifier passes through the dynamic frequency compensation circuit, the adjusted voltage signal VREG is output to the charge pump unit 10, thereby outputting a stable voltage VOUT. In this embodiment, the voltage VOUT at the output end of the charge pump unit 10 is a positive power supply voltage, for example, a positive power supply voltage of 3V~5V, and

[0061] .

[0062] The sub-pole size of the charge pump device is: (1)

[0063] The zero point size of the charge pump device is: (2)

[0064] During the operation of the charge pump device, the first NMOS transistor MT operates in the linear region and is equivalent to a resistor with a resistance value of Rt. The first PMOS transistor MREG operates in the saturation region. It is necessary to ensure that the voltage difference between the gate and source of the first PMOS transistor MREG is equal to the voltage difference between the gate and source of the first NMOS transistor MT, and is equal to the difference between the working power supply VDD and the output power supply of the operational amplifier 30, that is: VGSP=VGSN=VDD-VG.

[0065] Adjust the first PMOS transistor MREG , assuming VTHP≈VTHN, the resistance of the first NMOS transistor MT is: (3)

[0066] Then the size of the zero point (4)

[0067] Among them, μn is the electron mobility, Coxn is the gate oxide capacitance per unit area of ​​the NMOS transistor, (W / L)n is the width-to-length ratio of the first NMOS transistor MT, Kn represents the μnCoxn (W / L)n coefficient of the first NMOS transistor MT, Kp represents the μpCoxp (W / L)p coefficient of the first PMOS transistor MREG, μp is the hole mobility, Coxp is the gate oxide capacitance per unit area of ​​the PMOS transistor, (W / L)p is the width-to-length ratio of the first NMOS transistor MT, λ is the channel length modulation coefficient of the first PMOS transistor MREG, and Iload is the load current.

[0068] From formulas (1) and (4), it can be seen that the zero point Z1 and the secondary pole P2 are both proportional to the load current Iload. Therefore, as the load current Iload increases, the zero point Z1 and the secondary pole P2 both increase, or as the load current decreases, the zero point Z1 and the secondary pole P2 both decrease. By adjusting the Kn coefficient of the first NMOS transistor, the Kp coefficient of the first PMOS transistor, and the size of the first capacitor Cc, for example, by changing the process conditions such as the ion doping concentration during the preparation of the MOS transistor, the zero point Z1 and the secondary pole P2 increase with the load at the same time, so that the zero point Z1 can track and compensate the secondary pole P2, and the charge pump device can track the change of the load current Iload, achieve a higher system bandwidth, and obtain a faster transient response. Embodiment 2

[0069] The difference from the first embodiment is that Figure 5 As shown, the dynamic frequency compensation circuit 40 includes:

[0070] A first NMOS transistor MT, wherein a drain of the first NMOS transistor MT is connected to the output end of the operational amplifier 30, and a gate of the first NMOS transistor MT is connected to the working power supply VDD;

[0071] a first capacitor Cc, wherein one electrode of the first capacitor Cc is connected to the source of the first NMOS transistor MT, and the other electrode is connected to the output end of the charge pump unit 10;

[0072] A first PMOS transistor MREG, wherein a source of the first PMOS transistor MREG is connected to a working power supply VDD, a drain of the first PMOS transistor MREG is connected to an input end of the charge pump unit 10 , and a gate of the first PMOS transistor MREG is connected to an output end of the operational amplifier 30 .

[0073] The principle of dynamic frequency compensation in this embodiment is the same as that in the first embodiment. By adjusting the Kn coefficient of the first NMOS transistor, the Kp coefficient of the first PMOS transistor and the size of the first capacitor Cc, the zero point Z1 and the sub-pole P2 of the compensation load change increase with the increase of the load, or decrease with the decrease of the load at the same time. The zero point can track the compensation sub-pole to achieve high bandwidth gain and fast transient response, which will not be described in detail here. It should be noted that the first NMOS transistor MT and the first capacitor Cc in this embodiment are connected in series at both ends of the charge pump unit and the gate of the first PMOS transistor MREG, while the first PMOS transistor MREG and the first capacitor Cc in the first embodiment are connected to the output end of the operational amplifier, so that the capacitance value of the first capacitor Cc in the second embodiment can be set smaller, thereby reducing the area of ​​the circuit. Embodiment 3

[0074] Different from the first embodiment, in this embodiment, the output voltage VOUT of the charge pump unit 10 is a negative power supply voltage, for example, a negative voltage of 3V to 5V. Figure 6 As shown, the dynamic frequency compensation circuit 40 includes:

[0075] A first PMOS transistor MT, wherein a source of the first NMOS transistor MT is connected to the output terminal of the operational amplifier, and a gate of the first NMOS transistor MT is connected to the ground terminal;

[0076] a first capacitor Cc, wherein one electrode of the first capacitor Cc is connected to the drain of the first PMOS transistor MT, and the other electrode of the first capacitor Cc is connected to the output end of the charge pump unit 10;

[0077] A first NMOS transistor MREG, wherein a source of the first NMOS transistor MREG is connected to the ground terminal GND, a drain of the first NMOS transistor MREG is connected to the input terminal of the charge pump unit 10 , and a gate of the first NMOS transistor MREG is connected to the output terminal of the operational amplifier 30 .

[0078] In this embodiment, the voltage at the positive input terminal of the operational amplifier 30 is compared with the reference voltage VREF, and the compared voltage signal is provided to the gate of the first NMOS transistor MREG to control the switch of the first NMOS transistor MREG.

[0079] After the voltage output by the operational amplifier passes through the dynamic frequency compensation circuit, the adjusted voltage signal VREG is output to the charge pump unit 10, thereby outputting a stable voltage VOUT. In this embodiment, the voltage VOUT at the output end of the charge pump unit 10 is a negative power supply voltage, for example, a positive power supply voltage of -3V to -5V, and

[0080] .

[0081] The sub-pole size of the charge pump device is: (1)

[0082] The zero point size of the charge pump device is: (2)

[0083] During the operation of the charge pump device, the first PMOS transistor MT operates in the linear region and is equivalent to a resistor with a resistance value of Rt. The first NMOS transistor MREG operates in the saturation region. It is necessary to ensure that the voltage difference between the gate and source of the first NMOS transistor MREG is equal to the voltage difference between the gate and source of the first PMOS transistor MT, and is equal to the difference between the ground terminal GND and the output power supply of the operational amplifier 30, that is: VGSP=VGSN=VG-GND.

[0084] Adjust the resistance of the first NMOS transistor MREG. Assuming VTHP≈VTHN, the resistance of the first PMOS transistor MT is:

[0085]

[0086] Among them, μp is the hole mobility, Coxp is the gate oxide capacitance per unit area of ​​the NMOS transistor, (W / L)p is the width-to-length ratio of the first PMOS transistor MT, Kp represents the μpCoxp (W / L)p coefficient of the first PMOS transistor MT, Kn represents the μnCoxn (W / L)n coefficient of the first NMOS transistor MREG, μn is the electron mobility, Coxn is the gate oxide capacitance per unit area of ​​the NMOS transistor, (W / L)n is the width-to-length ratio of the first NMOS transistor MREG, λ is the channel length modulation coefficient of the first NMOS transistor MREG, and Iload is the load current.

[0087] From formulas (1) and (4), it can be seen that the zero point Z1 and the secondary pole P2 are both proportional to the load current Iload. Therefore, as the load current Iload increases, the zero point Z1 and the secondary pole P2 both increase, or as the load current decreases, the zero point Z1 and the secondary pole P2 both decrease. By adjusting the Kn coefficient of the first NMOS transistor, the Kp coefficient of the first PMOS transistor, and the size of the first capacitor Cc, for example, by changing the process conditions such as the ion doping concentration during the preparation of the MOS transistor, the zero point Z1 and the secondary pole P2 increase with the load at the same time, so that the zero point Z1 can track and compensate the secondary pole P2, and the charge pump device can track the change of the load current Iload, achieve a higher system bandwidth, and obtain a faster transient response. Embodiment 4

[0088] Different from the third embodiment, reference Figure 7 As shown, in this embodiment, the dynamic frequency compensation circuit includes:

[0089] a first PMOS transistor MT, wherein a source of the first PMOS transistor MT is connected to an input terminal of the charge pump unit 10 , and a gate of the first PMOS transistor MT is connected to a ground terminal GND;

[0090] a first capacitor Cc, wherein one electrode of the first capacitor Cc is connected to the drain of the first PMOS transistor MT, and the other electrode of the first capacitor Cc is connected to the output end of the charge pump unit 10;

[0091] A first NMOS transistor MREG, wherein a source of the first NMOS transistor MREG is connected to the ground terminal GND, a drain of the first NMOS transistor MREG is connected to the input terminal of the charge pump unit 10 , and a gate of the first NMOS transistor MREG is connected to the output terminal of the operational amplifier 30 .

[0092] The principle of dynamic frequency compensation in this embodiment is the same as that in the third embodiment. By adjusting the Kn coefficient of the first NMOS transistor, the Kp coefficient of the first PMOS transistor and the size of the first capacitor Cc, the change zero point Z1 and the sub-pole P2 of the compensation load increase simultaneously with the increase of the load, or decrease simultaneously with the decrease of the load. The zero point can track the compensation sub-pole to achieve high bandwidth gain and fast transient response, which will not be elaborated here.

[0093] refer to Figure 8 and Fig. 9 As shown, the prior art Figure 1 The simulation results of the charge pump device in the embodiment and the charge pump device of the present invention when the load is maximum Imax or minimum Imin are shown in Table 1. As can be seen from Table 1, the bandwidth of the prior art Maitreya compensation method is about 241~293KHz, while the bandwidth of the charge pump device of the present invention is about 834~1180KHz, which is much higher than the charge pump device in the prior art. In addition, the phase margin is not affected under different loads in the present invention.

[0094]

[0095] Table 1

[0096] To sum up, in the present invention, a dynamic frequency compensation circuit that tracks the load is used to compensate the charge pump unit. As the load current increases, the frequency of the dynamic zero point also increases. Therefore, the unit gain bandwidth of the system increases, which does not affect the stability of the system while improving the response speed.

[0097] Although the present invention has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A load-based dynamic frequency compensation method, characterized in that: The method realizes the zero point of the device changes with the load based on a dynamic frequency compensation unit, and compensates for the change of the secondary pole, thereby achieving the stability of the device; the device includes a charge pump unit and an error amplification unit, and the dynamic frequency compensation unit is connected between the charge pump unit and the error amplification unit; the dynamic frequency compensation unit includes a capacitor, a transistor 1 and a transistor 2, The capacitor and transistor 1 are used to realize the zero point, and the transistor 1 is connected to the output end of the error amplification unit; The gate of transistor 2 is connected to the output end of the error amplification unit, and the first electrode of transistor 2 is connected to the input end of the charge pump unit, wherein the voltage difference between the gate and source of transistor 2 is ensured to be equal to the voltage difference between the gate and source of transistor 1.

2. The load-based dynamic frequency compensation method according to claim 1, characterized in that: The zero and secondary pole of the device increase as the load increases, or decrease as the load decreases.

3. A load-based dynamic frequency compensation device, characterized in that: include: A charge pump unit, wherein the output end of the charge pump unit is connected to the voltage dividing module; an error amplifying unit, wherein the error amplifying unit is connected to the voltage dividing module; A dynamic frequency compensation unit, one end of which is connected to the output end of the error amplification unit, and the other end of which is connected to the charge pump unit, wherein the dynamic frequency compensation unit realizes that the zero point of the device changes with the load and compensates for the change of the secondary pole; The dynamic frequency compensation unit includes a capacitor, a transistor 1 and a transistor 2. The capacitor and transistor 1 are used to realize the zero point, and the transistor 1 is connected to the output end of the error amplification unit; The gate of transistor 2 is connected to the output end of the error amplifying unit, and the first electrode of transistor 2 is connected to the input end of the charge pump unit, wherein the voltage difference between the gate and source of transistor 2 is ensured to be equal to the voltage difference between the gate and source of transistor 1.

4. The load-based dynamic frequency compensation device according to claim 3, characterized in that: The zero point and the secondary pole increase as the load increases, or decrease as the load decreases.

5. The load-based dynamic frequency compensation device according to claim 3, characterized in that: The dynamic frequency compensation unit comprises: The transistor 1 is a first NMOS transistor, a drain of which is connected to the output end of the error amplifying unit, and a gate of which is connected to a working power supply; The capacitor is a first capacitor, one electrode of the first capacitor is connected to the source of the first NMOS transistor, and the other electrode of the first capacitor is connected to the ground; The transistor 2 is a first PMOS transistor, a source of which is connected to a working power supply, and a drain of which serves as the first electrode and is connected to an input end of the charge pump unit.

6. The load-based dynamic frequency compensation device according to claim 3, characterized in that: The dynamic frequency compensation unit comprises: The transistor 1 is a first NMOS transistor, a drain of which is connected to the output end of the error amplifying unit, and a gate of which is connected to a working power supply; The capacitor is a first capacitor, one electrode of the first capacitor is connected to the source of the first NMOS transistor, and the other electrode is connected to the output end of the charge pump unit; The transistor 2 is a first PMOS transistor, a source of which is connected to a working power supply, and a drain of which serves as the first electrode and is connected to an input end of the charge pump unit.

7. The load-based dynamic frequency compensation device according to claim 5 or 6, characterized in that: The output terminal of the charge pump unit is a positive power supply voltage.

8. The load-based dynamic frequency compensation device according to claim 3, characterized in that: The dynamic frequency compensation unit comprises: The transistor 1 is a first PMOS transistor, a source of which is connected to the output end of the error amplifying unit, and a gate of which is connected to the ground end; The capacitor is a first capacitor, one electrode of the first capacitor is connected to the drain of the first PMOS transistor, and the other electrode of the first capacitor is connected to the ground; The transistor 2 is a first NMOS transistor, a source of which is connected to the ground, and a drain of which serves as the first electrode and is connected to the input end of the charge pump unit.

9. The load-based dynamic frequency compensation device according to claim 3, characterized in that: The dynamic frequency compensation unit comprises: The transistor 1 is a first PMOS transistor, a source of which is connected to the output end of the error amplifying unit, and a gate of which is connected to the ground end; The capacitor is a first capacitor, one electrode of the first capacitor is connected to the drain of the first PMOS transistor, and the other electrode is connected to the output end of the charge pump unit; The transistor 2 is a first NMOS transistor, a source of which is connected to the ground, and a drain of which serves as the first electrode and is connected to the input end of the charge pump unit.

10. The load-based dynamic frequency compensation device according to claim 8 or 9, characterized in that: The output terminal of the charge pump unit is a negative power supply voltage.

11. The load-based dynamic frequency compensation device according to claim 3, characterized in that: The voltage divider module includes a first resistor and a second resistor connected in series, the first resistor is connected between the output end of the charge pump unit and the input end of the error amplification unit, and the second resistor is connected between the input end of the error amplification unit and a ground end.

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