Supporting multiple refresh rates in different regions of a panel display

Abstract

A system to reduce power consumed by a large screen display panel can include a display divided into a plurality of segments. A gaze tracker identifies a gaze area in which a viewer is looking, and increases a refresh rate for segments identified in the gaze area relative to segments outside the gaze area. A coloration rate of segments outside the gaze area can also be reduced to save even more power.

Description

TECHNICAL FIELD

[0001] Embodiments generally relate to display technology, and more particularly to partitioning a display and providing different refresh rates in areas of interest. BACKGROUND

[0002] In many households, large screen displays are typically 100 inches or larger. Such devices can consume a considerable amount of power. BRIEF DESCRIPTION OF DRAWINGS

[0003] Various advantages of embodiments will be apparent from reading the following description and drawings, in which:

[0004] Figure 1 is a block diagram illustrating a computer system configured to implement one or more aspects of the embodiments described herein;

[0005] Figures 2A-2D illustrates a parallel processor component according to an embodiment;

[0006] Figures 3A-3B is a block diagram of a graphics multiprocessor according to an embodiment;

[0007] Figures 4A-4F illustrates an exemplary architecture in which a plurality of GPUs are communicatively coupled to a plurality of multi-core processors;

[0008] Figure 5 illustrates a graphics processing pipeline according to an embodiment;

[0009] Figure 6 is a system block diagram of an electronic processing system of the kind that can be useful for gaze tracking;

[0010] Figures 7A-7C is a block diagram of a subsystem of Figure 6 in more detail;

[0011] Figure 8 is a block diagram of a partitioned large panel display according to an embodiment;

[0012] Figure 9 is a diagram showing a viewer enjoying a large panel display according to an embodiment;

[0013] Figure 10 is a flow diagram illustrating steps for providing multiple refresh rates in a partitioned large panel display;

[0014] Figure 11 is a block diagram of an example of a display with localized backlight capability according to an embodiment;

[0015] Figure 12A is a block diagram of an example of a data processing device according to an embodiment;

[0016] Figure 12B is a graphical illustration of an example of distance determination according to an embodiment;

[0017] Figure 13 is a block diagram of an example of a hierarchical display architecture according to an embodiment;

[0018] Figure 14 is a block diagram of an example of a display architecture including multiple display units according to an embodiment; and

[0019] Figure 15 is a block diagram of an example of a cloud-assisted media delivery architecture according to an embodiment;

[0020] Figures 16-18 is a block diagram of an example of an overview of a data processing system according to an embodiment;

[0021] Figure 19 is a block diagram of an example of a graphics processing engine according to an embodiment;

[0022] Figures 20-22 is a block diagram of an example of an execution unit according to an embodiment;

[0023] Figure 23 is a block diagram of an example of a graphics pipeline according to an embodiment;

[0024] Figures 24A-24B is a block diagram of an example of graphics pipeline programming according to an embodiment;

[0025] Figure 25 is a block diagram of an example of a graphics software architecture according to an embodiment;

[0026] Figure 26 is a block diagram of an example of an intellectual property (IP) core development system according to an embodiment; and

[0027] Figure 27 is a block diagram of an example of a system on a chip integrated circuit according to an embodiment. DETAILED DESCRIPTION

[0028] In the following description, numerous specific details are set forth to provide a more thorough understanding of the present application. However, it will be apparent to one of skill in the art upon

[0029] System Overview

[0030] Figure 1is a block diagram illustrating a computing system 100 configured to implement one or more aspects of the embodiments described herein. The computing system 100 includes a processing subsystem 101 with one or more processors 102 and a system memory 104 communicating via an interconnection path that can include a memory hub 105. The memory hub 105 can be a separate component coupled with one or more processors 102 via the interconnection path, or can be integrated within one or more processors 102. The memory hub 105 communicates with an I / O subsystem 111 via a communication link 106. The I / O subsystem 111 includes an I / O hub 107 that can enable the computing system 100 to receive input from one or more input devices 108. Additionally, the I / O hub 107 can enable output to one or more display devices 110A that can be included in the one or more processors 102. In one embodiment, one or more of the display devices 110A coupled with the I / O hub 107 can include a local, internal, or embedded display device.

[0031] In one embodiment, the processing subsystem 101 includes one or more parallel processor(s) 112 coupled to memory hub 105 via a bus or other communication link 113. The communication link 113 can be one of any number of standard-based communication links, such as a PCI Express, or can be a vendor specific communications interface or communications structure. In one embodiment, one or more parallel processor(s) 112 form a computationally intensive, parallel or vector processing system that can include a large number of processing cores and / or a large global cache memory. In one embodiment, one or more parallel processor(s) 112 form a graphics processing subsystem that can output pixels to one or more display device(s) 110A coupled via I / O hub 107. One or more parallel processor(s) 112 can also include a display controller and display interface (not shown) to enable a direct connection to one or more display device(s) 110B.

[0032] Within the I / O subsystem 111, a system storage unit 114 can be connected to the I / O hub 107 to provide storage mechanisms to store code to be executed by processing subsystem 101, as well as to store data to be accessed by the processing subsystem 101. An I / O switch 116 can be used to provide an interface mechanism to enable connections between the I / O hub 107 and other components such as a network adapter 118 and / or wireless network adapter 119 that can be integrated into the platform, as well as various other devices that can be added via one or more add-in devices 120. The network adapter 118 can be an Ethernet adapter or another wired network adapter. The wireless network adapter 119 can include one or more of a Wi-Fi, Bluetooth, near- field communication (NFC), or other network devices including one or more wireless radios.

[0033] The computing system 100 can include other components not explicitly shown including USB or other port connections, optical storage drives, video capture devices, and the like, which can also be connected to the I / O hub 107. The various components in the computing system 100 are interconnected using a communication path, which can be implemented using any suitable protocol, such as PCI (Peripheral Component Interconnect) -based protocols (e.g., PCI-Express), or any other bus or point-to-point communication interfaces and / or protocols (such as NV-Link high-speed interconnect or interconnect protocols known in the art). Figure 1 The communication path interconnecting the various components in the computing system 100 can be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect)-based protocol (e.g., PCI-Express), or any other bus or point-to-point communication interface and / or protocol, such as NV-Link high-speed interconnect, or interconnect protocols known in the art.

[0034] In one embodiment, the one or more parallel processors 112 incorporate circuitry optimized for graphics and video processing, including, for example, video output circuitry, and can constitute a graphics processing unit (GPU). In another embodiment, the one or more parallel processors 112 incorporate circuitry optimized for general use applications

[0035] It should be appreciated that the computing system 100 illustrated herein is illustrative and not limiting, and that variations and modifications are possible. The connection topology among the various components of the computing system 100, including the number and arrangement of bridges, the number of processors 102, and the number and arrangement of parallel processors 112 can be modified as desired. For example, in some embodiments, the system memory 104 is not connected via a bridge, but is directly connected to the processor(s) 102, while other devices communicate with the system memory 104 via the memory hub 105 and the processor(s) 102. In other alternative configurations, the parallel processor(s) 112 are connected to the I / O hub 107 or directly to one of the processor(s) 102, rather than to the memory hub 105. In still other embodiments, the I / O hub 107 and memory hub 105 are integrated into a single chip. Some embodiments can include two or more sets of the processor(s) 102 attached via multiple sockets, which can couple with two or more instances of the parallel processor(s) 112.

[0036] Some of the specific components shown herein are optional and can not be included in all implementations of the computing system 100. For example, any number of add-in cards or peripherals can be supported, or some components can be eliminated. Further, some architectures can use different terminology for components similar to those illustrated in Figure 1

[0037] Figure 2A A parallel processor 200 is illustrated according to one embodiment. The various components of the parallel processor 200 can be implemented, for example, using one or more integrated circuits, such as programmable processors, application specific integrated circuits (ASICs), or field programmable gate arrays (FPGAs). The parallel processor 200, according to one embodiment, is a variant of one or more of the parallel processors 112 shown in Figure 1

[0038] In one embodiment, the parallel processor 200 includes a parallel processing unit 202. The parallel processing unit includes an I / O unit 204 that enables communication with other devices including other instances of the parallel processing unit 202. The I / O unit 204 can be directly connected to the other devices. In one embodiment, the I / O unit 204 communicates with other devices via the use of a hub or switch, such as the memory hub 105. The connections between the memory hub 105 and the I / O unit 204 form a communication link 113. Within the parallel processing unit 202, the I / O unit 204 communicates with a host interface 206 and a memory crossbar switch 216, where the host interface 206 receives commands required to carry out processing tasks and the memory crossbar switch 216 facilitates communication with a memory 208.

[0039] ​​When the host interface 206 receives a command buffer via the I / O unit 204, the host interface 206 can direct work operations to execute those commands to the front end 208. In one embodiment, the front end 208 is coupled with a scheduler 210 that is configured to distribute commands or other work items to the processing cluster array 212. In one embodiment, the scheduler 210 ensures that the processing cluster array 212 is correctly configured and is in an enabled state before tasks are distributed to processing clusters of the processing cluster array 212. In one embodiment, the scheduler 210 is implemented via firmware logic executing on a microcontroller. The microcontroller- implemented scheduler 210 can be configured to perform complex scheduling and work distribution operations with coarse and fine grain granularity, enabling a fast preemption and context switch for threads executing on the processing array 212. In one embodiment, host software can prove a workload for scheduling on the processing array 212 via one of multiple graphics processing doorbells. The workload can then be automatically distributed by the scheduler 210 logic within the scheduler microcontroller on the processing array 212.

[0040] The processing cluster array 212 can include up to "N" processing clusters (e.g., cluster 214A, 214B, up to 214N). Each cluster 214A-214N of the processing cluster array 212 can execute a large number of concurrent threads. The scheduler 210 can allocate work to the clusters 214A-214N of the processing cluster array 212 using a variety of scheduling and / or work distribution algorithms, which can vary depending on the workload for each type of program or computation. The scheduling can be handled by the scheduler 210 dynamically or can be assisted in part by the compiler logic during compilation of program logic configured for execution on the processing cluster array 212. In one embodiment, different clusters 214A-214N of the processing cluster array 212 can be allocated for processing different types of programs or for performing different types of computations.

[0041] The processing cluster array 212 can be configured to perform a variety of processing operations. In one embodiment, the processing cluster array 212 is configured to perform general-purpose parallel compute operations. For example, the processing cluster array 212 can include logic to perform processing tasks including filtering of video and / or audio data, performing modeling operations including physical simulations, and performing data transformations.

[0042] In one embodiment, the processing cluster array 212 is configured to perform parallel general-purpose computing operations. In an embodiment in which the parallel processor 200 is configured to perform general-purpose computing operations, the processing cluster array 212 can include additional logic and / or circuitry to support such operations, including for example parallel floating point and fixed point accelerators: In one embodiment, the parallel processor 200 includes execution units 216A-216N being configured to perform operations on multiple data operands.

[0043] In one embodiment, when the parallel processor 200 is used to perform graphics processing, the scheduler 210 can be configured to divide the processing workload into approximately equal sized tasks, in order to better enable distribution of the graphics processing operations to multiple clusters 214A-214N of the processing cluster array 212. In some embodiments, portions of the processing cluster array 212 can be configured to perform different types of processing. For example a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform surface shading, and a third portion can be configured to perform pixel or other screen space operations, including rendering into a frame buffer. In some embodiments, the partitioning of processing tasks can be performed based upon the availability and capability of the processing clusters 214A-214N of the processing cluster array 212. In one embodiment, a processing task can be split into multiple sub-tasks, which are distributed to different clusters 214A-214N for parallel processing.

[0044] During operation, the processing cluster array 212 can receive processing tasks to be executed via the scheduler 210, which receives commands defining the processing tasks from the front end 208. For graphics processing operations, the processing task can include indices stored in registers or other storage mechanisms of the processing cluster array 212 used to identify characteristics of the data to be processed, such as texture data, vertex data, pixel data, and / or the like. The scheduler 210 can be configured to fetch such indices, or can receive the indices from the front end 208. The front end 208 can be configured to ensure the processing cluster array 212 is configured to be in an effective state before a workload specified by an incoming command buffer (e.g., a batch-buffer, a push buffer, and the like) is initiated.

[0045] Each of the one or more instances of parallel processing unit 202 can be coupled with a parallel processor memory 222. Parallel processor memory 222 can be accessed by the processing cluster array 212, as well as the I / O unit 204, via a memory crossbar 216. The memory crossbar 216 can be used to transfer data between the memory elements and the processing cluster array 212, and / or the I / O unit 204. The memory crossbar 216 can be configured to perform parallel memory access and release operations. The memory crossbar 216 can be configured to store or buffer multiple load and store operations, while the processing cluster array 212 is performing unrelated operations.

[0046] In various embodiments, memory units 224A-224N can include various types of memory devices including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR). In one embodiment, memory units 224A-224N can also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). Those skilled in the art will recognize that the specific implementation of memory units 224A-224N can vary, and that memory units 224A-224N can be selected from one of a variety of conventional designs. Render targets, such as frame buffers or texture maps, can be stored in memory units 224A-224N, allowing the partition units 220A-220N to write portions of each render target in parallel to efficiently use the available bandwidth of parallel processor memory 222. In some embodiments, a unified memory design that facilitates the use of system memory in combination with local cache memory can be advantageous to exclude local instances of parallel processor memory 222.

[0047] In one embodiment, any of the clusters 214A-214N of the processing cluster array 212 can process data to be written to any of the memory units 224A-224N within the parallel processor memory 222. The memory crossbar 216 can be configured to communicate the output of each cluster 214A-214N to any partition unit 220A-220N or another cluster 214A-214N, which can perform additional processing operations on the output. Each cluster 214A-214N can communicate through the memory crossbar 216 with the memory interface 218 to read from or write to various external memory devices. In one embodiment, memory crossbar 216 has a connection to memory interface 218 to communicate with an I / O unit 204, and a local instance of connection to the parallel processor memory 222, so that the processing units within different processing clusters 214A-214N can communicate with system memory or other memory that is not local to the parallel processor units 202. In one embodiment, memory crossbar 216 can use virtual channels to separate flow of traffic between clusters 214A-214N and partition units 220A-220N.

[0048] While a single instance of the parallel processor 200 is illustrated in the parallel processor 200, any number of instances of the parallel processor 200 can be included. For example, a plurality of instances of the parallel processor 200 can be provided on a single add-in card, or multiple add-in cards can be interconnected. The different instances of the parallel processor 200 can be configured to operate in association with with one or more other parallel processors 200. As one example and in one embodiment, some instances of the parallel processor 200 can include a higher precision floating point unit relative to other instances. Systems incorporating one or more instances of the parallel processor 200, or the parallel processor 200, can be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or hand-held personal computers, servers, workstations, game consoles, and / or embedded systems.

[0049] Figure 2B is a block diagram of a partition unit 220 according to one embodiment. In one embodiment, the partition unit 220 is a Figure 2AThe partition unit 220 is an example of one of the partition units 220A-220N of FIG. 2. As illustrated, the partition unit 220 includes an L2 cache 221, a frame buffer interface 225, and an ROP 226 (raster operations unit). The L2 cache 221 is a read / write cache configured to perform load and store operations received from the memory crossbar 216 and the ROP 226. Read misses and urgent writeback requests are output by the L2 cache 221 to the frame buffer interface 225 for processing. Updates can also be sent to the frame buffer via the frame buffer interface 225 for processing. In one embodiment, the frame buffer interface 225 interfaces with one of the memory units in the parallel processor memory, such as the memory units 224A-224N (e.g., within the parallel processor memory 222) of FIG. 2.

[0050] In graphics applications, the ROP 226 is a processing unit that performs raster operations such as stencil, z-test, blending, and so forth. The ROP 226 then outputs primed graphics data that is stored in graphics memory. In some embodiments the ROP 226 includes compression logic to compress depth or color data that is written to memory, and to decompress depth or color data that is read from memory. The compression logic can be lossless compression logic that uses one or more of a variety of compression algorithms. The type of compression performed by the ROP 226 can vary based on statistical properties of the data to be compressed. For example, in one embodiment, delta color compression is performed on depth and color data on a per-tile basis.

[0051] In some embodiments, the ROP 226 is included within each processing cluster (e.g., clusters 214A-214N of FIG. 2) instead of in the partition unit 220. In such embodiments, read and write requests for pixel fragment data are transmitted through the memory crossbar 216 instead of pixel fragment data. Pruned graphics data can be displayed on a display device, such as one of the one or more display devices 110, routed for further processing by the processor(s) 102, or routed for further processing by one of the processing entities within the parallel processor 200. Figure 1 Figure 2A

[0052] Figure 2C ​​is a block diagram of a processing cluster 214 within a parallel processing unit according to an embodiment. In one embodiment, the processing cluster is an instance of one of the processing clusters 214A-214N of FIG. 2. A processing cluster 214 can be configured to execute a large number of threads in parallel, where the term "thread" refers to an instance of a particular program executing on a particular set of input data. In some embodiments, single-instruction, multiple-data (SIMD) instruction issue techniques are used to support parallel execution of a large number of threads. In other embodiments, single-instruction, multiple-thread (SIMT) techniques are used to support parallel execution of a large number of typically synchronous threads. Unlike SIMD execution, where all processing engines typically execute the same instructions, SIMT allows different threads to follow divergent execution paths, though typically all threads within a group still execute the same instructions.

[0053] The operation of a processing cluster 214 can be controlled via a pipeline manager 232 that distributes processing tasks to SIMT parallel processors. The pipeline manager 232 receives instructions from the scheduler 210 of FIG. 2 and manages execution of those instructions via a graphics multiprocessor 234 and / or a texture unit 236. The illustrated graphics multiprocessor 234 is an exemplary instance of a SIMT parallel processor. However, various types of SIMT parallel processors of differing architectures can be included within a processing cluster 214. One or more instances of the graphics multiprocessor 234 can be included within a processing cluster 214. The graphics multiprocessor 234 can process data and a data crossbar 240 can be used to distribute the processed data to one of a number of possible destinations. The pipeline manager 232 can facilitate distribution by specifying destinations for processed data to be distributed via the data crossbar 240.

[0054] Each graphics multiprocessor 234 within a processing cluster 214 can include an identical set of functional execution logic (e.g., arithmetic logic, load store units, etc.). The functional execution logic can be configured in a pipelined manner in which new instructions can be issued before previous instructions are complete. The functional execution logic supports a variety of operations including integer and floating point arithmetic, comparison operations, Boolean operations, bit-shifting, and a range of single- and multiple-precision integer and floating-point mathematical functions. In one embodiment, the same functional-unit hardware can be leveraged to perform different operations using different configuration settings.

[0055] Instructions transferred to the processing cluster 214 form a thread. A set of threads executed on the set of parallel processing engines is a threadblock. One threadblock performs the same program for different input data. Each thread in the threadblock can be assigned to a different processing engine within the graphics multiprocessor 234. The threadblock can include fewer threads than are present in the processing engines within the graphics multiprocessor 234. When the threadblock includes fewer threads than are present in the processing engines, one or more of the processing engines can be idle during the execution of the threadblock. The threadblock can also include more threads than are present in the processing engines within the graphics multiprocessor 234. When the threadblock includes more threads than are present in the processing engines, multiple threadblocks can be executed in succession on the processing engines. In one embodiment, multiple threadblocks can be executed concurrently on the graphics multiprocessor 234.

[0056] In one embodiment, the graphics multiprocessor 234 includes an internal cache memory to perform load and store operations. In one embodiment, the graphics multiprocessor 234 can forfeit the internal cache and use the cache memory within the processing cluster 214 (e.g., the LI cache 308). Each graphics multiprocessor 234 can also have access to L2 Cache within the partition unit (e.g., the partition unit 220A-220N of FIG. 2), which is shared among all processing clusters 214 and can be used to communicate data between threads. The graphics multiprocessor 234 can also have access to a shared memory and / or a system memory, which can include one or more of a local parallel processor memory and a system memory. Any memory outside the parallel processor unit 202 can be accessed by the graphics multiprocessor 234 through the memory interface 218. Embodiments in which the processing cluster 214 includes multiple instances of graphics multiprocessor 234 can share a common set of instructions and data that can be stored in the LI cache 308.

[0057] Each processing cluster 214 can include an MMU 245 (memory management unit) configured to translate virtual addresses into physical addresses. In other embodiments, one or more instances of the MMU 245 can reside within the memory interface 218 of FIG. 2. The MMU 245 includes a set of page table entries (PTEs) used to translate virtual addresses into physical addresses and optional cache line indices. The MMU 245 can include an address translation lookaside buffer (TLB) or cache to reduce the latency of address translations. Processing the physical address can handle special cases, such as branch on address tried (BAT) instructions.

[0058] In graphics and compute applications, processing cluster 214 can be configured such that each graphics multiprocessor 234 is coupled to a texture unit 236 for performing texture mapping operations, e.g., determining texture sample positions, reading texture data, filtering texture data. Texture data is fetched from an internal texture LI cache (not shown) or, in some embodiments, from the LI cache within graphics multiprocessor 234, and, if desired for a particular application, from the L2 cache, local parallel processor memory, or system memory. Each graphics multiprocessor 234 outputs processed tasks to data crossbar 240 to provide processed tasks to another processing cluster 214 for further processing or storage in an L2 cache, local parallel processor memory, or system memory via memory crossbar 216. PreROP 242 (pre-raster operations unit) is configured to receive data from graphics multiprocessor 234, direct data to ROP units, which can be located within partition units (e.g., partition units 220A-220N of FIG. 2) as described herein. PreROP 242 unit can perform optimizations for color blending, organize pixel color data, and perform address translation.

[0059] It should be understood that the core architecture described herein is illustrative and that variations and modifications are possible. For example, any number of processing units, such as graphics multiprocessors 234, texture units 236, PreROP 242, etc., can be included within processing cluster 214. In addition, while only one processing cluster 214 is shown, any number of instances of parallel processing units can be included within processing cluster 214 as described herein. In one embodiment, each processing cluster 214 can be configured to operate independently of the other processing clusters 214 using separate and different processing units, LI caches, etc.

[0060] Figure 2D A graphics multiprocessor 234 according to one embodiment is shown. In such embodiments, graphics multiprocessor 234 is coupled with a pipeline manager 232 of a processing cluster 214. Graphics multiprocessor 234 has an execution pipeline that includes, without limitation, an instruction cache 252, an instruction unit 254, an address mapping unit 256, a register file 258, one or more general-purpose graphics processing unit (GPGPU) cores 262, and one or more load / store units 266. GPGPU cores 262 and load / store units 266 are coupled with a cache memory 272 and shared memory 270 via a memory and cache interconnect 268.

[0061] In one embodiment, instruction cache 252 receives a stream of instructions to be executed by the pipeline manager 232. The instructions are cached in the instruction cache 252 and dispatched for execution by the instruction unit 254. The instruction unit 254 can dispatch instructions to be executed by thread groups (e.g., warps) of instructions to the GPGPU cores 262. Each thread group can be assigned a unique thread group identifier and execute the same instructions with different data. The GPGPU cores 262 can fetch and execute these instructions, and then generate and populate the data cache 258 with the appropriate results. At least one batch of instructions (e.g., micro-ops, micro- operation packets, micro-threads, etc.) can be executed by the GPGPU cores 262 to conduct work on the data. The instruction cache 252 can receive multiple batches of instructions to be executed in parallel.

[0062] The register file 258 provides a set of registers to the functional units of the graphics processing engine 320. The register file 258 provides temporary storage for data computed by the functional units. In one embodiment, the register file 258 is split into registers files for each of the functional units (e.g., GPGPU cores 262, load / store unit 266) such that each functional unit has access to a dedicated portion of the register file 258. In one embodiment, the register file 258 is split into registers files for each of the different warps being executed by the graphics processing engine 320.

[0063] The GPGPU cores 262 can each include floating point, integer, and / or single instruction multiple data (SIMD) execution units supporting multiple programming models. In one embodiment, the GPGPU cores 262 are similar to the core described in FIG. 2A with respect to the number and type of instruction execution units, registers, and / or cache memory. For example, the GPGPU cores 262 described herein can be capable of executing multiple instructions

[0064] In one embodiment, the GPGPU cores 262 include SIMD execution logic capable of

[0065] The memory and cache interconnect 268 is an interconnect network that connects each of the functional units of graphics multiprocessor 324 to the register file 258 and shared memory 270. In one embodiment, the memory and cache interconnect 268 is a crossbar interconnect that allows load / store units 266 to initiate loads and stores between shared memory 270 and register file 258. Register file 258 can operate at similar frequencies as GPGPU cores 262, thus data transfers between GPGPU cores 262 and register file 258 are at very low latencies. Shared memory 270 can be used to enable communications between threads executing on the functional units within graphics multiprocessor 234. For example, cache memory 272 can be used by a first functional unit as a data cache, while the second functional unit uses the shared memory 270 as a program cache. Shared memory 270 can also be used for thread-safe execution of programs. In addition to storing automatic cached data, threads executing on GPGPU cores 262 can also store data in shared memory 270.

[0066] Figures 3A-3B FIGS. 13A-13C illustrate additional graphics multiprocessors, according to embodiments. The illustrated graphics multiprocessors 325, 350 are variations of the graphics multiprocessor 234 of FIG. 12. Figure 2C The illustrated graphics multiprocessors 325, 350 can be configured to be a streaming multiprocessor (SM) capable of executing a large number of execution threads in parallel.

[0067] Figure 3A FIG. 13A illustrates a graphics multiprocessor 325 according to another embodiment. The graphics multiprocessor 325 includes a number of clusters 325A. Each cluster 325A includes a number of SIMD units 325B. In one embodiment, the graphics multiprocessor 325 is a variant of the graphics multiprocessor 234 of FIG. 12. In another embodiment, the graphics multiprocessor 325 is a variant of the graphics multiprocessor 324 of FIG. 13A. Figure 2Dadditional instances of execution resource units of graphics processor 234. For example, graphics processor 325 can include multiple instances of instruction units 332A-332B, register file 334A-334B, and texture unit(s) 344A-344B. Graphics processor 325 also includes multiple sets of graphics or compute execution units (e.g., GPGPU cores 336A-336B, GPGPU cores 337A-337B, GPGPU cores 338A-338B) and multiple sets of load / store units 340A-340B. In one embodiment, the execution resource units have a common instruction cache 330, texture and / or data cache memory 342, and shared memory 346.

[0068] The various components can communicate via an interconnect 327. In one embodiment, the interconnect 327 includes one or more crossbar switches to facilitate communication between the various components of graphics processor 325. In one embodiment, the interconnect 327 is a separate, high-speed network structure layer on which each of the components of graphics processor 325 are stacked. The components of graphics processor 325 communicate with remote components via the interconnect 327. For example, GPGPU cores 336A-336B, 337A-337B, and 338A-338B can each communicate with shared memory 346 via the interconnect 327. The interconnect 327 can arbitrate communications between the components within graphics processor 325 to ensure fair bandwidth allocation.

[0069] Figure 3B A graphics processor 350 according to another embodiment is shown. The graphics processor includes multiple sets of execution resources 356A-356D, where each set of execution resources includes multiple instruction units, register file, GPGPU cores, and load store units, as shown in Figure 2D and Figure 3A The execution resources 356A-356D can work in conjunction with texture unit(s) 360A-360D for texture operations while sharing instruction cache 354 and shared memory 362. In one embodiment, the execution resources 356A-356D can share instruction cache 354 and shared memory 362, as well as multiple instances of texture and / or data cache memory 358A-358B. The various components can communicate via an interconnect 352 similar to the interconnect 327 of Figure 3A .

[0070] Those of skill in the art will appreciate that Figure 1 , Figures 2A-2D and Figures 3A-3BThe architecture described in the middle is descriptive and does not limit the scope of the present embodiments. Thus, the techniques described herein can be implemented on any suitably configured processing unit, including but not limited to one or more mobile application processors, one or more desktop or server central processing units (CPUs) including multi-core CPUs, one or more parallel processing units such as parallel processing unit 202 of FIG. 2, and one or more graphics processors or specialized processing units without departing from the scope of the embodiments described herein.

[0071] In some embodiments, a parallel processor or GPGPU as described herein can be communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general purpose GPU (GPGPU) functions. The GPU can be communicatively coupled to the host processor / cores over a bus or other interconnect (e.g., a high-speed

[0072] Techniques for GPU interconnection with host processor

[0073] Figure 4A FIG. 2 illustrates an exemplary architecture in which multiple GPUs 410-413 are communicatively coupled to multiple multi-core processors 405-406 over high-speed links 440-443 (e.g., buses, point-to-point interconnects, etc.). In one embodiment, high-speed links 440-443 support a communication throughput of 4GB / s, 30GB / s, 80GB / s or higher, depending on implementation. Various interconnect protocols can be used including, but not limited to, PCIe 4.0 or 5.0 and NVLink 2.0. However, the underlying principles of the application are not limited to any particular communication protocol or throughput.

[0074] Additionally, in one embodiment, two or more GPUs 410-413 are interconnected over high-speed links 444-445, which can be implemented using the same or different protocol / links than used for high-speed links 440-443. Similarly, two or more of multi-core processors 405-406 can be connected by high-speed link 433, which can be a Symmetric Multi-Processor (SMP) bus that runs at 20GB / s, 30GB / s, 120GB / s or higher. Alternatively, Figure 4AAll communication between the various system components shown in the middle can be accomplished using the same protocol / link (e.g., over a common interconnect fabric). However, as mentioned, the underlying principles of the application are not limited to any particular type of interconnect technology.

[0075] In one embodiment, each multi-core processor 405-406 is communicatively coupled to a processor memory 401-402 via a memory interconnect 430-431, respectively, and each GPU 410-413 is communicatively coupled to a GPU memory 420-423 through a GPU memory interconnect 450-453, respectively. The memory interconnects 430-431 and 450-453 can utilize the same or different memory access technologies. By way of example and not limitation, the processor memories 401-402 and GPU memories 420-423 can be volatile memory such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or can be non-volatile memory such as 3D XPoint or Nano-Ram. In one embodiment, a portion of the memory can be volatile memory and another portion can be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0076] As described below, while the various processors 405-406 and GPUs 410-413 can be physically coupled to particular memories 401-402, 420-423, respectively, a unified memory architecture can be implemented in which the same virtual system address space (also referred to as an "effective address" space) is distributed across all of the various physical memories. For example, the processor memories 401-402 can each include 64 GB of system memory address space, and the GPU memories 420-423 can each include 32 GB of system memory address space (resulting in a total of 256 GB of addressable memory in this example).

[0077] Figure 4B Figure illustrates additional details for an interconnect between a multi-core processor 407 and a graphics acceleration module 446, according to one embodiment. The graphics acceleration module 446 can include one or more GPU chips integrated on a line card coupled to the processor 407 via a high-speed link 440. Alternatively, the graphics acceleration module 446 can be integrated on the same package or chip as the processor 407.

[0078] The illustrated processor 407 includes multiple cores 460A-460D, each with a translation lookaside buffer 461 A-461 D and one or more caches 462A-462D. The cores can include various other components for executing instructions and processing data that are not illustrated to avoid obscuring the principles of the present application (e.g., instruction fetch units, branch prediction units, decoders, execution units, reorder buffers, etc.). The caches 462A-462D can include level 1 (L1) and level 2 (L2) caches. Additionally, one or more shared caches 426 can be included in the cache hierarchy and shared by the multiple sets of cores 460A-460D. For example, one embodiment of the processor 407 includes 24 cores, each with its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one of the L2 and L3 caches is shared by two adjacent cores. The processor 407 and graphics accelerator integrated module 446 are connected with system memory 441, which can include processor memory 401-402

[0079] Consistency is maintained for data and instructions stored in the various caches 462A-462D, 456 and system memory 441 via inter-core communication over the coherence bus 464. For example, each cache can have cache coherency logic / circuitry associated therewith to communicate over the coherence bus 464 in response to detecting a read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented over the coherence bus 464 to snoop cache accesses. Cache snoop / coherency techniques are well-known by those skilled in the art and are not described in detail herein to avoid obscuring the principles of the present application.

[0080] In one embodiment, the proxy circuit 425 communicably couples the graphics acceleration module 446 to the coherence bus 464, allowing the graphics acceleration module 446 to participate in the cache coherency protocol as a peer to the cores. In particular, the interface 435 provides connectivity to the proxy circuit 425 over the high-speed link 440 (e.g., a PCIe bus, NVLink, etc.), and the interface 437 connects the graphics acceleration module 446 to the link 440.

[0081] In one implementation, the accelerator integration circuit 436 provides cache management, memory access, context management and interrupt management services on behalf of the graphics processing engines 431, 432, N of the graphics acceleration module 446. The graphics processing engines 431, 432, N can each comprise a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 431, 432, N can comprise different types of graphics processing engines within a GPU such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines. In other words, the graphics acceleration module can be a GPU with a plurality of graphics processing engines 431-432, N or the graphics processing engines 431-432, N can be individual GPUs that are integrated on a common package, line card, or chip.

[0082] In one embodiment, the accelerator integration circuit 436 includes a memory management unit (MMU) 439 to provide for translation of virtual addresses into physical addresses and for access permission checks, etc. The MMU 439 can include memory pointers to page tables that store addresses of pages and permissions to access these pages. The MMU 439 provides a set of memory management translation tables (which can include one or more page tables) to map virtual addresses into physical addresses and to check access permissions. The MMU 439 can also include a translation lookaside buffer (TLB) to accelerate the transfer of data between the system memory 441 and the graphics processing engines 431-432, N. In one embodiment, the graphics acceleration module 446 includes a cache 438 to cache data (e.g., from the system memory 441) for processing by the graphics processing engines 431-432, N. In one embodiment, the cache 438 is shared by the graphics processing engines 431-432, N. In another embodiment, the cache 438 is separate for each of the graphics processing engines 431-432, N.

[0083] A set of registers 445 store context data for threads executed by the graphics processing engines 431-432, N and a context management circuit 448 manages thread contexts. For example, the context management circuit 448 can perform save and restore operations to save and restore the context of various threads during context switches (e.g., so that a second thread can be executed by the graphics processing engines when a first thread is saved and the second thread is stored). For example, upon a context switch, the context management circuit 448 can store the current register values to a designated area in memory (e.g., identified by a context pointer). It can then restore the register values upon return to the context. In one embodiment, an interrupt management circuit 447 receives and processes interrupts from system devices.

[0084] In one implementation, virtual / effective addresses from the graphics processing engines 431 are translated by the MMU 439 to real / physical addresses in the system memory 411. One embodiment of the accelerator integration circuit 436 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 446 and / or other accelerator devices. The graphics accelerator modules 446 can be dedicated to a single application executing on the processor 407 or can be shared between multiple applications. In one embodiment, a virtualized graphics execution environment is presented where resources of the graphics processing engines 431-432, N are shared with multiple applications or virtual machines (VMs). The resources can be subdivided into“tiles” that are allocated to different VMs and / or applications based on processing requirements and priorities associated with the VMs and / or applications.

[0085] Thus, the accelerator integration circuit functions as a bridge for the system of graphics acceleration module 446 and provides address translation and system memory cache services. In addition, the accelerator integration circuit 436 can provide virtualization facilities for the host processor to manage virtualization of graphics processing engines, interrupts, and memory management.

[0086] Because the hardware resources of the graphics processing engines 431-432, N are explicitly mapped to the real address space seen by the host processor 407, any host processor can directly address these resources using effective address values. In one embodiment, one function of the accelerator integration circuit 436 is the physical segregation of the graphics processing engines 431-432, N so that they appear as independent units to the system.

[0087] As mentioned, in the illustrated embodiment, one or more graphics memories 433-434, M are coupled to each of the graphics processing engines 431-432, N, respectively. The graphics memories 433-434, M store instructions and data for processing by each of the graphics processing engines 431-432, N. The graphics memories 433-434, M can be volatile memory such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM and / or can be non-volatile memory such as 3DXPoint or Nano-Ram.

[0088] In one embodiment, to reduce data traffic on link 440, a biasing technique is used to ensure that data stored in graphics memory 433-434, M is data that will be most frequently used by graphics processing engines 431-432, N and preferably not used by cores 460A-460D (at least not frequently). Similarly, the biasing mechanism attempts to keep data needed by the cores (and preferably not graphics processing engines 431-432, N) in the caches 462A-462D, 456 and system memory 411 of the cores.

[0089] Figure 4C FIG. 4B illustrates another embodiment in which accelerator integration circuit 436 is integrated within processor 407. In this embodiment, graphics processing engines 431-432, N communicate directly with interface 435 (which can also utilize any form of bus or interface protocol) through high-speed link 440 to interface 437 of accelerator integration circuit 436. Accelerator integration circuit 436 can execute operations identical to those described with respect to Figure 4B the same operations described with respect to the operations described with respect to

[0090] One embodiment supports different programming models including a dedicated process programming model (no graphics acceleration module virtualization) and a shared programming model (with virtualization). The latter can include a programming model controlled by accelerator integration circuit 436 and a programming model controlled by graphics acceleration module 446.

[0091] In one embodiment of the dedicated process model, graphics processing engines 431-432, N are dedicated to a single application or process under a single operating system. The single application can concentrate other application requests to graphics engines 431-432, N, thus providing virtualization within the VM / partition.

[0092] In the dedicated process programming model, graphics processing engines 431-432, N can be shared by multiple VM / application partitions. The shared model requires a system hypervisor to virtualize graphics processing engines 431-432, N to allow access by each operating system. For single partition systems without a hypervisor, graphics processing engines 431-432, N are owned by the operating system. In both cases, the operating system can virtualize graphics processing engines 431-432, N to provide access to each process or application.

[0093] For the shared programming model, graphics acceleration module 446 or individual graphics processing engines 431-432, N use a process handle to select a process element. In one embodiment, the process element is stored in system memory 411 and can be addressed using the effective to real address translation techniques described herein. The process handle can be an implementation specific value provided to the host process when registering its context with the graphics processing engines 431-432, N (i.e., calling system software to add the process element to a process element linked list). The lower 16 bits of the process handle can be an offset into the process element linked list of the process element.

[0094] Figure 4D FIGURE 11 illustrates an exemplary accelerator integration slice 490. As used herein, a "slice" includes a specified portion of the processing resources of accelerator integration circuit 436. Application effective address space 482 within system memory 411 stores process elements 483. In one embodiment, process elements 483 are stored in response to GPU invocations 481 from an application 480 executing on processor 407. Process elements 483 contain process state for corresponding application 480. A work descriptor (WD) 484 contained in process element 483 can be a single job requested by an application or can contain pointers to a queue of jobs. In the latter case, WD 484 is a pointer to a job request queue in application address space 482.

[0095] Graphics acceleration module 446 and / or individual graphics processing engines 431-432, N can be shared by all or a subset of the processes in a system. Embodiments of the present invention include infrastructure for setting up process state and sending WDs 484 to graphics acceleration module 446 to start jobs in a virtual environment.

[0096] In one implementation, the dedicated process programming model is implementation specific. In this model, a single process owns graphics acceleration module 446 or individual graphics processing engines 431. Since graphics acceleration module 446 is owned by a single process, at the point in time when graphics acceleration module 446 is assigned, the hypervisor initializes accelerator integration circuit 436 for the owned partition and the operating system initializes accelerator integration circuit 436 for the owned process.

[0097] In operation, a WD fetch unit 491 in accelerator integration slice 490 fetches a next WD 484, which includes an indication of work to be done by one of the graphics processing engines of graphics acceleration module 446. Data from WD 484 can be stored in registers 445 and used as illustrated by MMU 439, interrupt management circuit 447, and / or context management circuit 446. For example, one embodiment of MMU 439 includes segment / page walk circuitry to access segment / page tables 486 within OS virtual address space 485. Interrupt management circuit 447 can handle interrupt events 492 received from graphics acceleration module 446. Effective addresses 493 generated by graphics processing engines 431-432, N when performing graphics operations are translated to real addresses by MMU 439.

[0098] In one embodiment, a same set of registers 445 is replicated for each graphics processing engine 431-432, N and / or graphics acceleration module 446 and can be initialized by a hypervisor or operating system. Each of these replicated registers can be included in an accelerator integration slice 490. Exemplary registers that can be initialized by a hypervisor are shown in Table 1.

[0099] Table 1 - Hypervisor Initialized Registers

[0100] 1 Fragment control register 2 Real address (RA) scheduling process region pointer 3 Authority mask override register 4 Interrupt vector table entry offset 5 Interrupt vector table entry limit 6 Status register 7 Logical partition ID 8 Real address (RA) hypervisor accelerator utilization record pointer 9 Storage descriptor register

[0101] Exemplary registers that can be initialized by an operating system are shown in Table 2.

[0102] Table 2 - Operating System Initialized Registers

[0103] 1 Process and thread identification 2 Effective address (EA) context save / restore pointer 3 Virtual address (VA) accelerator utilization record pointer 4 Virtual address (VA) storage segment table pointer 5 Authority mask 6 Work descriptor

[0104] In one embodiment, each WD 484 is specific to a particular graphics acceleration module 446 and / or graphics processing engines 431-432, N. It contains all the information that the graphics processing engines 431-432, N need to do its work or it can be a pointer to a memory location where a command queue has been set up by an application for the work to be done.

[0105] Figure 4E Figure illustrates additional details for one embodiment of a shared model. This embodiment includes a hypervisor real address space 498 in which a list of process elements 499 is stored. The hypervisor real address space 498 is accessible via a hypervisor 496 that virtualizes the graphics acceleration module engines for an operating system 495.

[0106] The shared programming model allows all processes or a subset of processes from all partitions or a subset of partitions in the system to use the graphics acceleration module 446. There are two programming models in which the graphics acceleration module 446 is shared by multiple processes and partitions: time-sliced sharing and graphics-directed sharing.

[0107] In this model, the system hypervisor 496 owns the graphics acceleration module 446 and makes its functionality available to all operating systems 495. For the graphics acceleration module 446 to support hypervisor 496 virtualization, the graphics acceleration module 446 can follow these requirements: 1) Application job requests must be autonomous (i.e., state does not need to be maintained between jobs), or the graphics acceleration module 446 must provide a context save and restore mechanism. 2) Application job requests are guaranteed by the graphics acceleration module 446 to complete within a specified amount of time, including any translation faults, or the graphics acceleration module 446 provides the ability to preempt job processing. 3) The graphics acceleration module 446 must guarantee fairness between processes when operating in the directed sharing programming model.

[0108] In one embodiment, for the shared model, the application 480 needs to make an operating system 495 system call with a graphics acceleration module 446 type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore area pointer (CSRP). The graphics acceleration module 446 type describes the target acceleration function for this system call. The graphics acceleration module 446 type can be a system-specific value. The WD is formatted specifically for the graphics acceleration module 446 and can take the form of a graphics acceleration module 446 command, a valid address pointer to a user-defined structure, a valid address pointer to a command queue, or any other data structure used to describe work to be done by the graphics acceleration module 446. In one embodiment, the AMR value is the AMR state for the current process. The value passed to the operating system is similar to how the application sets the AMR. If the accelerator integration circuit 436 and graphics acceleration module 446 implementation does not support a user authority mask override register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before the AMR in the hypervisor call. The hypervisor 496 can optionally apply the current authority mask override register (AMOR) value before placing the AMR in the process element 483. In one embodiment, the CSRP is one of the registers 445 containing a valid address of a region in the application address space 482 for the graphics acceleration module 446 to save and restore context state. This pointer is optional if state does not need to be saved between jobs or when a job is preempted. The context save / restore region can be a fixed system memory.

[0109] Upon receiving a system call, the operating system 495 can verify that application 480 has been registered and authorized to use the graphics acceleration module 446. The operating system 495 then invokes the hypervisor 496 using the information shown in Table 3.

[0110] Table 3 - OS to Hypervisor Call Parameters

[0111] 1 Work descriptor (WD) 2 Authority mask register (AMR) value (may be overridden). 3 Effective address (EA) context save / restore region pointer (CSRP) 4 Process ID (PID) and optional thread ID (TID) 5 Virtual address (VA) accelerator utilization record pointer (AURP) 6 Virtual address of storage segment table pointer (SSTP) 7 Logical interrupt service number (LISN)

[0112] Upon receiving a call from the hypervisor, the hypervisor 496 verifies that the operating system 495 has been registered and authorized to use the graphics acceleration module 446. The hypervisor 496 then places the process element 483 into a linked list of process elements corresponding to the graphics acceleration module 446 type. The process element may include the information shown in Table 4.

[0113] Table 4 - Process Element Information

[0114] 1 Work descriptor (WD) 2 Authority mask register (AMR) value (may be overridden). 3 Effective address (EA) context save / restore region pointer (CSRP) 4 Process ID (PID) and optional thread ID (TID) 5 Virtual address (VA) accelerator utilization record pointer (AURP) 6 Virtual address of storage segment table pointer (SSTP) 7 Logical interrupt service number (LISN) 8 Interrupt vector table derived from hypervisor call parameters. 9 Status register (SR) value 10 Logical partition ID (LPID) 11 Real address (RA) hypervisor accelerator utilization record pointer 12 Storage descriptor register (SDR)

[0115] In one embodiment, the hypervisor initializes multiple accelerator integration slice 490 registers 445.

[0116] like Figure 4F As illustrated, one embodiment of the invention employs a unified memory addressable via a common virtual memory address space for accessing physical processor memories 401-402 and GPU memories 420-423. In this implementation, operations performed on GPUs 410-413 utilize the same virtual / effective memory address space to access processor memories 401-402 and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 401, a second portion to second processor memory 402, a third portion to GPU memory 420, and so on. The entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each processor memory 401-402 and GPU memory 420-423, allowing any processor or GPU to access any physical memory—with a virtual address mapped to that memory.

[0117] In one embodiment, bias / coherence management circuitry 494A-494E within one or more MMUs 439A-439E ensures cache coherence between the host processor's (e.g., 405) cache and the GPU 410-413 cache, and implements biasing techniques that indicate the physical memory where certain types of data should be stored. While in Figure 4FThe diagram illustrates several instances of bias / coherence management circuitry 494A-494E, but the bias / coherence circuitry can be implemented within the MMU of one or more host processors 405 and / or within the accelerator integrated circuit 436.

[0118] One embodiment allows GPU-attached memories 420-423 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology without suffering the typical performance drawbacks associated with system-wide cache coherence. The ability to access GPU-attached memories 420-423 as system memory without the heavy overhead of cache coherence provides a beneficial operating environment for GPU offload. This arrangement allows host processor 405 software to set up operands and access computation results without the overhead of traditional I / O DMA data copying. These traditional copies involve driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are inefficient compared to simple memory accesses. Meanwhile, the ability to access GPU-attached memories 420-423 without cache coherence overhead can be critical for the execution time of offloaded computations. For example, in scenarios with heavy streaming write memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPUs 410-413. The efficiency of operand setting, the efficiency of result access, and the efficiency of GPU computation all play a role in determining the effectiveness of GPU offload.

[0119] In one implementation, the choice between GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table can be used, which can be a page-granular structure comprising 1 or 2 bits for each memory page attached to the GPU (i.e., controlled at the memory page level). The bias table can be implemented within the stolen memory of one or more GPU-attached memories 420-423—with or without a bias cache in GPUs 410-413 (e.g., to cache frequently / recently used bias table entries). Alternatively, the entire bias table can be kept within the GPU.

[0120] In one implementation, the bias table entries associated with each access to the GPU-attached memory 420-423 are accessed before the actual access to the GPU memory, resulting in the following operations: First, local requests from GPUs 410-413 to look up their pages in the GPU bias are forwarded directly to the corresponding GPU memory 420-423. Local requests from GPUs to look up their pages in the host bias are forwarded to processor 405 (e.g., via a high-speed link as discussed above). In one embodiment, a request from processor 405 to look up the requested page in the host processor bias is performed as a normal memory read. Alternatively, requests directed to GPU bias pages can be forwarded to GPUs 410-413. If the GPU is not currently using the page, then the GPU can then transfer the page to the host processor bias.

[0121] The page's bias state can be changed through software-based mechanisms, hardware-assisted software-based mechanisms, or—for a finite set of cases—purely hardware-based mechanisms.

[0122] One mechanism for changing the bias state involves an API call (such as OpenCL), which in turn invokes the GPU's device driver. This device driver then sends a message (or queues a command descriptor) to the GPU to guide it in changing the bias state. For certain transitions, a cache dump flush operation is performed on the host machine. The cache dump flush operation is necessary for transitions from the host processor 405 bias to the GPU bias, but not for the reverse transition.

[0123] In one embodiment, cache coherence is maintained by temporarily rendering GPU-biased pages that are not cacheable by the host processor 405. To access these pages, the processor 405 may request access from the GPU 410, which, depending on its implementation, may grant access immediately or not. Therefore, to reduce communication between the processor 405 and the GPU 410, it is advantageous to ensure that GPU-biased pages are those required by the GPU but not by the host processor 405, and vice versa.

[0124] Graphics processing pipeline

[0125] Figure 5 The figure illustrates a graphics processing pipeline 500 according to one embodiment. In one embodiment, a graphics processor may implement the illustrated graphics processing pipeline 500. The graphics processor may be included within the parallel processing subsystem described herein, such as the parallel processor 200 of FIG2, which in one embodiment is... Figure 1Variations of the parallel processor(s) 112. As described herein, various parallel processing systems can implement the graphics processing pipeline 500 via one or more instances of parallel processing units (e.g., parallel processing unit 202 of FIG. 2). For example, a shader unit (e.g., graphics multiprocessor 234 of FIG. 3) can be configured to perform one or more functions of a vertex processing unit 504, a tessellation control processing unit 508, a tessellation evaluation processing unit 512, a geometry processing unit 516, and a fragment / pixel processing unit 524. The functions of the data assembler 502, primitive assemblers 506, 514, 518, tessellation unit 510, rasterizer 522, and raster operation unit 526 can also be performed by other processing engines within a processing cluster (e.g., processing cluster 214 of FIG. 3) and corresponding partitioning units (e.g., partitioning units 220A-220N of FIG. 2). The graphics processing pipeline 500 can also be implemented using dedicated processing units for one or more functions. In one embodiment, one or more portions of the graphics processing pipeline 500 may be executed by parallel processing logic within a general-purpose processor (e.g., a CPU). In one embodiment, one or more portions of the graphics processing pipeline 500 may access on-chip memory (e.g., parallel processor memory 222 in FIG2) via a memory interface 528, which may be an instance of memory interface 218 of FIG2.

[0126] In one embodiment, data assembler 502 is a processing unit that collects vertex data for surfaces and primitives. Data assembler 502 then outputs vertex data, including vertex attributes, to vertex processing unit 504. Vertex processing unit 504 is a programmable execution unit that executes vertex shader programs, lighting, and transformations of the vertex data specified by the vertex shader programs. Vertex processing unit 504 reads data stored in cache, local, or system memory for use in processing vertex data and can be programmed to transform vertex data from object-based coordinate representations to world space coordinate space or normalized device coordinate space.

[0127] The first instance of the primitive assembler 506 receives vertex attributes from the vertex processing unit 504. The primitive assembler 506 reads the stored vertex attributes as needed and constructs graphics primitives for processing by the tessellation control processing unit 508. Graphics primitives include triangles, line segments, points, patches, etc., as supported by various graphics processing application programming interfaces (APIs).

[0128] The tessellation control processing unit 508 treats input vertices as control points for the geometric patch. These control points are transformed from the input representation of the patch (e.g., the patch's basis) into a representation suitable for use in the surface evaluation performed by the tessellation evaluation processing unit 512. The tessellation control processing unit 508 can also compute tessellation factors for the edges of the geometric patch. The tessellation factor is applied to a single edge and quantifies the viewpoint-related level of detail associated with that edge. The tessellation unit 510 is configured to receive the tessellation factors for the edges of the patch and subdivide the patch surface into multiple geometric primitives, such as line, triangle, or quadrilateral primitives, which are transmitted to the tessellation evaluation processing unit 512. The tessellation evaluation processing unit 512 operates on the parameterized coordinates of the subdivided patch to generate a surface representation and vertex attributes for each vertex associated with the geometric primitive.

[0129] A second instance of the primitive assembler 514 receives vertex attributes from the subdivision evaluation processing unit 512, reads stored vertex attributes as needed, and constructs graphical primitives for processing by the geometry processing unit 516. The geometry processing unit 516 is a programmable execution unit that executes a geometry shader program to transform the graphical primitives received from the primitive assembler 514 and specified by the geometry shader program. In one embodiment, the geometry processing unit 516 is programmed to subdivide the graphical primitives into one or more new graphical primitives and compute parameters for rasterizing the new graphical primitives.

[0130] In some embodiments, the geometry processing unit 516 can add or remove elements from the geometry flow. The geometry processing unit 516 outputs parameters and vertices specifying new graphical primitives to the primitive assembler 518. The primitive assembler 518 receives the parameters and vertices from the geometry processing unit 516 and constructs graphical primitives for processing by the viewport scaling, culling, and clipping unit 520. The geometry processing unit 516 reads data stored in the parallel processor memory or system memory for use in processing geometry data. The viewport scaling, culling, and clipping unit 520 performs clipping, culling, and viewport scaling and outputs the processed graphical primitives to the rasterizer 522.

[0131] Rasterizer 522 can perform depth culling and other depth-based optimizations. Rasterizer 522 also performs scan transformations on new graphics primitives to generate fragments and outputs these fragments and associated overlay data to fragment / pixel processing unit 524. Fragment / pixel processing unit 524 is a programmable execution unit configured to execute fragment shader programs or pixel shader programs. Fragment / pixel processing unit 524 transforms fragments or pixels received from rasterizer 522 as specified by the fragment or pixel shader program. For example, fragment / pixel processing unit 524 can be programmed to perform operations including but not limited to texture mapping, shading, blending, texture correction, and perspective correction to produce shaded fragments or pixels output to raster operation unit 526. Fragment / pixel processing unit 524 can read data stored in parallel processor memory or system memory for use when processing fragment data. Fragment or pixel shader programs can be configured to shade at sample, pixel, tile, or other granularities depending on the sampling rate configured for the processing unit.

[0132] The raster operation unit 526 is a processing unit that performs raster operations including but not limited to stencil printing, z-testing, and blending, and outputs pixel data as processed graphic data for storage in a graphics memory (e.g., the parallel processor memory 222 in Figure 2 and / or such as...). Figure 1 The system memory 104 is used to display the data on one or more display devices 110 or to further process the data by one or more processors 102 or one or more parallel processors 112. In some embodiments, the raster operation unit 526 is configured to compress z-or color data written to memory and decompress z-or color data read from memory.

[0133] Refresh region

[0134] Now go to Figure 6 Embodiments of the electronic processing system 600 may include an application processor 601, a permanent storage medium 602 communicatively coupled to the application processor 601, and a graphics subsystem 603 communicatively coupled to the application processor 601. The system 600 may also include a sensing engine 604 communicatively coupled to the graphics subsystem 603 to provide sensing information, a focusing engine 605 communicatively coupled to the sensing engine 604 and the graphics subsystem 603 to provide focusing information, a motion engine 606 communicatively coupled to the sensing engine 604, the focusing engine 605, and the graphics subsystem 603 to provide motion information, and a collaboration engine 607 communicatively coupled to one or more of the motion engine 606, the focusing engine 605, and the sensing engine 604 to identify shared graphics components between two or more users in an environment and to share these shared graphics components with two or more users in the environment.

[0135] Embodiments of each of the application processor 601, permanent storage medium 602, graphics subsystem 603, sensing engine 604, focusing engine 605, motion engine 606, collaboration engine 607, and other system components described above can be implemented in hardware, software, or any suitable combination thereof. For example, hardware implementations may include configurable logic such as, for example, a programmable logic array (PLA), an FPGA, a complex programmable logic device (CPLD), or fixed-function logic hardware using circuitry techniques such as, for example, an ASIC, complementary metal-oxide-semiconductor (CMOS), or transistor-transistor (TTL) logic technology, or any combination thereof. Alternatively or additionally, these components may be implemented in one or more modules and stored in a machine-readable or computer-readable storage medium such as random access memory (RAM), read-only memory (ROM), programmable ROM (PROM), firmware, flash memory, etc., for execution by a processor or computing device. For example, computer program code used to perform component operations can be written in any combination of one or more operating system-appropriate / suitable programming languages, including object-oriented programming languages ​​such as PYTHON, PERL, JAVA, SMALLTALK, C++, C#, etc., and conventional procedural programming languages ​​such as the "C" programming language or similar programming languages.

[0136] For example, system 600 may include components and / or features similar to system 100, further configured with the collaboration engine described herein. Alternatively, graphics subsystem 603 may include components and / or features similar to parallel processing system 200, further configured with the collaboration engine as described herein. System 600 may also be adapted to work with stereo headsets.

[0137] Sensing engine example

[0138] Now go to Figure 7A The sensing engine 612 can obtain information from sensors, content, services, and / or other sources to provide sensing information. Sensing information may include, for example, image information, audio information, motion information, depth information, temperature information, biometric information, GPU information, etc. At a higher level, some embodiments can use sensing information to reduce workload or enhance the performance of the user's graphics system.

[0139] For example, a sensing engine may include a sensor hub communicatively coupled to a combination of multiple sources, such as a 2D camera, a 3D camera, a depth camera, a gyroscope, an accelerometer, an inertial measurement unit (IMU), a location service, a microphone, a proximity sensor, a thermometer, a biometric sensor, and / or a combination of sources that provide information to a focusing and / or motion engine. The sensor hub may be distributed across multiple devices. Information from the sensor hub may include input data from the user's device (e.g., touch data) or a combination thereof.

[0140] For example, one or more user devices may include one or more 2D, 3D, and / or depth cameras. One or more user devices may also include gyroscopes, accelerometers, IMUs, location services, thermometers, biometric sensors, etc. For example, a user may carry a smartphone (e.g., in a user's pocket) and / or wear wearable devices (e.g., smartwatches, activity monitors, and / or fitness trackers). One or more user devices may also include microphones that can be used to detect whether the user is speaking, making a phone call, talking to another person nearby, etc. The sensor hub may include some or all of the user's various devices capable of capturing information related to the user's actions or activities (e.g., including I / O interfaces of the user's devices that can capture keyboard / mouse / touch activity). The sensor hub may obtain information directly from the user's device's capturing devices (e.g., wired or wirelessly), or the sensor hub may integrate information from the device from a server or service (e.g., information can be uploaded from a fitness tracker to a cloud service that the sensor hub can download).

[0141] Focusing engine example

[0142] Turning to 7B, the focus engine 614 can obtain information from the sensing engine and / or motion engine and other sources to provide focus information. Focus information may include, for example, focus point, focus area, eye position, eye movement, pupil size, pupil dilation, depth of focus (DOF), content focus, content focus object, content focus area, etc. Focus information may also include prior focus information, determined future focus information, and / or predicted focus information (e.g., predicted focus point, predicted focus area, predicted eye position, predicted eye movement, predicted pupil size, predicted pupil dilation, predicted DOF, determined future content focus, determined future content focus object, determined future content focus area, predicted content focus, predicted content focus object, predicted content focus area, etc.).

[0143] At a higher level, some implementations can use focus information to reduce workload or enhance the performance of the user's graphics system based on: 1) assuming where the user is looking, 2) determining where the user is looking, 3) applying where the user wants to look, and / or 4) predicting where the user will look in the future. Within the focus area the user is looking at, some focus cues may be stronger. If the user is looking straight ahead, they can see things in sharp focus. When a scene or object is facing outwards, the user may notice motion, but not detail in sharp focus.

[0144] For example, if the graphics system has limited sensing information or processing capabilities (e.g., the attached head-mounted display (HMD) or host cannot provide or use that information), the focus information can be static and / or based on assumptions (e.g., assuming the user is viewing the center of the screen with a fixed eye position, DOF, etc.). Focus information can also change dynamically based on factors such as motion information (e.g., from a virtual reality (VR) headset), motion prediction information, and content information (e.g., motion within a scene). More preferably, a better user experience can be provided by offering a rich sensor array including eye tracking (e.g., sometimes referred to as gaze tracking) to identify the focus area and provide focus information. For example, some embodiments may include an eye tracker or obtain eye information from an eye tracker that tracks the user's eyes. Eye information may include eye position, eye movement, pupil size / dilation, depth of focus, etc. The eye tracker can capture images of the user's eyes, including the pupil. The user's focus and / or DOF can be determined, inferred, and / or estimated based on eye position and pupil dilation. The user can undergo a calibration process, which can help the eye tracker provide more accurate focus and / or DOF information.

[0145] For example, when a user wears a VR headset, the camera can capture an image of the pupil, and the system can determine where the user is looking (e.g., the area of ​​focus, depth, and / or direction). The camera can capture pupil dilation information, and the system can infer the user's area of ​​focus based on this information. For example, the human eye has a certain degree of focus (DOF), so if the person is focusing on something nearby, distant objects may appear blurry. Focus information can include the focal point at a focusing distance X and the DOF information of the increment (X), so the area of ​​focus can correspond to the X+ / - increment [X] located around the user's focal point. The magnitude of the DOF can vary with distance X (e.g., different increments at different focal lengths). For example, the user's DOF ​​can be calibrated and can vary in every direction (e.g., x, y, and z), making the function increment [X] not necessarily spherical.

[0146] In some embodiments, focus information may include content-based focus information. For example, in 3D, VR, and / or augmented reality (AR) environments, depth and / or distance information (e.g., where the user is in the virtual environment, where objects are located, and / or how far away objects are from the user) may be provided from the application. Content-based focus information may also include points, objects, or areas in the content that the application wants the user to focus on, such as something more interesting happening that the application wants the user to focus on. Because the application can know motion information for the content and / or which objects / areas in the next frame or scene might be more interesting to the user (e.g., objects that are about to enter the scene from the edge of the screen), the application may also be able to provide future content focus information.

[0147] Motion engine example

[0148] Now go to Figure 7C The motion engine 616 can obtain information from the sensing engine and / or focusing engine and other sources to provide motion information. Motion information may include, for example, head position, head velocity, head acceleration, head movement direction, eye velocity, eye acceleration, eye movement direction, object position, object velocity, object acceleration, object movement direction, etc. Motion information may also include prior motion information, determined future motion information, and / or predicted motion information (e.g., predicted head velocity, predicted head acceleration, predicted head position, predicted head movement direction, predicted eye velocity, predicted eye acceleration, predicted eye movement direction, determined future content position, determined future content object velocity, determined future content object acceleration, predicted object position, predicted object velocity, predicted object acceleration, etc.).

[0149] At a higher level, some embodiments can use motion information to reduce workload or enhance the performance of the user graphics system based on: 1) the user moves their head, 2) the user moves their eyes, 3) the user moves their body, 4) the application wants the user to turn their head, eyes, and / or body to a certain location, and / or 4) predicting where the user will turn their head, eyes, and / or body to in the future. Motion information can be readily determined from the sensed information. For example, head position, velocity, acceleration, direction of movement, etc., can be determined from accelerometers. Eye motion information can be determined by tracking eye position information over time (e.g., if the eye tracker only provides eye position information).

[0150] Some motion information can be content-based. For example, in games or aerial 3D content, an application can know how fast an object is moving and where it is. The application can (e.g., via API calls) provide this information to the motion engine. Content-based object motion information for the next frame / scene can also be fed into the motion engine for decision-making. Some content-based motion information can be determined by performing image processing or machine vision processing on the content.

[0151] For example, some embodiments of a machine vision system can analyze and / or perform feature / object recognition on images captured by a camera. For instance, machine vision and / or image processing can identify and / or recognize objects in a scene (e.g., an edge belonging to the front of a chair). Machine vision systems can also be configured to perform face recognition, gaze tracking, facial expression recognition, and / or gesture recognition, including body-level gestures, arm / leg-level gestures, hand-level gestures, and / or finger-level gestures. Machine vision systems can be configured to classify user actions. In some embodiments, a suitably configured machine vision system can be able to determine whether a user is in front of a computer, typing on a keyboard, using a mouse, using a touchpad, using a touchscreen, using an HMD, using a VR system, sitting, standing, and / or otherwise performing some other action or activity.

[0152] For example, a motion engine can acquire camera data relating to real-world objects in a scene and use this information to identify the motion and orientation of those objects. The motion engine can obtain latency information from a graphics processor. The motion engine can then predict the orientation of the real-world object in the next frame. The latency amount can be based on one or more of the following: the time taken to render the scene, the number of virtual objects in the scene, and the complexity of the scene. For example, a sensing engine can include one or more cameras to capture a real-world scene. These cameras can include one or more 2D cameras, 3D cameras, depth cameras, high-speed cameras, or other image capture devices. The real-world scene can include objects moving within it. Cameras can be coupled to an image processor to process data from the cameras to identify objects in the scene (e.g., including moving objects) and to identify the motion of those objects (e.g., including orientation information). The motion engine can determine predicted motion information based on tracking the motion of the objects and predict the future position of the objects based on measured or estimated latency (e.g., from capture time to rendering time). According to some embodiments, various motion tracking and / or motion prediction techniques can be enhanced using optical flow and other real-world motion estimation techniques to determine the next position of real-world objects. For example, some embodiments may use extended common filtering and / or perspective processing (e.g., from autonomous driving applications) to predict the motion of objects.

[0153] Now go toFigure 8 This illustrates one embodiment of the invention, which includes a system particularly useful for saving power in large displays 800. The display can be a large-screen television, possibly the kind found in many homes with sizes ranging up to 100 inches or larger. The display can be flat, or it can be one of the later curved screen models.

[0154] Content 802 in the form of a video stream can be fed to frame buffer memory 804. This content 802 can include any number of sources, such as cable or satellite with a set-top box (STB), camera feed, 3D game engine, computer display monitor output, etc. Each frame to be displayed on display 800 is loaded onto a surface in frame memory 804 and sent to display engine 806, which can be communicatively coupled to a processor such as CPU and / or GPU 808.

[0155] Figure 8 The system shown may also include a sensor unit 810, which may include a camera 812 and other sensors 814 such as motion sensors, microphones, etc. The sensor unit 810 may also communicate with a wearable device worn by the user. Details of possible embodiments of the sensor unit can be found by referring back to previous sections. Figures 6-7C The various sensing, motion, and focus engines discussed in the article are used to collect data.

[0156] According to an embodiment, the display 800 can be divided into a plurality of smaller addressable segments. In this example, the display 800 is divided into a plurality of adjacent hexagonal segments 816. Although hexagons are shown, segments 816 can be any convenient shape that can cover the display 800—preferably without overlap—such as triangles, squares, or other polygonal shapes. Moreover, since there can be more smaller segments 816 or fewer larger segments 816, these segments may not be drawn to scale. These segments 816 are shown for illustrative purposes; the user or viewer will not actually see the outlines of these segments 816. With this setup, the sensor unit 810 can provide the CPU / GPU 808 with viewer gaze and motion data 818 to inform the current gaze or predict the viewer's future gaze. In this way, the display engine 806 can be able to provide higher quality video only to the segment the viewer is currently gazing at, thereby driving the display link 820 to power down and reducing the power consumption of the entire panel display 800. In one embodiment, user gaze segment information is fed into the GPU / CPU 808. The CPU / GPU 808 uses this information to shade segments outside the user's gaze at a lower shading rate. This reduces the power and processing requirements of the GPU / CPU 808.

[0157] Now go to Figure 9 This illustrates a user / viewer 900 watching a program on a large-screen display 800 according to an embodiment of the present invention. Within the possible scope, from Figure 8 The same reference numerals have been reused for consistency. One or more cameras 812 on sensor unit 810 can be used to determine the gaze of viewer 900, as illustrated by dashed line 902. Here, the viewer has currently focused their attention on ski jumper 904. In this case, display engine 806 ( Figure 8 This can increase the refresh rate of the hexagonal segment (in this case, three segments) 906 while decreasing the refresh rate on all other parts of the display that the viewer 900 is not looking at. Additionally, further information about changes in the viewer 900's body position can be collected via a wearable device 908 worn on the viewer 900's head, and communication with the sensor 814 may be useful in predicting future gaze areas.

[0158] In addition, although Figure 9 It is shown as having one viewer, but there can be multiple viewer, and the sensor unit 810 can be able to sense multiple gaze areas and can provide higher refresh, brightness, and resolution in those hexagonal segments, just as shown for segment 906.

[0159] Now for reference Figure 10 The diagram illustrates a flowchart of one embodiment of the invention. At box 1000, the system can track a viewer's gaze. As previously discussed, this can be done by providing data from one or more cameras to a sensing engine communicating with a processor to identify the gaze region. In box 1002, the system identifies segments of the display within the gaze region. This can be a single segment or multiple adjacent segments. In the case of multiple viewers, there can be more than one gaze region. In box 1004, gaze region 906 ( Figure 9 Segments within the viewing area can be enhanced or have a higher quality than all other segments. This can be done by increasing the refresh rate for the viewing area in display engine 806 or sending a higher resolution to the viewing area 906. In box 1006, the refresh rate of all segments not in the refresh area 906 can be reduced, or a lower resolution can be sent. Since refreshes are less frequent, display power decreases, and display link power decreases, thus providing significant power savings. In box 1008, the viewer's gaze is continuously updated, and the process restarts 1010. Additionally, segments outside the user's gaze can have a lower shading rate. This reduces the power and processing requirements of the GPU / CPU 808.

[0160] Display techniques

[0161] Now go to Figure 11 The illustration shows a performance-enhanced computing system 1100. In the illustrated example, a processor 1110 is coupled to a display 1120. The processor 1110 typically produces images for display on an LCD panel 1150 of the display 1120. In one example, the processor 1110 includes communication interfaces such as, for example, Video Graphics Array (VGA), DisplayPort (DP) interface, Embedded DisplayPort (eDP) interface, High Definition Multimedia Interface (HDMI), Digital Video Interface (DVI), etc. The processor 1110 may be a graphics processor (e.g., a graphics processing unit / GPU) that processes graphics data and generates images (e.g., video frames, still images) displayed on the LCD panel 1150. Furthermore, the processor 1110 may include one or more image processing pipelines that generate pixel data. The image processing pipelines may conform to an OpenGL architecture or other suitable architecture. Additionally, the processor 1110 may be connected to a host processor (e.g., a central processing unit / CPU) that executes one or more device drivers that control and / or interact with the processor 1110.

[0162] The illustrated display 1120 includes a timing controller (TCON) 1130 that can individually address different pixels in the LCD panel 1150 and update each individual pixel in the LCD panel 1150 in each refresh cycle. In this regard, the LCD panel 1150 may include multiple liquid crystal elements, such as liquid crystals and integrated color filters. Each pixel of the LCD panel 1150 may respectively include a triple liquid crystal element with red, green, and blue color filters. The LCD panel 1150 can arrange pixels in a two-dimensional (2D) array controlled via row drivers 1152 and column drivers 1154 to update the image displayed by the LCD panel 1150. Therefore, the TCON 1130 can drive the row drivers 1152 and column drivers 1154 to address specific pixels of the LCD panel 1150. The TCON 1130 can also adjust the voltage supplied to the liquid crystal elements in the pixel to change the intensity of light passing through each of the three liquid crystal elements, and thus change the color of the pixel displayed on the surface of the LCD panel 1150.

[0163] The backlight 1160 may include multiple light-emitting elements, such as light-emitting diodes (LEDs), arranged at the edges of the LCD panel 1150. Thus, light generated by the LEDs can be diffused through the LCD panel 1150 by a diffuser (not shown). In another example, since each LED diffuses light through one or more corresponding pixels of the LCD panel 1150 located in front of the LED, in one configuration the LEDs are arranged in a 2D array directly behind the LCD panel 1150; this is sometimes referred to as direct backlighting. The light-emitting elements may also include compact fluorescent lamps (CFLs) arranged along one or more edges of the LCD panel 1150. To eliminate multiple edges, the combination of edges can be varied to achieve selective illumination of areas, where a smaller number of lighting elements than the total set are used at lower power.

[0164] The light-emitting element may also include one or more sheets of electroluminescent material placed behind the LCD panel 1150. In this case, light from the surface of the sheet can be dispersed through the pixels of the LCD panel 1150. Alternatively, the sheet can be divided into multiple regions, such as quadrants. In one example, each region is individually controlled to illuminate only a portion of the LCD panel 1150. Other backlighting solutions may also be used.

[0165] The illustrated display 1120 also includes a backlight controller (BLC) 1140 that provides voltage to the light-emitting elements of the backlight 1160. For example, the BLC 1140 may include a pulse-width modulation (PWM) driver (not shown) to generate a PWM signal that activates at least a portion of the light-emitting elements of the backlight 1160. The duty cycle and frequency of the PWM signal can cause the light generated by the light-emitting elements to dim. For example, a 100% duty cycle may correspond to the light-emitting elements being fully on, and a 0% duty cycle may correspond to the light-emitting elements being fully off. Therefore, intermediate duty cycles (e.g., 25%, 50%) typically cause the light-emitting elements to be on for a portion of a cycle proportional to the percentage of the duty cycle. The cycle may be fast enough that the flickering of the light-emitting elements is not noticeable to the human eye. Furthermore, the effect on the user may be that the level of light emitted by the backlight 1160 is lower than when the backlight 1160 is fully activated. The BLC 1140 may be separate from or incorporated into the TCON 1130.

[0166] Alternatively, an emitting display system can be used, in which the LCD panel 1150 is replaced by an emitting display panel (e.g., organic light-emitting diode / OLED), the backlight 1160 is omitted, and the row and column drivers 1152 and 1154 can be used to directly modulate the color and brightness of the pixels, respectively.

[0167] Distance-based display resolution

[0168] Figure 12A The illustration depicts a scenario where a user 1218 interacts with a data processing device 1200 including a display unit 1228. The display processing device 1200 may include, for example, a laptop computer, desktop computer, tablet computer, convertible tablet computer, mobile internet device (MID), personal digital assistant (PDA), wearable device (e.g., head-mounted display / HMD), media player, etc., or any combination thereof. The illustrated data processing device 1200 includes a processor 1224 (e.g., an embedded controller, microcontroller, host processor, graphics processor) coupled to a memory 1222, which may include storage locations addressable by the processor 1224. As will be discussed in more detail, a distance sensor 1210 enables distance-based display resolution relative to the display unit 1228.

[0169] The illustrated memory 1222 includes display data 1226 to be rendered on the display unit 1228. In one example, the processor 1224 performs data transformation on the display data 1226 before presenting it on the display unit 1228. A post-processing engine 1214 can be executed on the processor 1224 to receive the display data 1226 and the output of the proximity sensor 1210. The post-processing engine 1214 can modify the display data 1226 to enhance the readability of screen content on the display unit 1228, reduce power consumption in the data processing device 1200, or any combination thereof.

[0170] In addition to the operating system 1212 and application 1220, the illustrated memory 1222 also stores a display resolution setting 1216. The display resolution setting 1216 specifies the number of pixels of display data 1226 to be rendered on the display unit 1228 along its length and width dimensions. If the display data 1226 generated by application 1220 is incompatible with the format of the display unit 1228, the processor 1224 can configure the scaling of the display data 1226 to match the format of the display unit 1228. In this regard, the display resolution setting 1216 can be associated with and / or incorporated into configuration data that defines other settings for the display unit 1228. Furthermore, the display resolution setting 1216 can be defined based on unit distance or area (e.g., pixels per inch / PPI) or other suitable parameters.

[0171] Application 1220 can generate a user interface, in which user 1218 can interact with the user interface to select display resolution setting 1216 from one or more options provided through the user interface, input display resolution setting 1216 as a requested value, and so on. Therefore, display data 1226 can be resized to fit display resolution setting 1216 before being rendered on display unit 1228.

[0172] The distance sensor 1210 can track the distance between the user 1218 and the display unit 1228, where distance sensing can be triggered by a physical button associated with the data processing device 1200 / display unit 1228, by a user interface provided by the application 1220, and / or by the loading of the operating system 1220, etc. For example, during the boot of the data processing device 1200, the operating system 1212 can implement an automatic process to trigger distance sensing in the background or foreground. Distance sensing can be implemented periodically or continuously.

[0173] Figure 12B An example of a distance sensing scenario is shown. In the illustrated example, distance sensor 1210 uses transceiver 1208 to transmit electromagnetic beam 1202 in the direction of user 1218. Therefore, transceiver 1202 can be positioned on the forward surface of data processing device 1200. Figure 12A Electromagnetic beam 1202 can impact user 1218 and be reflected / scattered from user 1218 as a return electromagnetic beam 1204. The return electromagnetic beam 1204 can be generated by, for example, processor 1224 (…). Figure 12A ) and / or post-processing engine 1214 ( Figure 12A Analysis to determine the relationship between user 1218 and display unit 1228 ( Figure 12A The distance between them is 1206. A distance of 1206 can be used to adjust the display resolution setting to 1216.

[0174] Display layer

[0175] Now go to Figure 13The illustration shows a display system 1300, in which cascaded display layers 1361, 1362, and 1363 are used to achieve spatial / temporal super-resolution in display accessory 1360. In the illustrated example, processor 1310 provides original graphics data 1334 (e.g., video frames, still images) to system 1300 via bus 1320. Cascaded display programs 1331 can be stored in memory 1330, whereby cascaded display programs 1331 may be part of a display driver associated with display accessory 1360. The illustrated memory 1330 also includes the original graphics data 1334 and factored graphics data 1335. In one example, cascaded display programs 1331 include a temporal factor decomposition component 1332 and a spatial factor decomposition component 1333. The temporal factor decomposition component 1332 can perform temporal factor decomposition calculations, and the spatial factor decomposition component can perform spatial factor decomposition calculations. The cascaded display program 1331 can derive graphical data 1335 for rendering factorization on each display layer 1361, 1362, and 1363 based on user configuration and raw graphical data 1334.

[0176] The display accessory 1360 can be implemented as an LCD (Liquid Crystal Display) for applications such as head-mounted displays (HMDs). More specifically, the display accessory 1360 may include a set of LCD panel interface boards, lens accessories, etc. Each panel can operate at, for example, a native resolution of 1280×800 pixels and a refresh rate of 60Hz. Other native resolutions, refresh rates, display panel technologies, and / or layer configurations can be used.

[0177] Multiple display units

[0178] Figure 14 A graphics display system 1400 is illustrated, comprising a set of display units 1430 (1430a-1430n), which can typically be used to output a widescreen (e.g., panoramic) presentation 1440 including cohesive content in the form of cohesion and structured topology. In the illustrated example, a data processing device 1418 includes a processor 1415 that applies logic function 1424 to hardware profile data 1402 received from the set of display units 1430 via a network 1420. Applying logic function 1424 to the hardware profile data 1402 can create a set of automatic topology settings 1406 when the hardware profile data does not match a set of settings in a hardware profile lookup table 1412. The illustrated set of automatic topology settings 1406 is transmitted from the display processing device 1418 to the display units 1430 via the network 1420.

[0179] The processor 1415 can perform and execute the logic function 1424 upon receiving it from the display driver 1410. In this regard, the display driver 1410 may include an automatic topology module 1408 that automatically configures and constructs the topology of the display unit 1432 to create a presentation 1440. In one example, the display driver 1410 is a set of instructions that, when executed by the processor 1415, enable the data processing device 1418 to communicate with the display unit 1430, video card, etc., and perform automatic topology generation operations.

[0180] Data processing device 1418 may include, for example, a server, desktop computer, laptop computer, tablet computer, convertible tablet computer, MID, PDA, wearable device, media player, etc. Therefore, display processing device 1418 may include hardware control module 1416, storage device 1414, random access memory (RAM, not shown), controller card including one or more video controller cards, etc. In one example, display units 1430 are flat panel displays (e.g., liquid crystal, active matrix, plasma, etc.), HMDs, video projection devices, etc., that coordinate with each other to produce presentation 1440. Furthermore, presentation 1440 can be generated based on media files stored in storage device 1414, where media files may include, for example, movies, video clips, animations, advertisements, etc., or any combination thereof.

[0181] The term "topology" can be considered as the number, scaling, shape, and / or other configuration parameters of the first display unit 1430a, the second display unit 1430b, the third display unit 1430n, etc. Therefore, the topology of the display units 1430 allows the presentation 1440 to be consistently visually rendered, ensuring that the various parts of the presentation 1440 are proportional to and compatible with the original dimensions and extent of the media played through the display units 1430. Thus, the topology can constitute spatial relationships and / or geometric properties unaffected by continuous changes in the shape or size of the content rendered in the presentation 1440. In one example, the automatic topology module 1408 includes a timing module 1426, a control module 1428, a signal monitoring module 1432, and a signal display module 1434. The timing module 1426 can designate a specific display unit in the group of display units 1430 as a sample display unit. In this case, the timing module 1426 can designate the remaining display units 1430 as additional display units. In one example, timing module 1426 automatically sets the shape factor to be compatible with hardware profile data 1402, where rendering 1440 is automatically initiated by graphic signal sequence 1422.

[0182] In one example, control module 1428 modifies the set of automatic topology settings 1406. Additionally, signal monitoring module 1432 can automatically monitor the graphic signal sequence 1422 and trigger storage device 1414 to associate the set of automatic topology settings 1406 with hardware profile lookup table 1412. Furthermore, signal monitoring module 1432 can automatically detect changes in the set of display units 1430 based on a set of change criteria and automatically generate a new topology profile corresponding to the changes in the set of display units 1430. Therefore, the new topology profile can be applied to the set of display units 1430. If the graphic signal sequence 1422 does not meet a set of criteria, signal monitoring module 1432 can also trigger signal display module 1434 to reapply the set of automatic topology settings 1406. If hardware profile data 1402 does not support automatic topology display of graphic signal sequence 1422, data processing device 1418 can report an error and log the error in error log 1413.

[0183] Cloud-assisted media delivery

[0184] Now go to Figure 15 The cloud gaming system 1500 includes clients 1540 coupled to server 1520 via network 1510. Clients 1540 may typically be consumers of graphical content (e.g., games, virtual reality / VR, augmented reality / AR) hosted, processed, and rendered on server 1520. The illustrated server 1520 may be scalable, having the ability to serve graphical content to multiple clients simultaneously (e.g., by utilizing parallel and amortized processing and rendering resources). In one example, the scalability of server 1520 is limited by the capacity of network 1510. Therefore, there may be a threshold number of clients beyond which service is degraded for all clients.

[0185] In one example, server 1520 includes a graphics processor (e.g., GPU) 1530, a host processor (e.g., CPU) 1524, and a network interface card (NIC) 1522. NIC 1522 can receive requests for graphics content from client 1540. Requests from client 1540 can cause graphics content to be retrieved from memory via an application running on host processor 1524. Host processor 1524 can perform high-level operations, such as determining the position, collision, and motion of objects in a given scene. Based on these high-level operations, host processor 1524 can generate rendering commands that combine scene data and are executed by graphics processor 1530. Rendering commands can cause graphics processor 1530 to define scene geometry, shading, lighting, motion, textures, camera parameters, etc., for rendering via client 1540.

[0186] More specifically, the illustrated graphics processor 1530 includes a graphics renderer 1532, which performs the rendering process according to rendering commands generated by the host processor 1524. The output of the graphics renderer 1532 may be a stream of raw video frames provided to the frame capturer 1534. The illustrated frame capturer 1534 is coupled to an encoder 1536, which can compress / format the raw video stream for transmission over the network 1510. The encoder 1536 may use a variety of video compression algorithms, such as, for example, the H.264 standard from the International Telecommunication Union Telecommunication Standardization Sector (ITUT), the MPEG4 Advanced Video Coding (AVC) standard from the International Organization for Standardization / International Electrotechnical Commission (ISO / IEC), and so on.

[0187] The illustrated client 1540 can be a desktop computer, laptop computer, tablet computer, convertible tablet computer, wearable device, MID, PDA, media player, etc., and includes a NIC 1542 to receive video streams transmitted from server 1520. NIC 1522 may include the physical layer and the software layer foundation for the network interface in client 1540 to facilitate communication over network 1510. Client 1540 may also include a decoder 1544, which employs the same formatting / compression scheme as encoder 1536. Therefore, the decompressed video stream can be provided from decoder 1544 to video renderer 1546. The illustrated video renderer 1546 is coupled to display 1548, which visually presents graphical content.

[0188] As already mentioned, graphical content can include game content. In this regard, client 1540 can implement real-time interactive streaming, which involves collecting user input from input device 1550 and delivering the user input to server 1520 via network 1510. This real-time interactive component of cloud gaming may pose challenges regarding latency.

[0189] Additional system overview examples

[0190] Figure 16 This is a block diagram of a processing system 1600 according to one embodiment. In various embodiments, system 1600 includes one or more processors 1602 and one or more graphics processors 1608, and may be a single-processor desktop system, a multiprocessor workstation system, or a server system having a large number of processors 1602 or processor cores 1607. In one embodiment, system 1600 is a processing platform incorporated within a system-on-a-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

[0191] Embodiments of system 1600 may include or be incorporated within a server-based gaming platform, including a game and media console, a mobile game console, a handheld game console, or an online game console. In some embodiments, system 1600 is a mobile phone, smartphone, tablet computing device, or mobile internet device. Data processing system 1600 may also include, be coupled to, or be integrated within a wearable device, such as a smartwatch, smart glasses, augmented reality, or virtual reality device. In some embodiments, data processing system 1600 is a television or set-top box device having one or more processors 1602 and a graphical interface generated by one or more graphics processors 1608.

[0192] In some embodiments, one or more processors 1602 each include one or more processor cores 1607 for processing instructions that, when executed, perform operations for system and user software. In some embodiments, each of the one or more processor cores 1607 is configured to process a particular instruction set 1609. In some embodiments, the instruction set 1609 may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computation via Very Long Instruction Words (VLIW). Multiple processor cores 1607 may each process different instruction sets 1609, which may include instructions that facilitate the emulation of other instruction sets. Processor cores 1607 may also include other processing devices, such as digital signal processors (DSPs).

[0193] In some embodiments, processor 1602 includes cache memory 1604. Depending on the architecture, processor 1602 may have a single internal cache or multi-level internal caches. In some embodiments, cache memory is shared among various components of processor 1602. In some embodiments, processor 1602 also uses external caches (e.g., a Level 3 (L3) cache or an ultimate level cache (LLC)) (not shown), which can be shared among processor cores 1607 using known cache coherence techniques. Processor 1602 also includes a register file 1606, which may include different types of registers (e.g., integer registers, floating-point registers, status registers, and instruction pointer registers) for storing different types of data. Some registers may be general-purpose registers, while others may be specific to the design of processor 1602.

[0194] In some embodiments, processor 1602 is coupled to processor bus 1610 to transmit communication signals such as address, data, or control signals between processor 1602 and other components in system 1600. In one embodiment, system 1600 uses an exemplary “central” system architecture that includes a memory controller central hub 1616 and an input / output (I / O) controller central hub 1630. Memory controller central hub 1616 facilitates communication between memory devices and other components of system 1600, while I / O controller central hub (ICH) 1630 provides connectivity to I / O devices via a local I / O bus. In one embodiment, the logic of memory controller central hub 1616 is integrated within the processor.

[0195] Memory device 1620 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase-change memory device, or some other memory device with suitable performance for use as processing memory. In one embodiment, memory device 1620 may operate as system memory for system 1600 to store data 1622 and instructions 1621 for use when one or more processors 1602 execute an application or process. Memory controller hub 1616 is also coupled to an optional external graphics processor 1612, which may communicate with one or more graphics processors 1608 in processor 1602 to perform graphics and media operations.

[0196] In some embodiments, ICH 1630 enables peripheral devices to connect to memory device 1620 and processor 1602 via a high-speed I / O bus. I / O peripheral devices include, but are not limited to, an audio controller 1646, a firmware interface 1628, a wireless transceiver 1626 (e.g., Wi-Fi, Bluetooth), a data storage device 1624 (e.g., a hard disk drive, flash memory, etc.), and a conventional I / O controller 1640 for coupling conventional (e.g., Personal System 2 (PS / 2)) devices to the system. One or more Universal Serial Bus (USB) controllers 1642 connect input devices such as a keyboard and mouse 1644 combination. A network controller 1634 may also be coupled to ICH 1630. In some embodiments, a high-performance network controller (not shown) is coupled to processor bus 1610. It will be appreciated that the illustrated system 1600 is exemplary and not limiting, as other types of data processing systems with different configurations may also be used. For example, the I / O controller hub 1630 can be integrated into one or more processors 1602, or the memory controller hub 1616 and the I / O controller hub 1630 can be integrated into a separate external graphics processor, such as an external graphics processor 1612.

[0197] Figure 17 This is a block diagram of an embodiment of a processor 1700 having one or more processor cores 1702A-1702N, an integrated memory controller 1714, and an integrated graphics processor 1708. Elements have the same reference numerals (or names) as those in any other figures herein. Figure 17 Those components may operate or function in any manner similar to, but not limited to, those described elsewhere herein. Processor 1700 may include additional cores, up to and including additional cores 1702N, indicated by the dashed box. Each of processor cores 1702A-1702N includes one or more internal cache units 1704A-1704N. In some embodiments, each processor core may also access one or more shared cache units 1706.

[0198] Internal cache units 1704A-1704N and shared cache unit 1706 represent the cache memory hierarchy within processor 1700. The cache memory hierarchy may include at least one level of instruction and data cache in each processor core and one or more levels of shared intermediate cache, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, wherein the highest-level cache preceding external memory is classified as LLC. In some embodiments, cache coherence logic maintains coherence between the individual cache units 1706 and 1704A-1704N.

[0199] In some embodiments, the processor 1700 may further include a set of one or more bus controller units 1716 and a system agent core 1710. The one or more bus controller units 1716 manage a set of peripheral buses, such as one or more peripheral component interconnect buses (e.g., PCI, PCI Express). The system agent core 1710 provides management functionality for various processor components. In some embodiments, the system agent core 1710 includes one or more integrated memory controllers 1714 to manage access to various external memory devices (not shown).

[0200] In some embodiments, one or more of the processor cores 1702A-1702N include support for simultaneous multithreading. In such an embodiment, the system agent core 1710 includes components for coordinating and operating the cores 1702A-1702N during multithreaded processing. The system agent core 1710 may additionally include a power control unit (PCU) which includes logic and components for regulating the power states of the processor cores 1702A-1702N and the graphics processor 1708.

[0201] In some embodiments, processor 1700 further includes a graphics processor 1708 for performing graphics processing operations. In some embodiments, graphics processor 1708 is coupled to the shared cache unit 1706 and a system proxy core 1710 including one or more integrated memory controllers 1714. In some embodiments, display controller 1711 is coupled to graphics processor 1708 to drive graphics processor output to one or more coupled displays. In some embodiments, display controller 1711 may be a separate module coupled to graphics processor via at least one interconnect, or it may be integrated within graphics processor 1708 or system proxy core 1710.

[0202] In some embodiments, a ring-based interconnect unit 1712 is used to couple the internal components of the processor 1700. However, alternative interconnect units, such as point-to-point interconnects, switched interconnects, or other techniques including those well known in the art, may be used. In some embodiments, the graphics processor 1708 is coupled to the ring interconnect 1712 via I / O link 1713.

[0203] Exemplary I / O link 1713 represents at least one of a variety of I / O interconnects, including packaged I / O interconnects that facilitate communication between various processor components and a high-performance embedded memory module 1718, such as an eDRAM module. In some embodiments, each of the processor cores 1702-1702N and the graphics processor 1708 uses the embedded memory module 1718 as a shared last-level cache.

[0204] In some embodiments, processor cores 1702A-1702N are homogeneous cores executing the same instruction set architecture. In another embodiment, processor cores 1702A-1702N are heterogeneous in terms of instruction set architecture (ISA), wherein one or more processor cores 1702A-N execute a first instruction set, while at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, processor cores 1702A-1702N are heterogeneous in terms of microarchitecture, wherein one or more cores with relatively high power consumption are coupled to one or more power cores with lower power consumption. Additionally, processor 1700 may be implemented on one or more chips or as a SoC integrated circuit having the components shown, among other components.

[0205] Figure 18This is a block diagram of a graphics processing unit 1800, which may be a discrete graphics processing unit or a graphics processing unit integrated with multiple processing cores. In some embodiments, the graphics processing unit communicates via a memory-mapped I / O interface to registers on the graphics processing unit and using commands placed in processor memory. In some embodiments, the graphics processing unit 1800 includes a memory interface 1814 for accessing memory. The memory interface 1814 may be an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory.

[0206] In some embodiments, the graphics processor 1800 further includes a display controller 1802 to drive display output data to a display device 1820. The display controller 1802 includes hardware for one or more overlay planes for the display and combination of multi-layer video or user interface elements. In some embodiments, the graphics processor 1800 includes a video codec engine 1806 to encode media into one or more media encoding formats, decode from one or more media encoding formats, or transcode between one or more media encoding formats, including but not limited to Moving Picture Experts Group (MPEG) formats such as MPEG-2, Advanced Video Coding (AVC) formats such as H.264 / MPEG-4 AVC, and SMPTE 421M / VC-1, as well as Joint Picture Experts Group (JPEG) formats such as JPEG and Animated JPEG (MJPEG).

[0207] In some embodiments, the graphics processor 1800 includes a block image transfer (BLIT) engine 1804 to perform two-dimensional (2D) rasterizer operations, including, for example, bit boundary block transfer. However, in one embodiment, one or more components of the graphics processing engine (GPE) 1810 are used to perform 2D graphics operations. In some embodiments, the graphics processing engine 1810 is a computational engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0208] In some embodiments, GPE 1810 includes a 3D pipeline 1812 for performing 3D operations, such as rendering 3D images and scenes using processing functions acting on 3D primitive shapes (e.g., rectangles, triangles, etc.). The 3D pipeline 1812 includes programmable and fixed-function elements that perform various tasks within those elements and / or produce execution threads to the 3D / media subsystem 1815. While the 3D pipeline 1812 can be used to perform media operations, embodiments of GPE 1810 also include a media pipeline 1816 specifically designed to perform media operations such as video post-processing and image enhancement.

[0209] In some embodiments, the media pipeline 1816 includes fixed-function or programmable logic units to perform one or more specialized media operations, such as video decoding acceleration, video deinterleaving, and video encoding acceleration, in place of or on behalf of the video codec engine 1806. In some embodiments, the media pipeline 1816 further includes thread-producing units to produce threads for execution on the 3D / media subsystem 1815. The produced threads perform computations on media operations for one or more graphics execution units included in the 3D / media subsystem 1815.

[0210] In some embodiments, the 3D / media subsystem 1815 includes logic for executing threads produced by the 3D pipeline 1812 and the media pipeline 1816. In one embodiment, the pipeline sends thread execution requests to the 3D / media subsystem 1815, which includes thread dispatch logic for arbitrating and dispatching various requests to available thread execution resources. Execution resources include an array of graphics execution units for processing 3D and media threads. In some embodiments, the 3D / media subsystem 1815 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory, including registers and addressable memory, for sharing data between threads and storing output data.

[0211] 3D / media processing

[0212] Figure 19 This is a block diagram of a graphics processing engine 1910 of a graphics processor according to some embodiments. In one embodiment, GPE 1910 is... Figure 18 A version of GPE 1810 shown. Elements having the same reference numerals (or names) as those in any other figures herein. Figure 19 The components may operate or function in any manner similar to those described elsewhere in this document, but are not limited thereto.

[0213] In some embodiments, GPE 1910 is coupled to command fluidizer 1903, which provides a command stream to GPE 3D and media pipelines 1912, 1916. In some embodiments, command fluidizer 1903 is coupled to memory, which may be system memory or one or more internal cache memories and shared cache memories. In some embodiments, command fluidizer 1903 receives commands from memory and sends the commands to 3D pipeline 1912 and / or media pipeline 1916. The command is an instruction retrieved from a ring buffer that stores commands for 3D and media pipelines 1912, 1916. In one embodiment, the ring buffer may additionally include a batch command buffer that stores a batch of multiple commands. 3D and media pipelines 1912, 1916 process commands by performing operations via logic within the respective pipeline or by dispatching one or more execution threads to execution unit array 1914. In some embodiments, the execution unit array 1914 is scalable, such that the array includes a variable number of execution units based on the target power and performance level of the GPE 1910.

[0214] In some embodiments, the sampling engine 1930 is coupled to memory (e.g., cache memory or system memory) and the execution unit array 1914. In some embodiments, the sampling engine 1930 provides a memory access mechanism for the execution unit array 1914, which allows the execution array 1914 to read graphics and media data from memory. In some embodiments, the sampling engine 1930 includes logic for performing specialized image sampling operations for media.

[0215] In some embodiments, the specialized media sampling logic in the sampling engine 1930 includes a denoising / deinterlacing module 1932, a motion estimation module 1934, and an image scaling and filtering module 1936. In some embodiments, the denoising / deinterlacing module 1932 includes logic for performing one or more denoising or deinterlacing algorithms on the decoded video data. The deinterlacing logic combines alternating fields of interlaced video content into a single video frame. The denoising logic reduces or removes data noise from the video and image data. In some embodiments, the denoising and deinterlacing logics are motion-adaptive and use spatial or temporal filtering based on the amount of motion detected in the video data. In some embodiments, the denoising / deinterlacing module 1932 includes dedicated motion detection logic (e.g., within the motion estimation engine 1934).

[0216] In some embodiments, the motion estimation engine 1934 provides hardware acceleration for video operations by performing video acceleration functions such as motion vector estimation and prediction on video data. The motion estimation engine determines motion vectors that describe the transformations of image data between consecutive video frames. In some embodiments, the graphics processor media codec uses the video motion estimation engine 1934 to perform operations on video at the macroblock level, operations that may otherwise be computationally too intensive to be performed by a general-purpose processor. In some embodiments, the motion estimation engine 1934 is typically used in graphics processor components to assist in video decoding and processing functions that are sensitive to or adapted to the direction or magnitude of motion within video data.

[0217] In some embodiments, the image scaling and filtering module 1936 performs image processing operations to enhance the visual quality of the generated images and videos. In some embodiments, the scaling and filtering module 1936 processes image and video data during sampling operations before providing data to the execution unit array 1914.

[0218] In some embodiments, the GPE 1910 includes a data port 1944, which provides additional mechanisms for the graphics subsystem to access memory. In some embodiments, the data port 1944 facilitates memory access to operations including render target writes, constant buffer reads, temporary memory space read / writes, and media surface access. In some embodiments, the data port 1944 includes cache memory space for caching memory accesses. The cache memory may be a single data cache or may be divided into multiple caches (e.g., render buffer cache, constant buffer cache, etc.) for multiple subsystems accessing memory via the data port. In some embodiments, threads executing on execution units in the execution unit array 1914 communicate with the data port by exchanging messages via a data distribution interconnect coupled to each subsystem of the GPE 1910.

[0219] Execution unit

[0220] Figure 20 This is a block diagram of another embodiment of the graphics processor 2000. Elements having the same reference numerals (or names) as those in any other figures herein. Figure 20 The components may operate or function in any manner similar to those described elsewhere in this document, but are not limited thereto.

[0221] In some embodiments, the graphics processor 2000 includes a ring interconnect 2002, a pipelined front end 2004, a media engine 2037, and graphics cores 2080A-2080N. In some embodiments, the ring interconnect 2002 couples the graphics processor to other processing units, including other graphics processors or one or more general-purpose processor cores. In some embodiments, the graphics processor is one of many processors integrated within a multi-core processing system.

[0222] In some embodiments, the graphics processor 2000 receives batch commands via a ring interconnect 2002. Incoming commands are interpreted by a command streamer 2003 in a pipeline front-end 2004. In some embodiments, the graphics processor 2000 includes scalable execution logic for performing 3D geometry processing and media processing via one or more graphics cores 2080A-2080N. For 3D geometry processing commands, the command streamer 2003 supplies commands to a geometry pipeline 2036. For at least some media processing commands, the command streamer 2003 supplies commands to a video front-end 2034 coupled to a media engine 2037. In some embodiments, the media engine 2037 includes a video quality engine (VQE) 2030 for video and image post-processing and a multi-format encoding / decoding (MFX) engine 2033 for providing hardware-accelerated media data encoding and decoding. In some embodiments, the geometry pipeline 2036 and the media engine 2037 each generate execution threads for thread execution resources provided by at least one graphics core 2080A.

[0223] In some embodiments, the graphics processor 2000 includes scalable thread execution resource feature modular cores 2080A-2080N (sometimes referred to as core shards), each having a plurality of sub-cores 2050A-2050N and 2060A-2060N (sometimes referred to as core sub-shards). In some embodiments, the graphics processor 2000 may have any number of graphics cores 2080A to 2080N. In some embodiments, the graphics processor 2000 includes a graphics core 2080A having at least a first sub-core 2050A and a second sub-core 2060A. In other embodiments, the graphics processor is a low-power processor having a single sub-core (e.g., 2050A). In some embodiments, the graphics processor 2000 includes a plurality of graphics cores 2080A-2080N, each including a set of first sub-cores 2050A-2050N and a set of second sub-cores 2060A-2060N. Each sub-core in the set of first sub-cores 2050A-2050N includes at least a first set of execution units 2052A-2052N and media / texture samplers 2054A-2054N. Each sub-core in the set of second sub-cores 2060A-2060N includes at least a second set of execution units 2062A-2062N and samplers 2064A-2064N. In some embodiments, each sub-core 2050A-2050N and 2060A-2060N shares a set of shared resources 2070A-2070N. In some embodiments, the shared resources include shared cache memory and pixel operation logic. Other shared resources may also be included in various embodiments of the graphics processor.

[0224] Figure 21 The figure illustrates thread execution logic 2100 of an array of processing elements employed in some embodiments of GPE. Elements having the same reference numerals (or names) as those in any other figures herein. Figure 21 The components may operate or function in any manner similar to those described elsewhere in this document, but are not limited thereto.

[0225] In some embodiments, thread execution logic 2100 includes a pixel shader 2102, a thread dispatcher 2104, an instruction cache 2106, a scalable execution unit array including multiple execution units 2108A-2108N, a sampler 2110, a data cache 2112, and a data port 2114. In one embodiment, the included components are interconnected via an interconnect structure linking each component. In some embodiments, thread execution logic 2100 includes one or more connections to a memory such as system memory or cache memory via one or more of the instruction cache 2106, data port 2114, sampler 2110, and execution unit arrays 2108A-2108N. In some embodiments, each execution unit (e.g., 2108A) is an individual vector processor capable of executing multiple concurrent threads and processing multiple data elements in parallel for each thread. In some embodiments, the execution unit arrays 2108A-2108N include any number of individual execution units.

[0226] In some embodiments, the execution unit arrays 2108A-2108N are primarily used to execute "shader" programs. In some embodiments, the execution units in arrays 2108A-2108N execute instruction sets that include native support for many standard 3D graphics shader instructions, enabling the execution of shader programs from graphics libraries (e.g., Direct 3D and OpenGL) with minimal transformations. The execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general processing (e.g., computation and media shaders).

[0227] Each execution unit in the execution unit arrays 2108A-2108N operates on an array of data elements. The number of data elements is the "execution size" or the number of channels used for instructions. An execution channel is a logical execution unit for data element access, masking, and flow control within an instruction. The number of channels can be independent of the number of physical arithmetic logic units (ALUs) or floating-point units (FPUs) for a particular graphics processor. In some embodiments, the execution units 2108A-2108N support both integer and floating-point data types.

[0228] The execution unit instruction set includes Single Instruction Multiple Data (SIMD) instructions. Various data elements can be stored in registers as packed data types, and the execution unit will process these elements based on their data size. For example, when operating on a 256-bit wide vector, the 256 bits of the vector are stored in registers, and the execution unit operates on the vector as four separate 64-bit packed data elements (quad-word (QW) size data elements), eight separate 32-bit packed data elements (double-word (DW) size data elements), sixteen separate 16-bit packed data elements (word (W) size data elements), or 32 separate 8-bit data elements (byte (B) size data elements). However, different vector widths and register sizes are possible.

[0229] One or more internal instruction caches (e.g., 2106) are included in thread execution logic 2100 to cache thread instructions for the execution unit. In some embodiments, one or more data caches (e.g., 2112) are included to cache thread data during thread execution. In some embodiments, sampler 2110 is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, sampler 2110 includes specialized texture or media sampling functionality to process texture or media data during the sampling process before providing sampled data to the execution unit.

[0230] During execution, the graphics and media pipeline sends thread initiation requests to thread execution logic 2100 via thread production and dispatch logic. In some embodiments, thread execution logic 2100 includes a local thread dispatcher 2104 that arbitrates thread initiation requests from the graphics and media pipeline and instantiates the requested thread on one or more execution units 2108A-2108N. For example, the geometry pipeline (e.g., Figure 20 2036) dispatches vertex processing, tessellation, or geometry processing threads to thread execution logic 2100 ( Figure 21 In some embodiments, thread dispatcher 2104 may also handle runtime thread spawning requests from the shader program.

[0231] Once the geometric object group has been processed and rasterized into pixel data, pixel shader 2102 is dispatched to further compute output information and cause the results to be written to an output surface (e.g., a color buffer, depth buffer, stencil buffer, etc.). In some embodiments, pixel shader 2102 computes values ​​of various vertex attributes to be interpolated onto the rasterized object. In some embodiments, pixel shader 2102 then executes a pixel shader program provided by an application programming interface (API). To execute the pixel shader program, pixel shader 2102 dispatches a thread to an execution unit (e.g., 2108A) via thread dispatcher 2104. In some embodiments, pixel shader 2102 uses texture sampling logic in sampler 2110 to access texture data in a texture map stored in memory. Arithmetic operations on the texture data and input geometry data compute pixel color data for each geometric fragment, or discard one or more pixels for further processing.

[0232] In some embodiments, data port 2114 provides a memory access mechanism for thread execution logic 2100, outputting processed data to memory for processing on the graphics processor output pipeline. In some embodiments, data port 2114 includes or is coupled to one or more cache memories (e.g., data cache 2112) to cache data for memory access via the data port.

[0233] Figure 22 This is a block diagram illustrating a graphics processor instruction format 2200 according to some embodiments. In one or more embodiments, the graphics processor execution unit supports an instruction set having multiple instruction formats. Solid line block diagrams show components typically included in the execution unit instructions, while dashed lines represent optional components or components included only in a subset of the instructions. In some embodiments, the instruction format 2200 described and illustrated are macro instructions, as they are instructions supplied to the execution unit—as opposed to micro-operations generated from instruction decoding once the instruction is processed.

[0234] In some embodiments, the graphics processor execution unit natively supports instructions in 128-bit format 2210. A 64-bit compact instruction format 2230 may be available for some instructions, depending on the selected instructions, instruction options, and number of operands. The native 128-bit format 2210 provides access to all instruction options, while some options and operations are restricted to 64-bit format 2230. The native instructions available in 64-bit format 2230 vary depending on the embodiment. In some embodiments, instructions are compressed in part using a set of index values ​​in index field 2213. The execution unit hardware references a set of compression tables based on the index values ​​and uses the output of the compression tables to reconstruct the native instructions in 128-bit format 2210.

[0235] For each format, instruction opcode 2212 defines the operation to be performed by the execution unit. The execution unit executes each instruction in parallel on multiple data elements of each operand. For example, in response to an add instruction, the execution unit performs a simultaneous add operation on each color channel representing a texture element or image element. By default, the execution unit executes each instruction on all data channels of the operand. In some embodiments, instruction control field 2214 enables control over certain execution options, such as channel selection (e.g., prediction) and data channel order (e.g., allocation). For 128-bit instructions 2210, execution size field 2216 limits the number of data channels to be executed in parallel. In some embodiments, execution size field 2216 is not available for use in the 64-bit compact instruction format 2230.

[0236] Some execution unit instructions have up to three operands, including two source operands src0 2220 and src1 2222 and a destination 2218. In some embodiments, the execution unit supports dual-destination instructions, where one of the destinations is implicit. Data manipulation instructions may have a third source operand (e.g., SRC22224), where the instruction opcode 2212 determines the number of source operands. The last source operand of an instruction may be an immediate (e.g., hard-coded) value passed with the instruction.

[0237] In some embodiments, the 128-bit instruction format 2210 includes access / addressing mode information 2226 specifying, for example, whether to use direct register addressing mode or indirect register addressing mode. When using direct register addressing mode, the register addresses of one or more operands are directly provided by bits in the instruction 2210.

[0238] In some embodiments, the 128-bit instruction format 2210 includes an access / addressing mode field 2226, which specifies the addressing mode and / or access mode for the instruction. In one embodiment, the access mode is used to define the data access alignment for the instruction. Some embodiments support access modes including a 16-byte aligned access mode and a 1-byte aligned access mode, wherein the byte alignment of the access mode determines the access alignment of the instruction operands. For example, when in a first mode, instruction 2210 may use byte-aligned addressing for both source and destination operands, and when in a second mode, instruction 2210 may use 16-byte aligned addressing for all source and destination operands.

[0239] In one embodiment, the addressing mode portion of the access / addressing mode field 2226 determines whether the instruction uses direct or indirect addressing. When using direct register addressing mode, the bits in instruction 2210 directly provide the register addresses of one or more operands. When using indirect register addressing mode, the register addresses of one or more operands can be calculated based on the address register value and the address immediate field in the instruction.

[0240] In some embodiments, instructions are grouped based on the 2212-bit field of the opcode to simplify opcode decoding 2240. For an 8-bit opcode, bits 4, 5, and 6 allow the execution unit to determine the type of opcode. The precise opcode grouping shown is merely an example. In some embodiments, the move and logic opcode group 2242 includes data move and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, the move and logic group 2242 shares five most significant bits (MSB), where the move (mov) instruction is of the form 0000xxxxb and the logic instruction is of the form 0001xxxxb. The flow control instruction group 2244 (e.g., call, jump (jmp)) includes instructions of the form 0010xxxxb (e.g., 0x20). The miscellaneous instruction group 2246 includes a mixture of instructions, including synchronization instructions (e.g., wait, send) of the form 0011xxxxb (e.g., 0x30). Parallel math instruction group 2248 includes component-based arithmetic instructions (e.g., addition, multiplication (mul)) in the form of 0100xxxxb (e.g., 0x40). Parallel math group 2248 performs arithmetic operations in parallel on the data path. Vector math group 2250 includes arithmetic instructions (e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). Vector math group performs arithmetic operations on vector operands, such as dot product calculations.

[0241] Graphics pipeline

[0242] Figure 23 This is a block diagram of another embodiment of the graphics processor 2300. Elements having the same reference numerals (or names) as those in any other figures herein. Figure 23 The components may operate or function in any manner similar to those described elsewhere in this document, but are not limited thereto.

[0243] In some embodiments, the graphics processor 2300 includes a graphics pipeline 2320, a media pipeline 2330, a display engine 2340, thread execution logic 2350, and a rendering output pipeline 2370. In some embodiments, the graphics processor 2300 is a graphics processor within a multi-core processing system including one or more general-purpose processing cores. The graphics processor is controlled by registers written to one or more control registers (not shown) or by commands issued to the graphics processor 2300 via a ring interconnect 2302. In some embodiments, the ring interconnect 2302 couples the graphics processor 2300 to other processing components, such as other graphics processors or general-purpose processors. Commands from the ring interconnect 2302 are interpreted by a command streamer 2303, which supplies instructions to the various components of the graphics pipeline 2320 or the media pipeline 2330.

[0244] In some embodiments, command fluidizer 2303 guides the operation of vertex acquirer 2305, which reads vertex data from memory and executes vertex processing commands provided by command fluidizer 2303. In some embodiments, vertex acquirer 2305 provides vertex data to vertex shader 2307, which performs coordinate space transformation and lighting operations on each vertex. In some embodiments, vertex acquirer 2305 and vertex shader 2307 execute vertex processing instructions by dispatching execution threads to execution units 2352A and 2352B via thread dispatcher 2331.

[0245] In some embodiments, execution units 2352A and 2352B are arrays of vector processors having an instruction set for performing graphics and media operations. In some embodiments, execution units 2352A and 2352B have an attached L1 cache 2351, which is dedicated to each array or shared between arrays. The cache can be configured as a data cache, an instruction cache, or partitioned into a single cache containing data and instructions in different partitions.

[0246] In some embodiments, the graphics pipeline 2320 includes a tessellation component for performing hardware-accelerated tessellation of 3D objects. In some embodiments, a programmable shell shader 2311 configures the tessellation operation. A programmable domain shader 2317 provides back-end evaluation of the tessellation output. A tessellation unit 2313 operates in the direction of the shell shader 2311 and includes dedicated logic for generating a set of detailed geometric objects based on a coarse geometric model provided as input to the graphics pipeline 2320. In some embodiments, the tessellation components 2311, 2313, and 2317 can be bypassed if tessellation is not used.

[0247] In some embodiments, the complete geometry object can be processed by the geometry shader 2319 via one or more threads dispatched to execution units 2352A, 2352B, or it can proceed directly to the trimmer 2329. In some embodiments, the geometry shader operates on the entire geometry object, rather than on vertices or vertex patches as in previous stages of the graphics pipeline. If tessellation is disabled, the geometry shader 2319 receives input from the vertex shader 2307. In some embodiments, the geometry shader 2319 can be programmed by a geometry shader program to perform geometric tessellation when the tessellation unit is disabled.

[0248] Prior to rasterization, clipper 2329 processes vertex data. Clipper 2329 may be a fixed-function clipper or a programmable clipper with clipping and geometry shader functionality. In some embodiments, rasterizer 2373 (e.g., a depth testing component) in the render output pipeline 2370 dispatches pixel shaders to transform geometric objects into their per-pixel representation. In some embodiments, pixel shader logic is included in thread execution logic 2350. In some embodiments, an application may bypass rasterizer 2373 and access unrasterized vertex data via outflow unit 2323.

[0249] The graphics processor 2300 has an interconnect bus, interconnect structure, or some other interconnect mechanism that allows data and messages to be passed between the main components of the processor. In some embodiments, execution units 2352A, 2352B and associated cache(s) 2351, texture and media sampler(s) 2354, and texture / sampler cache(s) 2358 are interconnected via data port 2356 to perform memory accesses and communicate with the processor's rendering output pipeline components. In some embodiments, sampler(s), cache(s) 2351, 2358, and execution units 2352A, 2352B each have a separate memory access path.

[0250] In some embodiments, the rendering output pipeline 2370 includes a rasterizer 2373 that transforms vertex-based objects into associated pixel-based representations. In some embodiments, the rasterizer logic includes a windower / masker unit that performs fixed-function triangle and line rasterization. Associated renderer cache 2378 and depth cache 2379 are also available in some embodiments. Pixel operation component 2377 performs pixel-based operations on the data, but in some cases, pixel operations associated with 2D operations (e.g., bit-block image transfer with blending) are performed by the 2D engine 2341, or replaced at display time by the display controller 2343 using an overlay display plane. In some embodiments, a shared L3 cache 2375 is available to all graphics components, allowing data to be shared without using main system memory.

[0251] In some embodiments, the graphics processor media pipeline 2330 includes a media engine 2337 and a video front-end 2334. In some embodiments, the video front-end 2334 receives pipeline commands from a command streamer 2303. In some embodiments, the media pipeline 2330 includes a separate command streamer. In some embodiments, the video front-end 2334 processes media commands before sending them to the media engine 2337. In some embodiments, the media engine 2337 includes thread production functionality to produce threads for dispatch to thread execution logic 2350 via a thread dispatcher 2331.

[0252] In some embodiments, the graphics processor 2300 includes a display engine 2340. In some embodiments, the display engine 2340 is external to the processor 2300 and coupled to the graphics processor via a ring interconnect 2302 or some other interconnect bus or structure. In some embodiments, the display engine 2340 includes a 2D engine 2341 and a display controller 2343. In some embodiments, the display engine 2340 includes dedicated logic capable of operating independently of the 3D pipeline. In some embodiments, the display controller 2343 is coupled to a display device (not shown), which may be a system-integrated display device, such as in a laptop computer, or an external display device attached via a display device connector.

[0253] In some embodiments, the graphics pipeline 2320 and media pipeline 2330 may be configured to perform operations based on multiple graphics and media programming interfaces and not specific to any one application programming interface (API). In some embodiments, driver software for the graphics processor translates API calls that are specific to a particular graphics or media library into commands processed by the graphics processor. In some embodiments, support is provided for the Open Graphics Library (OpenGL) and Open Computing Language (OpenCL) from the Khronos Group, the Direct3D library from Microsoft, or both OpenGL and D3D may be supported. Support may also be provided for the open-source computer vision library (OpenCV). Future APIs with compatible 3D pipelines will also be supported if a pipeline mapping from future APIs to the graphics processor pipeline is possible.

[0254] Graphics pipeline programming

[0255] Figure 24A This is a block diagram illustrating a graphics processor command format 2400 according to some embodiments. Figure 24B This is a block diagram illustrating a graphics processor command sequence 2410 according to an embodiment. Figure 24A Solid lines in the diagram show components that are typically included in the graphics command, while dashed lines indicate optional components or components that are only included in a subset of the graphics command. Figure 24A An exemplary graphics processor command format 2400 may include data fields for identifying the target client 2402 of the command, a command operation code (opcode) 2404, and related data 2406 for the command. In some commands, a sub-opcode 2405 and a command size 2408 are also included.

[0256] In some embodiments, client 2402 specifies a client unit of a graphics device that processes command data. In some embodiments, a graphics processor command parser examines the client field of each command to adjust further processing of the command and routes the command data to the appropriate client unit. In some embodiments, the graphics processor client unit includes a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline for processing commands. Once a client unit receives a command, it reads opcode 2404 and sub-opcode 2405—if present—to determine the operation to be performed. The client unit uses information in data field 2406 to execute the command. For some commands, an explicit command size 2408 is expected to specify the size of the command. In some embodiments, the command parser automatically determines the size of at least some commands based on the command opcode. In some embodiments, commands are aligned via multiple double words.

[0257] Figure 24B The flowchart illustrates an exemplary graphics processor command sequence 2410. In some embodiments, software or firmware of a data processing system characterized by an embodiment of a graphics processor uses a version of the illustrated command sequence to set up, execute, and terminate a set of graphics operations. The example command sequence is shown and described for illustrative purposes only, as the embodiments are not limited to these specific commands or the command sequence. Moreover, commands can be issued as a batch of commands in a command sequence, such that the graphics processor will process the command sequence at least partially simultaneously.

[0258] In some embodiments, the graphics processor command sequence 2410 may begin with a pipeline dump clearing command 2412 to cause any active graphics pipeline to complete its current pending commands. In some embodiments, the 3D pipeline 2422 and the media pipeline 2424 do not operate simultaneously. Pipeline dump clearing is performed to cause any pending commands to be completed by the active graphics pipeline. In response to pipeline dump clearing, the command parser for the graphics processor suspends command processing until the active graphics engine completes its pending operations and the relevant read cache is invalidated. Optionally, any data marked as "dirty" in the renderer cache may be cleared during memory dumping. In some embodiments, pipeline dump clearing command 2412 may be used before placing the graphics processor in a low-power state or for pipeline synchronization.

[0259] In some embodiments, a pipeline selection command 2413 is used when a sequence of commands requires the graphics processor to explicitly switch between pipelines. In some embodiments, only one pipeline selection command 2413 is required in the execution context before a pipeline command is issued—unless the context requires issuing commands for two pipelines. In some embodiments, a pipeline dump clearing command 2412 is required immediately preceding the pipeline switch via pipeline selection command 2413.

[0260] In some embodiments, pipeline control command 2414 configures the graphics pipeline for operation and is used to program the 3D pipeline 2422 and the media pipeline 2424. In some embodiments, pipeline control command 2414 configures the pipeline state for the active pipeline. In one embodiment, pipeline control command 2414 is used for pipeline synchronization and to clear data from one or more cache memories within the active pipeline before processing batch commands.

[0261] In some embodiments, the return buffer state command 2416 is used to configure a set of return buffers for a given pipeline to write data. Some pipeline operations require allocating, selecting, or configuring one or more return buffers to which intermediate data is written during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform cross-thread communication. In some embodiments, the return buffer state 2416 includes selecting the size and number of return buffers for a set of pipeline operations.

[0262] The remaining commands in the command sequence differ based on the active pipeline used for the operation. Based on pipeline determination 2420, a customized command sequence is made for either the 3D pipeline 2422 that begins with 3D pipeline state 2430 or the media pipeline 2424 that begins with media pipeline state 2440.

[0263] Commands for 3D pipeline state 2430 include 3D state setting commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables to be configured before processing 3D primitive commands. The values ​​of these commands are determined at least in part based on the specific 3D API being used. In some embodiments, 3D pipeline state 2430 commands can also selectively disable or bypass certain pipeline elements—if these elements will not be used.

[0264] In some embodiments, 3D primitive 2432 commands are used to submit 3D primitives to be processed by the 3D pipeline. Commands and associated parameters passed to the graphics processor via 3D primitive 2432 commands are forwarded to the vertex extraction function in the graphics pipeline. The vertex extraction function uses the 3D primitive 2432 command data to generate a vertex data structure. The vertex data structure is stored in one or more return buffers. In some embodiments, 3D primitive 2432 commands are used to perform vertex operations on the 3D primitives via a vertex shader. To process the vertex shader, the 3D pipeline 2422 dispatches shader execution threads to the graphics processor execution unit.

[0265] In some embodiments, the 3D pipeline 2422 is triggered by executing command 2434 or an event. In some embodiments, register writes trigger command execution. In some embodiments, execution is triggered by a "go" or "kick" command in a command sequence. In one embodiment, pipeline synchronization commands are used to trigger command execution to clear the command sequence via a graphics pipeline dump. The 3D pipeline performs geometry processing on 3D primitives. Once the operation is complete, the resulting geometry is rasterized, and the pixel engine shades the resulting pixels. Additional commands for controlling pixel shading and pixel backend operations may also be included for these operations.

[0266] In some embodiments, when performing media operations, the graphics processor command sequence 2410 follows the media pipeline 2424 path. Typically, the specific use and programming of the media pipeline 2424 depends on the media or computational operation to be performed. During media decoding, specific media decoding operations can be offloaded to the media pipeline. In some embodiments, the media pipeline can also be bypassed, and media decoding can be performed wholly or partially using resources provided by one or more general-purpose processing cores. In one embodiment, the media pipeline also includes elements for general-purpose graphics processing unit (GPGPU) operations, wherein the graphics processor is used to perform SIMD vector operations using computational shader programs that are not explicitly associated with the rendering of graphics primitives.

[0267] In some embodiments, the media pipeline 2424 is configured in a manner similar to that of the 3D pipeline 2422. Prior to the media object command 2442, a set of media pipeline status commands 2440 are dispatched or placed in a command queue. In some embodiments, the media pipeline status commands 2440 include data configuring media pipeline elements that will be used to process media objects. This includes data configuring video decoding and video encoding logic within the media pipeline, such as encoding or decoding formats. In some embodiments, the media pipeline status commands 2440 also support the use of one or more pointers to "indirect" status elements that contain batch status settings.

[0268] In some embodiments, media object command 2442 supplies a pointer to a media object for processing by the media pipeline. The media object includes a memory buffer containing video data to be processed. In some embodiments, all media pipeline states must be valid before issuing media object command 2442. Once the pipeline states are configured and media object command 2442 is queued, media pipeline 2424 is triggered via execution command 2444 or an equivalent execution event (e.g., register write). The output from media pipeline 2424 can then be post-processed by operations provided by 3D pipeline 2422 or media pipeline 2424. In some embodiments, GPGPU operations are configured and executed in a manner similar to media operations.

[0269] Graphics software architecture

[0270] Figure 25The figure illustrates an exemplary graphics software architecture for a data processing system 2500 according to some embodiments. In some embodiments, the software architecture includes a 3D graphics application 2510, an operating system 2520, and at least one processor 2530. In some embodiments, the processor 2530 includes a graphics processor 2532 and one or more general-purpose processor cores 2534. The graphics application 2510 and the operating system 2520 each execute in the system memory 2550 of the data processing system.

[0271] In some embodiments, the 3D graphics application 2510 includes one or more shader programs, which include shader instructions 2512. The shader language instructions may be a high-level shader language, such as High-Level Shading Language (HLSL) or OpenGL Shading Language (GLSL). The application also includes executable instructions 2514 in machine language suitable for execution by a general-purpose processor core 2534. The application also includes graphics objects 2516 defined by vertex data.

[0272] In some embodiments, the operating system 2520 is a Microsoft® Windows® operating system from Microsoft Corporation, a proprietary Unix-like operating system, or an open-source Unix-like operating system using a variant of the Linux kernel. When the Direct3D API is used, the operating system 2520 uses a front-end shader compiler 2524 to compile any shader instructions 2512 in HLSL into a lower-level shader language. Compilation can be just-in-time (JIT) compilation or application-enabled shader pre-compilation. In some embodiments, high-level shaders are compiled into low-level shaders during the compilation of the 3D graphics application 2510.

[0273] In some embodiments, the user-mode graphics driver 2526 includes a back-end shader compiler 2527 for translating shader instructions 2512 into a hardware-specific representation. When the OpenGL API is used, shader instructions 2512 in the GLSL high-level language are passed to the user-mode graphics driver 2526 for compilation. In some embodiments, the user-mode graphics driver 2526 uses operating system kernel-mode functionality 2528 to communicate with the kernel-mode graphics driver 2529. In some embodiments, the kernel-mode graphics driver 2529 communicates with the graphics processor 2532 to dispatch commands and instructions.

[0274] IP core implementation

[0275] One or more aspects of at least one embodiment can be implemented by representative code stored on a machine-readable medium, which represents and / or defines logic within an integrated circuit, such as a processor. For example, the machine-readable medium may include instructions representing various logics within a processor. When read by a machine, the instructions can cause the machine to manufacture logic to perform the techniques described herein. This representation, referred to as an "IP core," is a reusable unit of logic for an integrated circuit that can be stored on a tangible machine-readable medium as a hardware model describing the structure of the integrated circuit. The hardware model can be supplied to various customers or manufacturing facilities that load it onto manufacturing machines that produce the integrated circuit. The integrated circuit can be manufactured such that the circuit performs the operations described in association with any of the embodiments described herein.

[0276] Figure 26 This is a block diagram illustrating an IP core development system 2600, according to an embodiment, that can be used to fabricate integrated circuits to perform operations. The IP core development system 2600 can be used to generate modular, reusable designs that can be incorporated into larger designs or used to build entire integrated circuits (e.g., SOC integrated circuits). Design facility 2630 can generate software simulation 2610 of the IP core design using a high-level programming language (e.g., C / C++). Software simulation 2610 can be used to design, test, and verify the behavior of the IP core. Register transfer level (RTL) designs can then be created or synthesized from the simulation model 2600. RTL design 2615 is an abstraction of the behavior of an integrated circuit, modeling the flow of digital signals between hardware registers that include associated logic performed using modeled digital signals. In addition to RTL design 2615, low-level designs at the logic level or transistor level can also be created, designed, or synthesized. Therefore, specific details of the initial design and simulation can vary.

[0277] The RTL design 2615 or its equivalent can be further synthesized by the design facility into a hardware model 2620, which may be a hardware description language (HDL) or some other representation of physical design data. The HDL can be further simulated or tested to validate the IP core design. The IP core design can be stored in non-volatile memory 2640 (e.g., hard disk, flash memory, or any non-volatile storage medium) for delivery to a third-party manufacturing facility 2665. Alternatively, the IP core design can be transmitted via a wired connection 2650 or a wireless connection 2660 (e.g., via the Internet). The manufacturing facility 2665 can then manufacture an integrated circuit at least partially based on the IP core design. The manufactured integrated circuit can be configured to perform operation according to at least one embodiment described herein.

[0278] Figure 27This is a block diagram illustrating an exemplary system on a chip integrated circuit 2700 that can be fabricated using one or more IP cores according to an embodiment. The exemplary integrated circuit includes one or more application processors 2705 (e.g., a CPU), at least one graphics processor 2710, and may additionally include an image processor 2715 and / or a video processor 2720, any of which may be a modular IP core from the same or more different design facilities. The integrated circuit includes peripheral or bus logic, including a USB controller 2725, a UART controller 2730, an SPI / SDIO controller 2735, and an I... 2 S / I 2 C controller 2740. Additionally, the integrated circuit may include a display device 2745, which is coupled to one or more High Definition Multimedia Interface (HDMI) controllers 2750 and Mobile Industrial Processor Interface (MIPI) display interfaces 2755. Storage may be provided by a flash memory subsystem 2760 including flash memory and a flash memory controller. A memory interface for accessing SDRAM or SRAM memory devices may be provided via a memory controller 2765. Some integrated circuits also include an embedded security engine 2770.

[0279] Additionally, the processor in the integrated circuit 2700 may include other logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0280] Advantageously, any of the above systems, processors, graphics processors, devices and / or methods can be integrated with or utilize the configuration of any (e.g., or a portion thereof) of the various embodiments described herein, including those described, for example, in the following additional notes and examples.

[0281] Additional notes and examples

[0282] Example 1 may include a system for reducing power consumption by a display, the system comprising: a display divided into multiple segments; a display engine communicatively coupled to the display and capable of addressing each of the multiple segments; and a gaze tracker communicatively coupled to a processor and the display engine to identify segments within a gaze region, wherein the display engine increases the refresh rate for the identified segments within the gaze region relative to segments outside the gaze region to save power.

[0283] Example 2 may include the system in Example 1, wherein segments outside the gaze region have a lower shading rate to save power.

[0284] Example 3 may include the system of any one of Examples 1 to 2, wherein the plurality of segments are hexagonal in shape.

[0285] Example 4 may include the system of any of Examples 1 to 2, wherein the display is a curved display.

[0286] Example 5 may include the system of any of Examples 1 to 2, and further include: a wearable device worn by a viewer for tracking body movement; and a sensor communicatively coupled to the processor to use body movement to predict future gaze areas.

[0287] Example 6 may include the system in Example 5, wherein there is more than one gaze region.

[0288] Example 7 may include a method for reducing the power consumption of a display, comprising: dividing the display into multiple addressable segments; following a user's gaze on the display; identifying one or more adjacent segments within the gaze region; and providing a higher quality image for the segments within the gaze region compared to segments outside the gaze region.

[0289] Example 8 may include the method as in Example 7, wherein the plurality of segments are hexagonal in shape.

[0290] Example 9 may include the method as in Example 7, wherein providing higher quality images to segments in the gaze region includes an increased refresh rate.

[0291] Example 10 may include the method as in Example 7, wherein providing higher quality images to segments within the gaze region includes a reduced refresh rate in segments outside the gaze region.

[0292] Example 11 may include methods as in Example 7, and may also include identifying multiple gaze regions.

[0293] Example 12 may include methods as in Example 7, and may also include collecting body motion data from wearable devices to help predict future gaze areas.

[0294] Example 13 may include the method as in Example 7, and further include reducing the shading rate for segments outside the gaze region to save power.

[0295] Example 14 may include an apparatus for reducing power consumption by a display, the apparatus comprising: a display engine communicatively addressable for each of a plurality of segments of the display; and a gaze tracker communicatively coupled to a processor and the display engine to identify segments in one or more gaze regions, wherein the display engine increases the refresh rate for the identified segments in the one or more gaze regions relative to segments outside the one or more gaze regions.

[0296] Example 15 may include the method as in Example 14, wherein segments outside the gaze region have a lower shading rate to save power.

[0297] Example 16 may include the method as in Example 14, wherein the plurality of segments are hexagonal in shape.

[0298] Example 17 may include the method as in Example 14, wherein the display is a curved display.

[0299] Example 18 may include the method as in Example 14, and further include: one or more wearable devices worn by one or more viewers for tracking body movement; and sensors communicatively coupled to the processor to use body movement to predict future gaze areas.

[0300] Example 19 may include at least one machine-readable medium comprising a plurality of instructions which, in response to being executed on a computing device, cause the computing device to perform a method according to any one of Examples 7 to 13.

[0301] Example 20 may include an apparatus for reducing power consumption by a display, including components for dividing the display into multiple addressable segments, components for following a user's gaze on the display, components for identifying one or more adjacent segments within the gaze area, and components for providing a higher quality image to the segments within the gaze area compared to segments outside the gaze area.

[0302] Example 21 may include the apparatus as described in Example 20, wherein the plurality of segments are hexagonal in shape.

[0303] Example 22 may include a device as in Example 20, wherein the component for providing higher quality images to segments in the gaze region includes an increased refresh rate.

[0304] Example 23 may include the apparatus as in Example 20, wherein the component for providing higher quality images to segments within the gaze region includes a reduced refresh rate in segments outside the gaze region.

[0305] Example 24 may include the apparatus as in Example 20, and also includes components for identifying multiple gaze regions.

[0306] Example 25 may include a device as in Example 20, and also includes components for collecting body motion data from a wearable device to help predict future gaze areas.

[0307] Example 26 may include the apparatus as in Example 20, and further include components for reducing the shading rate for segments outside the gaze region to save power.

[0308] The term “coupling” may be used herein to refer to any type of direct or indirect relationship between the components under discussion and may be applied to electrical, mechanical, fluid, optical, electromagnetic, electromechanical, or other connections. Additionally, unless otherwise indicated, the terms “first,” “second,” etc., may be used herein merely to facilitate discussion and do not carry any particular temporal or chronological significance. Furthermore, it should be understood that the indefinite article “a” or “an” carries the meaning of “one or more” or “at least one.”

[0309] As used in this application and claims, a list of items connected by the term "one or more of..." can refer to any combination of the listed items. For example, the phrase "one or more of A, B, or C" can mean A, B, C; A and B; A and C; B and C; or A, B, and C.

[0310] The embodiments have been described above with reference to specific examples. However, those skilled in the art will understand that various modifications and changes can be made thereto without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the foregoing description and drawings are to be considered illustrative rather than restrictive.

Claims

1. A system for reducing power consumption by a display, comprising: A display, the display being divided into multiple segments; A display engine communicatively coupled to the display and capable of addressing each of the plurality of segments; A gaze tracker, provided at a display and communicatively coupled to a processor and a display engine, identifies segments within a viewer's gaze region, wherein the segment identification is based at least in part on focus information, including content-based focus information provided by an application, the focus information being based on where the viewer is assumed to be looking, where the viewer is determined to be looking, where the application wants the viewer to look, and where the viewer will look in the future, the content-based focus information including depth information and motion information, wherein the gaze tracker includes a sensor unit comprising one or more cameras, motion sensors, and microphones for tracking the viewer's gaze; The display engine increases the refresh rate for segments identified within the gaze region relative to segments outside the gaze region in order to save power.

2. The system according to claim 1, wherein, The segments outside the gaze area have a lower shading rate to save power.

3. The system according to any one of claims 1 to 2, wherein, The multiple segments are hexagonal in shape.

4. The system according to any one of claims 1 to 2, wherein, The display is a curved display.

5. The system according to any one of claims 1 to 2, further comprising: Wearable devices worn by viewers to track body movement; and A sensor communicatively coupled to the processor to use body movement to predict future gaze areas.

6. The system according to claim 5, wherein, There is more than one gaze region.

7. A method for reducing power consumption by a display, comprising: Divide the display into multiple addressable segments; Use a gaze tracker provided at the display to determine the user's gaze on the display; Identify one or more adjacent segments of the display within the gaze region, wherein the identification of one or more adjacent segments is based at least in part on focus information, including content-based focus information provided by the application, the focus information being based on where the user is assumed to be looking, where the user is determined to be looking, where the application wants the user to look, and wherein the content-based focus information predicts where the user will look in the future, including depth information and motion information, and Segments within the gaze region are provided with higher quality images compared to segments outside the gaze region; The gaze tracker is provided at the display and includes a sensor unit comprising one or more cameras, motion sensors, and microphones for tracking the user's gaze.

8. The method according to claim 7, wherein, The multiple segments are hexagonal in shape.

9. The method according to claim 7, wherein, Providing higher quality images to segments within the gaze region includes increasing the refresh rate.

10. The method according to claim 7, wherein, Providing higher quality images to segments within the gaze region includes reducing the refresh rate in segments outside the gaze region.

11. The method of claim 7, further comprising identifying a plurality of gaze regions.

12. The method of claim 7, further comprising: Collect body motion data from wearable devices to help predict future gaze areas.

13. The method of claim 7, further comprising reducing the shading rate of segments outside the gaze region to save power.

14. An apparatus for reducing power consumption by a display, comprising: A screen display, viewed by one or more viewers, the display being divided into multiple segments; A display engine communicatively coupled to the display and capable of addressing each of the plurality of segments; A gaze tracker, provided at the screen display and communicatively coupled to a processor and a display engine, the processor being used to identify segments of the display in one or more gaze regions, wherein the identification of segments is based at least in part on focus information, including content-based focus information provided by an application, the focus information being based on where one or more viewers are assumed to be looking, where one or more viewers are determined to be looking, where the application wants one or more viewers to be looking, and predicting where one or more viewers will be looking in the future, the content-based focus information including depth information and motion information. The gaze tracker includes a sensor unit and one or more cameras, the cameras being used to track the gaze of one or more viewers, and the sensor unit including a motion sensor and a microphone. The display engine will increase the refresh rate for segments identified within the one or more viewing regions relative to segments outside the one or more viewing regions.

15. The apparatus according to claim 14, wherein, Segments outside the gaze area will have a lower shading rate to save power.

16. The apparatus according to claim 14, wherein, The multiple segments will be hexagonal in shape.

17. The apparatus according to claim 14, wherein, The display will be a curved display.

18. The apparatus of claim 14, further comprising: One or more wearable devices worn by one or more viewers to track body movement; and A sensor communicatively coupled to the processor to use body movement to predict future gaze areas.

19. An apparatus for reducing power consumption by a display, comprising: A component used to divide a display into multiple addressable segments; A component used to determine a user's gaze on the display using a gaze tracker provided at the display. Components for identifying one or more adjacent segments of the display within the gaze area, wherein the identification of one or more adjacent segments is based at least in part on focus information, including content-based focus information provided by an application, the focus information being based on where the user is assumed to be looking, where the user is determined to be looking, where the application wants the user to look, and wherein the content-based focus information predicts where the user will look in the future, including depth information and motion information, and A component used to provide higher quality images to segments within the gaze region compared to segments outside the gaze region; The gaze tracker is provided at the display and includes a sensor unit comprising one or more cameras, motion sensors, and microphones for tracking the user's gaze.

20. The apparatus according to claim 19, wherein, The multiple segments are hexagonal in shape.

21. The apparatus according to claim 19, wherein, The components used to provide higher quality images to segments within the gaze region include an increased refresh rate.

22. The apparatus according to claim 19, wherein, The component for providing higher quality images to segments within the gaze region includes a reduced refresh rate in segments outside the gaze region.

23. The apparatus of claim 19 further includes components for identifying a plurality of gaze regions.

24. The apparatus of claim 19, further comprising: Components used to collect body motion data from wearable devices to help predict future gaze areas.

25. The apparatus of claim 19, further comprising: A component for reducing the shading rate of segments outside the gaze region.

26. A computer-readable medium having instructions thereon that, when executed, cause a computer device to perform the method according to any one of claims 1-13.

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