Mixed-precision floating-point operation circuit in a dedicated processing block

Abstract

Mixed precision floating point operation circuits in special purpose processing blocks are disclosed. Embodiments relate to integrated circuits having circuits that efficiently perform mixed precision floating point arithmetic operations. Such circuits can be implemented in special purpose processing blocks. The special purpose processing blocks can include configurable interconnect circuits to support a variety of different usage modes. For example, the special purpose processing blocks can implement fixed point addition, floating point addition, fixed point multiplication, floating point multiplication, sum of two multiplications, with or without conversion to a second floating point precision, followed by a subsequent addition in the second floating point precision if needed, to name a few. In some embodiments, two or more special purpose processing blocks can be arranged in a cascade chain and together perform more complex operations such as a recursive mode dot product of two vectors of floating point numbers having a first floating point precision and output the dot product in a second floating point precision.

Description

TECHNICAL FIELD

[0001] This embodiment relates to integrated circuits, and more particularly, to mixed-precision floating-point operation circuits in special-purpose processing blocks in integrated circuits. BACKGROUND

[0002] As the complexity of applications increases, it is becoming more common to include special-purpose processing blocks in integrated circuits. Such special-purpose processing blocks can be partially or fully hardwired to perform one or more specific tasks, such as logical or mathematical operations. Special-purpose processing blocks can also contain one or more specialized structures, such as arrays of configurable memory elements.

[0003] Examples of structures that are typically implemented in such special-purpose processing blocks include multipliers, adders, accumulators, arithmetic logic units (ALUs), barrel shifters, various memory elements or storage circuits, such as first-in-first-out (FIFO) circuits, last-in-first-out (LIFO) circuits, serial-in-parallel-out (SIPO) shift register circuits, parallel-in-serial-out (PISO) shift register circuits, random access memory (RAM) circuits, read-only memory (ROM) circuits, content addressable memory (CAM) circuits, and register files, logical AND, logical NAND, logical OR, logical NOR arrays, and the like, or combinations thereof.

[0004] One particularly useful type of special-purpose processing block, which is sometimes also referred to as a digital signal processing (DSP) block, can be used to process digital signals such as video signals, audio signals, and the like. Such blocks are often also referred to as multiply-accumulate (MAC) blocks because they include structures to perform multiplication operations, as well as summation and / or accumulation of the multiplication operations.

[0005] Integrated circuits, such as programmable integrated circuits, often include special-purpose processing blocks. Each of those special-purpose processing blocks includes multipliers, adders, and registers, as well as programmable connectors (e.g., multiplexers) that allow the various components of the block to be configured in different ways.

[0006] Typically, the arithmetic operators (adders and multipliers) in such special-purpose processing blocks are fixed-point operators. If floating-point operators are needed, they are constructed outside the special-purpose processing block using the device's general-purpose programmable logic, or using a combination of fixed-point operators inside the special-purpose processing block and additional logic in the general-purpose programmable logic. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 A diagram showing an illustrative integrated circuit, such as a programmable integrated circuit, in accordance with some embodiments.

[0008] Figure 2is a diagram of two illustrative special purpose processing blocks for performing mixed precision floating point operations according to some embodiments.

[0009] Figure 3 is a diagram of two illustrative special purpose processing blocks of a first stage arranged in a cascade chain and together performing a recursive mode dot product operation according to some embodiments.

[0010] Figure 4 is a diagram of two illustrative special purpose processing blocks of a first stage arranged in a cascade chain and together performing a recursive mode dot product operation and an accumulation operation according to some embodiments.

[0011] Figure 5 is a diagram of six illustrative special purpose processing blocks arranged in a cascade chain and generating a dot product of two floating point number vectors according to some embodiments.

[0012] Figure 6 is a diagram of four illustrative special purpose processing blocks arranged in a cascade chain and performing a recursive mode dot product of two floating point number vectors and an accumulation of the result according to some embodiments.

[0013] Figure 7 is a diagram of a flowchart showing illustrative operations of an integrated circuit for operating to generate a dot product of first and second vectors according to some embodiments.

[0014] Figure 8 is a cross-sectional view of a magnetic data storage medium encoded with a set of machine executable instructions for configuring an integrated circuit to generate a dot product of first and second vectors according to some embodiments.

[0015] Figure 9 is a cross-sectional view of an optically readable data storage medium encoded with a set of machine executable instructions for configuring an integrated circuit to generate a dot product of first and second vectors according to some embodiments. DETAILED DESCRIPTION

[0016] The present embodiments provided herein relate to integrated circuits, and more particularly, to mixed precision floating point operation circuits in special purpose processing blocks in integrated circuits.

[0017] Floating point numbers are commonly used to represent real numbers in scientific notation in computing systems and are designed to cover large ranges of numerical values and different precision requirements. The IEEE 754 standard, ANSI / IEEE Std. 754-2008, published on August 29, 2008, is commonly used for floating point numbers. A floating point number includes three different parts: a sign, a mantissa (sometimes also referred to as significant), and an exponent. Each of these parts can be represented by a binary number and has a different number of bits depending on the precision in the format of the IEEE 754 standard. For example, a single precision floating point number can require 32 bits, which are allocated as follows: 1 sign bit (bit 31), 8 exponent bits (bits [30:23]), and 23 mantissa bits (bits [22:0]). A double precision floating point number can require 64 bits, including 1 sign bit (bit 63), 11 exponent bits (bits [62:52]), and 52 mantissa bits (bits [51:0]). A half precision floating point number can require 16 bits, including 1 sign bit (bit 15), 5 exponent bits (bits [14:10]), and 10 mantissa bits (bits [9:0]).

[0018] According to the IEEE 754 standard, the mantissa can also have additional bits. A mantissa with additional bits is sometimes also referred to as an extended mantissa. For example, an extended single precision mantissa can have 5 additional bits (i.e., an extended single precision mantissa can consist of 28 bits instead of 23 bits). The last three bits added to the right of the least significant bits (LSBs) represent rounding, guard, and sticky bits.

[0019] The rounding and guard bits can provide additional accuracy when performing arithmetic operations. For example, dividing a mantissa that has a '1' in the least significant bit position by 2 can cause the rounding bit to become '1'. An additional division by 2 can cause the guard bit to become '1'. Thus, the rounding and guard bits enable a number representation that is smaller than the mantissa to be able to represent accurately without these additional bits. The sticky bit can record any bits of value '1' that are shifted out of the precision of the mantissa by performing a logical OR operation with the rounding and guard bits.

[0020] Two bits can be added beyond the most significant bit (MSB) position, if needed, and can absorb any overflow that results from floating point arithmetic operations.

[0021] A single bit is used to represent the sign of a floating point number according to the IEEE 754 standard, where 0 represents a positive number and 1 represents a negative number.

[0022] The exponent of a floating point number is preferably an unsigned binary number, ranging from 0 to 255 for the single precision format. In order to represent very small numbers, it is necessary to use negative exponents. Therefore, the exponent preferably has a negative bias. For single precision floating point numbers, the bias is preferably -127. For example, an exponent value of 140 actually represents (140 - 127) = 13, and a value of 100 represents (100 - 127) = -27. For double and half precision floating point numbers, the exponent bias is preferably -1023 and -15, respectively.

[0023] As discussed above, according to the IEEE 754 standard, the mantissa is a normalized number (i.e. it has no leading zeros and represents the precision component of the floating point number). Because the mantissa is stored in binary format, the leading bit can either be 0 or 1, but for a normalized number it will always be 1. Therefore, in a system where numbers are always normalized, the leading bit need not be stored and can be implied effectively to give the mantissa an extra precision bit.

[0024] Specialized processing blocks that perform arithmetic operations often include multiple multipliers, adders, registers, and programmable connectors (e.g. multiplexers) that allow the various components of the specialized processing block to be configured in different ways. Typically, the arithmetic operators in such specialized processing blocks are fixed point operators.

[0025] If floating point operators are required, they are constructed outside of the specialized processing block (e.g. using additional logic in the integrated circuit, or using a combination of fixed point operators inside the specialized processing block and additional logic in the integrated circuit).

[0026] However, as the complexity of applications increases, the use of floating point operators becomes more common. Furthermore, different applications can have different precision requirements. For example, some applications can require the use of double precision floating point arithmetic operators, while for other applications it is sufficient to use half precision floating point arithmetic operators. Therefore, it is desirable to provide specialized processing blocks that can be adapted to efficiently implement floating point operations with different precisions (e.g. half precision floating point operations and / or single precision floating point operations and / or double precision floating point operations and / or quadruple precision floating point operations and / or octuple precision floating point operations, according to the IEEE 754 standard).

[0027] Those skilled in the art will realize that the exemplary embodiments can be practiced with some or all of these specific details, or with other details. In other instances, well known operations have not been described in detail in order not to unnecessarily obscure the embodiments.

[0028] Figure 1 A diagram illustrating an illustrative integrated circuit, such as programmable integrated circuit 100, according to some embodiments.

[0029] The programmable integrated circuit 100 can have input-output circuits 102 for driving signals out of the programmable integrated circuit 100 and for receiving signals from other devices. The input-output circuits 102 can include conventional input-output circuits, serial data transceiver circuits, differential receiver and transmitter circuits, or other circuits for connecting one integrated circuit to another.

[0030] As shown, the input-output circuits 102 can be positioned near the periphery of the programmable integrated circuit 100. If desired, the programmable integrated circuit 100 can have input-output circuits 102 arranged differently. For example, the input-output circuits 102 can form one or more columns of input-output circuits that can be positioned anywhere on the programmable integrated circuit, such as distributed evenly across the width of the programmable integrated circuit. If desired, the input-output circuits 102 can form one or more rows of input-output elements, such as distributed across the height of the programmable integrated circuit. Alternatively, the input-output circuits 102 can form islands of input-output elements distributed across the surface of the programmable integrated circuit or clustered in selected areas.

[0031] The vertical and horizontal interconnect resources 140 and 150, such as global and local vertical and horizontal conductive lines and buses, can be used to route signals on the programmable integrated circuit 100. The vertical and horizontal interconnect resources 140 and 150 include conductive lines and programmable connections between respective conductive lines, and are therefore sometimes referred to as programmable interconnect, configurable interconnect, or configurable interconnect circuits.

[0032] The programmable logic region can include programmable components such as digital signal processing circuits 120 and storage circuits 130 (which can be organized in dedicated blocks), or other combinational and sequential logic circuits organized in logic array blocks 110. The programmable logic region can be configured to perform custom logic functions. If desired, the digital signal processing circuits 120 and storage circuits 130 can have limited configurability. In some embodiments, the programmable logic region can include additional dedicated blocks, such as programmable phase-locked loop circuits, programmable delay-locked loop circuits, or other dedicated blocks with limited configurability.

[0033] In some embodiments, the digital signal processing circuits 120 can be adaptable to efficiently implement floating point operations with different precisions. For example, the digital signal processing circuits 120 can implement half-precision floating point operations and / or single-precision floating point operations and / or double-precision floating point operations and / or quadruple-precision floating point operations, and so on.

[0034] In some embodiments, multiple blocks of the digital signal processing circuit 120 can be arranged in a cascade chain, and two or more blocks in the cascade chain of the digital signal processing circuit 120 can together implement a dot product of two vectors.

[0035] For example, each block of the digital signal processing circuit 120 can implement one or more multiplication operations, each generating a respective product by multiplying a tuple of one of the two vectors with a tuple of the other of the two vectors. If desired, a first block of the digital signal processing circuit 120 can generate a sum of the respective products generated by the first block and provide the sum at a cascade output, sometimes also referred to as a chain out, a cascade input port, a chain input port, or a cascade chain input.

[0036] A second block of the digital signal processing circuit 120 can receive the sum from the first block at a cascade input, sometimes also referred to as a cascade in, a cascade input port, a chain input port, or a cascade chain input, via a cascade or chain connection.

[0037] The second block can generate a sum of the respective products generated by the second block and the sum received at the cascade input, and provide the generated sum at a cascade output for further processing, if desired, in additional blocks of the digital signal processing circuit 120.

[0038] The programmable integrated circuit 100 can include programmable memory elements. These memory elements can be loaded with configuration data, sometimes also referred to as programming data, using the input-output circuit 102. Once loaded, each of the memory elements provides a corresponding static control signal that controls operation of an associated logic component in the programmable logic region. In a typical scenario, the output of a memory element to be loaded is applied to a gate of a transistor in the programmable logic region to turn on or off certain transistors and thereby configure the logic and routing paths in the programmable logic region. Programmable logic circuit elements that can be controlled in this way include portions of multiplexers (e.g., multiplexers used to form routing paths in the programmable interconnect), look-up tables, logic arrays, XOR, AND, OR, NAND, and NOR logic gates, pass gates, inverters, and the like.

[0039] The memory elements can use any appropriate volatile and / or non-volatile memory structure, such as random access memory (RAM) cells, fuses, anti-fuses, programmable read-only memory cells, mask- and laser-programmed structures, combinations of these structures, and the like. Because the memory elements are loaded with configuration data during programming, the memory elements are sometimes referred to as configuration memory, configuration RAM, or programmable memory elements.

[0040] Any suitable architecture can be used to organize the circuits of programmable integrated circuit 100. As one example, the logic of programmable integrated circuit 100 can be organized in a series of rows and columns of larger programmable logic regions, each of which contains a plurality of smaller logic regions.

[0041] The smaller regions can be, for example, regions of logic sometimes referred to as logic elements (LEs), each of which contains a lookup table, one or more registers, and programmable multiplexer circuits. The smaller regions can also be, for example, regions of logic sometimes referred to as adaptive logic modules (ALMs) or slices. Each logic region can include a pair of adders, a pair of associated registers, a shift register, and one or more lookup tables or other shared combinational logic (i.e., resources from a pair of LEs, sometimes referred to in this context as adaptive logic elements (ALEs)). The larger regions can be, for example, logic array blocks (LABs) or configurable logic blocks (CLBs) containing a plurality of logic elements or a plurality of ALMs or a plurality of slices.

[0042] During programming of the device, configuration data is loaded into programmable integrated circuit 100, which configures the programmable logic regions so that their logic resources perform the desired logic functions.

[0043] In Figure 2 One illustrative embodiment of a special-purpose processing block 200 that can be adapted for efficiently implementing mixed-precision floating-point arithmetic operations is shown in FIG. 1. In this logical representation, implementation details such as registers and some programmable routing features such as multiplexers and routing are omitted to simplify the discussion, which can allow routing of the outputs of certain structures near that component or directly out of the special-purpose processing block. In addition, some of the elements shown can be implemented more than once in actual embodiments. For example, multiplier 202 can actually represent two or more multipliers.

[0044] As shown, special-purpose processing block 200 can include input ports 271, 273, 275, 277, and 279, output port 280, chain-in port 262 (sometimes also referred to as a cascade-in port or a cascade input), chain-out port 263 (sometimes also referred to as a cascade-out port or a cascade output), multiplexers 230, 231, 232, and 235, multiplier stage 205, adder circuits 203 and 204, registers 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, and 223, and conversion function circuit 250. Multiplier stage 205 can include multiplier circuits 201 and 202.

[0045] The special-purpose processing block 200 can produce an output signal at an output port 280 and receive input signals at input ports 271, 273, 275, 277, and 279. If desired, the special-purpose processing block 200 can be arranged in a cascading chain with other special-purpose processing blocks (e.g., in a row or column) and receive additional input signals from an adjacent special-purpose processing block at a chain-in port 262 via a direct cascading connection and provide additional output signals to another adjacent special-purpose processing block at a chain-out port 263 via another direct cascading connection.

[0046] In some embodiments, the adder circuit 203 and the multiplier stage 205 with the multiplier circuits 201 and 202 can operate on floating-point numbers of a first floating-point precision (e.g., according to the IEEE 754 standard, half-precision, single-precision, double-precision, quadruple-precision, or octuple-precision), and the adder circuit 204 can operate on floating-point numbers of a second floating-point precision (e.g., according to the IEEE 754 standard, half-precision, single-precision, double-precision, quadruple-precision, or octuple-precision). If desired, the second floating-point precision can be different from the first floating-point precision.

[0047] As one example, the second floating-point precision can be a higher precision than the first floating-point precision. For example, according to the IEEE 754 standard, if the first floating-point precision is half-precision, the second floating-point precision can be single-precision, double-precision, quadruple-precision, or octuple-precision; if the first floating-point precision is single-precision, the second floating-point precision can be double-precision, quadruple-precision, or octuple-precision; if the first floating-point precision is double-precision, the second floating-point precision can be quadruple-precision or octuple-precision; or if the first floating-point precision is quadruple-precision, the second floating-point precision can be octuple-precision.

[0048] As another example, the second floating-point precision can be a lower precision than the first floating-point precision. For example, according to the IEEE 754 standard, if the first floating-point precision is octuple-precision, the second floating-point precision can be half-precision, single-precision, double-precision, or quadruple-precision; if the first floating-point precision is quadruple-precision, the second floating-point precision can be half-precision, single-precision, or double-precision; if the first floating-point precision is double-precision, the second floating-point precision can be half-precision or single-precision; or if the first floating-point precision is single-precision, the second floating-point precision can be half-precision.

[0049] In some embodiments, the conversion function circuit 250 can convert the output of the adder circuit 203 from the first floating-point precision to the second floating-point precision. For example, the output of the adder circuit 203 can be a half-precision floating-point number and the conversion function circuit can convert the sum of the products to a single-precision floating-point number. As another example, the output of the adder circuit 203 can be a double-precision floating-point number and the conversion function circuit 250 can convert the sum of the products to a single-precision floating-point number.

[0050] To convert a floating-point number from a first floating-point precision to a second floating-point precision that is higher than the first floating-point precision (which is sometimes also referred to as up-conversion), the conversion function circuit 250 can increase the number of bits of the mantissa and the number of bits of the exponent, and adjust the offset of the exponent accordingly. For example, to convert a half-precision floating-point number to a single-precision floating-point number, the conversion function circuit 250 can increase the size of the mantissa from 10 bits to 23 bits (e.g., by adding 13 zeros to the right of the least significant bit (LSB) position) and increase the size of the exponent from 5 bits to 8 bits (e.g., by adding 3 zeros to the left of the most significant bit (MSB) position). The conversion function circuit 250 can adjust the offset of the exponent by adding 112 to the half-precision floating-point exponent.

[0051] To convert a floating-point number from a first floating-point precision to a second floating-point precision that is lower than the first floating-point precision (which is sometimes also referred to as down-conversion), the conversion function circuit 250 can decrease the number of bits of the mantissa (e.g., by rounding), adjust the offset of the exponent accordingly, and decrease the number of bits of the exponent.

[0052] If desired, the conversion function circuit 250 can include special case conversions (e.g., a first floating-point precision number can be denormalized, zero, infinity, or not-a-number (NaN)). As one example, a denormalized first floating-point precision number can be converted to zero, which is sometimes also referred to as denormals-are-zero (DAZ). As another example, in down-conversion, a zero, denormalized number, or too-large exponent can be converted to zero, and an infinity or exponent overflow can be converted to infinity.

[0053] The configurable interconnect circuit in the special-purpose processing block 200 can route signals between the input ports 271, 273, 275, 277, and 279, the output port 280, the chain-in port 262, the chain-out port 263, the multiplier circuits 201 and 202, the adder circuits 203 and 204, the registers 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, and 223, and the conversion function circuit 250.

[0054] As shown, the configurable interconnect circuit can include multiplexers 230, 231, 232, and 235, as well as interconnects, which are sometimes also referred to as routing tracks. The configurable interconnect circuit can be used to bypass some of the components of the special-purpose processing block 200. For example, multiplexer 231 can select between the output of the transformation function circuit 250 and the output of the multiplier stage 205, thereby bypassing registers 218 and 219 and adder circuit 203. Similarly, multiplexer 235 can select between the output of register 223 and the output of adder circuit 203, thereby implementing a bypass path that bypasses the transformation function circuit 250, multiplexer 231, register 221, adder circuit 204, and register 223.

[0055] The configurable interconnect circuit can include additional multiplexers to increase the flexibility of connecting different components of the special-purpose processing block 200 and to allow additional bypass paths, if desired. For example, an additional multiplexer before registers 218 and 219 can implement a bypass path near the multiplier stage 205, an additional multiplexer after a register (e.g., register 218, 219, 220, etc.) can implement a bypass path near the respective register, etc.

[0056] Control signals can control the selections performed by multiplexers 230, 231, 232, and 235. The control signals can be generated by logic circuits that dynamically control the selections of the respective multiplexers and / or stored in storage circuits. The logic circuits and / or storage circuits can be located inside the special-purpose processing block 200. If desired, some or all of the logic circuits and / or storage circuits can be located outside the special-purpose processing block 200 and can provide the control signals to the respective multiplexers through additional input ports.

[0057] The control signals can be stored individually for each multiplexer or in groups for multiple multiplexers. The storage circuits can load the control signals during configuration or reconfiguration of the special-purpose processing block 200. In some embodiments, the storage circuits can be programmable memory elements of an integrated circuit (e.g., programmable integrated circuit 100). Figure 1 The control signals can be stored individually for each multiplexer or in groups for multiple multiplexers. The storage circuits can load the control signals during configuration or reconfiguration of the special-purpose processing block 200. In some embodiments, the storage circuits can be programmable memory elements of an integrated circuit (e.g., programmable integrated circuit 100).

[0058] Multiplexer 230 can select between routing the output of the transformation function circuit 250 and registers 220 and 223 to the cascade output 263. Multiplexer 231 can select between routing the output of the multiplier stage 205, the transformation function circuit 250, and register 220 to register 221. Multiplexer 232 can select between routing the output of register 220 and a signal from the cascade input 262 to register 222. Multiplexer 235 can select between routing the output of the transformation function circuit 250 and register 223 to the output port 280.

[0059] In Figure 2 In a logical representation of the special-purpose processing block 200, the special-purpose processing block 200 can perform a fixed-point addition, a floating-point addition, a fixed-point multiplication, a floating-point multiplication, a sum of two multiplications, with or without conversion to a second floating-point precision, and the latter followed by a subsequent addition, if needed, in a second floating-point precision, and so on.

[0060] Consider a scenario in which the special-purpose processing block 200 receives input signals A, B, C, D, and E at input ports 271, 273, 275, 277, and 279, respectively, and a chain-in signal CHAIN IN at a cascade input 262. Further consider that the input signals A, B, C, and D are signals encoding floating-point numbers in a first floating-point precision (e.g., half-precision, single-precision, double-precision, or quadruple-precision according to the IEEE 754 standard), and that the input signal E and the chain-in signal CHAIN IN are signals encoding floating-point numbers in a second floating-point precision that is higher than the first floating-point precision (e.g., single-precision if the first floating-point precision is half-precision, double-precision if the first floating-point precision is single-precision, quadruple-precision if the first floating-point precision is double-precision, or octuple-precision if the first floating-point precision is quadruple-precision, according to the IEEE 754 standard).

[0061] In this scenario, the multiplier stage 205 can compute the product of A and B (i.e., A*B) in the multiplier circuit 201 and the product of C and D (i.e., C*D) in the multiplier circuit 202. The products can be stored in registers 218 and 219, respectively, if needed. The adder circuit 203 can generate the sum of the products (i.e., A*B+C*D).

[0062] In some embodiments, the conversion function circuit 205 can convert the sum of the products from the first floating-point precision to the second floating-point precision. For example, the sum of the products can be a half-precision floating-point number and the conversion function circuit can convert the sum of the products to a single-precision floating-point number. As another example, the sum of the products can be a double-precision floating-point number and the conversion function circuit 250 can convert the sum of the products to a single-precision floating-point number.

[0063] The configurable interconnect circuit can select the output of the conversion function circuit 250 in the multiplexer 231 and the CHAIN IN signal at the cascade input 262 in the multiplexer 232, thereby routing the converted sum of the products from the output of the conversion function circuit 250 to the adder circuit 204 and the CHAIN IN signal from the cascade input 262 to the adder circuit 204.

[0064] If desired, adder circuit 204 can add the sum of products to the CHAIN IN signal to generate another sum signal. Multiplexer 235 of the configurable interconnect circuit can select between the sum of products from adder circuit 203 and the other sum signal from adder circuit 204. The configurable interconnect circuit can route the sum of products to output 280 by selecting the output of adder circuit 203 in multiplexer 235. Alternatively, the configurable interconnect circuit can route the other sum to output 280 by selecting the output of adder circuit 204 in multiplexer 235.

[0065] In certain embodiments, special-purpose processing block 200 can implement additional features. For example, special-purpose processing block 200 can include a path from an output of register 223 to an additional input of multiplexer 231 or to an additional input of multiplexer 232, thereby enabling implementation of an accumulation operation, if desired.

[0066] Based on the configuration of the configurable interconnect circuit, special-purpose processing block 200 can implement different arithmetic operations as described above. Figure 3 FIG. 2 is a diagram of two illustrative special-purpose processing blocks 200A and 200B arranged in a cascade chain and together implementing a recursive mode dot product operation according to some embodiments.

[0067] If desired, Figure 2 Special-purpose processing block 200 can implement each of special-purpose processing blocks 300A and 300B. In Figure 3 In the logical representation of FIG. 3, implementation details of special-purpose processing blocks 300A and 300B such as registers and some programmable routing features such as multiplexers are omitted to simplify the discussion.

[0068] As shown, both special-purpose processing blocks 300A and 300B can include inputs 371, 372, 375, and 377, input 380, transformation function circuit 350, multiplier circuits 301 and 302, and adder circuits 303 and 304. A cascade connection can couple the cascade output of special-purpose processing block 300B to the cascade input of special-purpose processing block 300A.

[0069] In some embodiments, multiplier circuits 301 and 302 and adder circuit 303 can operate on floating-point numbers of a first floating-point precision, adder circuit 304 can operate on floating-point numbers of a second floating-point precision, and transformation function circuit 350, which can operate in a similar manner as transformation function circuit 250 of Figure 2 FIG. 2) can be coupled to the output of adder circuit 303 to convert the output of adder circuit 303 from the first floating-point precision to the second floating-point precision.

[0070] Consider a scenario in which the special-purpose processing blocks 300A and 300B together generate a dot product of a first vector Y having tuples A, C, E, and G (i.e., Y = (A, C, E, G)T) with a second vector Z having tuples B, D, F, and H (i.e., Z = (B, D, F, H)T). Further consider that the tuples of the vectors Y and Z have a first floating-point precision (e.g., according to IEEE Standard 754, half-precision, single-precision, double-precision, or quad-precision).

[0071] In this scenario, at the input terminals 371, 375, 373, and 377, respectively, the special-purpose processing block 300A can receive two tuples from each of the vectors Y and Z (e.g., tuples A and C from the vector Y and tuples B and D from the vector Z), and the special-purpose processing block 300B can receive the other two tuples from each of the vectors Y and Z (e.g., tuples E and G from the vector Y and tuples F and H from the vector Z).

[0072] The multiplier circuits 301 and 302, the adder circuit 303, and the transform function circuit 350 of the special-purpose processing block 300B can generate a first partial result having a second floating-point precision based on the second quaternary reduction of the tuples of the vectors Y and Z received at the input terminals 371, 373, 375, and 377. The second floating-point precision has a higher precision than the first floating-point precision (e.g., according to IEEE Standard 754, single-precision, double-precision, quad-precision, octuple-precision). For example, in the special-purpose processing block 300B, the multiplier circuit 301 can generate the product E*F, the multiplier circuit 302 can generate the product G*H, and the adder circuit 303 can generate the sum E*F + G*H of the products. The transform function circuit 350 in the special-purpose processing block 300B can convert the sum E*F + G*H of the products from the first floating-point precision to the second floating-point precision as outlined above, thereby generating the first partial result.

[0073] Similarly, the multiplier circuits 301 and 302, the adder circuit 303, and the transform function circuit 350 of the special-purpose processing block 300A can generate a second partial result having the second floating-point precision based on the second quaternary reduction of the tuples of the vectors Y and Z received at the input terminals 371, 373, 375, and 377. For example, in the special-purpose processing block 300A, the multiplier circuit 301 can generate the product A*B, the multiplier circuit 302 can generate the product C*D, and the adder circuit 303 can generate the sum A*B + C*D of the products. The transform function circuit 350 in the special-purpose processing block 300A can convert the sum A*B + C*D of the products from the first floating-point precision to the second floating-point precision as outlined above, thereby generating the second partial result.

[0074] The configurable interconnect circuit in special-purpose processing block 300A and 300B can route the first partial result from the transformation function circuit 350 in special-purpose processing block 300B to the adder circuit 304 in the second special-purpose processing block 300A via the cascade connection and route the second partial result from the transformation function circuit 350 to the adder circuit 304 in special-purpose processing block 300A.

[0075] The adder circuit 304 of special-purpose processing block 300A can generate the dot product of vectors Y and Z (i.e., Y*Z = A*B+C*D+E*F+G*H) by performing a binary reduction (i.e., addition) of the first and second partial results and provide the dot product as signal J at the output 380 of special-purpose processing block 300A.

[0076] Figure 4 is a diagram of two illustrative special-purpose processing blocks arranged in a cascade chain and together implementing a first stage of a recursive mode dot product operation and accumulation operation in accordance with some embodiments.

[0077] If desired, Figure 2 The special-purpose processing block 200 of FIG. 2 can implement each of special-purpose processing blocks 400A and 400B. In Figure 4 In the logical representation of FIG. 4, implementation details (such as registers) and some programmable routing features (such as multiplexers) of special-purpose processing blocks 400A and 400B are omitted to simplify the discussion.

[0078] As shown, both special-purpose processing blocks 400A and 400B can include input terminals 471, 473, 475, and 477, output terminal 480, transformation function circuit 450, multiplier circuits 401 and 402, and adder circuits 403 and 404. Special-purpose processing block 400B can further include input terminal 479 and register 405 coupled between the output of adder circuit 404 and output terminal 480 and the input of adder circuit 404. The cascade connection can couple the cascade output of special-purpose processing block 400B to the cascade input of special-purpose processing block 400A.

[0079] Special-purpose processing blocks 400A and 400B can together implement a first stage of a recursive mode dot product operation and accumulation operation in accordance with some embodiments. Figure 3The dot product of vectors Y and Z described in the middle. If desired, the special-purpose processing block 400B can additionally implement an accumulation operation on the signal I received at input 479. For example, the signal I can encode a floating-point number of a different floating-point precision than the signals A, B, C, D, E, F, G, or H. The adder circuit 404 of the special-purpose processing block 400B can add the signal stored in register 405 (e.g., zero at reset) to the signal received at input 479. The register 405 can store the sum generated by the adder circuit 404 and the adder circuit 404 can add the stored sum to the signal received at input 479, thereby implementing an accumulation operation.

[0080] By using two special-purpose processing blocks 300A and 300B of Figure 3 as building blocks for adjacent special-purpose processing blocks, a recursive tree for generating the dot product of two vectors can be constructed. Figure 5 is a diagram of six illustrative special-purpose processing blocks arranged in a cascade chain and generating the dot product of two vectors of floating-point numbers according to some embodiments.

[0081] If desired, Figure 2 The special-purpose processing block 200 of Figure 5 In the logical representation of the special-purpose processing block 200, implementation details of the special-purpose processing blocks 500A, 500B, 500C, 500D, 500E, and 500F (such as registers) and some programmable routing features (such as multiplexers) are omitted to simplify the discussion.

[0082] As shown, each of the special-purpose processing blocks 500A-500F (i.e., 500A, 500B, 500C, 500D, 500E, and 500F) can include inputs 571, 573, 575, and 577, outputs 580, a conversion function circuit 550, multiplier circuits 501 and 502, and adder circuits 503 and 504. The special-purpose processing blocks 500B, 500C, 500D, and 500E can further include an input 579. Cascade connections can couple the cascade outputs of the special-purpose processing blocks 500F, 500E, 500D, 500C, and 500B to the cascade inputs of the special-purpose processing blocks 500E, 500D, 500C, 500B, and 500A, respectively.

[0083] Consider a scenario in which the specialized processing blocks 500A-500F together implement a dot product of a vector Y having elements A, C, E, G, I, K, M, O, Q, S, U, W (i.e., Y = (A, C, E, G, I, K, M, O, Q, S, U, W)T) with a vector Z having elements B, D, F, H, J, L, N, P, R, T, V, and X (i.e., Z = (B, D, F, H, J, L, N, P, R, T, V, X)T). Further consider that the elements of the vectors Y and Z have a first floating-point precision (e.g., according to IEEE Standard 754, half-precision, single-precision, double-precision, or quadruple-precision).

[0084] In this scenario, the specialized processing block 500A can receive at the inputs 571, 573, 575, and 577, two elements from each of the vectors Y and Z (e.g., elements A and C from the vector Y and elements B and D from the vector Z). Similarly, each of the specialized processing blocks 500B-500F can receive at the inputs 571, 573, 575, and 577, two elements from each of the vectors Y and Z (e.g., 500B receives elements E and G from the vector Y and elements F and H from the vector Z, 500C receives I, J, K, and L, 500D receives M, N, O, P, 500E receives Q, R, S, T, and 500F receives U, V, W, and X).

[0085] Each pair of specialized processing blocks can generate a partial result based on a quaternary reduction of the elements of the vectors Y and Z received at the inputs 571, 573, 575, and 577, followed by a binary reduction of the partial result generated in the current specialized processing block with the partial result generated in the adjacent specialized processing block, as implementing a first stage of a recursive pattern dot product operation as shown in Figure 3

[0086] For example, the multiplier circuits 501 and 502, the adder circuit 503, and the transformation function circuit 550 of the specialized processing block 500B can generate a sum-of-products E*F + G*H converted from the first floating-point precision to a second floating-point precision having a higher floating-point precision as outlined above, thereby generating one partial result. Similarly, the multiplier circuits 501 and 502, the adder circuit 503, and the transformation function circuit 550 of the specialized processing block 500A can generate a sum-of-products A*B + C*D converted from the first floating-point precision to the second floating-point precision, thereby generating another partial result.

[0087] The configurable interconnect circuit in the specialized processing blocks 500A and 500B can route the two partial results to the adder circuit 504 in the specialized processing block 500A. ​

[0088] Adder circuit 504 of specialized processing block 500A may generate a first-level result (i.e., A*B+C*D+E*F+G*H) of the dot product of vectors Y and Z by performing binary reduction (i.e., addition) of the two partial results (i.e., A*B+C*D and E*F+G*H) and provide the first-level result of the dot product at output 580 of specialized processing block 500. Similarly, specialized processing blocks 500C and 500D may generate a first-level result I*J+K*L+M*N+O*P and specialized processing blocks 500E and 500F may generate a first-level result Q*R+S*T+U*V+W*X.

[0089] By using the building blocks of adjacent dedicated processing blocks (i.e., 500A and 500B, 500C and 500D and 500E and 500F), a recursive tree can be constructed. For example, dedicated processing blocks 500A-500F can be connected via routing resources external to the dedicated processing blocks (e.g., using Figure 1 The vertical interconnect resources 140 and the horizontal interconnect resources 150 of the programmable integrated circuit 100 are used to route the first-level results of the dot product of vectors Y and Z (i.e., the outputs of the dedicated processing blocks 500A, 500C, and 500E) to the input terminals 579 of the dedicated processing blocks 500B, 500C, and 500E, respectively.

[0090] As shown, the configurable interconnect circuitry in specialized processing blocks 500B and 500C can route the first-stage result I*J+K*L+M*N+O*P from input 579 of specialized processing block 500C to adder circuit 504 of specialized processing block 500B via a cascade connection, and can route the first-stage result A*B+C*D+E*F+G*H from input 579 to adder circuit 504 of specialized processing block 500B. Dedicated processing block 500B can use adder 504 to generate a second-stage result (i.e., A*B+C*D+E*F+G*H+I*J+K*L+M*N+O*P) and provide the second-stage result at output 580.

[0091] This second stage result can be routed via routing resources external to specialized processing blocks 500A-500F to input 579 of specialized processing block 500D, and from there to adder 504 of specialized processing block 500D. Configurable interconnect circuitry in specialized processing blocks 500D and 500D can route the first stage result Q*R+S*T+U*V+W*X from input 579 of specialized processing block 500E to adder circuit 504 of specialized processing block 500D via a cascade connection. Specialized processing block 500D can use adder 504 to generate the final dot product result (i.e., A*B+C*D+E*F+G*H+I*J+K*L+M*N+O*P+Q*R+S*T+U*V+W*X) in the third stage and provide the final dot product at output 580.

[0092] If necessary, you can Figure 5 Register pipelining can be performed at any level of the recursion tree described in

[15] (e.g., to simplify routing and / or increase speed). Since the subsequent-stage adders after the first stage (i.e., adders 504 of dedicated processing blocks 500B and 500D) are completely independent of the first-stage adders (and completely independent of each other), the subsequent-stage adders can be placed in any of the dedicated processing blocks 500B, 500D, or 500F where adder 504 is not used in the first stage of the dot product calculation. This can be useful, for example, in later stages where there may be longer stage-to-stage lengths.

[0093] The adder circuit 504 of the dedicated processing block 500F may be omitted because the dot product of two vectors having N tuples in each vector requires N multiplier circuits and (N-1) adder circuits. Alternatively, the Nth adder circuit 504 may be used independently for other purposes.

[0094] Figure 6 is a diagram of four illustrative specialized processing blocks 600A-600D (ie, 600A, 600B, 600C, and 600D) arranged in a cascade chain and performing a recursive pattern dot product of two vectors of floating point numbers and accumulation of the results, in accordance with some embodiments.

[0095] If necessary, Figure 2 The dedicated processing block 200 may implement each of the dedicated processing blocks 600A-600D. Figure 6 In the logical representation of FIG, implementation details of the dedicated processing blocks 600A and 600D (such as registers) and some programmable routing features (such as multiplexers) are omitted to simplify the discussion.

[0096] As shown, each of the specialized processing blocks 600A-600D may include inputs 671, 673, 675, and 677, an output 680, a transformation function circuit 650, multiplier circuits 601 and 602, and adder circuits 603 and 604. Specialized processing blocks 600B, 600C, and 600D may further include an input 679, and specialized processing block 600D may include a register 605 that may implement an accumulator with adder circuit 604. Cascade connections may couple the cascade outputs of specialized processing blocks 600D, 600C, and 600B to the cascade inputs of specialized processing blocks 600C, 600B, and 600A, respectively.

[0097] As an example, the dedicated processing blocks 600A-600D may be implemented in Figure 5In other words, the dedicated processing blocks 600A-600D may generate a dot product Y*Z = A*B+C*D+E*F+G*H+I*J+K*L+M*N+O*P of a vector Y having tuples A, C, E, G, I, K, M, and O (i.e., Y = (A, C, E, G, I, K, M, O)^T) and a vector Z having tuples B, D, F, H, J, L, N, and P (i.e., Z = (B, D, F, H, J, L, N, P)^T), and provide the dot product at the output 680 of the dedicated processing block 600B.

[0098] If desired, the dot product can be routed to the input 679 of the dedicated processing block 600D via routing resources external to the dedicated processing blocks 600A-600D, and from there to the adder 604 of the dedicated processing block 600D. The adder circuit 604 of the dedicated processing block 600D can add the signal stored in the register 605 (e.g., zero upon reset) to the signal received at the input 679. The register 605 can store the sum generated by the adder circuit 604, and the adder circuit 604 can add the stored sum to the signal received at the input 679, thereby performing an accumulation operation of the dot product.

[0099] Figure 7 is an illustration of a flowchart showing illustrative operation of an integrated circuit for operating to generate a dot product of first and second vectors, in accordance with some embodiments.

[0100] During operation 710, the integrated circuit may utilize a first dedicated processing block to generate a first partial result of a first floating point precision. As an example, such as Figure 1 The programmable integrated circuit 100 may include Figure 3 and the dedicated processing block 300B may generate a sum of products E*F+G*H as a first partial result having a first floating point precision (eg, a single precision floating point format).

[0101] During operation 720, the integrated circuit may provide a first partial result at a cascade output of the first dedicated processing block. For example, Figure 3 The dedicated processing block 300B may provide a first partial result (ie the sum of products E*F+G*H) at the cascade output.

[0102] During operation 730, the integrated circuit may receive a first partial result from a cascade output of a first specialized processing block at a cascade input of a second specialized processing block via a cascade connection. Figure 3 The dedicated processing block 300A may receive the sum of products E*F+G*H from the dedicated processing block 300B at a cascade input via a cascade connection.

[0103] During operation 740, the integrated circuit may generate a second partial result having the first floating point precision based on the quaternary reduction of the two tuples having the second floating point precision from each of the first and second vectors in the second dedicated processing block. Figure 3 Dedicated processing block 300A may receive tuples A and C from vector Y and tuples B and D from vector Z. If desired, tuples A, B, C, and D may be in a second floating point precision (e.g., half-precision floating point format). Dedicated processing block 300A may use multiplier circuits 301 and 302 and adder circuit 303, followed by a conversion to the first floating point precision in cast function circuit 350, to generate a sum of products A*B+C*D as a second partial result in the first floating point precision (e.g., single-precision floating point format).

[0104] During operation 750, the integrated circuit may generate a dot product by performing a binary reduction of the first and second partial results in a second dedicated processing block. Figure 3 The adder circuit 304 in the dedicated processing block 300A can generate a dot product by adding the first partial product (i.e., E*F+G*H) and the first partial product (i.e., A*B+C*D), thereby generating a dot product of the vector Y having the tuples A, C, E, and G and the vector Z having the tuples B, D, F, and H.

[0105] A machine-readable medium may encode instructions for performing a method on an integrated circuit according to some embodiments (e.g., as provided by Figure 7 The method described herein includes instructions for configuring an integrated circuit to generate a dot product of a first and a second vector. A suitable computer or similar device can execute these instructions, thereby implementing the method in the integrated circuit. For example, a personal computer can be equipped with an interface (to which the integrated circuit can be connected), and the method can be programmed into the integrated circuit through the interface with the help of a suitable software tool and / or a user of the personal computer.

[0106] In some embodiments, the instructions for carrying out the method may be generated by other instructions encoded on the same or additional machine-readable medium. In other words, a first instruction set (e.g., a C language compiler or an electronic design automation (EDA) tool) executed on a computer or similar device may generate a second instruction set (e.g., assembly code or a series of bits for programming a configurable circuit), whereby the second instruction set is included in an integrated circuit (e.g., a microprocessor or a programmable integrated circuit device (e.g., a microprocessor)). Figure 1 A method is performed on a programmable integrated circuit 100).

[0107] A machine-readable medium can include any type of device or technology enabling storage of instructions and / or data including semiconductor memory devices (whether volatile or non-volatile, such as, for example, DRAM, SRAM, flash memory, and the like), magnetic storage devices, optical storage devices, or any combination thereof.

[0108] Figure 8 A cross-section of a magnetic data storage medium 800 is shown that can be encoded with machine-executable program code that can be executed by a system such as the aforementioned personal computer or other computer or similar device. The medium 800 can be a floppy disk or hard disk or magnetic tape having a suitable substrate 810 (which can be conventional) and a suitable coating 820 (which can be conventional) containing magnetic domains on one or both sides that can be changed magnetically in their polarization or orientation. Except in the case where the medium 800 is magnetic tape, the medium 800 can also have an opening for receiving the spindle of a disk drive or other data storage device.

[0109] The domains of the coating 820 of the medium 800 can be polarized or oriented to encode machine-executable program code in a manner that can be conventional for execution by a programmed system (such as a personal computer or other computer or similar system) having a socket or peripheral attachment into which an integrated circuit to be configured can be inserted for the purpose of configuring appropriate portions of the integrated circuit (including its special-purpose processing blocks, if any) in accordance with some embodiments.

[0110] Figure 9 A cross-section of an optical readable data storage medium 900 is shown that can be encoded with the aforementioned machine-executable program code to be executed by a system such as the aforementioned personal computer or other computer or similar device. The medium 900 can be a Blu-ray Disc (BD), a conventional compact disc (CD) read-only memory (ROM), or a digital versatile disc (DVD, sometimes also known as a digital video disc) read-only memory (ROM), or any rewritable medium such as a CD R, CD RW, DVD R, DVD RW, DVD+R, DVD+RW, or DVD-RAM, or an optical readable and magneto-optical rewritable magneto-optical disc. The medium 900 can have a suitable substrate 910 and a suitable coating 920 typically on one or both sides of the substrate 910.

[0111] In the case of a CD-based or DVD-based medium as is known, the coating 920 is reflective and is imprinted with a plurality of pits 930 arranged on one or more layers to encode a machine executable program. The arrangement of pits is read by reflecting laser light off the surface of the coating 920. A protective coating 940 can be provided on top of the coating 920.

[0112] In the case of a magneto-optical disk as is known, the coating 920 has no pits 930, but has a plurality of magnetic domains whose polarization or orientation can be changed magnetically when heated above a certain temperature, for example, by a laser. The orientation of the domains can be read by measuring the polarization of laser light reflected from the coating 920. The arrangement of domains can encode a program as described above.

[0113] The methods and apparatus described herein can be incorporated into any suitable circuit or system of circuits. For example, the methods and apparatus can be incorporated into many types of devices, such as microprocessors or other integrated circuits. Exemplary integrated circuits include programmable array logic (PAL), programmable logic arrays (PLA), field programmable logic arrays (FPGA), electrically programmable logic devices (EPLD), electrically erasable programmable logic devices (EEPLD), logic cell array (LCA), field programmable gate array (FPGA), coarse grain reconfigurable architecture (CGRA), digital signal processing (DSP) circuit, application specific standard products (ASSP), application specific integrated circuits (ASIC), just to name a few.

[0114] The integrated circuits described herein can be part of a data processing system, which includes one or more of the following components: a processor; a memory; I / O circuitry and peripherals. The data processing system can be used in a variety of applications such as computer networking, data networking, instrumentation, video processing, digital signal processing, or any suitable other application in which the advantages of circuits that efficiently perform mixed-precision floating-point arithmetic operations are desired.

[0115] The integrated circuit can be configured to perform a variety of different logical functions. For example, the integrated circuit can be configured as a processor or controller that works in cooperation with a system processor. The integrated circuit can also be used as an arbiter for arbitrating access to shared resources in a data processing system. In yet another example, the integrated circuit can be configured as an interface between a processor and one of the other components in a system. In one embodiment, the integrated circuit can be one of a family of devices owned by the assignee.

[0116] Although the method operations were described in a particular order, it should be understood that other housing can be performed in between operations, described operations can be adjusted so that they occur at slightly different times, or can be distributed in a system which allows the occurrence of the processing operations at various intervals associated with the processing. The various operations can be carried out in any order, depending on the implementation desired.

[0117] The foregoing merely illustrates the principles of the embodiments and various modifications can be made by those skilled in the art without departing from the scope and spirit of the embodiments disclosed herein. The embodiments described hereinabove in the context of particular embodiments are not meant to be limiting, but merely illustrative, and the scope of the embodiments will be determined from the claims.

[0118] The following examples relate to further embodiments.

[0119] Example 1 is an integrated circuit that generates a dot product of first and second vectors and includes: a first special processing block that provides a first partial result of a first floating point precision; and a second special processing block that receives the first partial result from the first special processing block via a cascaded connection and includes: a first floating point arithmetic operator circuit that generates a second partial result of a first floating point precision based on a quaternary reduction of two tuples from each of the first and second vectors; and a second floating point arithmetic operator circuit that generates the dot product by performing a binary reduction of the first and second partial results.

[0120] Example 2 includes the subject matter of Example 1, wherein the first floating point arithmetic operator circuit further includes: a first multiplier circuit that generates a first product based on a first tuple of the two tuples from the first vector and a first tuple of the two tuples from the second vector, wherein the first product is of the second floating point precision; and a second multiplier circuit that generates a second product based on a second tuple of the two tuples from the first vector and a second tuple of the two tuples from the second vector, wherein the second product is of the second floating point precision.

[0121] Example 3 includes the subject matter of Example 2, wherein the first floating point arithmetic operator circuit further includes an adder circuit that generates a sum of the first product and the second product, wherein the sum is of the second floating point precision.

[0122] Example 4 includes the subject matter of Example 3, wherein the first floating point arithmetic operator circuit further includes a conversion function circuit that receives the sum from the adder circuit and generates the second partial result by converting the sum from the second floating point precision to the first floating point precision.

[0123] Example 5 includes the subject matter of Example 4, wherein the conversion function circuit increases a mantissa size of the sum from the second floating point precision to the first floating point precision.

[0124] Example 6 includes the subject matter of any one of Examples 4 or 5, wherein the transition function circuit adjusts the offset of the exponent of the sum from the offset of the second floating-point precision to the offset of the second floating-point precision.

[0125] Example 7 includes the subject matter of any one of Examples 4-6, wherein the second specialized processing block further includes an output port coupled to the second floating-point arithmetic operator circuit, and a bypass path between the adder circuit and the output port, wherein the bypass path bypasses the transition function circuit and the second floating-point arithmetic operator circuit.

[0126] Example 8 includes the subject matter of any one of Examples 1-7, wherein the second floating-point arithmetic operator circuit further includes an adder circuit that generates the dot product by adding the first and second partial results.

[0127] Example 9 is a method for operating an integrated circuit that generates a dot product of first and second vectors, comprising generating, with a first specialized processing block, a first partial result of a first floating-point precision; providing the first partial result at a cascaded output of the first specialized processing block; receiving the first partial result from the cascaded output of the first specialized processing block at a cascaded input of a second specialized processing block via a cascaded connection; generating a second partial result of the first floating-point precision based on a quaternary reduction of two tuples of the second floating-point precision from each of the first and second vectors in the second specialized processing block; and generating the dot product by performing a binary reduction of the first and second partial results in the second specialized processing block.

[0128] Example 10 includes the subject matter of Example 9, wherein generating the second partial result further comprises: using a first multiplier circuit to generate a first product based on a first tuple of the two tuples from the first vector and a first tuple of the two tuples from the second vector, wherein the first product is of the second floating-point precision; and using a second multiplier circuit to generate a second product based on a second tuple of the two tuples from the first vector and a second tuple of the two tuples from the second vector, wherein the second product is of the second floating-point precision.

[0129] Example 11 includes the subject matter of Example 10, further comprising using an adder circuit to generate a sum of the first product and the second product, wherein the sum is of the second floating-point precision.

[0130] Example 12 includes the subject matter of Example 11, further comprising using a transition function circuit that receives the sum from the adder circuit and generates the second partial result by converting the sum from the second floating-point precision to the first floating-point precision.

[0131] Example 13 includes the subject matter of Example 12, further comprising using the transition function circuit to increase a size of an exponent of the sum from the second floating-point precision to the first floating-point precision.

[0132] Example 14 includes the subject matter of any one of Examples 12 or 13, further including adjusting the offset of the exponent of the sum from the offset of the second floating-point precision to the offset of the second floating-point precision with the transformation function circuit.

[0133] Example 15 includes the subject matter of any one of Examples 12-14, further including bypassing the transformation function circuit on a bypass path that couples the adder circuit to an output port of the second special-purpose processing block.

[0134] Example 16 is a non-transitory machine-readable storage medium encoded with instructions for configuring an integrated circuit device to generate a dot product of first and second vectors, where the integrated circuit device includes first and second special-purpose processing blocks coupled by a cascade connection, where each of the first and second special-purpose processing blocks includes first and second floating-point arithmetic operator circuits and a configurable interconnect circuit, the instructions comprising: instructions to configure the first floating-point arithmetic operator circuit in the first special-purpose processing block to generate a first partial result having a first floating-point precision based on a first biquad of a first two tuples having a second floating-point precision from each of the first and second vectors; instructions to configure the configurable interconnect circuit in the first and second special-purpose processing blocks to route the first partial result from the first floating-point arithmetic operator circuit in the first special-purpose processing block to the second arithmetic operator circuit in the second special-purpose processing block via the cascade connection; instructions to configure the first floating-point arithmetic operator circuit in the second special-purpose processing block to generate a second partial result having the first floating-point precision based on a second biquad of a second two tuples having the second floating-point precision from each of the first and second vectors, and instructions to configure the second floating-point arithmetic operator circuit in the second special-purpose processing block to generate the dot product by performing a binary reduction of the first and second partial results.

[0135] Example 17 includes the subject matter of Example 16, further including instructions to generate the instructions of Example 16.

[0136] Example 18 includes the subject matter of any one of Examples 16 or 17, where the instructions to configure the first floating-point arithmetic operator circuit in the first special-purpose processing block further include: instructions to configure a first multiplier circuit to generate a first product based on a first tuple of the first two tuples from the first vector and a first tuple of the first two tuples from the second vector, where the first product has the second floating-point precision; and instructions to configure a second multiplier circuit to generate a second product based on a second tuple of the first two tuples from the first vector and a second tuple of the first two tuples from the second vector, where the second product has the second floating-point precision.

[0137] Example 19 includes the subject matter of Example 18, wherein the instructions to configure the first floating-point arithmetic operator circuit in the first special-purpose processing block further comprise instructions to configure the adder circuit to generate a sum number of the first product and the second product, wherein the sum number has the second floating-point precision.

[0138] Example 20 includes the subject matter of Example 19, wherein the instructions to configure the first floating-point arithmetic operator circuit in the first special-purpose processing block further comprise instructions to configure the conversion function circuit to generate the second partial result by converting the sum number from the second floating-point precision to the first floating-point precision.

[0139] Example 21 includes the subject matter of Example 20, further comprising instructions to increase a size of a significand of the sum number from the second floating-point precision to the first floating-point precision.

[0140] Example 22 includes the subject matter of any of Examples 20 or 21, further comprising instructions to adjust an offset of the significand of the sum number from an offset of the second floating-point precision to an offset of the first floating-point precision.

[0141] Example 23 includes the subject matter of Example 19, wherein the instructions to configure the second floating-point arithmetic operator circuit in the second special-purpose processing block to generate the dot product by performing a binary reduction of the first and second partial results further comprise instructions to add the first and second partial results.

[0142] Example 24 is an integrated circuit to generate a dot product of first and second vectors, comprising a first special-purpose processing block to provide a first partial result of a first floating-point precision; and a second special-purpose processing block to receive the first partial result from the first special-purpose processing block via a cascaded connection, and comprising a first means to generate a second partial result of the first floating-point precision based on a quaternary reduction of two tuples of the second floating-point precision from each of the first and second vectors, and a second means to generate the dot product by performing a binary reduction of the first and second partial results.

[0143] Example 25 includes the subject matter of Example 24, further comprising a storage circuit to store at least one tuple of the first vector.

[0144] Example 26 includes the subject matter of Example 25, wherein the storage circuit is selected from the group consisting of a first-in-first-out circuit, a last-in-first-out circuit, a serial-in-parallel-out shift register circuit, a random access memory circuit, a read-only memory circuit, a content-addressable memory circuit, and a register file.

[0145] Example 27 includes the subject matter of any of Examples 24 or 25, further comprising a configurable interconnect circuit comprising an interconnect resource to route the first and second vectors to the first and second special-purpose processing blocks.

[0146] Example 28 includes the subject matter of Example 27, wherein the interconnect resources external to the first and second specialized processing blocks further comprise vertical interconnect resources and horizontal interconnect resources.

[0147] Example 29 includes the subject matter of Example 28, further comprising a plurality of conductive lines.

[0148] Example 30 includes the subject matter of Example 29, further comprising a programmable connection between a first conductive line of the plurality of conductive lines and a second conductive line of the plurality of conductive lines.

[0149] Example 31 includes the subject matter of any of Examples 28-30, wherein the vertical and horizontal interconnect resources route signals on the integrated circuit.

[0150] Example 32 includes the subject matter of Example 27, wherein the configurable interconnect circuit further comprises a plurality of multiplexers.

[0151] Example 33 includes the subject matter of Example 32, further comprising a multiplexer of the plurality of multiplexers that selects between a first output of the transformation function circuit and a second output of the multiplier stage.

[0152] Example 34 includes the subject matter of any of Examples 24, 25, or 27, further comprising a programmable logic region.

[0153] Example 35 includes the subject matter of Example 34, wherein the programmable logic region further comprises a plurality of logic blocks selected from a group consisting of a logic array block and a configurable logic block.

[0154] Example 36 includes the subject matter of Example 35, wherein at least one logic block of the plurality of logic blocks further comprises a plurality of logic block components.

[0155] Example 37 includes the subject matter of Example 36, wherein at least one logic block component of the plurality of logic block components is selected from a group consisting of a lookup table circuit, a register, a slice, an additional adder, and a shift register.

[0156] The embodiments described above are presented for purposes of illustration and description only and not limitation. The present application is limited only by the appended claims.

Claims

1. An integrated circuit for generating a dot product of a first and a second vector, comprising: a first dedicated processing block that provides a first partial result at a first floating point precision; as well as a second dedicated processing block receiving the first partial result from the first dedicated processing block via a cascade connection and comprising: a first floating-point arithmetic operator circuit that generates a second partial result having a first floating-point precision based on a quaternary reduction of two tuples having a second floating-point precision from each of the first and second vectors; and a second floating-point arithmetic operator circuit that generates a dot product by performing a binary reduction of the first and second partial results, wherein the first floating-point arithmetic operator circuit further comprises: a first multiplier circuit that generates a first product based on a first tuple from the two tuples of the first vector and a first tuple from the two tuples of the second vector, wherein the first product has a second floating point precision; and a second multiplier circuit that generates a second product based on a second tuple from the two tuples of the first vector and a second tuple from the two tuples of the second vector, wherein the second product has a second floating point precision, wherein the first floating point arithmetic operator circuit further comprises: an adder circuit that generates a sum of the first product and the second product, wherein the sum has a second floating point precision, wherein the first floating point arithmetic operator circuit further comprises: A transformation function circuit receives the sum from the adder circuit and generates a second partial result by converting the sum from the second floating-point precision to the first floating-point precision, wherein the transformation function circuit increases the exponent size of the sum from the second floating-point precision to the first floating-point precision, and wherein the transformation function circuit adjusts the offset of the exponent of the sum from the offset of the second floating-point precision to the offset of the first floating-point precision.

2. The integrated circuit of claim 1 , wherein the second dedicated processing block further comprises: coupled to an output port of a second floating-point arithmetic operator circuit; as well as A bypass path is provided between the adder circuit and the output port, wherein the bypass path bypasses the transformation function circuit and the second floating-point arithmetic operator circuit.

3. The integrated circuit of any one of claims 1-2, wherein the second floating-point arithmetic operator circuit further comprises: An adder circuit that generates a dot product by adding the first and second partial results.

4. The integrated circuit of claim 1 , further comprising: Storage circuit.

5. The integrated circuit of claim 4, wherein the storage circuit is selected from the group consisting of a first-in-first-out circuit, a last-in-first-out circuit, a serial-in-parallel-out shift register circuit, a random access memory circuit, a read-only memory circuit, a content addressable memory circuit, and a register file.

6. The integrated circuit of claim 1, further comprising a configurable interconnect circuit comprising interconnect resources.

7. The integrated circuit of claim 6 , wherein the interconnect resources external to the first and second dedicated processing blocks further comprise: vertically interconnected resources; as well as Horizontally interconnect resources.

8. The integrated circuit of claim 7, further comprising: Multiple conductive threads.

9. The integrated circuit of claim 8, further comprising: A programmable connection is provided between a first conductive line of the plurality of conductive lines and a second conductive line of the plurality of conductive lines.

10. The integrated circuit of any one of claims 7-9, wherein vertical and horizontal interconnect resources route signals on the integrated circuit.

11. The integrated circuit of claim 6, wherein the configurable interconnect circuit further comprises: Multiple multiplexers.

12. The integrated circuit of any one of claims 1, 4 or 6, further comprising: Programmable logic area.

13. A method for operating an integrated circuit for generating a dot product of first and second vectors, comprising: generating a first partial result of a first floating-point precision using a first dedicated processing block; providing a first partial result at a cascade output of the first dedicated processing block; receiving a first partial result from a cascade output of a first dedicated processing block at a cascade input of a second dedicated processing block via a cascade connection; generating a second partial result having the first floating point precision based on a quaternary reduction of two tuples having the second floating point precision from each of the first and second vectors in a second dedicated processing block; as well as Generating a dot product by performing a binary reduction of the first and second partial results in a second dedicated processing block, wherein generating the second partial result further comprises: generating a first product using a first multiplier circuit based on a first tuple from the two tuples of the first vector and a first tuple from the two tuples of the second vector, wherein the first product has a second floating point precision; and generating a second product based on a second tuple from the two tuples of the first vector and a second tuple from the two tuples of the second vector using a second multiplier circuit, wherein the second product has a second floating point precision, further comprising: generating a sum of the first product and the second product using an adder circuit, wherein the sum has a second floating point precision; using a conversion function circuit that receives the sum from the adder circuit and generates a second partial result by converting the sum from the second floating point precision to the first floating point precision; Using a transformation function circuit, the exponent size of the sum is increased from the second floating point precision to the first floating point precision; The shift function circuit is used to adjust the offset of the exponent of the sum from the offset of the second floating point precision to the offset of the first floating point precision.

14. The method according to claim 13, further comprising: The transformation function circuit is bypassed in a bypass path coupling the adder circuit to the output port of the second dedicated processing block.

15. A non-transitory machine-readable storage medium comprising code that, when executed, causes a machine to perform the method of any one of claims 13-14.

16. An apparatus for operating an integrated circuit for generating a dot product of first and second vectors, comprising: means for generating a first partial result of a first floating point precision using a first dedicated processing block; means for providing a first partial result at a cascade output of the first dedicated processing block; means for receiving a first partial result from a cascade output of a first dedicated processing block at a cascade input of a second dedicated processing block via a cascade connection; means for generating a second partial result having a first floating point precision based on a quaternary reduce of two tuples having a second floating point precision from each of the first and second vectors in a second dedicated processing block; as well as means for generating a dot product by performing a binary reduction of the first and second partial results in a second dedicated processing block, wherein the means for generating the second partial result further comprises: means for generating a first product using a first multiplier circuit based on a first tuple from the two tuples of the first vector and a first tuple from the two tuples of the second vector, wherein the first product has a second floating point precision; and means for generating, using a second multiplier circuit, a second product based on a second tuple from the two tuples of the first vector and a second tuple from the two tuples of the second vector, wherein the second product has a second floating point precision, further comprising: means for generating a sum of a first product and a second product using an adder circuit, wherein the sum has a second floating point precision means for using a conversion function circuit that receives the sum from the adder circuit and generates a second partial result by converting the sum from the second floating point precision to the first floating point precision; means for increasing the exponent size of the sum from the second floating point precision to the first floating point precision using a transformation function circuit; The device is configured to adjust the offset of the exponent of the sum from the offset of the second floating point precision to the offset of the first floating point precision by using a transformation function circuit.

17. The apparatus according to claim 16, further comprising: Means for bypassing the transformation function circuit in a bypass path coupling the adder circuit to the output port of the second dedicated processing block.

18. A computer program product comprising instructions which, when executed by a processor, cause the processor to perform the method according to any one of claims 13 to 14.

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