Technique for remapping pending bit array read requests

Abstract

A technique for remapping pending bit array read requests includes a computing device including a plurality of data storage devices, a request manager, and a remapping manager. The request manager is used to receive a request to read PBA data from a main PBA mapped to a plurality of sub-pending bit arrays (PBAs). Each sub-PBA is associated with a different data storage device in the data storage device. The request includes attribute data indicating an address in the main PBA from which the PBA data is to be read. The remapping manager is used to determine one or more bit addresses from the attribute data, compare the one or more bit addresses with the addresses of the sub-PBAs in the main PBA to determine a set of sub-PBAs to be read, and map the one or more bit addresses to the determined set of sub-PBAs to be read.

Description

Background Art

[0001] Non-volatile memory remapping (NVM-r) typically supports remapping of up to three peripheral component interconnect express (PCIe) data storage devices, such as solid state devices. If message-signaled interrupts, such as in the MSI-X manner, are supported by the data storage device, the MSI-X table and pending bit array (PBA) structures of the advanced host controller interface (AHCI) controller (e.g., serial advanced technology attachment (SATA) controller) connected to the data storage device, as well as the MSI-X table and pending bit array structures of the data storage device itself, are presented to the software executed by the computing device as a single "master" MSI-X table and a single "master" PBA. The MSI-X table typically embodies as a set of entries, each entry called a vector, indicating the structure of the message that can be sent to the device to cause an interrupt. Each bit in the PBA typically indicates whether the message at the corresponding location in the MSI-X table is pending (e.g., will be sent to the corresponding device to cause an interrupt). Brief Description of the Drawings

[0002] The concepts described herein are illustrated in the drawings by way of example and not by way of limitation. For the sake of simplicity and clarity of illustration, the elements illustrated in the figures are not necessarily drawn to scale. Where considered appropriate, reference labels have been repeated between the figures to indicate corresponding or analogous elements.

[0003] Figure 1 is a simplified block diagram of at least one embodiment of a computing device that provides access to a pending bit array for remapping;

[0004] Figure 2 is Figure 1 a simplified block diagram of at least one embodiment of a data storage device included in a computing device;

[0005] Figure 3 is Figure 1 a simplified block diagram of at least one embodiment of an input / output system of a computing device;

[0006] Figure 4 is an environment that can be established by Figure 1 a simplified block diagram of at least one embodiment of a computing device;

[0007] Figures 5 - 8 is an environment that can be established by Figure 1Simplified flowchart of at least one embodiment of a method for remapping access to pending bit array data performed by a computing device;

[0008] Figure 9 Pseudocode for determining a start bit address and an end bit address from attribute data included in a read request;

[0009] Figure 10 Simplified block diagram of the arrangement of sub-pending bit arrays within a main pending bit array address space and the corresponding conditions indicating various sets of sub-pending bit arrays that can be associated with a read request;

[0010] Figure 11 List of sets of pseudocode that can be used to determine translated start and end addresses for reading pending bit array data;

[0011] Figure 12 Simplified block diagram of the relationship between a main pending bit array and multiple sub-pending bit arrays;

[0012] Figure 13 Simplified block diagram for forcing data to zero beyond the last byte of sub-pending bit array data;

[0013] Figure 14 Simplified block diagram for merging split data for each of multiple sets of sub-pending bit array data;

[0014] Figure 15 Simplified block diagram for shifting sub-pending bit array data by a number of bytes corresponding to the starting position of the sub-pending bit array data within the address space of the main pending bit array;

[0015] Figure 16 Simplified block diagram for shifting sub-pending bit array data by a number of bits;

[0016] Figure 17 Simplified block diagram for selecting a double word or a quad word for reading sub-pending bit array data according to the read request length;

[0017] Figure 18 Simplified block diagram for shifting sub-pending bit array data to match a corresponding start bit in the main pending bit array; and

[0018] Figure 19 Simplified block diagram for masking sub-pending bit array data beyond the last bit. DETAILED DESCRIPTION

[0019] While the concepts of the present disclosure are susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and will be described in detail herein. It should be understood, however, that the intention is not to limit the concepts of the present disclosure to the particular forms disclosed, but on the contrary, to cover all modifications, equivalents, and alternatives consistent with the present disclosure and the appended claims.

[0020] References in this specification to "one embodiment", "an embodiment", "an illustrative embodiment", etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may or may not include that particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Additionally, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is considered within the knowledge of those skilled in the art to implement such feature, structure, or characteristic in connection with other embodiments, whether or not explicitly described. Additionally, it should be appreciated that items included in a list in the form of "at least one of A, B, and C" may mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C). Similarly, items listed in the form of "at least one of A, B, or C" may mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C).

[0021] In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried by or stored on a transient or non-transitory machine-readable (e.g., computer-readable) storage medium, which may be read and executed by one or more processors. A machine-readable storage medium may embody any storage device, mechanism, or other physical structure for storing or transmitting information in a form readable by a machine (e.g., volatile or non-volatile memory, optical disc or other media device).

[0022] In the drawings, some structural or method features are shown in a specific arrangement and / or order. However, it should be appreciated that such specific arrangement and / or order may not be necessary. Rather, in some embodiments, such features may be arranged in a different manner and / or order than shown in the illustrative figures. Additionally, the inclusion of a structural or method feature in a particular figure does not imply that such feature is required in all embodiments, and in some embodiments may not be included, or may be combined with other features.

[0023] Now refer to Figure 1, The illustrative computing device 100 for remapping access to a pending bit array (PBA) can be embodied as any type of computing device capable of performing the functions described herein. For example, in some embodiments, the computing device 100 can be embodied as, but not limited to, a computer, a server computer, a laptop computer, a notebook computer, a tablet computer, a smartphone, a consumer electronic device, a smart appliance, and / or any other computing device capable of performing functions to provide remapping of read requests to a main PBA to one or more sub-PBAs associated with a (one or more) corresponding data storage device. As Figure 1 shown, the illustrative computing device 100 includes a processor 102, a main memory 104, an input / output subsystem 106, and a data storage subsystem 108 including a set of data storage devices 110, the set of data storage devices 110 including data storage devices 112, 114, 116. Of course, in other embodiments, the computing device 100 can include other or additional components, such as those typically found in a computer (e.g., a communication subsystem, a display, peripheral devices, etc.). Additionally, in some embodiments, one or more of the illustrative components can be incorporated into another component or otherwise be part of another component. For example, in some embodiments, the main memory 104 or a portion thereof can be incorporated into the processor 102.

[0024] In a typical system, the size of the PBA for each of the data storage devices is fixed (e.g., non-programmable), as providing such a feature may cause misalignment of the sub-PBAs (e.g., the PBAs associated with each data storage device) in the main PBA structure, potentially resulting in data access errors. However, in an illustrative embodiment, the computing device 100 enables programming of the size of the sub-PBAs in the main PBA presented to software executed by the processor 102. Thus, the resulting sub-PBAs may not be aligned to any byte, dword, or quadword boundary. In an illustrative embodiment, the computing device 100 maps a read request that includes attribute data indicating a section (e.g., an address and a length) of the main PBA to be read, converts the attribute data into one or more bit addresses (e.g., a start bit address and an end bit address), determines which of the sub-PBAs to read from the bit addresses, and issues a corresponding request to the data storage device 110 (e.g., from one cycle router of the I / O subsystem 106 associated with the SATA controller to another cycle router of the I / O subsystem 106 associated with the data storage device 110) to read from the corresponding PBA. Additionally, in operation, the computing device 100 may receive PBA data from a sub-PBA (e.g., the PBA of the data storage device 110 associated with the original read request) and merge the received PBA data back into the main PBA.

[0025] The processor 102 may be embodied as any type of processing device capable of performing the functions described herein. For example, the processor 102 may be embodied as a single or multi-core processor, microcontroller, or other processor or processing / control circuitry having one or more processor cores. Similarly, the main memory 104 may be embodied as any type of volatile or non-volatile memory or data storage capable of performing the functions described herein. In operation, the main memory 104 may store various data and software used during operation of the computing device 100, such as main PBA data, sub-PBA data, remapping data, MSI-X table data, operating system, applications, programs, libraries, and drivers. The main memory 104 is communicatively coupled to the processor 102 via the I / O subsystem 106. Of course, in other embodiments (e.g., those in which the processor 102 includes a memory controller), the main memory 104 may be directly communicatively coupled to the processor 102. In an illustrative embodiment, the main memory 104 is accessible via direct memory access (DMA) to enable devices (such as the data storage device 110) to read from and write to the main memory 104 without relying on the processor 102 to act as an intermediary.

[0026] The I / O subsystem 106 can be embodied as circuitry and / or components that facilitate input / output operations with the processor 102, main memory 104, data storage subsystem 108, and other components of the computing device 100. For example, the I / O subsystem 106 can be embodied as or otherwise include a memory controller hub, an input / output control center, a firmware device, a communication link (i.e., a point-to-point link, a bus link, a wire, a cable, an optical waveguide, a printed circuit board trace, etc.), and / or other components and subsystems to facilitate input / output operations. In some embodiments, the I / O subsystem 106 can form part of a system-on-chip (SoC) and can be incorporated, along with the processor 102, main memory 104, and other components of the computing device 100, on a single integrated circuit chip.

[0027] The data storage subsystem 108 can be embodied as any type of device configured for short-term or long-term data storage, such as, for example, memory devices and circuits, solid state drives, memory cards, hard disk drives, or other data storage devices. In an illustrative embodiment, the data storage subsystem 108 includes the set of data storage devices 110, which includes data storage devices 112, 114, and 116, which are embodied as solid state drives in the illustrative embodiment and are capable of responding to interrupts caused by memory writes to the main memory 104 according to the MSI-X or a similar in-band interrupt generation scheme. However, in other embodiments, the data storage device 114 can be embodied as or include any other memory device capable of performing the functions described herein. Additionally, although the data storage devices 110 are shown in Figure 1 , it should be understood that in other embodiments, the data storage subsystem 108 can include a different number of data storage devices 110. Reference Figure 2 describes the data storage devices 110 in more detail.

[0028] The computing device 100 can additionally include a remapping logic unit 124, which can be embodied as any dedicated device or circuit capable of efficiently remapping data accesses from the main PBA to various sub-PBAs of the data storage devices 110 and merging the data received from the sub-PBAs back into the main PBA. The remapping logic unit 124 can be included in the I / O subsystem 106 and / or the processor 102.

[0029] The computing device 100 can also include a communication subsystem 118, which can be embodied as one or more devices and / or circuits capable of enabling communication with one or more other computing devices. The communication subsystem 118 can be configured to communicate with other computing devices using any suitable communication protocol, including, for example, wireless data communication protocols, cellular communication protocols, and / or wired communication protocols.

[0030] Additionally or alternatively, computing device 100 may include a display 120. The display 120 may be embodied as or otherwise utilize any suitable display technology, including for example, a liquid crystal display (LCD), a light emitting diode (LED) display, a cathode ray tube (CRT) display, a plasma display, and / or other displays usable in a computing device. The display may include a touch screen sensor that uses any suitable touch screen input technology to detect a user's tactile selection of information displayed on the display, including but not limited to, a resistive touch screen sensor, a capacitive touch screen sensor, a surface acoustic wave (SAW) touch screen sensor, an infrared touch screen sensor, an optical imaging touch screen sensor, an acoustic touch screen sensor, and / or other types of touch screen sensors. Additionally or alternatively, computing device 100 may include one or more peripheral devices 122. Such peripheral devices 122 may include any type of peripheral device commonly found in a computing device, such as speakers, a mouse, a keyboard, and / or other input / output devices, interface devices, and / or other peripheral devices.

[0031] Now referring to Figure 2 , in the illustrative embodiment, each data storage device 110 includes a data storage controller 202 and a memory 214, and the memory illustratively includes a non-volatile memory 216 and a volatile memory 218. The local memory 206 and / or the memory 214 may store an MSI-X table, which may be embodied as any data indicating messages that may be sent to the data storage device 110 via message signal interrupts (e.g., by writing to the main memory 104), as well as a pending bit array (PBA) indicating the status (e.g., pending or non-pending) of the possible messages represented in the MSI-X table.

[0032] As discussed in more detail below, during use, the data storage controller 202 is configured to respond to messages (such as messages signaled by interrupts (e.g., MSI-X messages)) to read and / or write data to a memory 214 (e.g., non-volatile memory 216) and to provide data indicative of the status of the messages (e.g., pending bit array data). In an illustrative embodiment, the data storage controller 202 includes a processor or processing circuit 204, a local memory 206, a host interface 208, a buffer 210, and memory control logic (also referred to herein as a “memory controller”) 212. The memory controller 212 may be in the same die or integrated circuit as the processor 204 or memories 206, 214, or in a die or integrated circuit separate from those of the processor 204 and memories 206, 214. In some cases, the processor 204, memory controller 212, and memories 206, 214 may be implemented in a single die or integrated circuit. Of course, in other embodiments, the data storage controller 202 may include additional devices, circuits, and / or components commonly found in a drive controller of a solid state drive.

[0033] The processor 204 may be embodied as any type of processor capable of performing the functions described herein. For example, the processor 204 may be embodied as a single or multi-core processor, a digital signal processor, a microcontroller, or other processor or processing / control circuit. Similarly, the local memory 206 may be embodied as any type of volatile and / or non-volatile memory or data storage capable of performing the functions described herein. In an illustrative embodiment, the local memory 206 stores firmware and / or other instructions executable by the processor 204 to perform the functions of the data storage controller 202. In some embodiments, the processor 204 and local memory 206 may form part of a SoC and may be incorporated onto a single integrated circuit chip along with other components of the data storage controller 202.

[0034] The host interface 208 may also be embodied as any type of hardware processor, processing circuitry, input / output circuitry, and / or a collection of components capable of facilitating communication between the data storage device 110 and a host device or service (e.g., a host driver or application executed by the processor 102 of the computing device 100). That is, the host interface 208 embodies or establishes an interface for accessing data stored on the data storage device 110 (e.g., stored in the memory 214). To do so, the host interface 208 may be configured to utilize any suitable communication protocol and / or technology to facilitate communication with the data storage device 110 depending on the type of the data storage device. For example, in some embodiments, the host interface 208 may be configured to communicate with the host device or service using PCIe, SATA, Serial Attached SCSI (SAS), Universal Serial Bus (USB), and / or other communication protocols and / or technologies.

[0035] The buffer 210 of the data storage controller 202 is embodied as a volatile memory used by the data storage controller 202 to temporarily store data being read from or written to the memory 214. The specific size of the buffer 210 may depend on the total storage size of the memory 214. The memory control logic 212 is illustratively embodied as hardware circuitry and / or a device that is configured to control read / write access to data at a specific storage location of the memory 214.

[0036] The non-volatile memory 216 may be embodied as any type of data storage that is capable of storing data in a persistent manner (even if power to the non-volatile memory 216 is interrupted). For example, in an illustrative embodiment, the non-volatile memory is embodied as flash memory (e.g., NAND memory). In other embodiments, the non-volatile memory 216 may be embodied as a memory device using chalcogenide phase change material (e.g., chalcogenide glass), byte or block addressable write-in-place non-volatile memory, ferroelectric transistor random access memory (FeTRAM), nanowire-based non-volatile memory, phase change memory (PCM), memory incorporating memristor technology, magnetoresistive random access memory (MRAM), or any combination of spin transfer torque (STT)-MRAM.

[0037] Volatile memory 218 may be embodied as any storage medium that requires power to maintain the state of data stored by the medium. Examples of volatile memory may include various types of random access memory (RAM), such as dynamic random access memory (DRAM) or static random access memory (SRAM). One particular type of DRAM that may be used is synchronous dynamic random access memory (SDRAM). In a particular embodiment, the DRAM complies with standards promulgated by JEDEC, such as JESD79F for double data rate (DDR) SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, or JESD79-4A for DDR4 SDRAM (these standards are available at www.jedec.org). Such standards (and similar standards) may be referred to as DDR-based standards, and the communication interface of data storage device 110 that implements such standards may be referred to as a DDR-based interface.

[0038] Now refer to Figure 3, an embodiment of the I / O subsystem 106 can form an architecture referred to herein as fabric 300 through which components of the computing device 100 can communicate. Fabric 300 includes backbones 302, 304, which can be embodied as data communication buses capable of transferring data to and from devices connected to the backbones 302, 304. Additionally, each backbone 302, 304 is connected to a corresponding loop router 310, 330, each of which can be embodied as any device capable of routing data to and from devices on the corresponding backbone 302, 304 or routing data to another loop router 310, 330. In an illustrative embodiment, a bus controller 312 (e.g., an AHCI SATA bus controller) is connected to backbone 302. Additionally, loop router 310 is connected to backbone 302. In operation, loop router 310 can receive (e.g., from software executed by processor 102) a read request to read PBA data from a primary PBA exposed to the software, and remap the attributes of the request to corresponding address data that can be used by loop router 330 to route one or more corresponding read requests to one or more of the data storage devices 110 corresponding to the requested PBA data, such as through the corresponding PCIe interfaces 322, 324, 326 of data storage devices 112, 114, 116. Loop router 310 can also receive PBA data associated with the various data storage devices 110 and merge the PBA data back into the primary PBA for use by the software that requested the PBA data. Thus, in the illustrative embodiment, loop router 310 can include a remapping logic unit 124. Additionally, in the illustrative embodiment, loop router 330 can include a plurality of sub-components 332, 334, 336 capable of routing data to and from corresponding data storage devices 112, 114, 116.

[0039] Now refer to Figure 4, in use, computing device 100 may establish environment 400. Illustrative environment 400 includes request manager 420 and remapping manager 430. Each of the components of environment 400 may be embodied as firmware, software, hardware, or a combination thereof. For example, the various components and logic of environment 400 may form part of or otherwise be established by I / O subsystem 106, remapping logic unit 124, processor 102, main memory 104, and / or data storage subsystem 108. Thus, in some embodiments, any one or more of the components of environment 400 may be embodied as a circuit or collection of electrical devices (e.g., request manager 420, remapping manager 430, etc.). In an illustrative embodiment, environment 400 includes master pending bit array (PBA) data 402, which may be embodied as any data indicative of a combined set of pending bit arrays for data storage device 110 and bus controller 312. Additionally, in an illustrative embodiment, environment 400 includes sub-PBA data 404, which may be embodied as any data indicative of each individual pending bit array for each of bus controller 312 and data storage device 110 (e.g., in local memory 206 of the corresponding data storage device 110). Thus, in the illustrative environment, master PBA data 402 includes sub-PBA data 404 for each of bus controller 312 and data storage device 110, which is remapped to a different address space such that the sub-PBA data 404 is exposed to software via a single PBA. Additionally, in an illustrative embodiment, environment 400 includes remapping data 406, which may be embodied as any data indicative of a translated version of the attributes of one or more read requests for PBA data directed to the address space of master PBA data 402, as well as the attributes corresponding to the address space of sub-PBA data 404. Additionally, environment 400 may include MSI-X table data 408, which may be embodied as any data indicative of a combined set of message signal interrupts for each of bus controller 312 and data storage device 110.

[0040] In an illustrative embodiment, request manager 420 is configured to receive, such as from software executed by processor 102, a request to read pending bit array data, and request manager 420 may be embodied as hardware, firmware, software, virtualized hardware, emulation architecture, and / or a combination thereof as discussed above. In an illustrative embodiment, the request includes attribute data, which may be embodied as any data indicative of a segment of master PBA data 402 to be read. In an illustrative embodiment, request manager 420 is additionally configured to Figure 3The switching fabric 300 routes requests, such as read requests having translated attributes associated with the address space of the sub-PBA data 404, between devices (e.g., data storage device 110), and receives the sub-PBA data 404 from the device (e.g., data storage device 110) in response to the request.

[0041] The remapping manager 430 is configured to remap attribute data from the address space of the primary PBA data 402 to the corresponding address space of the sub-PBA data 404 and to merge the sub-PBA data 404 received from one or more devices (e.g., one or more of the data storage devices 110) back into the primary PBA data 402. The remapping manager 430 may be embodied as hardware, firmware, software, virtualized hardware, an emulation architecture, and / or a combination thereof as discussed above. To do so, in an illustrative embodiment, the remapping manager 430 includes an attribute remapper 432 and a data merger 434. In an illustrative embodiment, the attribute remapper 432 is configured to determine one or more bit addresses from the attribute data, compare the one or more bit addresses to the address of the sub-PBA in the primary PBA to determine the set of sub-PBAs to be read, and map the one or more bit addresses to the determined set of sub-PBAs to be read. In an illustrative embodiment, the data merger 434 is configured to merge the PBA data received from the sub-PBA (e.g., sub-PBA data 404) into the primary PBA (e.g., primary PBA data 402). It should be appreciated that each of the attribute remapper 432 and the data merger 434 may be embodied as hardware, firmware, software, virtualized hardware, an emulation architecture, and / or a combination thereof. For example, the attribute remapper 432 may be embodied as a hardware component, while the data merger 434 is embodied as a virtualized hardware component or some other combination of hardware, firmware, software, virtualized hardware, an emulation environment, and / or a combination thereof.

[0042] Now referring to Figure 5, in use, computing device 100 may execute method 500 for remapping an access (e.g., a read request) to pending bit array data. Method 500 begins at 502, where computing device 100 determines whether to enable remapping of access to pending bit array data. In an illustrative embodiment, computing device 100 may determine to enable remapping if data storage device 110 is capable of supporting (e.g., in response to) a message signal interrupt (e.g., MSI-X). In other embodiments, computing device 100 may determine to enable remapping based on other factors. Regardless, in response to the determination to enable remapping, method 500 proceeds to block 504, where computing device 100 generates a PBA indicating multiple sub-PBAs. In doing so, in an illustrative embodiment, computing device 100 generates a master PBA (e.g., master PBA data 402) indicating the PBA of the SATA controller (e.g., bus controller 312) and a sub-PBA (e.g., sub-PBA data 404) for each of the multiple data storage devices 110, as indicated in block 506. Subsequently, method 500 proceeds to block 508, where computing device 100 receives a request including attribute data indicating an address in the master PBA (e.g., in the address space of master PBA data 402). In doing so, in an illustrative embodiment, computing device 100 may receive a request including attribute data indicating an address, a length (e.g., the amount of data to be read starting from the address), first byte enable data indicating which of four bytes in the first doubleword associated with the request are valid, and last byte enable data indicating which of four bytes in the last doubleword associated with the request are valid, as indicated in block 510. In an illustrative embodiment, computing device 100 receives a read request at a cyclic router 310 associated with the SATA controller (e.g., bus controller 312), as indicated in block 512. Additionally, as indicated in block 514, when receiving the read request, computing device 100 receives a read request in which the address is a doubleword address. Further, in an illustrative embodiment, computing device 100 receives the read request from software executed by computing device 100 (e.g., by processor 102). In block 518, computing device 100 determines whether a read request has been received. If not, method 500 loops back to block 508, where computing device 100 continues to wait for a read request. Otherwise, method 500 proceeds to Figure 6 block 520, where computing device 100 remaps the read request (e.g., the attribute data of the read request) to one or more sub-PBAs (e.g., the (one or more) address spaces of one or more sets of sub-PBA data 404).

[0043] Now refer to Figure 6, in block 520, computing device 100 determines one or more bit addresses based on the attribute data of the received read request. In doing so, in an illustrative embodiment, computing device 100 determines a start bit address and an end bit address, as indicated in block 522. When determining one or more bit addresses, in an illustrative embodiment, computing device 100 converts the address in the attribute data from a double-word address into one or more bit addresses, as indicated in block 524. In an illustrative embodiment, loop router 310 associated with a SATA controller (e.g., bus controller 312) determines one or more bit addresses, as indicated in block 526. Now refer to Figure 9 , the pseudocode 900 includes an instruction set 910 for calculating the start bit address and another instruction set 920 that can be used to determine the end bit address based on the attribute data (e.g., address (ADDR), first byte enable (FBE) data, last byte enable (LBE) data, and length (LEN) data).

[0044] Referring back to Figure 6 , method 500 then proceeds to block 528, where computing device 100 compares the one or more bit addresses determined in block 520 with the addresses of the sub-PBAs (e.g., the location of each set of sub-PBA data 404 in the main PBA data 402) to determine the set of sub-PBAs to be read (e.g., sub-PBA data 404). In doing so, in an illustrative embodiment, computing device 100 compares the start bit address and the end bit address (e.g., the addresses determined in block 522) with the addresses of the sub-PBAs, as indicated in block 530. In an illustrative embodiment, computing device 100 determines the number of sub-PBAs associated with the bit addresses, as indicated in 532. Additionally, computing device 100 determines whether the bit addresses cross a quadword boundary, as indicated in block 534. In response to determining that the bit addresses cross a quadword boundary, in an illustrative embodiment, computing device 100 determines one or more split addresses (e.g., the addresses on either side of the quadword boundary), as indicated in block 536. Now refer to Figure 10, showing the arrangement 1000 of the sub-PBA 1020 within the main PBA address space 1010 and the corresponding conditions 1030 (e.g., condition 00, condition 01, condition 10, and condition 11) indicating various sets of sub-PBAs that can be associated with a set of bit addresses. In condition 00, the entire read is within one of the sub-PBAs. Conversely, in condition 01, the read starts from one sub-PBA (e.g., sub-PBA n-1), spans to the next sub-PBA (e.g., sub-PBA n), and ends there. Similarly, in condition 10, the read starts from one sub-PBA (e.g., sub-PBA n-1) and spans to the next sub-PBA (e.g., sub-PBA n). However, in condition 10, the read ends in a subsequent sub-PBA (e.g., sub-PBA n+1). Finally, in condition 11, the read starts from one sub-PBA (e.g., sub-PBA n), spans to a subsequent sub-PBA (e.g., sub-PBA n+1), and ends therein.

[0045] Referring back to Figure 6 , method 500 then proceeds to block 538, where computing device 100 maps the bit address to the address of the determined set of sub-PBAs to be read (e.g., the set determined in block 528). In doing so, in the illustrative embodiment, computing device 100 determines the translated attribute data for each new read request corresponding to each sub-PBA in the determined set, as indicated in block 540. In the illustrative embodiment, computing device 100 determines the translated address attribute for each new read request, as indicated in block 542. In the illustrative embodiment, computing device 100 determines the translated length attribute for each new read request, as indicated in block 544. Additionally, computing device 100 determines the translated first byte enable attribute for each new read request, as indicated in block 546. Computing device 100 also determines the translated last byte enable attribute for each read request, as indicated in block 548. Now referring to Figure 11, the pseudo-code 1100 includes an instruction set 1110 that can be used to determine the translated start address for conditions 00 and 11, and an instruction set 1120 that can be used to determine the translated start address for conditions 01 and 10 based on the comparison of the start bit address and the sub-PBA address in block 530. Additionally, the pseudo-code 1100 includes an instruction set 1130 that can be used to determine the end address for conditions 00 and 01, and another instruction set 1140 that can be used to determine the end address for conditions 10 and 11. The computing device 100 can split the translated address when the read request crosses a quadword boundary. In such a case, the computing device 100 generates two read requests, where one read request starts from the translated ADDR[63:0] and ends at the quadword boundary, and the second request starts from the quadword boundary and extends to the translated ADDRend[63:0]. The split is valid when the translated ADDRend[3] is not equal to ADDR[3].

[0046] When determining the translated length attribute, in an illustrative embodiment, the computing device 100 determines the length based on (i) whether the split operation is performed and (ii) the conditions of the sub-PBA read address, as shown in Table 1 below.

[0047]

[0048] Table 1.

[0049] Additionally, in an illustrative embodiment, the computing device 100 can determine the translated first byte enable attribute based on the data in the translated address attribute (i.e., ADDR[1:0]), as shown in Table 2 below.

[0050] When the translated ADDR[1:0] is the following The translated FBE[3:0] at sub - PBA is 11 1000B 10 1100B 01 1110B 00 1111B

[0051] Table 2.

[0052] Additionally, in an illustrative embodiment, the computing device 100 can determine the translated last byte enable attribute based on the translated end address, the translated length attribute, whether the split is performed, and the translated last byte enable attribute, as shown in Table 3 below:

[0053]

[0054] Table 3.

[0055] Subsequently, the method proceeds to Figure 7 block 550, where the computing device 100 sends one or more new read requests with the translated attribute data (e.g., the (one or more) new requests generated in Figure 6 block 540) to read the determined set (e.g., in Figure 6one or more sub-PBAs (e.g., sub-PBA data 404) in the set determined in block 528. In doing so, a loop router (e.g., loop router 310) associated with the SATA controller (e.g., bus controller 312) can send one or more new read requests to a loop router (e.g., loop router 330) associated with the data storage device 110, as indicated in block 552. In turn, a loop router (e.g., loop router 330) associated with the data storage device 110 can send one or more new read requests to one or more data storage devices 110 associated with the determined set of sub-PBAs (e.g., data storage devices 110 having the requested sub-PBA data 404 in their memories 206, 214), as indicated in block 554.

[0056] Then, method 500 proceeds to block 556, where computing device 100 receives the requested sub-PBA data 404 in response to the one or more new read requests, as indicated in block 556. In doing so, computing device 100 receives sub-PBA data 404 from data storage device 110 in response to the one or more new read requests, as indicated in block 558. In an illustrative embodiment, loop router 330 initially receives the requested sub-PBA data 404 from data storage device 110 and then routes it to loop router 310. Subsequently, in block 560, computing device 100 that has received sub-PBA data 404 from one or more of data storage devices 110 begins the process of merging the received sub-PBA data 404 back into the main PBA data 402 (e.g., for use by software executed by processor 102). In block 560, computing device 100 determines whether there is sub-PBA data 404 to be merged. In response to determining that there is sub-PBA data 404 to be merged, method 500 proceeds to block 562, where computing device 100 aligns the received sub-PBA data 404 for a given sub-PBA with the corresponding location in the main PBA (e.g., main PBA data 402). In doing so, computing device 100 can combine data for split sub-PBAs, as indicated in block 564. Additionally, when aligning the received sub-PBA data 404, computing device 100 shifts the current sub-PBA data 404 to the initial byte 0, bit 0 position, as indicated in block 566. Subsequently, computing device 100 shifts the current sub-PBA data 404 according to the location of the sub-PBA data 404 in the main PBA (e.g., main PBA data 402), as indicated in block 568. Additionally, computing device 100 masks unused bits in the sub-PBA data 404, as indicated in block 570. In doing so, in an illustrative embodiment, computing device 100 sets the unused bits to zero, as indicated in block 572.

[0057] Subsequently, method 500 loops back to block 560 to determine whether additional sub-PBA data 404 (e.g., sub-PBA data 404 from a different data storage device 110) has been received. If so, method 500 proceeds to block 562 to align the additional sub-PBA data 404. Method 500 can loop through blocks 560 to 572 until all received sub-PBA data 404 has been aligned. It should be understood that although blocks 560 to 572 are shown sequentially as if operating on each set of sub-PBA data 404 sequentially, computing device 100 can instead align all received sub-PBA data 404 simultaneously. In response to determining at block 560 that there is no more sub-PBA data 404 to merge, method 500 proceeds to Figure 8 block 574, where computing device 100 combines the aligned sub-PBA data 404 in the main PBA data 402. In doing so, computing device 100 can combine the aligned PBA data by ORing all of the aligned PBA data together, as indicated in block 576. Additionally, in the illustrative embodiment, computing device 100 stores the combined and aligned sub-PBA data 404 in the main PBA data 402, as indicated in block 578. In the illustrative embodiment, loop router 310 can perform the operations in blocks 562 to 578. Subsequently, in block 580, computing device 100 returns the requested PBA data (e.g., back to the software that requested the PBA data) from the main PBA data 402 in response to a read request. Then, method 500 loops back to Figure 5 block 508, where computing device 100 waits to receive another read request.

[0058] Now referring to Figure 12 , relationship 1200 between sub-PBA data 404 (e.g., sub-PBA0, sub-PBA1, sub-PBA2) and main PBA data 402 associated with various devices including bus controller 312 (e.g., sub-PBA AHCI) and data storage device 110 is shown. During the merging of sub-PBA data 404 into main PBA data 402, there are several possible scenarios that can occur. For example, there are at most two reads of a single set of sub-PBA data 404 for a given read request of main PBA data 402 (e.g., one read request can split into a first split read request and a second split read request). However, there can be more than one set of reads of sub-PBA data 404 simultaneously, including reads of sub-PBA data 404 of bus controller 312. Alternatively, there can be exactly one read of exactly one set of sub-PBA data 404 (e.g., sub-PBA data 404 associated with only one of the data storage devices 110). Still referring to Figure 12, As an example scenario, there are two reads for sub - PBA0 and one read for sub - PBA1. The first data from sub - PBA0 is a one - bit read, and the second data from sub - PBA1 is less than a double - word read, while the data from sub - PBA1 is a cross - double - word read. Starting with the data for each individual sub - PBA (e.g., each individual set of sub - PBA data 404), computing device 100 stores the data if it is the first split. Now refer to Figure 13 , beyond the last byte of the stored data, computing device 100 forces the stored data to 0, and the stored data can be a quad - word or a double - word. Now refer to Figure 14 , computing device 100 merges the first and second split data for each set of sub - PBA data 404 that is read (e.g., for sub - PBA1 and for sub - PBA0). In doing so, computing device 100 checks the lengths of the first and second splits at the second split's data stage. Additionally, computing device 100 cascades the data from the previous step. In doing so, if the first split is a double - word, computing device 100 takes 32 bits of the stored data. Alternatively, if the first split is a quad - word, computing device 100 takes 64 bits of the stored data. If there is no split, computing device 100 uses 0 in place of the data that would otherwise be provided by the second split. Subsequently, and now refer to Figure 15 , computing device 100 shifts the sub - PBA data 404 to the byte position of the sub - PBA data 404 in the address space of the main PBA data 402. For example, if the target starting byte of the sub - PBA data 404 in the address space of the main PBA data 402 is byte 3, computing device 100 shifts the sub - PBA data 404 three bytes to the right.

[0059] Then, and now refer to Figure 16 , computing device 100 shifts the sub - PBA data 404 according to the starting bit of the sub - PBA data 404 in the address space of the main PBA data 402. For example, if the starting bit of the sub - PBA data 404 in the address space of the main PBA data 402 is bit 7, computing device 100 shifts the sub - PBA data 404 seven bits. Additionally, and now refer to Figure 17 , after shifting the sub - PBA data 404 according to the corresponding position in the main PBA data 402, computing device 100 selects a double - word or a quad - word according to the read request length. Subsequently, and now refer to Figure 18 , computing device 100 again shifts the sub - PBA data 404 according to the corresponding starting bit in the main PBA data 402. For example, if the starting bit of the main PBA data 402 is at bit 7, computing device 100 shifts the sub - PBA data 404 seven bits to the right. Now refer to Figure 19, after shifting the sub-PBA data 404 by a plurality of bits and past the last bit, the computing device 100 masks the sub-PBA data 404. The computing device 100 then combines the sub-PBA data 404 into the main PBA data 402 by ORing the sub-PBA data 404 together (e.g., ORing the sub-PBA1 data and the sub-PBA0 data together).

[0060] The above reference to a memory device also applies to different memory types and, in particular, to any memory having a bank group architecture. A memory device generally refers to volatile memory technology. Volatile memory is memory whose state (and thus the data stored thereon) is indeterminate if power to the device is interrupted. Non-volatile memory refers to memory whose state is determinate even if power to the device is interrupted. Dynamic volatile memory requires refreshing the data stored in the device to maintain the state. An example of dynamic volatile memory includes DRAM (Dynamic Random Access Memory), or a variant thereof, such as synchronous DRAM (SDRAM). The memory subsystem as described herein can be compatible with multiple memory technologies, such as DDR4 (DDR version 4, initial specification published by JEDEC in September 2012), DDR4E (in development by JEDED), LPDDR4 (Low Power Double Data Rate (LPDDR) version 4, JESD209-4, originally published by JEDEC in August 2014), WIO2 (Wide I / O 2 (Wide IO2), JESE229-2, originally published by JEDEC in August 2014), HBM (High Bandwidth Memory DRAM, JESD235, originally published by JEDEC in October 2013), DDR5 (DDR version 5, currently under discussion by JEDEC), LPDDR5 (currently under discussion by JEDED), HBM2 (HBM version 2), currently under discussion by JEDEC, and / or others, as well as technologies derived or extended based on such specifications.

[0061] In addition to or in place of volatile memory, in one embodiment, the reference to a memory device can refer to a non-volatile memory device whose state is determinate even if power to the device is interrupted.

[0062] Examples Illustrative examples of the techniques disclosed herein are provided below. Embodiments of the techniques can include any one or more of the above examples and any combination thereof.

[0063] Example 1 includes a computing device for remapping a pending bit array read request. The computing device includes: a plurality of data storage devices; a request manager configured to receive a request to read pending bit array (PBA) data from a master PBA mapped to a plurality of sub-PBAs, where each sub-PBA is associated with a different one of the data storage devices, and the request includes attribute data indicating an address in the master PBA from which to read the PBA data; a remapping manager configured to determine one or more bit addresses from the attribute data, compare the one or more bit addresses with the addresses of the sub-PBAs in the master PBA to determine a set of sub-PBAs to be read, and map the one or more bit addresses to the determined set of sub-PBAs to be read.

[0064] Example 2 includes the subject matter of Example 1, and wherein mapping the one or more bit addresses includes determining translated attribute data for a read request associated with each sub-PBA in the determined set.

[0065] Example 3 includes the subject matter of either Example 1 or 2, and wherein the request manager is further configured to send one or more read requests to the plurality of data storage devices to read one or more sub-PBAs in the determined set.

[0066] Example 4 includes the subject matter of any one of Examples 1-3, and wherein the request manager is further configured to receive PBA data from each sub-PBA in the determined set in response to the one or more read requests; and the remapping manager is further configured to merge the received PBA data into the master PBA.

[0067] Example 5 includes the subject matter of any one of Examples 1-4, and wherein merging the received PBA data into the master PBA includes: aligning the received PBA data from the sub-PBA with an associated location in the master PBA; and combining the aligned PBA data in the master PBA.

[0068] Example 6 includes the subject matter of any one of Examples 1-5, and wherein combining the aligned PBA data includes performing an or (OR) operation on the received PBA data associated with the sub-PBA.

[0069] Example 7 includes the subject matter of any one of Examples 1-6, and wherein aligning the received PBA data from the sub-PBA includes: shifting the PBA data from the sub-PBA to an initial position; shifting the PBA data according to the position of the sub-PBA associated in the master PBA; and masking unused bits in the PBA data associated with the sub-PBA.

[0070] Example 8 includes the subject matter of any one of Examples 1-7, and wherein masking the unused bits includes setting the unused bits to zero.

[0071] Example 9 includes the subject matter of any one of Examples 1-8, and wherein receiving a read request includes receiving a read request including attribute data indicating an address in the master PBA, a length indicating the amount of data to be read, first byte enable data, and last byte enable data; and wherein determining the translated attribute data includes determining a translated address, a translated length, translated first byte enable data, and translated last byte enable data.

[0072] Example 10 includes the subject matter of any one of Examples 1-9, and wherein determining one or more bit addresses includes determining a start bit address and an end bit address.

[0073] Example 11 includes the subject matter of any one of Examples 1-10, and wherein determining one or more bit addresses includes converting an address from a doubleword address into one or more bit addresses.

[0074] Example 12 includes the subject matter of any one of Examples 1-11, and wherein comparing one or more bit addresses includes comparing the start bit address and the end bit address with the address of a sub PBA.

[0075] Example 13 includes the subject matter of any one of Examples 1-12, and wherein the remapping manager is further configured to determine whether the start bit address and the end bit address cross a quadword boundary; and determine a set of split addresses in response to determining that the start bit address and the end bit address cross a quadword boundary.

[0076] Example 14 includes a method for remapping a pending bit array read request, the method including: receiving, by a computing device, a request to read PBA data from a master PBA mapped to a plurality of sub-pending bit arrays (PBAs), wherein each sub PBA is associated with a different data storage device among a plurality of data storage devices, and the request includes attribute data indicating an address in the master PBA from which the PBA data is to be read; determining, by the computing device, one or more bit addresses from the attribute data; comparing, by the computing device, the one or more bit addresses with the addresses of the sub PBAs in the master PBA to determine a set of sub PBAs to be read; and mapping, by the computing device, the one or more bit addresses to the determined set of sub PBAs to be read.

[0077] Example 15 includes the subject matter of Example 14, and wherein mapping the one or more bit addresses includes determining translated attribute data for read requests associated with each sub PBA in the determined set.

[0078] Example 16 includes the subject matter of any one of Examples 14 and 15, and further includes sending, by the computing device, one or more read requests to the plurality of data storage devices to read one or more sub PBAs in the determined set.

[0079] Example 17 includes the subject matter of any one of Examples 14 - 16 and further includes: receiving, by a computing device, PBA data from each sub - PBA in the determined set in response to the one or more read requests; and merging, by the computing device, the received PBA data into the main PBA.

[0080] Example 18 includes the subject matter of any one of Examples 14 - 17, and wherein merging the received PBA data into the main PBA includes: aligning the received PBA data from the sub - PBA with an associated location in the main PBA; and combining the aligned PBA data in the main PBA.

[0081] Example 19 includes the subject matter of any one of Examples 14 - 18, and wherein combining the aligned PBA data includes performing an OR operation on the received PBA data associated with the sub - PBA.

[0082] Example 20 includes the subject matter of any one of Examples 14 - 19, and wherein aligning the received PBA data from the sub - PBA includes: shifting the PBA data from the sub - PBA to an initial position; shifting the PBA data according to the position of the associated sub - PBA in the main PBA; and masking unused bits in the PBA data associated with the sub - PBA.

[0083] Example 21 includes the subject matter of any one of Examples 14 - 20, and wherein masking the unused bits includes setting the unused bits to zero.

[0084] Example 22 includes the subject matter of any one of Examples 14 - 21, and wherein receiving a read request includes receiving a read request that includes attribute data indicating an address in the main PBA, a length indicating the amount of data to be read, first - byte enable data, and last - byte enable data; and wherein determining the translated attribute data includes determining a translated address, a translated length, translated first - byte enable data, and translated last - byte enable data.

[0085] Example 23 includes the subject matter of any one of Examples 14 - 22, and wherein determining one or more bit addresses includes determining a starting bit address and an ending bit address.

[0086] Example 24 includes the subject matter of any one of Examples 14 - 23, and wherein determining one or more bit addresses includes converting an address from a double - word address into one or more bit addresses.

[0087] Example 25 includes the subject matter of any one of Examples 14 - 24, and wherein comparing one or more bit addresses includes comparing the starting bit address and the ending bit address with the address of the sub - PBA.

[0088] Example 26 includes the subject matter of any one of Examples 14-25 and further includes: determining, by a computing device, whether a start bit address and an end bit address cross a quadword boundary; and determining, by the computing device and in response to determining that the start bit address and the end bit address cross the quadword boundary, a set of split addresses.

[0089] Example 27 includes one or more machine-readable storage media having stored thereon a plurality of instructions that, in response to being executed, cause a computing device to perform the method of any one of Examples 14-26.

[0090] Example 28 includes a computing device for remapping a pending bit array read request, the computing device including: means for receiving a request to read PBA data from a main PBA mapped to a plurality of sub-pending bit arrays (PBAs), where each sub-PBA is associated with a different data storage device of a plurality of data storage devices, and the request includes attribute data indicating an address in the main PBA from which to read the PBA data; means for determining, from the attribute data, one or more bit addresses; means for comparing the one or more bit addresses with the addresses of the sub-PBAs in the main PBA to determine a set of sub-PBAs to be read; and means for mapping the one or more bit addresses to the determined set of sub-PBAs to be read.

[0091] Example 29 includes the subject matter of Example 28, and wherein the means for mapping the one or more bit addresses includes means for determining translated attribute data for a read request associated with each sub-PBA in the determined set.

[0092] Example 30 includes the subject matter of any one of Examples 28 and 29 and further includes means for sending one or more read requests to the plurality of data storage devices to read one or more sub-PBAs in the determined set.

[0093] Example 31 includes the subject matter of any one of Examples 28-30 and further includes: means for receiving, in response to the one or more read requests, PBA data from each sub-PBA in the determined set; and means for merging the received PBA data into the main PBA.

[0094] Example 32 includes the subject matter of any one of Examples 28-31, and wherein the means for merging the received PBA data into the main PBA includes: means for aligning the received PBA data from the sub-PBA with an associated location in the main PBA; and means for combining the aligned PBA data in the main PBA.

[0095] Example 33 includes the subject matter of any one of Examples 28 - 32, and wherein the component for combining the aligned PBA data includes a component for performing an operation on the received PBA data associated with the sub - PBA.

[0096] Example 34 includes the subject matter of any one of Examples 28 - 33, and wherein the component for aligning the received PBA data from the sub - PBA includes: a component for shifting the PBA data from the sub - PBA to an initial position; a component for shifting the PBA data according to the position of the associated sub - PBA in the main PBA; and a component for masking unused bits in the PBA data associated with the sub - PBA.

[0097] Example 35 includes the subject matter of any one of Examples 28 - 34, and wherein the component for masking unused bits includes a component for setting the unused bits to zero.

[0098] Example 36 includes the subject matter of any one of Examples 28 - 35, and wherein the component for receiving a read request includes a component for receiving a read request including attribute data indicating an address in the main PBA, a length indicating the amount of data to be read, first - byte enable data, and last - byte enable data; and wherein the component for determining the translated attribute data includes a component for determining the translated address, the translated length, the translated first - byte enable data, and the translated last - byte enable data.

[0099] Example 37 includes the subject matter of any one of Examples 28 - 36, and wherein the component for determining one or more bit addresses includes a component for determining a start bit address and an end bit address.

[0100] Example 38 includes the subject matter of any one of Examples 28 - 37, and wherein the component for determining one or more bit addresses includes a component for converting an address from a double - word address into one or more bit addresses.

[0101] Example 39 includes the subject matter of any one of Examples 28 - 38, and wherein the component for comparing one or more bit addresses includes a component for comparing the start bit address and the end bit address with the address of the sub - PBA.

[0102] Example 40 includes the subject matter of any one of Examples 28 - 39, and further includes: a component for a computing device to determine whether the start bit address and the end bit address cross a quad - word boundary; and a component for the computing device and in response to determining that the start bit address and the end bit address cross a quad - word boundary to determine a set of split addresses.

[0103] The first embodiment relates to a computing device, including:

[0104] A plurality of data storage devices;

[0105] A request manager for receiving a request to read PBA data from a master PBA mapped to a plurality of sub-pending bit arrays (PBAs), where each sub-PBA is associated with a different data storage device in a data storage device, and the request includes attribute data indicating an address in the master PBA from which the PBA data is to be read;

[0106] A remapping manager for determining one or more bit addresses from the attribute data, comparing the one or more bit addresses with the addresses of the sub-PBAs in the master PBA to determine a set of sub-PBAs to be read, and mapping the one or more bit addresses to the determined set of sub-PBAs to be read.

[0107] A second embodiment includes the computing device according to the first embodiment, wherein mapping the one or more bit addresses includes determining translated attribute data for a read request associated with each sub-PBA in the determined set.

[0108] A third embodiment includes the computing device according to the second embodiment, wherein the request manager is further configured to send one or more read requests to the plurality of data storage devices to read one or more sub-PBAs in the determined set.

[0109] A fourth embodiment includes the computing device according to the third embodiment, wherein the request manager is further configured to receive PBA data from each sub-PBA in the determined set in response to the one or more read requests; and the remapping manager is further configured to merge the received PBA data into the master PBA.

[0110] A fifth embodiment includes the computing device according to the fourth embodiment, wherein merging the received PBA data into the master PBA includes:

[0111] Aligning the received PBA data from the sub-PBA with an associated location in the master PBA; and

[0112] Combining the aligned PBA data in the master PBA.

[0113] A sixth embodiment includes the computing device according to the fifth embodiment, wherein combining the aligned PBA data includes performing an or (OR) operation on the received PBA data associated with the sub-PBA.

[0114] A seventh embodiment includes the computing device according to the fifth embodiment, wherein aligning the received PBA data from the sub-PBA includes:

[0115] Shifting the PBA data from the sub-PBA to an initial position;

[0116] Shift the PBA data according to the positions of the associated sub-PBAs in the main PBA; and

[0117] Mask unused bits in the PBA data associated with the sub-PBA.

[0118] The eighth embodiment includes the computing device according to the seventh embodiment, wherein masking the unused bits includes setting the unused bits to zero.

[0119] The ninth embodiment includes the computing device according to the first embodiment, wherein receiving a read request includes receiving a read request that includes attribute data indicating an address in the main PBA, a length indicating the amount of data to be read, first byte enable data, and last byte enable data; and

[0120] wherein determining the translated attribute data includes determining a translated address, a translated length, translated first byte enable data, and translated last byte enable data.

[0121] The tenth embodiment includes the computing device according to the first embodiment, wherein determining one or more bit addresses includes determining a start bit address and an end bit address.

[0122] The eleventh embodiment includes the computing device according to the first embodiment, wherein determining one or more bit addresses includes converting an address from a double-word address into one or more bit addresses.

[0123] The twelfth embodiment relates to one or more machine-readable storage media that include a plurality of instructions stored thereon, the plurality of instructions when executed by a computing device cause the computing device to:

[0124] Receive a request to read PBA data from a main PBA mapped to a plurality of sub-pending bit arrays (PBAs), wherein each sub-PBA is associated with a different data storage device among a plurality of data storage devices, and the request includes attribute data indicating an address in the main PBA from which the PBA data is to be read;

[0125] Determine one or more bit addresses from the attribute data;

[0126] Compare the one or more bit addresses with the addresses of the sub-PBAs in the main PBA to determine a set of sub-PBAs to be read; and

[0127] Map the one or more bit addresses to the determined set of sub-PBAs to be read.

[0128] The thirteenth implementation includes one or more machine-readable storage media according to the twelfth implementation, wherein mapping the one or more bit addresses includes determining translated attribute data for read requests associated with each sub-PBA in the determined set.

[0129] The fourteenth implementation includes one or more machine-readable storage media according to the thirteenth implementation, wherein the plurality of instructions, when executed, further cause the computing device to send one or more read requests to the plurality of data storage devices to read one or more sub-PBAs in the determined set.

[0130] The fifteenth implementation includes one or more machine-readable storage media according to the fourteenth implementation, wherein the plurality of instructions, when executed, further cause the computing device to:

[0131] Receive PBA data from each sub-PBA in the determined set in response to the one or more read requests; and merge the received PBA data into the main PBA.

[0132] The sixteenth implementation includes one or more machine-readable storage media according to the fifteenth implementation, wherein merging the received PBA data into the main PBA includes:

[0133] Aligning the received PBA data from the sub-PBA with the associated location in the main PBA; and

[0134] Combining the aligned PBA data in the main PBA.

[0135] The seventeenth implementation includes one or more machine-readable storage media according to the sixteenth implementation, wherein combining the aligned PBA data includes performing an OR operation on the received PBA data associated with the sub-PBA.

[0136] The eighteenth implementation includes one or more machine-readable storage media according to the sixteenth implementation, wherein aligning the received PBA data from the sub-PBA includes:

[0137] Shifting the PBA data from the sub-PBA to the initial position;

[0138] Shifting the PBA data according to the position of the associated sub-PBA in the main PBA; and

[0139] Masking the unused bits in the PBA data associated with the sub-PBA.

[0140] The nineteenth implementation includes one or more machine-readable storage media according to the eighteenth implementation, wherein masking the unused bits includes setting the unused bits to zero.

[0141] The twentieth embodiment includes one or more machine-readable storage media according to the twelfth embodiment, wherein receiving a read request includes receiving a read request including attribute data indicating an address in the main PBA, a length indicating the amount of data to be read, first-byte enable data, and last-byte enable data; and

[0142] wherein determining the translated attribute data includes determining a translated address, a translated length, translated first-byte enable data, and translated last-byte enable data.

[0143] The twenty-first embodiment includes one or more machine-readable storage media according to the twelfth embodiment, wherein determining one or more bit addresses includes determining a start bit address and an end bit address.

[0144] The twenty-second embodiment relates to a method, including:

[0145] receiving, by a computing device, a request to read PBA data from a main PBA mapped to a plurality of sub-pending bit arrays (PBAs), wherein each sub-PBA is associated with a different data storage device among a plurality of data storage devices, and the request includes attribute data indicating an address in the main PBA from which the PBA data is to be read;

[0146] determining, by the computing device, one or more bit addresses from the attribute data;

[0147] comparing, by the computing device, the one or more bit addresses with addresses of sub-PBAs in the main PBA to determine a set of sub-PBAs to be read; and

[0148] mapping, by the computing device, the one or more bit addresses to the determined set of sub-PBAs to be read.

[0149] The twenty-third embodiment includes the method according to the twenty-second embodiment, wherein mapping the one or more bit addresses includes determining translated attribute data for a read request associated with each sub-PBA in the determined set.

[0150] The twenty-fourth embodiment includes the method according to the twenty-third embodiment, further including sending, by the computing device, one or more read requests to the plurality of data storage devices to read one or more sub-PBAs in the determined set.

[0151] The twenty-fifth embodiment includes the method according to the twenty-fourth embodiment, further including:

[0152] receiving, by the computing device, PBA data from each sub-PBA in the determined set in response to the one or more read requests; and

[0153] The computing device combines the received PBA data into the main PBA.

Claims

1. A computing device, comprising: multiple data storage devices; a request manager to receive a request to read PBA data from a master PBA mapped to a plurality of sub-PBAs, wherein each sub-PBA is associated with a different one of the data storage devices, and the request includes attribute data indicating an address in the master PBA from which to read the PBA data; A remapping manager is configured to determine one or more bit addresses from the attribute data, compare the one or more bit addresses with addresses of sub-PBAs in the main PBA to determine a set of sub-PBAs to be read, and map the one or more bit addresses to the determined set of sub-PBAs to be read. 2 . The computing device of claim 1 , wherein mapping the one or more bit addresses comprises determining translated attribute data for a read request associated with each sub-PBA in the determined set. 3 . The computing device of claim 2 , wherein the request manager is further configured to send one or more read requests to the plurality of data storage devices to read the one or more sub-PBAs in the determined set.

4. The computing device of claim 3, wherein the request manager is further configured to receive PBA data from each sub-PBA in the determined set in response to the one or more read requests; and The remapping manager is further configured to merge the received PBA data into the primary PBA.

5. The computing device of claim 4, wherein merging the received PBA data into the master PBA comprises: aligning received PBA data from the child PBA with associated locations in the primary PBA; as well as The aligned PBA data is combined in the main PBA. 6 . The computing device of claim 5 , wherein combining the aligned PBA data comprises performing an OR operation on the received PBA data associated with the sub-PBAs.

7. The computing device of claim 5, wherein aligning received PBA data from sub-PBAs comprises: Shifting PBA data from a sub-PBA to an initial position; Shifting PBA data according to the location of the associated sub-PBA in the main PBA; as well as Mask unused bits in the PBA data associated with a sub-PBA. The computing device of claim 7 , wherein masking the unused bits comprises setting the unused bits to zero.

9. The computing device of claim 1 , wherein receiving a read request comprises receiving a read request including attribute data indicating an address in a primary PBA, a length indicating an amount of data to be read, first byte enable data, and last byte enable data; and Wherein determining the translated attribute data includes determining a translated address, a translated length, a translated first byte enable data, and a translated last byte enable data.

10. The computing device of claim 1, wherein determining one or more bit addresses comprises determining a starting bit address and an ending bit address.

11. The computing device of claim 1, wherein determining the one or more bit addresses comprises converting an address from a doubleword address to the one or more bit addresses.

12. A computing device for remapping a pending bit array read request, the computing device comprising: means for receiving a request to read PBA data from a master PBA mapped to a plurality of sub-PBAs, wherein each sub-PBA is associated with a different data storage device of a plurality of data storage devices, and the request includes attribute data indicating an address in the master PBA from which to read the PBA data; means for determining one or more bit addresses from attribute data; means for comparing the one or more bit addresses with addresses of sub-PBAs in the main PBA to determine a set of sub-PBAs to read; as well as Means for mapping the one or more bit addresses to the determined set of sub-PBAs to be read.

13. The computing device of claim 12, wherein means for mapping the one or more bit addresses comprises means for determining translated attribute data for a read request associated with each sub-PBA in the determined set.

14. The computing device of claim 13, further comprising means for sending one or more read requests to the plurality of data storage devices to read the one or more sub-PBAs in the determined set.

15. The computing device of claim 14, further comprising: means for receiving PBA data from each sub-PBA in the determined set in response to the one or more read requests; as well as Component used to merge received PBA data into the main PBA.

16. The computing device of claim 15, wherein the means for merging the received PBA data into the master PBA comprises: means for aligning received PBA data from a child PBA with an associated location in a master PBA; as well as Means for combining aligned PBA data in a master PBA.

17. The computing device of claim 16, wherein the means for combining the aligned PBA data comprises means for performing an OR operation on the received PBA data associated with the sub-PBA.

18. The computing device of claim 16, wherein the means for aligning received PBA data from sub-PBAs comprises: means for shifting PBA data from a sub-PBA to an initial position; means for shifting PBA data according to the location of the associated sub-PBA in the main PBA; and Means for masking unused bits in the PBA data associated with a sub-PBA.

19. The computing device of claim 18, wherein the means for masking unused bits comprises means for setting the unused bits to zero.

20. The computing device of claim 12, wherein the means for receiving a read request comprises means for receiving a read request including attribute data indicating an address in a primary PBA, a length indicating an amount of data to be read, first byte enable data, and last byte enable data; and Wherein the means for determining the translated attribute data includes means for determining the translated address, the translated length, the translated first byte enable data, and the translated last byte enable data.

21. The computing device of claim 12, wherein the means for determining one or more bit addresses comprises means for determining a starting bit address and an ending bit address.

22. A method comprising: receiving, by a computing device, a request to read PBA data from a master PBA mapped to a plurality of sub-PBAs, wherein each sub-PBA is associated with a different data storage device of a plurality of data storage devices, and the request includes attribute data indicating an address in the master PBA from which to read the PBA data; determining, by a computing device, one or more bit addresses from the attribute data; comparing, by the computing device, the one or more bit addresses with addresses of sub-PBAs in the main PBA to determine a set of sub-PBAs to read; as well as The one or more bit addresses are mapped, by the computing device, to the determined set of sub-PBAs to be read.

23. The method of claim 22, wherein mapping the one or more bit addresses comprises determining translated attribute data for a read request associated with each sub-PBA in the determined set.

24. The method of claim 23, further comprising sending, by a computing device, one or more read requests to the plurality of data storage devices to read the one or more sub-PBAs in the determined set.

25. The method according to claim 24, further comprising: receiving, by the computing device in response to the one or more read requests, PBA data from each sub-PBA in the determined set; as well as The received PBA data is merged into the master PBA by the computing device.

26. An apparatus comprising: means for receiving a request to read PBA data from a master PBA mapped to a plurality of sub-PBAs, wherein each sub-PBA is associated with a different data storage device of a plurality of data storage devices, and the request includes attribute data indicating an address in the master PBA from which to read the PBA data; means for determining one or more bit addresses from attribute data; means for comparing the one or more bit addresses with addresses of sub-PBAs in the main PBA to determine a set of sub-PBAs to read; as well as Means for mapping the one or more bit addresses to the determined set of sub-PBAs to be read.

27. The apparatus of claim 26, wherein means for mapping the one or more bit addresses comprises means for determining translated attribute data for a read request associated with each sub-PBA in the determined set.

28. The apparatus of claim 27, further comprising means for sending one or more read requests to the plurality of data storage devices to read the one or more sub-PBAs in the determined set.

29. The apparatus according to claim 28, further comprising: means for receiving PBA data from each sub-PBA in the determined set in response to the one or more read requests; as well as Component used to merge received PBA data into the main PBA.

30. A computer readable medium having stored thereon instructions which, when executed, cause a computing device to perform the method of any one of claims 22 to 25.

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