Apparatus, method and system for immediate cache associativity

Abstract

Provided are apparatus, methods, and systems for immediate cache associativity for a cache memory having a cache location as a cache for a non-volatile memory. Data to be added to the cache memory is received for a target address in the non-volatile memory. A direct-mapped cache location in the cache memory is determined based on the target address in the non-volatile memory. In response to the direct-mapped cache location storing data for another address in the non-volatile memory, the data for the target address is written at an available cache location in the cache memory different from the direct-mapped cache location. In response to the direct-mapped cache location not storing data for the other address in the non-volatile memory, the data for the target address is written in the direct-mapped cache location.

Description

Technical Field

[0001] Embodiments described herein generally relate to apparatus, methods, and systems for immediate cache associativity. Background Art

[0002] Different cache algorithms can be used to determine where to place data in a faster cache device or in a first level memory that is directed to an address for a larger, typically slower memory such as a second level memory. A direct-mapped cache algorithm applies a hash function to a portion of a data address to determine a unique location in the cache where data for that address is stored. When looking for read data for a read address in a direct-mapped cache, the direct-mapped cache location that may have read data for that read address is known, and the cache algorithm must ensure that data for a different address other than that read address is not located in the direct-mapped cache location because multiple addresses from a larger second level memory device map to one address in the cache memory. If the data for that read address is not at the direct-mapped cache location, there is a read miss, and the data needs to be retrieved from the second level memory.

[0003] A set associative cache maps each address to a set of cache locations or blocks so that data for the address can be stored in any cache location in the set to which the address is mapped. When looking for a read address in the set to which the read address is mapped, all cache locations in the set need to be read to determine if they have data for the read address, which is determined by looking for a cache location in the set that has a tag portion of the address that matches the tag portion of the read address. Summary of the invention

[0004] According to a first aspect of the present invention, there is provided an apparatus for immediate cache associativity, switching between using a set associative cache and a direct-mapped cache, the apparatus comprising: a cache memory; a byte-addressable write-in-place non-volatile memory; and a cache manager, which is to: determine a direct-mapped cache location in the cache memory according to a target address in the non-volatile memory; in response to the direct-mapped cache location storing data for another address in the non-volatile memory, write the data for the target address at an available cache location in the cache memory different from the direct-mapped cache location; and in response to the direct-mapped cache location not storing data for the non-volatile memory, write the data for the target address to the available cache location in the cache memory different from the direct-mapped cache location. data for another address in a non-volatile memory, writing the data for the target address in a direct-mapped cache location, wherein each address from the non-volatile memory maps to a set of a plurality of sets of cache locations in the cache memory, wherein each address from the non-volatile memory maps to one of the plurality of sets, and wherein an available cache location at which the data for the target address is written is in the set of cache locations to which the target address is mapped, and wherein the cache manager is further to: indicate in the remapping information at least a portion of the target address and an available cache location in the cache memory that is different from the directly-mapped cache location at which the data for the target address is written.

[0005] According to a second aspect of the present invention, there is provided a system for immediate cache associativity, switching between using a set-associative cache and a direct-mapped cache, the system comprising: a cache memory; a non-volatile memory; and a processor, the processor comprising a cache manager, which is to: determine a direct-mapped cache location in the cache memory according to a target address in the non-volatile memory; in response to the direct-mapped cache location storing data for another address in the non-volatile memory, write the data for the target address at an available cache location in the cache memory different from the direct-mapped cache location; and in response to the direct-mapped cache location not storing data for the non-volatile memory, write the data for the target address to an available cache location in the cache memory different from the direct-mapped cache location. data for another address in a volatile memory, writing the data for the target address in a directly mapped cache location, wherein each address from the non-volatile memory maps to a set of a plurality of sets of cache locations in the cache memory, wherein each address from the non-volatile memory maps to one of the plurality of sets, and wherein an available cache location at which the data for the target address is written is in the set of cache locations to which the target address is mapped, and wherein the cache manager further: indicates in the remapping information at least a portion of the target address and an available cache location in the cache memory that is different from the directly mapped cache location at which the data for the target address is written.

[0006] According to a third aspect of the present invention, there is provided a method for immediate cache associativity, switching between using a set associative cache and a direct-mapped cache for a cache memory having a cache location as a cache for a non-volatile memory, the method comprising: determining a direct-mapped cache location in the cache memory based on a target address in the non-volatile memory; in response to the direct-mapped cache location storing data for another address in the non-volatile memory, writing the data for the target address at an available cache location in the cache memory different from the direct-mapped cache location; and in response to the direct-mapped cache location not storing data for the non-volatile memory, writing the data for the target address at an available cache location in the cache memory different from the direct-mapped cache location. data for another address in a volatile memory, writing the data for the target address in a directly mapped cache location, wherein each address from the non-volatile memory maps to a set of a plurality of sets of cache locations in the cache memory, wherein each address from the non-volatile memory maps to one of the plurality of sets, and wherein an available cache location at which the data for the target address is written is in the set of cache locations to which the target address is mapped, and wherein the method further comprises indicating in the remapping information at least a portion of the target address and an available cache location in the cache memory, the available cache location being different from the directly mapped cache location at which the data for the target address is written.

[0007] According to a fourth aspect of the present invention, there is provided an apparatus for immediate cache associativity, comprising means for performing the steps of the method according to the third aspect.

[0008] According to a fifth aspect of the present invention, there is provided a computer readable medium comprising instructions, which when executed cause a computer to perform the method according to the third aspect.

[0009] According to a sixth aspect of the present invention, there is provided a computer program product comprising instructions, which when executed cause a computer to perform the method according to the third aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The embodiments are described by way of example with reference to the accompanying drawings, which are not drawn to scale and in which like reference numerals refer to similar elements.

[0011] Figure 1 An embodiment of a system having two levels of memory used by a processor is illustrated.

[0012] Figure 2 An embodiment of an address as known in the art is illustrated.

[0013] Figure 3 An embodiment of the contents of a cache location in a cache memory is illustrated.

[0014] Figure 4 An embodiment of a remapping information entry is illustrated.

[0015] Figure 5 An embodiment of an operation of adding data to a first memory cache is illustrated.

[0016] Figure 6 An embodiment of an operation of reading data from a first memory cache is illustrated.

[0017] Figure 7 The diagram shows where you can deploy Figure 1 Embodiments of a system of memory devices. DETAILED DESCRIPTION

[0018] The processor main memory may include two memory levels including a faster access first level smaller memory (such as a dynamic random access memory (DRAM) system) that caches data for a second level larger and slower memory. The second level memory is presented to the host and operating system as main memory, while the first level memory acts as a cache and is transparent to the operating system. The management of this two-level memory (2LM) may be performed by a 2LM engine in the host's processor.

[0019] Two-level main memory includes two memory levels including a faster access first level smaller volatile memory (such as a dynamic random access memory (DRAM) system) that caches data for a second level larger and slower or byte addressable write-in place non-volatile memory. The first level memory may be referred to as near memory or cache memory, and the second level memory may be referred to as far memory or non-volatile memory.

[0020] The advantage of a direct mapped cache is that the location of the requested read address in the cache is known, and the data can be retrieved directly without having to perform a tag search of multiple cache locations, as is performed with a set associative cache. However, since multiple addresses from the second level memory are mapped to one cache location for a direct mapped cache, the likelihood of a read miss is increased. The advantage of a set associative cache is that the miss rate is reduced because the read address can be stored in any of the cache locations in the group to which it is mapped. However, the need to perform a tag search before accessing the cache significantly increases read latency. An ideal cache would act as a direct mapped cache when conflicts are rare, and as a set associative cache when these conflicts are more common.

[0021] The described embodiments provide an immediate associative cache that uses a direct mapped cache for read addresses that are more recently accessed and are likely to have a higher hit rate, and then switches to a set associative cache for read addresses that are less recently accessed, which are stored using the set associative cache to reduce read misses for less recently accessed or frequently accessed data. However, lower latency is provided for faster direct mapped cache locations for more frequently accessed data (i.e., more recently accessed data). In this way, when cache conflicts are rare, direct mapped cache locations are used to provide high hit rates, and when cache conflicts are more common, set associative cache is used to maintain high hit rates as cache conflicts increase (i.e., read addresses mapped to the same direct mapped cache location in the cache are being accessed more frequently).

[0022] In the following description, numerous specific details are set forth, such as logic implementations, opcodes, means for specifying operands, resource partitioning / sharing / copying implementations, types and interrelationships of system components, and logic partitioning / integration selections, in order to provide a more thorough understanding of the present invention. However, those skilled in the art will appreciate that the present invention can be practiced without such specific details. In other examples, control structures, gate-level circuits, and full software instruction sequences are not shown in detail to avoid obscuring the present invention. Those of ordinary skill in the art will be able to implement appropriate functionality without excessive experimentation using the included descriptions.

[0023] References in the specification to "one embodiment," "an embodiment," "an example embodiment," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but not every embodiment may necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Certain embodiments relate to storage device electronic assemblies. Embodiments include both apparatus and methods for forming electronic assemblies.

[0024] Figure 1An embodiment of a system 100 having a processor 102 is illustrated, the processor 102 including multiple processing cores 104 and an on-chip cache memory controller 106 to interface with a cache memory 110, also referred to as a cache memory, cache, or first level memory. The cache memory controller 106 includes logic to access the cache memory 110, and may also communicate with a non-volatile memory controller 112 to access addresses in a non-volatile memory 114 or second level memory. The cache memory controller 106 includes a cache manager 108 to use the cache memory 110 as a cache to store data for addresses in the non-volatile memory 114 in cache locations 300 or cache blocks in the cache memory 110. The cache memory controller 106 may access the first level memory 110 and the non-volatile memory controller 112 through an interface 116, which, by way of example and not limitation, includes a memory bus, a peripheral component interconnect (PCI) bus, such as a Peripheral Component Interconnect Express (PCIe) bus, or the like.

[0025] The cache memory 110 and the non-volatile memory 114 may comprise the main memory of the processor 102 , wherein the cache memory 110 operates as a cache for the non-volatile memory 114 , having cache locations 300 that cache data and addresses from the non-volatile memory 114 .

[0026] In one embodiment, the cache memory 110 may be composed of one or more volatile memory devices that require power to maintain the state of the data stored by the medium. Non-limiting examples of volatile memory may include various types of random access memory (RAM), such as dynamic random access memory (DRAM), dual in-line memory module (DIMM), synchronous dynamic random access memory (SDRAM), etc. In a specific embodiment, the DRAM of the memory component may comply with standards promulgated by JEDEC, such as JESD79F for DDR SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, JESD79-4A for DDR4 SDRAM, JESD209 for low power DDR (LPDDR), JESD209-2 for LPDDR2, JESD209-3 for LPDDR3, and JESD209-4 for LPDDR4 (these standards are available at www.jedec.org). Such a standard (and similar standards) may be referred to as a DDR-based standard, and a communication interface of a storage device implementing such a standard may be referred to as a DDR-based interface.

[0027] The non-volatile memory 114 may be composed of byte-addressable write-in-place non-volatile memory devices, such as ferroelectric random access memory (FeTRAM), nanowire-based non-volatile memory, three-dimensional (3D crosspoint) memory, phase change memory (PCM), memory combined with memristor technology, magnetoresistive random access memory (MRAM), spin transfer torque (STT)-MRAM, SRAM, storage devices, etc. In some embodiments, the 3D crosspoint memory may include a transistor-free stackable crosspoint architecture, where memory cells are located at the intersection of word lines and bit lines and are individually addressable, and where bit storage is based on changes in bulk resistance. In other embodiments, the non-volatile memory 114 may include block-addressable non-volatile memory, such as NAND die (e.g., single-level cell (SLC), multi-level cell (MLC), triple-level cell (TLC) NAND memory, etc.).

[0028] The cache manager 108 determines whether data requested by an application transmitting a read request to the processor 102 using an address in the non-volatile memory 114 is in the cache memory 110, and if not in the cache memory 110, the cache manager 108 retrieves the requested data from the non-volatile memory 114 and stores it in the cache memory 110 so that it can be used for faster cache access for future accesses.

[0029] In one embodiment, cache manager 108 may be part of a two-level memory ("2LM") engine that manages main memory for a processor having first and second level memory devices. In other embodiments, cache manager 108 may be part of a combined caching agent and local agent configuration that is used to cache data from second level memory 114 in first level memory 110, such as provided with Intel Corporation QuickPath Interconnect logic. Other types of techniques and protocols may be used to implement cache manager 108 to maintain first level memory 110 as a cache for a larger second level memory 114.

[0030] The system 100 may also communicate with input / output (I / O) devices, which may include input devices (eg, keyboard, touch screen, mouse, etc.), display devices, graphics cards, ports, network interfaces, and the like.

[0031] Figure 2An embodiment of components of an address 200 for addressing a location in a non-volatile memory 114 as is known in the art is illustrated and includes tag bits 202 (such as most significant bits) that uniquely identify the address 200 in a cache group identified by group bits 204 of the address 200 and block offset bits 206 that include least significant bits of the address 200 for locating data in the cache location.

[0032] Figure 3 The cache location 300 in the cache memory 110 is shown. i (also referred to as a cache block), and includes: a valid / dirty flag 302 indicating that the cache location 300 i Whether it has valid data and dirty (eg, updated) data; a tag 304 having the tag bits 202 from the address 200 for the non-volatile memory 114; a cache location 300 i and one or more data bytes 308 for address 200 1 、308 2 ……308 b .

[0033] The priority information 306 indicates the priority of the data stored in the cache location / block 300. i The priority 306 may include an indication of the cache location 300. i If there are one or more bits for indicating priority, those bits may indicate a relative degree of recency of use, such that the priority or recency of use of data decreases over time if the data has not been accessed over time. Accessing cache location 300 i The data at the cache location will have the recency of use or priority increased to the highest value, such as the Most Recently Used (MRU) value. In some embodiments, there may be a finite number of priority or recency of use values, so that multiple cache locations may have the same recency of use value. For example, the degree of recency of use may be expressed by a Least Recently Used (LRU) class, where some classes indicate that the data has been accessed more recently than data associated with other LRU classes. In an alternative embodiment, each cache location 300 may have a priority or recency of use value. i There may be a unique priority 306 or recency of use in a least recently used (LRU) list, which would require more bits to represent. i In embodiments where the devices are grouped into groups, the priority or recency of use (eg, LRU class) will be relative to the same group 120.i Other cache locations in .

[0034] Figure 1 204 are shown as cache groups (eg, 120 i ), and each cache location is represented as a cache group 120 i Each address 200 can be directly mapped to a cache group 120 identified by a group bit 204. i Position 300 i Each address 200 will be mapped to a group 120 identified by the group bit 204 of the address. i A unique direct-mapped cache location in 300 DM , where multiple of the addresses 200 in the non-volatile memory 114 may map to the same direct mapped cache location.

[0035] In one embodiment, the cache manager 108 may apply a hash function to the tag bits 202 of the address 200 that produces a mapping to the group 120 identified by the group bits 204. i Direct mapped cache location 300 in i The hash function is used to generate a value for each cache group 120 having different tag bits 202 (the different tag bits 202 have the same group bit 204, that is, are mapped to the same cache group 120). i ) can result in the same hash value for the bits identifying the same direct-mapped cache location for those addresses. In this way, some of the addresses 200 having the same set of bits 204 will have the same direct-mapped cache location 300 in the cache memory 110. i In an alternative embodiment, the group 120 for an address may be determined by a subset of bits from the group bits 204. i For example, if each group has 8 cache locations / blocks, also called slots, the bottom 3 bits of group bits 204 may be used to determine the group 120 for address 200. i Direct-mapped cache locations in .

[0036] The cache manager 108 maintains remapping information 400 ( Figure 1 ), the remapping information 400 provides a cache location 300 corresponding to a direct-mapped cache location that is not for an address. iFor example, in certain situations described below, cache manager 108 may store data for address 200 at a location in the group for address that is not a direct-mapped cache location based on tag 202 of address 200. In such a case, remapping information 400 will indicate a location for address 200 that is not stored in its direct-mapped cache location.

[0037] Figure 4 The remapping information entry 400 is shown i In an embodiment, the remapping information entry 400 i The address 200 is stored in the cache memory 110 at a location 300 that is not a direct-mapped cache location for the address 200. i , of which 400 i It may include: a tag 402 of the address tag 202; a group 404 including group bits 204 for the address 200; and locations 406 or blocks in the group 404, where data for the address 200 and the address 200 are stored, the locations 406 or blocks including locations other than direct-mapped cache locations for the address 200.

[0038] In one embodiment, to save space, the remap information 400 may only maintain one group 120 for each location in the cache. i A limited number of remapping information entries 400 i To limit the size of the remapping information 400, the remapping information 400 i A table or other data structure may be included. In this case, the remapped and remapped information entry 400 i Those addresses not indicated in the can only be checked by checking the location 300 i The tag 304 in the cache is located to determine the cache location 300 that has data for the requested address. i .

[0039] In one embodiment, cache controller 106 including cache manager 108 and remapping information 400 may be implemented on an integrated circuit or chip forming processor 102 as part of a system on chip (SOC) implementation. In an alternative embodiment, cache manager 108 and remapping information 400 may be implemented as software executed by processor 102 to perform cache management at an operating system level.

[0040] Figure 5 Execution by the cache manager 108 to add cache locations 300 in the cache memory 110 is illustrated. iAn embodiment of adding data for a write to the nonvolatile memory 114 or for a read miss operation, where the requested data is not in the cache memory 110. Upon receiving (at block 500) a request for a target address 200 in the nonvolatile memory 114 T When data is to be added to cache memory 110, cache manager 108 uses group bit 204 to determine group 120. i and tag bits 202 to determine (at block 502) the direct mapped cache location 300 for the target address. DM , such as applying a hash function to tag bits 202 to determine the group 120 identified by group bits 204 i It is determined (at block 504) whether there is a direct-mapped cache location 300 DM Another address in, such as having the same T The tag bits 202 of the direct-mapped cache location 300 are different from the tag bits 304. If (at block 504) the determined direct-mapped cache location 300 DM If there is no data for a different address, that is, no valid data is stored, or data for the target address is stored, that is, the same tag bit 202 is present, then the target address 200 will be T The data is written (at block 506) to the direct mapped cache location 300 DM , and in the case of a direct-mapped cache location 300 DM The priority information 306 of the data being written at the location indicated (at block 508) as a high priority. For example, the most recently used value may be indicated as the value for the direct mapped cache location 300 being written. DM Priority information 306. For cache group 120 i Position 300 i Other priorities may have their priority or recency of use lowered.

[0041] If (at block 504) there is a direct mapped cache location 300 DM The cache manager 108 then determines the cache location 300 according to the cache location 300. DM The priority information 306 determines (at block 510) the direct-mapped cache location 300 DM The priority (e.g., recency of use) of the data at the direct-mapped cache location 300 is determined to be high priority, which may include a priority value greater than a threshold value or a most recently used (MRU) value. DM The priority of the data at the cache location is not high, that is, the data has a relatively low recency of use, then if (at block 512) the direct-mapped cache location 300DM If the data at is dirty, then the cache will be fetched from direct mapped cache location 300. DM Data is demoted to direct mapped cache location 300 DM From block 512, control continues back to block 506 to write the data for the target address to the direct mapped cache location 300. DM If direct-mapped cache location 300 DM If the data at is not dirty (ie, updated), then the direct-mapped cache location 300 DM It will simply be overwritten at block 506 .

[0042] If (at block 504) the direct-mapped location 300 DM If the priority of the data at the target address is high priority, or a predetermined threshold priority or recency is used, the cache manager 108 determines (at block 514) whether there is a target address 200 based on the group bit 204 that does not have data. T Mapped to cache location 300 in the set i If such an empty position is found 300 i , the cache manager 108 will target the target address 200 T The data and target address are written (at block 516) to the group 120 that does not have data. i Position 300 i . Will target the cache location 300 being written i The priority 306 of is indicated (at block 518) as high. The cache manager 108 also remaps the entry 400 in the information 400 i The indication (at block 520) has the value set to the target address 200 T The tag 202 of the tag 402 is set to the target address 200 T The set 406 of the set bits 204 and the set to which the data is written to the cache location 300 i The position in the group 406. If there is a maximum number of entries for the group 400 i , then the new entry 400 i Will replace the group 120 i Another entry in the remapping information 400.

[0043] If (at block 514) there is no target address 200 that does not have data (ie, is available to be written to), T Group bit 204 maps to group 120 i , the cache manager 108 determines (at block 522) that the group 120 has data with a low priority.i Position 300 i , such as the least recently used priority 306. If (at block 524) the data at the determined location is dirty, it is demoted. T Data and destination address 200 T Write (at block 526) to group 120 i Then, control continues to block 518 to update the position 300i to be written. i and the priority of the remapping information 400 .

[0044] use Figure 5 , first considers a direct mapped cache location for the data being added to the cache, and if the direct mapped cache location already has high priority cache data with high recency of use, then another location in the cache set for the target address may be selected to store the data for the target address. At this point, the cache manager 108 switches from direct mapped cache to cache associativity. With the described embodiment, used locations other than direct mapped cache locations are indicated in the remapping information to provide fast lookup of set associative locations for the target address of the added data.

[0045] Figure 6 An embodiment of the operations performed by the cache manager 108 to read data at a read address in the non-volatile memory 114 by first verifying whether the requested read data is in the cache memory 110. Upon receiving (at block 600) a request for a read address 200 in the non-volatile memory 114, the cache manager 108 may execute a read operation to obtain data from the non-volatile memory 114. R When a read request is received, the cache manager 108 determines (at block 602) the cache address for the read address 200 R Direct mapped cache location 300 DM , use group bit 204 to determine group 120 i and tag bit 202 to identify group 120 i A specific location in 300 i The cache manager 108 may apply a hash function to the tag bits 202 to determine the group 120 identified by the group bits 204. i The cache manager 108 determines (at block 604) whether there is a cache location for the direct-mapped cache location 300. DM Read address 200 in R Data such as data with respect to read address 200 R The tag bits 202 of the direct-mapped cache location 300 are the same as the tag bits 304. If (at block 604) the determined direct-mapped cache location 300DM Indeed, there is a read address 200 R , then cache location 300 will be directly mapped DM The data at is returned (at block 606) to the read request, i.e., a cache hit, and the direct-mapped cache location 300 is cached. DM The priority information 306 indicates (at block 608) high, such as most recently used or high LRU class.

[0046] If (at block 604) the cache location 300 is directly mapped DM The data at address 200 does not have R , the cache manager 108 determines (at block 610) whether the remapping information 400 has an entry 400. i , entry 400 i The tag 402 and group 404 bits match the read address 200 R The tag 202 and group bit 204. If there is a read address 200 R Remapping information entry 400 i , the cache manager 108 then determines the entry 400 i Determine (at block 612) the read address 200 R The location in the group 406 of FIG. 406 is returned (at block 614 ) to the read request, and the priority information 308 for the read data at the location 406 is indicated (at block 616 ) as high.

[0047] If (at block 610) the remap information 400 does not have an entry 400 i , where entry 400 i has a match to the read address 200 R If the tag 202 and group 204 bits of the cache address 200 are the tag 402 and group 404 bits of the cache address 200, the cache manager 108 determines (at block 618) whether there is a read address 200. R The mapped address has a match with the read address 200 R The position 300 of the group of label 202 and label 304 i , a set-associative tag search. If so, the cache manager 108 indicates (at block 620) in the remap information 400 the read address 200 in field 402 R The tag 202 and the entry 400 i The position of the tag in the field 406 in the group 300 i If there are the maximum number of entries for the group, create an entry for reading data 400 i Can replace the group 120i The entry 400 in the remapping information 400 j Then, control continues to block 614 to return the data at the determined location.

[0048] If (at block 618) there is no read address 200 R Mapped to has read address 200 R Cache location 300 in the group i , there is a cache miss, and the cache manager 108 accesses (at block 622) the data at the read address from the non-volatile memory 114 to return to the read request. The cache manager 108 will then execute (at block 624) Figure 5 The operations in the embodiment of the present invention are to add the read data for the read miss to the cache location 300 in the cache memory 110. i .

[0049] use Figure 6 In an embodiment of the present invention, the cache manager 108 first uses the direct mapped cache to check the direct mapped cache location for the requested read data, and if not there, uses the remapping information 400 to determine whether the requested read data is in a mapped cache location 300 other than the direct mapped cache location. i If the remapping information 400 does not provide a cache location with the requested data, the cache manager 108 switches to a set associative cache to perform a tag search to search for a tag of the requested read address at each cache location in the set.

[0050] Figure 7An embodiment of a system 700 is illustrated in which the cache memory 110 may be deployed as a cache memory 710 and the non-volatile memory 114 may be deployed as a system memory device 708 and / or a storage device. The system includes a processor 704 in communication via a bus 706 with a system memory device 708 in which executing programs, operands, and parameters are cached, and another memory device 710, which may include a volatile or other fast access memory device to cache data for the system memory 708. The processor 704 may also communicate with input / output (I / O) devices 712a, 712b, which may include input devices (e.g., keyboard, touch screen, mouse, etc.), display devices, graphics cards, ports, network interfaces, etc. Memory 708 and cache 710 may be coupled to an interface on the system 700 motherboard, mounted on the system 700 motherboard, or deployed in an external memory device or accessible over a network.

[0051] It should be appreciated that references throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in at least one embodiment of the present invention. Therefore, it is emphasized and should be appreciated that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various parts of this specification do not necessarily refer to the same embodiment. In addition, particular features, structures, or characteristics may be combined as appropriate in one or more embodiments of the present invention.

[0052] Similarly, it should be appreciated that in the foregoing description of embodiments of the invention, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure, thereby aiding in the understanding of one or more of the various inventive aspects. However, this disclosure method should not be interpreted as reflecting the intent that the claimed subject matter requires more features than those expressly recited in each claim. On the contrary, as reflected in the appended claims, inventive aspects lie in not all of the features of a single foregoing disclosed embodiment. Therefore, the claims appended to the detailed description are hereby expressly incorporated into the detailed description.

[0053] Reference characters such as b, i, and n used herein are used herein to designate variable numbers of instances of elements, which may represent the same or different values, and may represent the same or different values ​​when used with different or the same elements in different described instances.

[0054] Example

[0055] The following examples pertain to further embodiments.

[0056] Example 1 is a device for immediate cache associativity that switches between using a set-associative cache and a direct-mapped cache, the device comprising: a cache memory; a byte-addressable write-in-place non-volatile memory; and a cache manager that: determines a direct-mapped cache location in the cache memory based on a target address in the non-volatile memory; in response to the direct-mapped cache location storing data for another address in the non-volatile memory, writes the data for the target address at an available cache location in the cache memory that is different from the direct-mapped cache location; and in response to the direct-mapped cache location not storing data for another address in the non-volatile memory, writes the data for the target address in the direct-mapped cache location.

[0057] In Example 2, the subject matter of Examples 1 and 3-10 may optionally include mapping each address from the non-volatile memory to a plurality of groups of cache locations in the cache memory, wherein each address from the non-volatile memory maps to one of the plurality of groups, and wherein data for a target address is written to an available cache location in the group of cache locations to which the target address is mapped.

[0058] In Example 3, the subject matter of Examples 1, 2, and 4-10 can optionally include the cache manager further: generating remapping information including a number of remapped addresses for each set that is less than the number of cache locations in each set.

[0059] In Example 4, the subject matter of Examples 1-3 and 5-10 may optionally include that the cache manager further: indicates in the remapping information at least a portion of the target address and an available cache location in the cache memory, wherein the available cache location is different from the directly mapped cache location where the data for the target address is written.

[0060] In Example 5, the subject matter of Examples 1-4 and 6-10 may optionally include that the cache manager further: receives a read request for a read address in a non-volatile memory; in response to a direct-mapped cache location in the cache memory having data for the read address, returns the data for the read address from the direct-mapped cache location for the read address; in response to the direct-mapped cache location not including the data for the read address, determines whether the read address is indicated in the remapping information at a cache location in the cache memory that is different from the direct-mapped cache location for the read address; and in response to determining that the read address is indicated in the remapping information, returns the data for the read address indicated in the remapping information.

[0061] In Example 6, the subject matter of Examples 1-5 and 7-10 may optionally include that the cache manager further: in response to determining that the remapping information does not indicate the read address, determining whether the read address is in one of a set of cache locations to which the read address is mapped; and in response to determining that the read address is in one of the set of cache locations, returning data for the read address at one of the cache locations in the group.

[0062] In Example 7, the subject matter of Examples 1-6 and 8-10 may optionally include that the cache manager further: in response to the direct-mapped cache location storing data for another address, determining whether the data in the direct-mapped cache location in the cache memory has a high priority; and in response to determining that the data in the direct-mapped cache location does not have a high priority, writing the data for the target address at the direct-mapped cache location, wherein in response to the data in the direct-mapped cache location having a high priority, the data for the target address is written to an available cache location.

[0063] In Example 8, the subject matter of Examples 1-7 and 9-10 may optionally include data in the cache memory having a high priority or a low priority based on the recency of access to the data, wherein relatively more recently accessed data has a high priority and relatively less recently accessed data does not have a high priority.

[0064] In Example 9, the subject matter of Examples 1-8 and 10 may optionally include that the cache manager further: processes cache locations in a group of multiple groups of cache locations in a cache memory to which the target address is mapped to determine one of the cache locations in the group with a low priority, wherein the available cache locations to which the data is written include the cache location in the group with the lower priority to which the target address is mapped.

[0065] In Example 10, the subject matter of Examples 1-9 can optionally include: a processor including an integrated circuit; and a cache controller implemented on the processor integrated circuit die. The cache controller includes a cache manager and manages access to the cache memory and communicates with the non-volatile memory.

[0066] Example 11 is a system for immediate cache associativity that switches between using a set-associative cache and a direct-mapped cache, the system comprising: a cache memory; a non-volatile memory; and a processor, the processor comprising a cache manager that: determines a direct-mapped cache location in the cache memory based on a target address in the non-volatile memory; in response to the direct-mapped cache location storing data for another address in the non-volatile memory, writes the data for the target address at an available cache location in the cache memory that is different from the direct-mapped cache location; and in response to the direct-mapped cache location not storing data for another address in the non-volatile memory, writes the data for the target address in the direct-mapped cache location.

[0067] In Example 12, the subject matter of Examples 11 and 13-18 may optionally include mapping each address from the non-volatile memory to a plurality of groups of cache locations in the cache memory, wherein each address from the non-volatile memory maps to one of the plurality of groups, and wherein data for a target address is written to an available cache location in the group of cache locations to which the target address is mapped.

[0068] In Example 13, the subject matter of Examples 11, 12, and 14-18 may optionally include that the cache manager further: indicates in the remapping information at least a portion of the target address and an available cache location in the cache memory, wherein the available cache location is different from the directly mapped cache location where the data for the target address is written.

[0069] In Example 14, the subject matter of Examples 11-13 and 15-18 may optionally include that the cache manager further: receives a read request for a read address in a non-volatile memory; in response to a direct-mapped cache location in the cache memory having data for the read address, returns the data for the read address from the direct-mapped cache location for the read address; in response to the direct-mapped cache location not including the data for the read address, determines whether the read address is indicated in the remapping information at a cache location in the cache memory that is different from the direct-mapped cache location for the read address; and in response to determining that the read address is indicated in the remapping information, returns the data for the read address indicated in the remapping information.

[0070] In Example 15, the subject matter of Examples 11-14 and 16-18 may optionally include the cache manager further: in response to determining that the remapping information does not indicate the read address, determining whether the read address is in one of a set of cache locations to which the read address is mapped; and in response to determining that the read address is in one of the set of cache locations, returning data for the read address at one of the cache locations in the group.

[0071] In Example 16, the subject matter of Examples 11-15 and 17-18 may optionally include that the cache manager further: in response to the direct-mapped cache location storing data for another address, determining whether the data in the direct-mapped cache location in the cache memory has a high priority; and in response to determining that the data in the direct-mapped cache location does not have a high priority, writing the data for the target address at the direct-mapped cache location, wherein in response to the data in the direct-mapped cache location having a high priority, the data for the target address is written to an available cache location.

[0072] In Example 17, the subject matter of Examples 11-16 and 18 may optionally include data in the cache memory having a high priority or a low priority based on the recency of access to the data, wherein relatively more recently accessed data has a high priority and relatively less recently accessed data does not have a high priority.

[0073] In Example 18, the subject matter of Examples 11-17 may optionally include that the cache manager further: processes cache locations in a group of multiple groups of cache locations in a cache memory to which the target address is mapped to determine one of the cache locations in the group with a low priority, wherein the available cache locations to which the data is written include the cache location in the group with the lower priority to which the target address is mapped.

[0074] Example 19 is a method for immediate cache associativity, switching between using a set associative cache and a direct mapped cache for a cache memory having a cache location that is a cache for a non-volatile memory, the method comprising: determining a direct mapped cache location in the cache memory based on a target address in the non-volatile memory; in response to the direct mapped cache location storing data for another address in the non-volatile memory, writing the data for the target address at an available cache location in the cache memory different from the direct mapped cache location; and in response to the direct mapped cache location not storing data for another address in the non-volatile memory, writing the data for the target address in the direct mapped cache location.

[0075] In Example 20, the subject matter of Examples 19 and 21-25 may optionally include mapping each address from the non-volatile memory to a plurality of groups of cache locations in the cache memory, wherein each address from the non-volatile memory maps to one of the plurality of groups, and wherein data for a target address is written to an available cache location in the group of cache locations to which the target address is mapped.

[0076] In Example 21, the subject matter of Examples 19, 20, and 22-25 may optionally include indicating in the remapping information at least a portion of the target address and an available cache location in the cache memory, wherein the available cache location is different from the directly mapped cache location where data for the target address is written.

[0077] In Example 22, the subject matter of Examples 19-21 and 23-25 ​​may optionally include: receiving a read request for a read address in a non-volatile memory; in response to a direct-mapped cache location in a cache memory having data for the read address, returning the data for the read address from the direct-mapped cache location for the read address; in response to the direct-mapped cache location not including the data for the read address, determining whether the read address is indicated in remapping information at a cache location in the cache memory that is different from the direct-mapped cache location for the read address; and in response to determining that the read address is indicated in the remapping information, returning the data for the read address indicated in the remapping information.

[0078] In Example 23, the subject matter of Examples 19-22 and 24-25 may optionally include: in response to determining that the remapping information does not indicate a read address, determining whether the read address is in one of a set of cache locations to which the read address is mapped; and in response to determining that the read address is in one of the set of cache locations, returning data for the read address at one of the cache locations in the group.

[0079] In Example 24, the subject matter of Examples 19-23 and 25 may optionally include: in response to the direct-mapped cache location storing data for another address, determining whether the data in the direct-mapped cache location in the cache memory has a high priority; and in response to determining that the data in the direct-mapped cache location does not have a high priority, writing the data for the target address at the direct-mapped cache location, wherein in response to the data in the direct-mapped cache location having a high priority, the data for the target address is written to an available cache location.

[0080] In Example 25, the subject matter of Examples 19-24 may optionally include: based on the recency of access to the data, the data in the cache memory has a high priority or a low priority, wherein relatively more recently accessed data has a high priority and relatively less recently accessed data does not have a high priority.

[0081] Example 26 is a device for immediate cache associativity that switches between using a set-associative cache and a direct-mapped cache for a cache memory having a cache location that is a cache for a non-volatile memory, the device comprising: a component for determining a direct-mapped cache location in the cache memory based on a target address in the non-volatile memory; a component for writing the data for the target address at an available cache location in the cache memory different from the direct-mapped cache location in response to the direct-mapped cache location storing data for another address in the non-volatile memory; and a component for writing the data for the target address in the direct-mapped cache location in response to the direct-mapped cache location not storing data for another address in the non-volatile memory.

[0082] Example 27 is an apparatus comprising means for performing a method as claimed in any preceding claim.

[0083] Example 28 is a machine-readable storage comprising machine-readable instructions which, when executed, implement a method as claimed in any preceding claim or implement an apparatus as claimed in any preceding claim.

Claims

1. An apparatus for immediate cache associativity, switching between using a set associative cache and a direct mapped cache, the apparatus comprising: Cache memory; Byte addressable writes to non-volatile memory; and A cache manager that: determining a direct mapped cache location in a cache memory based on a target address in a non-volatile memory; In response to the direct-mapped cache location storing data for another address in the non-volatile memory, writing the data for the target address at an available cache location in a cache memory different from the direct-mapped cache location; and In response to the direct-mapped cache location not storing data for another address in the non-volatile memory, writing data for the target address in the direct-mapped cache location, wherein each address from the non-volatile memory maps to one of a plurality of sets of cache locations in the cache memory, wherein each address from the non-volatile memory maps to one of the plurality of sets, and wherein data for the target address is written to an available cache location in the set of cache locations to which the target address maps, and The cache manager also: At least a portion of the target address and an available cache location in the cache memory is indicated in the remapping information, the available cache location being different from the directly mapped cache location at which data for the target address is written.

2. The apparatus of claim 1, wherein the cache manager further comprises: Remapping information is generated that includes a number of remapped addresses for each set that is less than the number of cache locations in each set.

3. The apparatus of claim 1, wherein the cache manager further comprises: receiving a read request for a read address in a non-volatile memory; and in response to a direct-mapped cache location in the cache memory having data for the read address, returning the data for the read address from the direct-mapped cache location for the read address; In response to the direct-mapped cache location not including data for the read address, determining whether the read address is indicated in the remapping information at a cache location in the cache memory other than the direct-mapped cache location for the read address; and In response to determining that a read address is indicated in the remapping information, data for the read address indicated in the remapping information is returned.

4. The apparatus of claim 3, wherein the cache manager further comprises: In response to determining that the remapping information does not indicate the read address, determining whether the read address is in one of a set of cache locations to which the read address is mapped; and In response to determining that the read address is in one of the set of cache locations, data for the read address at one of the cache locations in the set is returned.

5. The apparatus of claim 1, wherein the cache manager further comprises: responsive to the direct-mapped cache location storing data for another address, determining whether the data in the direct-mapped cache location in the cache memory has a high priority; and In response to determining that the data in the direct-mapped cache location does not have a high priority, writing data for the target address at the direct-mapped cache location, wherein in response to the data in the direct-mapped cache location having a high priority, writing the data for the target address to an available cache location.

6. The apparatus of claim 5, wherein data in the cache memory has a high priority or a low priority based on the recency of access to the data, wherein relatively more recently accessed data has a high priority and relatively less recently accessed data does not have a high priority.

7. The apparatus of claim 6, wherein the cache manager further comprises: Cache locations in a group of multiple groups of cache locations in a cache memory to which a target address is mapped are processed to determine one of the cache locations in the group that has a low priority, wherein available cache locations to which data is written include the cache location in the group with the lower priority to which the target address is mapped.

8. The apparatus according to any one of claims 1 to 7, further comprising: processors, including integrated circuits; as well as A cache memory controller is implemented on the processor integrated circuit die, wherein the cache memory controller includes a cache manager and manages access to the cache memory and communicates with the non-volatile memory.

9. A system for immediate cache associativity, switching between using a set associative cache and a direct mapped cache, the system comprising: Cache memory; non-volatile memory; and A processor comprising a cache manager to: determining a direct mapped cache location in a cache memory based on a target address in a non-volatile memory; In response to the direct-mapped cache location storing data for another address in the non-volatile memory, writing the data for the target address at an available cache location in a cache memory different from the direct-mapped cache location; and In response to the direct-mapped cache location not storing data for another address in the non-volatile memory, writing data for the target address in the direct-mapped cache location, wherein each address from the non-volatile memory maps to one of a plurality of sets of cache locations in the cache memory, wherein each address from the non-volatile memory maps to one of the plurality of sets, and wherein data for the target address is written to an available cache location in the set of cache locations to which the target address maps, and The cache manager also: At least a portion of the target address and an available cache location in the cache memory is indicated in the remapping information, the available cache location being different from the directly mapped cache location at which data for the target address is written.

10. The system of claim 9, wherein the cache manager further comprises: receiving a read request for a read address in a non-volatile memory; and in response to a direct-mapped cache location in the cache memory having data for the read address, returning the data for the read address from the direct-mapped cache location for the read address; In response to the direct-mapped cache location not including data for the read address, determining whether the read address is indicated in the remapping information at a cache location in the cache memory other than the direct-mapped cache location for the read address; and In response to determining that a read address is indicated in the remapping information, data for the read address indicated in the remapping information is returned.

11. The system of claim 10, wherein the cache manager further comprises: In response to determining that the remapping information does not indicate the read address, determining whether the read address is in one of a set of cache locations to which the read address is mapped; and In response to determining that the read address is in one of the set of cache locations, data for the read address at one of the cache locations in the set is returned.

12. The system of claim 9, wherein the cache manager further comprises: responsive to the direct-mapped cache location storing data for another address, determining whether the data in the direct-mapped cache location in the cache memory has a high priority; and In response to determining that the data in the direct-mapped cache location does not have a high priority, writing data for the target address at the direct-mapped cache location, wherein in response to the data in the direct-mapped cache location having a high priority, writing the data for the target address to an available cache location.

13. The system of claim 12, wherein data in the cache memory has a high priority or a low priority based on recency of access to the data, wherein relatively more recently accessed data has a high priority and relatively less recently accessed data does not have a high priority.

14. The system of claim 13, wherein the cache manager further comprises: Cache locations in a group of multiple groups of cache locations in a cache memory to which a target address is mapped are processed to determine one of the cache locations in the group that has a low priority, wherein available cache locations to which data is written include the cache location in the group with the lower priority to which the target address is mapped.

15. A method for immediate cache associativity, switching between using a set associative cache and a direct mapped cache, for a cache memory having cache locations as a cache for a non-volatile memory, the method comprising: determining a direct mapped cache location in a cache memory based on a target address in a non-volatile memory; In response to the direct-mapped cache location storing data for another address in the non-volatile memory, writing the data for the target address at an available cache location in a cache memory different from the direct-mapped cache location; and In response to the direct-mapped cache location not storing data for another address in the non-volatile memory, writing data for the target address in the direct-mapped cache location, wherein each address from the non-volatile memory maps to one of a plurality of sets of cache locations in the cache memory, wherein each address from the non-volatile memory maps to one of the plurality of sets, and wherein data for the target address is written to an available cache location in the set of cache locations to which the target address maps, and The method further comprises: At least a portion of the target address and an available cache location in the cache memory is indicated in the remapping information, the available cache location being different from the directly mapped cache location at which data for the target address is written.

16. The method of claim 15, further comprising: receiving a read request for a read address in a non-volatile memory; as well as in response to a direct-mapped cache location in the cache memory having data for the read address, returning the data for the read address from the direct-mapped cache location for the read address; In response to the direct-mapped cache location not including data for the read address, determining whether the read address is indicated in the remapping information at a cache location in the cache memory other than the directly-mapped cache location for the read address; as well as In response to determining that a read address is indicated in the remapping information, data for the read address indicated in the remapping information is returned.

17. The method of claim 16, further comprising: In response to determining that the remapping information does not indicate the read address, determining whether the read address is in one of a set of cache locations to which the read address is mapped; as well as In response to determining that the read address is in one of the set of cache locations, data for the read address at one of the cache locations in the set is returned.

18. The method of claim 15, further comprising: responsive to the direct mapped cache location storing data for another address, determining whether the data in the direct mapped cache location in the cache memory has a high priority; as well as In response to determining that the data in the direct-mapped cache location does not have a high priority, writing data for the target address at the direct-mapped cache location, wherein in response to the data in the direct-mapped cache location having a high priority, writing the data for the target address to an available cache location.

19. The method of claim 18, wherein data in the cache memory has a high priority or a low priority based on recency of access to the data, wherein relatively more recently accessed data has a high priority and relatively less recently accessed data does not have a high priority.

20. An apparatus for immediate cache associativity, comprising means for performing the steps of the method according to any one of claims 15 to 19.

21. A computer readable medium comprising instructions which, when executed, cause a computer to perform the method according to any one of claims 15 to 19.

22. A computer program product comprising instructions which, when executed, cause a computer to perform the method according to any one of claims 15 to 19.

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