Integrated circuit package substrate having microstrip architecture and electrically grounded surface conductive layer

Abstract

Described herein are integrated circuit structures and related devices and methods having a package substrate with a microstrip architecture as the uppermost layer and a surface conductive layer electrically connected to an internal ground plane of the package substrate. In one aspect of the disclosure, the integrated circuit package substrate can have an internal ground plane, a dielectric layer, a microstrip signal layer as a top transmission signal layer, a solder resist layer, and a surface conductive layer electrically connected to the internal ground plane in the package substrate. In another aspect of the disclosure, the integrated circuit package substrate can include varying thicknesses of the dielectric and / or solder resist layers to optimize electrical performance by having the microstrip signal layer closer to the internal ground layer than the surface conductive layer.

Description

Technical Field

[0001] This disclosure generally relates to the field of semiconductor packaging, and more specifically, to methods and apparatus for semiconductor packaging with improved electrical performance. Background Technology

[0002] Semiconductor dies are typically connected to larger circuit boards, such as motherboards and other types of printed circuit boards (PCBs), via a package substrate. The package substrate typically has two sets of connection points: a first set for connecting to one or more dies, and a less densely packed second set for connecting to the PCB. The package substrate generally consists of alternating sequences of multiple organic insulating or dielectric layers and multiple patterned conductive layers forming traces between the insulating layers. Striplines and microstrips are two common integrated circuit designs used for package substrates. Stripline architectures have signal line layers sandwiched between two ground planes. Microstrip architectures have only a ground plane below the signal line layers. In most applications, striplines are preferred over microstrips because of their lower crosstalk, although they require additional layers. Continuous advancements in integrated circuit technology have led to a demand for package substrates with fewer layers, higher electrical performance, and lower crosstalk. Attached Figure Description

[0003] The embodiments described herein are illustrated in the accompanying drawings by way of example rather than limitation, in which similar reference numerals indicate similar features. The following drawings are illustrative, and other processing techniques or stages may be used depending on the subject matter described herein. The drawings are not necessarily drawn to scale. Furthermore, some general details have been omitted to avoid obscuring the inventive concepts described herein.

[0004] Figure 1 This is a schematic diagram of an exemplary integrated circuit package according to some embodiments of the present disclosure.

[0005] Figure 2A This is a schematic cross-sectional view of an exemplary integrated circuit package substrate having microstrip wiring and an electrically grounded conductive layer on the surface of the package substrate according to some embodiments of the present disclosure.

[0006] Figure 2B and 2C This is a schematic top plan view of an exemplary integrated circuit package substrate having microstrip wiring and an electrically grounded conductive layer on the surface of the package substrate according to some embodiments of the present disclosure.

[0007] Figures 3A-3F This is a schematic diagram of an exemplary integrated circuit package substrate having microstrip wiring and an electrically grounded metal layer on the surface of a package substrate, according to some embodiments of the present disclosure.

[0008] Figures 4A-4DThis is a schematic cross-sectional view of an exemplary integrated circuit package substrate illustrating the formation of an electrically grounded surface conductive layer according to some embodiments of the present disclosure.

[0009] Figure 5 This is a flowchart of an exemplary integrated circuit package substrate having a microstrip architecture and an electrically grounded conductive layer on the surface of a package substrate, according to some embodiments of the present disclosure.

[0010] Figure 6A This is a schematic cross-sectional view of an exemplary integrated circuit package having microstrip wiring and an electrically grounded surface conductive layer according to some embodiments of the present disclosure, and showing the corrected impedance differential.

[0011] Figure 6B The corrected impedance derivative is illustrated according to some embodiments of this disclosure. Figure 6A A schematic diagram of the top plan view of the signal lines in the diagram.

[0012] Figure 7A and 7B This is a top view of a wafer and die that can be used in any embodiment of the IC structure disclosed herein.

[0013] Figure 7C It is a cross-sectional side view of an integrated circuit device that can be used in any embodiment of the integrated circuit structure disclosed herein.

[0014] Figure 8 It can be a cross-sectional side view of an integrated circuit device assembly that can include any embodiment of the integrated circuit structure disclosed herein.

[0015] Figure 9 It can be a block diagram of an exemplary computing device that may include any embodiment of the IC structure disclosed herein. Detailed Implementation

[0016] This document discloses an integrated circuit package substrate having a microstrip transmission line as a top signal metallization layer and a conductive layer on the surface of the package substrate electrically connected to a ground plane inside the package substrate, as well as related structures, apparatus, and methods. For example, in some embodiments, the integrated circuit package substrate may include an internal ground plane, a microstrip signal layer as a top transmission line layer, and a conductive layer on the surface of the package substrate electrically connected to the internal ground plane in the package substrate. In some embodiments, the integrated circuit package substrate may further include a dielectric layer between the internal ground plane and the microstrip signal layer, and a solder resist layer on the microstrip signal layer. In some embodiments, the integrated circuit package substrate may further include different thicknesses of the dielectric and solder resist layers to optimize electrical performance by having a microstrip signal layer that is closer to the internal ground plane than the surface ground layer. In some embodiments, the integrated circuit package substrate may include a modification of the microstrip transmission line geometry to match the impedance value of the region below or covered by the surface conductive layer with the impedance value of the region not covered by the surface conductive layer.

[0017] A typical microstrip circuit architecture includes a substrate, a ground plane structure disposed on the substrate, a dielectric layer disposed on the ground plane structure, and a conductor strip structure (i.e., a strip of conductive or superconducting material) disposed on the dielectric layer. In this arrangement, a single ground plane is used for a given conductor strip, and the conductor strip is separated from the ground plane by the dielectric layer. This type of transmission line can be called a "microstrip line".

[0018] A typical stripline circuit architecture includes a substrate, a lower ground plane disposed on the substrate, a lower dielectric layer disposed on the lower ground plane, a conductor strip disposed on the lower dielectric layer, an upper dielectric layer disposed on the conductor strip, and an upper ground plane disposed on the upper dielectric layer. In this arrangement, there are two ground planes for a given conductor strip, and the conductor strip is separated from each ground plane by a corresponding dielectric layer (i.e., the conductor strip is provided or sandwiched between two ground planes). This type of transmission line can be called a "stripline".

[0019] The package substrate can be multilayered, for example, in which multiple microstrip and stripline structures are stacked on top of each other to form a package substrate stack. In this architecture, the upper ground plane layer of the stripline structure can serve as the lower ground plane layer of the next microstrip or stripline structure stack, and the upper dielectric layer can serve as the substrate for depositing the next ground plane layer.

[0020] High-performance electronics typically combine stripline wiring with microstrip wiring because stripline wiring offers superior far-end crosstalk performance, such as reduced crosstalk and high thermomechanical reliability. From an electrical performance perspective, the superiority of stripline transmission lines may be at least partly due to the fact that stripline construction can support balanced wave propagation in both even and odd modes, achieving theoretically zero far-end crosstalk. However, the benefits of stripline performance are obtained at the cost of additional dielectric and ground planes, including increased overall package manufacturing costs and increased z-height (also referred to herein as thickness).

[0021] The various integrated circuit structures described herein provide package substrates for microstrip wiring with improved far-end crosstalk performance. Specifically, some embodiments disclosed herein provide a semiconductor package assembly including a package substrate having a microstrip architecture on an uppermost metallization layer and an electrically grounded metal layer on the surface of the package substrate electrically coupled to a ground plane inside the package substrate, to create a structure in which the microstrip signal line layer is a top transmission line layer sandwiched between two ground layers to reduce crosstalk and improve electrical performance. This document discloses an integrated circuit package including a package substrate having an inner ground plane layer, a dielectric layer, a microstrip transmission line layer, a solder resist layer, and an electrically grounded metal layer on the surface of the package substrate electrically connected to the inner ground plane layer of the microstrip line structure via vias. The inner ground layer may also be referred to herein as an inner ground plane and an inner ground plane layer. Thus, the various embodiments disclosed herein can provide an integrated circuit package in which, by adding a single layer to the package substrate, the microstrip line is actually sandwiched between top and bottom ground planes, as in a stripline structure. In the various embodiments disclosed herein, an electrically grounded surface metal layer (also referred to herein as a surface conductive layer, surface conductive plane, surface ground layer, or surface ground plane) may cover the entire exposed surface of the package substrate or only a portion of the exposed surface. In some embodiments, for example, the surface conductive layer may be an electroless metal layer constituting the frame of the die, such that the entire area not covered by the die, and optionally not covered by the underfill, is covered by the surface conductive layer. In some embodiments, the surface conductive layer may be patterned to cover only a portion of the surface of the package substrate, for example, covering a rectangular area on one side of the die and leaving the remaining surface uncovered. The various embodiments disclosed herein also provide for varying the layer thickness to optimize electrical performance by placing the signal layer closer to the internal ground plane than to the surface conductive layer.

[0022] In the following detailed description, aspects of exemplary embodiments are described using terminology commonly employed by those skilled in the art to convey the essence of the work to those skilled in the art. For example, as used herein, "high-k dielectric" refers to a material with a dielectric constant higher than silicon oxide. In another example, the term "interconnect" is used to describe any element formed of a conductive material for providing electrical connections to one or more components associated with an integrated circuit (IC) or / or electrical connections between various such components. Generally, "interconnect" can refer to both trenches (sometimes also called "lines") and vias. Typically, the term "trench" is used to describe conductive elements isolated by interconnect support layers, which typically include interlayer low-k dielectrics provided within the plane of the IC chip. Such trenches are typically stacked into several levels. On the other hand, the term "via" is used to describe conductive elements that extend through an insulating layer and interconnect two or more trenches of different conductive layers. For this purpose, vias are provided that are generally perpendicular to the plane of the IC package. Vias can interconnect two trenches in adjacent levels or two trenches in non-adjacent levels. Typically, microvias have a diameter of less than or equal to 150 micrometers (μm). The term "metallized stack" refers to one or more interconnects stacked together to provide connections to different circuit components of an IC package. As used herein, the terms "conductor strip," "interconnect," "wire," "conductor," "transmission line," "signal line," "trace," and "wiring" may be used interchangeably to describe the circuitry of an IC package.

[0023] Throughout this specification and in the claims, the term "connection" refers to a direct connection between connected things, such as an electrical, mechanical, or magnetic connection, without any intermediary means. The term "coupling" refers to a direct or indirect connection between things that are connected or indirectly connected via one or more passive or active intermediary means, such as a direct electrical, mechanical, or magnetic connection. The terms "circuit" or "module" can refer to one or more passive and / or active components arranged to cooperate with each other to provide a desired function. The term "signal" can refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal. The meanings of "a" and "described" include plural references. The meaning of "in" includes both "in" and "on".

[0024] Unless otherwise stated, the use of ordinal adjectives such as “first,” “second,” and “third” to describe common objects merely indicates that different instances of similar objects are being mentioned, and is not intended to imply that the objects described in this way must be in a given sequence, order, or any other manner in time or space.

[0025] For the purposes of this disclosure, the phrases “A and / or B” and “A or B” mean (A), (B), or (A and B). For the purposes of this disclosure, the phrases “A, B, and / or C” mean (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). When used in reference to measurement ranges, the term “between” includes the endpoints of the measurement range. As used herein, the notation “A / B / C” means (A), (B), and / or (C).

[0026] If applicable, the terms “left,” “right,” “front,” “upper,” “lower,” “rear,” “top,” “bottom,” “above,” “below,” “above,” “between,” etc., used in the specification and claims are for descriptive purposes and are not necessarily used to describe permanent relative positions. For example, another layer above or below a layer may be in direct contact with that layer or may have one or more interlayers. Furthermore, a layer between two layers may be in direct contact with both layers or may have one or more interlayers. Conversely, a first layer “above” a second layer is in direct contact with that second layer. Similarly, unless explicitly stated otherwise, a feature between two features may be in direct contact with an adjacent feature or may have one or more interlayers.

[0027] The specification uses the phrase "in an embodiment," which can refer to one or more of the same or different embodiments. Furthermore, as used with respect to embodiments of this disclosure, the terms "comprising," "having," etc., are synonyms.

[0028] Numerous details are set forth in the following description to provide a more thorough explanation of embodiments of the present disclosure. However, those skilled in the art will appreciate that embodiments of the present disclosure can be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the present disclosure.

[0029] Figure 1This is a cross-sectional view of a portion of an integrated circuit structure 100 having a package substrate according to various embodiments, the package substrate having microstrip wiring as an uppermost signal layer and a surface conductive layer electrically coupled to an internal ground plane. Component 100 may include an integrated circuit package having a die 102, a package substrate 104, and a conductive layer 106 electrically grounded and electrically coupled 138 to a ground plane within the package substrate on the top surface of the package substrate. Component 100 may include a die 102 connected to the package substrate 104, the package substrate 104 having a first-level interconnect side 108 and a second-level interconnect side 110. The device side of the die 102 may be coupled to the package substrate 104 via the first-level interconnect (FLI) 108. In some embodiments, the area between the die 102 and the package substrate 104 may be filled with an underfill 140, the underfill being a molding compound or any other suitable material for filling the gap between the die 102 and the package substrate 104. The underfill 140 can be applied using any suitable technique, such as transfer molding, capillary underfill, or epoxy flux as part of a thermally conductive bonding (TCB) process. In some embodiments, the underfill 140 may extend beyond the area defined by die 102. Component 100 may include multiple dies coupled to package substrate 104 or to another die in a stacked package (PoP) configuration. Package substrate 104 may be coupled to another electrical component (not shown), such as a motherboard, via secondary interconnect (SLI) 110. Package substrate 104 may include electrical pathways for signal or power routing between FLI 108 and SLI 110, as is known in the art.

[0030] As shown, the package substrate 104 may include a carrier 112 (also referred to herein as a substrate or core), a first metal layer 120, a first dielectric layer 122, a second metal layer 124, a second dielectric layer 126, a third metal layer 128, a third dielectric layer 130, a fourth metal layer 132, a solder resist layer 134, and conductive vias 136, 142, 144, and 146 connecting the different metal layers. Multiple metal and dielectric layers are formed on both sides of the carrier 112, but for simplicity, only the upper side of the carrier 112 is described in detail. The description of the metallized stack on the upper side of the carrier also applies to the metallized stack on the bottom side of the carrier 112.

[0031] In some embodiments, the carrier 112 may be rigid to provide a flat and stable surface to facilitate strict design rules during manufacturing, or may be, for example, an ultra-thin core (UTC) to reduce the z-height. The carrier 112 may be made of any suitable material, such as stainless steel, glass, silicon, glass fiber reinforced epoxy, etc. In some embodiments, the carrier 112 may include plated through-holes (PTH) 114. In some embodiments, the carrier 112 may be temporary, such that the encapsulation substrate is coreless, and may include a release layer on which a first metal layer 120 may be deposited. The first metal layer 120 may be a foil layer and may be made of any suitable metal, such as copper. The first metal layer 120 may be laminated onto the surface of the carrier 112, may be plated, or in other cases deposited using any suitable means. In some examples, the surface of the carrier 112 may include the first metal layer 120 such that when the first metal layer 120 is nickel, the carrier may be referred to as a nickel-clad carrier, or when the first metal layer 120 is copper, the carrier may be referred to as a copper-clad carrier, and so on. Nickel and copper are advantageous metals because they are easy to deposit. In some embodiments, the metal layer thickness can be between 3 μm and 20 μm.

[0032] The metallized sub-stack 116 may include a first metal layer 120, a first dielectric layer 122, a second metal layer 124, a second dielectric layer 126, and a third metal layer 128, forming a stripline architecture in which a signal layer (i.e., the second metal layer 124) is sandwiched between two ground layers (i.e., the first and third metal layers 120, 128). In some embodiments, the ground plane layers are continuous. In other embodiments (as shown), the ground plane layers are discontinuous.

[0033] The metallized sub-stack 118 may include a third metal layer 128, a third dielectric layer 130, and a fourth metal layer 132, which is a microstrip architecture in which the signal layer (i.e., the fourth metal layer 132) is above the ground layer (i.e., the third metal layer 128). A solder resist layer 134 may be deposited on the fourth metal layer and patterned to provide conductive contacts for the FLI 108 and the surface ground layer 106.

[0034] One or more dielectric layers 122, 126, 130 can be formed using any suitable process and any suitable material, including, for example, chemical vapor deposition (CVD), film lamination, slot coating and curing, atomic layer deposition (ALD), or spin coating. Examples of dielectric materials that can be used include, but are not limited to, epoxy-based materials / films, ceramic / silica-filled epoxide films, polyimide films, filled polyimide films, other organic materials, and other inorganic dielectric materials known from semiconductor processing, as well as silicon dioxide (SiO2), carbon-doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicones such as silsesquioxanes, siloxanes, or organosilicon glass (OSG). One or more dielectric layers can be formed using dielectric materials known for their suitability in integrated circuit structures, such as materials having a low dielectric constant (k) and / or low dielectric loss (Df). Typically, low-k films have a lower dielectric constant than SiO2, which has a dielectric constant of approximately 4.0. Low-k films with dielectric constants of approximately 2.7 to approximately 3 are typical in current semiconductor manufacturing processes. Typically, low-Df films have a Df value of less than 0.004. The dielectric layer may include vias or air gaps to further reduce its dielectric constant.

[0035] In some embodiments, the thickness of the dielectric layer may be increased to allow planarization, for example, by grinding, by lapping, chemical mechanical polishing (CMP), or by wet or dry etching. In some embodiments, the thickness of the dielectric layer may be minimized to reduce the etching time required to expose one or more vias in subsequent processing operations. In some embodiments, the dielectric layer thickness may be 3 μm to 30 μm.

[0036] In some embodiments, electrical interconnects are formed by patterning a dielectric layer to create one or more trenches or via openings, and then a conductive material can be used to fill the trenches or via openings to form the interconnects. Typically, a feature used to form electrical interconnects is a pit of arbitrary shape formed in the substrate or a layer deposited on the substrate. For example, any suitable through-via forming technique can be used to form through-via conductive pathways 136, 138, 142, 144, 146. In some embodiments, conductive trenches or via openings can be formed by laser drilling, by conventional wet or dry etching semiconductor processing techniques, or by another suitable process. Vias can be formed on a single dielectric layer or can be formed through multiple dielectric layers, and can have contact pads on the top and bottom surfaces. In some embodiments, through-vias can include multiple conductive trace layers connected by multiple vias. The diameter of the via can be any suitable scale and can vary based on the I / O scale of the package substrate. In some embodiments, the diameter / size of the via can be from 50 micrometers (μm) to 100 μm. In some embodiments, the diameter of the via can be varied from top to bottom, such that the bottom diameter is smaller than the top diameter.

[0037] In some embodiments, electrical interconnects can be formed by depositing a photoresist and patterning it using, for example, photolithography. Conductive material can be deposited into openings formed by the patterned photoresist layer to form conductive traces and pads. Conductive vias can be formed by depositing and patterning a second photoresist layer over a first photoresist layer and filling the openings with conductive material. As is known in the art, the photoresist layer can be formed using any suitable process such as lamination and can be positively or negatively charged to generate cross-linked and non-cross-linked portions using ultraviolet light used to pattern the conductive material layer. The non-cross-linked portions decompose to form openings in which conductive material can be deposited. In some embodiments, electroless plating can be used to form the conductive material. In some embodiments, copper plating, copper sputtering, etc., can be used to form conductive lines and pads. Although Figure 1 The vias shown are illustrated as having generally parallel sidewalls, but vias can have any profile shape (e.g., as specified by the manufacturing operations used to form the via). In some embodiments, the vias have generally vertical sidewalls. In some embodiments, the vias have sloping sidewalls to form a tapered via.

[0038] The conductive material can be any type of conductive metal. In some embodiments, the conductive material can be copper. In some embodiments, the opening can be filled with the same or different conductive materials. For example, the wire can include or be made of copper (Cu) or substantially made of copper (Cu), while the via can include or be made of or substantially made of one or more bulk materials, including aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), nickel (Ni), iron (Fe), and molybdenum (Mo) and / or one or more alloys including aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), magnesium (Mg), boron (B), phosphorus (P), nitrogen (N), carbon (C), and sulfur (S).

[0039] According to known methods, such as the semi-additive process (SAP), additional deposits in the package substrate can be constructed by laminating, curing, drilling and desmearing the dielectric layer, and then performing a plating process to form a conductive layer or conductive lines and conductive vias.

[0040] like Figure 1 As shown, the surface conductive layer 106 may be plated onto the package substrate and electrically connected to the internal ground plane (i.e., the third metal layer 128) via vias 136, 138. The surface ground layer 106 may be electrically connected to the internal ground plane via multiple vias. The surface ground layer 106 may be any suitable conductor serving as the surface conductive layer, such as copper or nickel. In some embodiments, the surface conductive layer 106 may be a metal layer plated on the top layer of the package substrate (i.e., on top of the solder resist layer 134). In some embodiments, the surface conductive layer 106 is continuous and covers the entire surface of the package substrate not covered by the die 102 and (if used) the underfill 140. In some embodiments, the surface conductive layer 106 may have multiple segments and may cover only a portion of the package substrate surface.

[0041] Figure 2A This is a schematic cross-sectional view of an exemplary integrated circuit package 200 having microstrip wiring and a surface conductive layer electrically connected to a ground plane inside the package substrate. Component 200 may include an integrated circuit package having a die 202, a package substrate 204, and a surface conductive layer 206 serving as the top layer of the package substrate, electrically coupled to a ground plane within the package substrate. The device side of the die 202 may be coupled to the package substrate 204 via a first-level interconnect (FLI) 208, and the area between the die 202 and the package substrate 204 may be filled with an underfill 210, which may be a molding compound or any other suitable material for filling gaps.

[0042] Figure 2AA simplified schematic diagram is shown of a metallized stack having only microstrip architectures 216, 218 on both sides of a substrate 212. In some embodiments, the microstrip package may include a core (often referred to as an ultrathin core (UTC)) from 100 micrometers (μm) to 200 micrometers thick, having stacked layers of core-based substrates on both sides of the core. In some embodiments, the microstrip package may be coreless. Figure 2A As shown, the microstrip layers on the top side 216 and bottom side 218 of the core 212 include internal ground plane layers 220 and 221, dielectric layers 222 and 223, microstrip trace layers 224 and 225 serving as upper and lower signal metallization layers, and solder resist layers 230 and 231. As shown, the ground layer on the top side of the core 220 is electrically connected to the ground layer on the bottom side of the core 221 through a plated via 214. In some embodiments, such as... Figure 2A As shown, solder resist layers 230 and 231 can be deposited on the upper and / or lower microstrip trace layers. The surface ground layer 206 can be electrically connected to the internal ground plane 220 through vias 226, 228, 234, and 236.

[0043] Figure 2B and 2C yes Figure 2A A schematic diagram of the top plan view of an exemplary integrated circuit package. Figure 2B A die 202, an underfill 210 extending beyond the die, and a surface conductive layer 206a are shown, the surface conductive layer 206a forming a framework between the die 202 and the underfill 210. The surface conductive layer 206a is offset from the die 202 by the underfill 210. In some embodiments, such as Figure 2B As shown, the surface conductive layer 206a is a continuous structure covering the remaining surface area of ​​the package substrate. Although only one die is shown, multiple dies can be attached to the package substrate. Figure 2C The diagram shows a die 202, an underfill 210 extending beyond the die 202, and surface conductive planes 206b and 206c, which are not continuous and only cover a portion of the package substrate surface. In some embodiments, such as Figure 2B and 2CAs shown, the surface conductive layer can be a single conductive layer or multiple conductive layers, and can have any suitable shape and size. For example, the surface conductive layer can be formed as a rectangle, square, L-shape, or any other shape. The surface conductive layer can be formed from any suitable conductive material. In some embodiments, the surface conductive material is made of copper. In some embodiments, the surface conductive material is made of nickel. In some embodiments, the surface conductive material is made of aluminum. In some embodiments, the surface conductive material is made of palladium. In some embodiments, the surface conductive material is made of gold. In some embodiments, the surface conductive material is made of silver. In some embodiments, the surface conductive material is made of one or more alloys, such as alloys of copper, nickel, aluminum, palladium, gold, and / or silver. In some embodiments, the surface conductive material is made of a combination of materials, such as a combination of copper, nickel, aluminum, palladium, gold, and / or silver, and / or alloys thereof. The surface conductive layer can be one or more layers. In some embodiments, for example, the surface conductive layer can include a nickel / palladium / gold plating layer. The surface conductive layer can be formed on the solder resist surface by any suitable means, such as electroless metal plating or metal sputtering. Refer to the following regarding Figures 4A-4D The description provides a detailed description of the process used to form the surface conductive layer.

[0044] In some embodiments, contact pads may be formed between the surface conductive layer and the package substrate. In some embodiments, solder resist may be disposed on the package substrate, and openings may be formed through the solder resist layer and the dielectric layer, and the openings may be filled with conductive material to electrically connect the surface conductive layer to the internal ground plane.

[0045] The various operations will be described as multiple discrete operations in a manner most helpful for understanding this disclosure. However, the order in which they are described should not be construed as implying that these operations must depend on this order or that each operation is performed only once. Specifically, these operations do not need to be performed in the presented order and may be repeated or performed in a different order (e.g., in parallel). The described operations may be performed in an order different from that in the described embodiments. Various additional operations may be performed, and / or the described operations may be omitted in additional embodiments.

[0046] exist Figures 3A-3F Method 300 is described in the text, and as follows: Figure 3A As shown, the method begins by providing layers of ground plane material 304, 305 on both sides of the substrate 302. A plated via 306 can be formed by mechanically drilling through the substrate 302 and the internal ground layers 304, 305 to create a via. The via can be plated with metal 308, 309, such as copper, and filled (or plugged) with a conductive material, such as copper, to form the plated via 306.

[0047] As described above, the substrate 302 can be made of any material suitable for constructing the encapsulation substrate. The thickness of the substrate or core 302 can range from approximately 100 μm to 1500 μm. In some embodiments, the thickness is approximately 100 μm to 400 μm.

[0048] The internal ground plane materials 304 and 305 may comprise any conductive or superconducting material suitable for serving as an interconnect in an integrated circuit, such as copper, nickel, aluminum, palladium, gold, or combinations thereof. The internal ground plane materials 304 and 305 may be deposited on the substrate 302 using any known technique for depositing conductive / superconducting materials, such as atomic layer deposition (ALD), physical vapor deposition (PVD) (e.g., vapor deposition, magnetron sputtering, or electron beam deposition), chemical vapor deposition (CVD), or electroplating. In various embodiments, the thickness of the ground plane material layers 304 and 305 may be between 10 and 200 micrometers (μm), including all values ​​and ranges therein. In some embodiments, the thickness of the ground plane material layers 304 and 305 may be between 20 and 40 μm. In some embodiments, the thickness may be approximately 25 μm.

[0049] The thickness of the metal-plated portion can range from 3 μm to 40 μm. In some embodiments, the thickness is approximately 20 μm. The diameter of the plated via can range from 200 μm to 500 μm. In some embodiments, the diameter of the plated via is approximately 350 μm.

[0050] As used herein, the term “thickness” refers to the dimension of a particular element or layer measured along the z-axis, the term “width” refers to the dimension of a particular element or layer measured along the y-axis, and the term “length” refers to the dimension of a particular element or layer measured along the x-axis.

[0051] like Figure 3B As shown, the plated through-hole plug 306 and the metal-plated portions 308, 309 can be planarized by grinding or any other suitable process. Optionally, a layer of copper or other suitable material 310, 311 can be formed on the ground layers 304, 305 to cover the plated through-hole 306.

[0052] like Figure 3CAs shown, method 300 can proceed by patterning layers of ground plane materials 304, 305 and (if used) capping materials 310, 311 312, 313 to form a ground plane layer structure that will serve as a transmission line layer. Then, dielectric layers 314, 315 are deposited and patterned. The ground plane structures 304, 305 and optionally 310, 311 can have any shape / geometry suitable for serving as ground plane conductors for microstrip lines. In some embodiments, the inner ground planes 304, 305 are continuous and cover the entire surface of the substrate 302. In some embodiments, the inner ground planes 312, 313 are patterned and cover a portion of the surface of the substrate 302. Typically, practical applications limit the width of the ground plane structure because the ground plane would ideally be an infinite plane.

[0053] In some embodiments, after patterning and etching the ground plane layer, the substrate can be cleaned to remove surface-bound organic and metallic contaminants, as well as subsurface contaminants. In some embodiments, cleaning can be performed using, for example, chemical solutions (e.g., peroxides) and / or by combining ultraviolet radiation with ozone and / or by oxidizing the surface (e.g., using thermal oxidation) and then removing the oxides (e.g., using hydrofluoric acid).

[0054] In various embodiments, any suitable patterning technique can be used to form a ground plane at a desired location on a substrate. This patterning technique is, for example, a patterning technique employing a photoresist or other mask that defines the scale and location of the future ground plane conductor. Exemplary photoresist patterning techniques may include depositing a photoresist on a substrate. The photoresist may be a positive or negative photoresist and may include, for example, poly(methyl methacrylate), poly(methylglutarimide), DNQ / phenolic varnish, or SU-8 (an epoxy-based negative photoresist). The photoresist may be chemically enhanced, include a photoacid generator, and may be based on a polymer or copolymer containing an aromatic or alicyclic hydrocarbon norbornene derivative (e.g., for etch resistance) and having a protecting group such as a t-butyl group. The polymer may include polystyrene or acrylate polymers. The photoresist can be deposited via, for example, a spin-coating casting process. The photoresist can then be patterned by projecting the image light of the desired pattern onto it using photolithography, such as optical lithography, immersion lithography, deep UV lithography, extreme UV lithography, or other techniques. A developer, such as tetramethylammonium hydroxide (TMAH) with or without a surfactant, can be applied to the photoresist, for example, by spin coating, and a portion of the photoresist is removed to expose the area of ​​the underlying layer associated with the desired pattern. In some embodiments, the substrate can be baked before or after any of the above actions. For example, the substrate can be pre-baked to remove surface water. After applying the photoresist, a post-application bake can be performed, in which at least a portion of the solvent in the photoresist is removed. After exposure, a post-exposure bake can be performed to induce a chemical reaction, such as deprotecting the photoresist. After patterning, the photoresist can be hard-baked.

[0055] Next, layers of dielectric material 314, 315 are provided on the substrate 302 on which ground planes 312, 313 are formed. The dielectric material 314, 315 can be selected from any dielectric material suitable for the further manufacturing processes described herein. For example, since the dielectric layers 314, 315 will need to be etched to form vias 316, the etch properties of potential candidate materials are considered when selecting a suitable material for this layer. In addition to suitable etch characteristics, some other considerations when selecting a suitable material may include, for example, the possibility of smooth film formation, low shrinkage and outgassing, and good dielectric properties (e.g., low electrical leakage, an appropriate value of dielectric constant, and thermal stability). Examples of dielectric materials that can be used as materials for the dielectric layer 446 include, but are not limited to, silicon dioxide (SiO2), carbon-doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicones such as silsesquioxanes, siloxanes, or organosilicon glass (OSG).

[0056] In some embodiments, as is typically done in conventional processes, dielectric materials 314, 315 may include oxides deposited on ground plane conductors 312, 313 using, for example, chemical vapor deposition or / and plasma-enhanced chemical vapor deposition. In some embodiments, dielectric materials 314, 315 may include dielectric materials formed on ground plane conductors 312, 313 using coating techniques involving crosslinking liquid precursors into solid dielectric materials. In some embodiments, the surfaces of ground plane conductors 312, 313 may be cleaned or treated, for example, using chemical or plasma cleaning or applying heat in a controlled environment, prior to the application of the dielectric to reduce surface contamination and minimize interface traps and / or promote adhesion. In some embodiments, an “interface layer” may be applied between ground plane conductors 312, 313 and dielectric materials 314, 315 to prevent, reduce, or minimize the spontaneous and uncontrolled formation of other interface layers. In some embodiments, an adhesion promoter or adhesion layer may be applied prior to the application of the dielectric.

[0057] Planarization can also be performed to achieve relatively smooth planar surfaces for dielectric layers 314, 315. In various embodiments, planarization can be performed using wet or dry planarization processes. In one embodiment, planarization can be performed using chemical mechanical planarization (CMP), which can be understood as a process that utilizes polishing surfaces, abrasives, and slurries to remove excess material and planarize the surface.

[0058] The thickness of dielectric layers 314 and 315 can be varied and can depend on the desired distance between the microstrip signal layer and the ground plane. For example, dielectric layers 314 and 315 can have a thickness between 10 μm and 40 μm, including all values ​​and ranges therein, with typical ground thicknesses between 15 μm and 25 μm.

[0059] Method 300 may then proceed to form one or more vias 316 in the dielectric layers 314, 315 to connect to the ground planes 312, 313. The number, size, and shape of the vias 316 can vary and may depend on, for example, the conductive or superconducting material used to fill the vias, the size and shape of the ground planes 312, 313, and the etching process used to form the vias 316. For example, in some embodiments, a plurality of vias arranged along two lines at the edges of the ground planes 312, 313 may be used. However, in other embodiments, any other number of vias 316 arranged in any location and of any shape / geometry suitable for providing electrical interconnection to the ground plane conductors 312, 313 of the microstrip lines may be used.

[0060] Conductive vias, lines, and pads can be formed using any suitable method (including photolithography and / or electroless plating) and can comprise one or more layers. Conductive vias, lines, and pads can be formed from any suitable conductive material, such as copper (Cu), aluminum (Al), gold (Au), silver (Ag), and / or alloys thereof. In some embodiments, the metal used for conductive interconnects is copper or an alloy of copper. Via openings extend from the surfaces of dielectric layers 314, 315 to ground plane structures 312, 313. Lines extend horizontally across the dielectric layers, and contact pads are generally aligned with connection points to extend the contact area. Dielectric layers 314, 315 at least partially surround via openings 316, 317 to physically and electrically isolate them from each other and from other openings (not shown) that may be formed.

[0061] In various embodiments, the dimensions of vias 316 and 317 can be between 50 μm and 150 μm for the x and y axes, including all values ​​and ranges therein. The diameters of the top and bottom contact pads 316 and 317 can be in the range of 100 μm to 200 μm, or can be any other suitable size depending on manufacturing tolerances and reliable contact performance.

[0062] In various embodiments, any type of etching technique can be used, possibly involving etching in combination with patterning (such as the patterning described above), to form vias 316, 317. For example, once patterning has been completed to expose portions of the underlying layers 314, 315 in a patterned mask defining the future location and arrangement of vias 316, 317, the exposed portions of the underlying layers 314, 315 can then be chemically etched. During etching, exposed portions of the surfaces of the dielectric layers 314, 315 are removed until the desired depth is reached, thereby forming via openings 316, 317 in the dielectric layers 314, 315. If photoresist patterning is used to generate the mask for forming the vias, the remaining photoresist can optionally be removed by, for example, an ashing process in which the photoresist is exposed to oxygen or fluorine, which combine with the photoresist to form ash.

[0063] like Figure 3D As shown, method 300 can then proceed by filling one or more vias 316, 317 in dielectric layers 314, 315 with a conductive or superconducting material suitable for providing electrical connections to ground planes 312, 313. In various embodiments, the via material may include any conductive or superconducting material suitable for serving as an interconnect in an integrated circuit, such as the material described above with reference to the material of ground plane layers 304, 305. In some embodiments, the via material may be the same as the material of ground plane layers 304, 305. In other embodiments, at least some of the conductive or superconducting materials used in the different elements described herein may be different.

[0064] Vias 316 and 317 can be filled using any suitable technique for filling via openings (e.g., CVD or PVD). Planarization can also be performed using, for example, any of the planarization processes described above, to expose the surface of the dielectric layer that may be covered by the via material due to the deposition of the material into the via openings.

[0065] In some embodiments, one or more diffusion and adhesion barrier layers known in the art may be deposited into the opening before the opening is filled with the via material. Diffusion barriers are known to be used to reduce the diffusion of conductive / superconducting via material from the via, and adhesion barriers are known to be used to promote adhesion between the conductive / superconducting via material and the wall of the via opening.

[0066] Next, a conductor strip material layer can be provided on the surface of the dielectric material 314, 315 having vias 316, 317, and then patterned 318, 319 thereon. The considerations described above with reference to the ground plane materials 304, 305 apply to the conductor strip materials 318, 319 and their deposition, and therefore will not be repeated here for the sake of brevity. In some embodiments, the conductor strip materials 318, 319 may be the same as the material of the ground plane layers 304, 305 and / or the material of the vias 316, 317 in the dielectric layers 314, 315.

[0067] In some embodiments, the surface of the dielectric material 314, 315 or (if used) the etch stop layer (not shown) may be cleaned or treated, for example, using chemical or plasma cleaning or applying heat in a controlled environment, before applying the conductor strip material 318, 319, to reduce surface contamination and minimize interface traps and / or promote adhesion. In some embodiments, an adhesion promoter or adhesion layer may be applied before applying the conductor strip material 318, 319.

[0068] In various embodiments, the layer thickness of conductor strip materials 318, 319 can be between 10 μm and 40 μm, including all values ​​and ranges therein, for example, between 20 μm and 30 μm. Method 300 can then proceed to pattern the layers of conductor strip materials 318, 319 to form a structure of conductor strips that will function as transmission lines. In various embodiments, depending on the circuit design, the width of conductor strips 318, 319 can be between a few micrometers and hundreds or thousands of micrometers. In some embodiments, the width of the conductor strip is between 0.05 and 20 micrometers, including all values ​​and ranges therein, for example, between 1 and 11 micrometers, or between 3 and 5 micrometers. In various embodiments, the width of conductor strips 318, 319 can be between 20 micrometers and 40 micrometers, including all values ​​and ranges therein. In various embodiments, any kind of conventional patterning technique can be used to form conductor strips 318, 319. The description provided above for patterning ground planes 304 and 304 is applicable to patterning conductor strips 318 and 319, and therefore will not be repeated here for the sake of brevity.

[0069] like Figure 3E As shown, method 300 may continue to deposit solder resist layers 320, 321 on the surfaces of dielectric materials 314, 315 having conductor strip materials 318, 319, and then pattern the solder resist layers 320, 321 322, 323. The solder resist material may be, for example, polyimide or a similar material.

[0070] In some embodiments, the thicknesses of the dielectric and solder resist layers can be varied to optimize electrical performance. For example, the solder resist layer thickness can be greater than the dielectric layer thickness, bringing the microstrip signal layer closer to the internal ground plane and drawing the electrical return path toward the internal ground plane instead of the surface conductive layer. For example, in some embodiments, the solder resist layer thickness can be equal to or greater than 18 μm, and the dielectric layer thickness can be less than 18 μm. In some embodiments, the solder resist layer thickness can be 18 μm or greater, and the dielectric layer thickness can be 15 μm or less. In some embodiments, the thicknesses of the dielectric and solder resist layers can be further optimized based on the type and properties of the metals used for the respective layers. For example, a surface conductive plane made of nickel has a higher permeability value (i.e., compared to 1.256 × 10⁻⁶ for an internal ground plane made of copper) than an internal ground plane made of copper. - 6 Compared to H / m, nickel has a ratio of 1.26 × 10⁻⁶. -4 H / m), so the solder resist layer, which is thicker than the dielectric layer, can improve electrical performance by optimizing the return path to the internal ground layer.

[0071] like Figure 3F As shown, die 332 can be attached to the package substrate via FLI 328 and may have underfill 334. A surface conductive layer 326 may form a framework for die 332 and underfill 334 to cover the remaining surface of the package substrate. Surface conductive layer 326 may be a thin layer of unplated metal plated on top of solder resist layer 320. Surface ground layer 326 may be electrically connected to internal ground layer 304 via vias 316, 324. In some embodiments, surface conductive layer 326 may cover the entire remaining surface of the package substrate (i.e., the area not covered by die, underfill, and other components). In some embodiments, surface conductive layer 326 may cover only one or more selected areas of the package substrate surface. In some embodiments, surface conductive layer 326 covers the area from the edge of the die or underfill to the edge of the package substrate, such that there is no impedance differential along the signal line length.

[0072] In some embodiments, such as Figure 3FAs shown, the package substrate can be completed by applying controlled collapse chip connection (C4) bump formation to the top die contact area 328 for die 332 attachment and applying chip capacitor (C / C) assemblies to the bottom contact areas 329, 330 for attaching the package substrate to, for example, a motherboard (not shown). In some embodiments, a surface finish, such as unplated metal or patterned copper, can be applied to expand the available metal area for die attachment. In some embodiments, assembly can be performed on exposed copper, wherein the surface is protected by a thin surface finish, such as an organic solderability preserver (OSP) or immersion gold (Au).

[0073] The substrate with the terminating layer can be a single package substrate or a repeating unit that can undergo a unitization process, in which each unit is separated from each other to form a single package substrate. The unitization process can occur after the C4 bumping process or at any other suitable point in the process, including after a surface conductive layer has already been deposited on the surface of the package substrate. The unitized substrate can have any suitable size and any suitable thickness; typically, the substrate size can be 50 mm by 50 mm, and the thickness can be between 100 μm and 2000 μm. Although... Figures 3A-3F Only two conductive layers and one dielectric layer are shown, but it is easy to understand that the package substrate can have multiple alternating layers of conductive and dielectric materials, and different signal architectures can be present in the conductive layers, with the microstrip wiring layer being the topmost metallization layer.

[0074] Figures 4A-4D This is a schematic cross-sectional view of an exemplary integrated circuit package substrate 400 showing the formation of an electrically grounded surface conductive layer according to some embodiments of the present disclosure. Figure 4A This is a simplified schematic diagram of the packaging substrate 400, which has a core 402, plated vias 404, an internal ground plane 406, a dielectric layer 408, a microstrip signal layer 410, and a solder resist layer 412. Figures 4A-4D For clarity, only the top side of the package substrate is shown; however, conductive and dielectric layers can be formed on both sides of the substrate 402. The solder resist layer 412 can be patterned and cured to include via openings 414, 416 for connecting the surface conductive layer to the internal ground plane and bump pad openings 418 for FLI connections to the die.

[0075] Figure 4B The image shows a package substrate after photoresist patterning 420, where the photoresist covers areas that will not be plated. Photoresist patterning can include lamination, patterning, development, removal, and cleaning.

[0076] Figure 4CThe encapsulation substrate after electroplating is shown, wherein plated metal fills via openings 422, 423 and a thin metal layer covers the surface 424 (i.e., the surface conductive layer) that is not covered by photoresist. The surface conductive layer 424 can be electrically connected to the internal ground plane 406 through vias 422, 423.

[0077] The surface conductive layer may comprise a single layer or may comprise one or more layers. Any suitable process may be used to form the surface conductive layer, including patterning with a photoresist material and plating with a conductive material. Typically, an electrolytic deposition process involves depositing metal onto a substrate from an electrolyte solution containing ions of the metal to be deposited. A negative bias is applied to the substrate. The electrolyte solution may be referred to as a plating bath or electroplating bath. The metal cations are attracted to the negatively biased substrate. The negatively biased substrate reduces the ions and metal deposited onto the substrate. In some embodiments, the surface conductive layer may be formed by photolithography and / or electroless plating. The surface conductive layer may be formed from any suitable conductive material. In some embodiments, the surface conductive material is made of copper. In some embodiments, the surface conductive material is made of nickel. In some embodiments, the surface conductive material is made of aluminum. In some embodiments, the surface conductive material is made of palladium. In some embodiments, the surface conductive material is made of gold. In some embodiments, the surface conductive material is made of silver. In some embodiments, the surface conductive material is made of one or more alloys, such as alloys of copper, nickel, aluminum, palladium, gold, and / or silver. In some embodiments, the surface conductive material is made of a combination of materials, such as a combination of copper, nickel, aluminum, palladium, gold, and silver, and / or alloys thereof. The surface conductive layer can be of any suitable thickness based on processing parameters and material properties. In some embodiments, the surface conductive layer can have an average thickness between 20 nm and 5 μm. In some embodiments, the thickness of the surface conductive layer is approximately 2 μm. The surface conductive layer can be one or more layers. In some embodiments, for example, the surface conductive layer can include a nickel / palladium / gold plating. The surface conductive layer can be deposited using any suitable process. In some embodiments, the surface conductive layer can be deposited using electroless metal plating. In some embodiments, the surface conductive layer can be deposited by electroplating. In some embodiments, the surface conductive layer is formed of nickel and deposited using electroless plating. Metals deposited by electroplating typically have different properties than those deposited by electroless plating. For example, nickel deposited using electroplating can have an increased magnetomotive force, can be a thicker layer, can have a higher melting point, and can have a higher percentage of nickel content. In contrast, nickel deposited using electroless plating is typically an alloy and can have a smaller percentage of nickel content, can be deposited more uniformly, can have increased hardness, and can have reduced magnetic potential. The detectable differences in grain structure between electroplating and electroless plating are identifiable, as known in the prior art. Thus, the process for depositing the conductive layer on the surface can be determined by identifying the characteristics of the material.

[0078] In some embodiments, the photoresist layer can be patterned using a photolithographic patterning process (e.g., exposure through a wiring layer mask using a radiation source and development using a developer) to pattern traces and pads. As shown, conductive material is deposited into the openings formed by the patterned photoresist layer to form conductive vias and a surface conductive layer. In some embodiments, electrolytic copper plating is used to deposit the surface conductive layer. In some embodiments, the surface conductive layer can be formed using metal plating processes, sputtering metal, etc. The conductive material can be deposited only on a portion of the exposed surface area, or it can be deposited to cover the remaining exposed surface area of ​​the solder resist layer.

[0079] In some embodiments, the surface of the solder resist layer can be roughened to increase the physical bonding area and improve adhesion between the surface conductive layer and the solder resist layer. Surface roughness provides a mechanical anchor for the overlay. Any suitable roughening process (e.g., chemical roughening) can be used to roughen the surface of the underlying layer. In some embodiments, a seed crystal of a material used to promote adhesion between the surface conductive layer and the solder resist layer can be used; for example, a palladium seed crystal can be used to increase adhesion. Standard electroless seed layers are typically about 1 micrometer (μm) thick and require surface roughening for mechanical adhesion. In some embodiments, an underlying adhesion layer can be deposited to improve adhesion between the surface conductive layer and the solder resist layer. Standard sputtered seed layers can be thinner, but an adhesion layer such as a titanium film is used to maintain good adhesion.

[0080] Figure 4D The package substrate is shown after the 426 photoresist film has been removed and the bump pads have been exposed for finishing and attaching the connector core.

[0081] Figure 5 This is a flowchart of an exemplary method for manufacturing an integrated circuit package substrate according to various embodiments, the integrated circuit package substrate having a microstrip architecture as the uppermost layer, a solder resist layer, and a surface conductive layer on top of the solder resist layer that is electrically connected to an internal ground plane of the microstrip structure in the package substrate. Although various operations discussed with reference to this method are shown in a specific order, the operations can be performed in any suitable order (e.g., any combination of parallel or serial execution), and the operations can be repeated or omitted where appropriate.

[0082] At 502, an internal ground plane can be formed on a substrate. The substrate can be a carrier or core, or it can be another deposited layer in a metallization stack, such as a dielectric layer. At 504, a dielectric layer can be formed on the internal ground plane. At 506, a microstrip signal layer can be formed on the dielectric layer. At 508, a solder resist layer can be formed on the microstrip signal layer. At 510, a surface conductive layer can be formed on the solder resist layer. For example, the surface conductive layer can be formed by electroless metal plating. At 512, an electrical connection can be formed between the surface conductive layer and the internal ground plane. The electrical connection can be one or more electrical connections and can be formed by one or more vias. If formed by more than one via, each via can be formed and connected during the deposition of each layer. For example, during the deposition of each layer, an electrical connection in the package substrate can be formed, as referenced. Figures 3A-3F As stated above.

[0083] Figure 6A This is a schematic cross-sectional view of the top portion of an exemplary integrated circuit package according to various embodiments, wherein impedance differential is corrected by changing the geometry of the microstrip transmission line. Figure 6A As shown, the integrated circuit package 600 may include a die 602 and a package substrate 604 having a surface conductive layer 606. Figure 6A For clarity, only the top side of the package substrate is shown; however, conductive and dielectric layers may be formed on both sides of the substrate 612. The die 602 can be connected to the package substrate 604 via an FLI 608 and optionally has an underfill 610. The package substrate 604 may include a substrate 612, plated vias 614, an internal ground plane 616, a dielectric layer 618, microstrip signal layers 620 and 621, and a solder resist layer 622. The microstrip signal layer may include transmission lines with different geometries, wherein one portion 620 of the line is wider than another portion 621. A surface conductive layer 606 may be deposited in the solder resist layer 622 and electrically connected to the internal ground plane 616 via one or more vias 624 and 626. In some embodiments, as shown, the surface conductive layer 606 may cover only a portion of the surface of the package substrate, which may result in a change in impedance between the area covered by the surface conductive layer and the area not covered by the surface conductive layer. The dashed line A-A'630 indicates the separation between uncovered and covered areas.

[0084] Figure 6B According to various embodiments Figure 6A A schematic diagram of the top plan view of a microstrip transmission line illustrates a change in the microstrip transmission line geometry to correct impedance differences that may occur because the surface conductive layer only covers a portion of the package substrate surface. Figure 6BAs shown, the microstrip transmission line on the right side 620 of the A-A' line is not covered by the surface conductive layer 606 and has, for example, an impedance value of 40 ohms 636. The microstrip transmission line on the left side 621 of the A-A' line is covered by the surface conductive layer and has a different geometry, wherein the transmission line is thinner to reduce the impedance to approximately the same value of 40 ohms 638. The transmission line can be patterned with narrow and wide segments so that the impedance values ​​can be approximately the same and within the range required by the integrated circuit package. The impedance value can be calculated using methods known in the prior art, and the transmission line geometry can be changed accordingly to match the impedance value across the length of the line. By maintaining the impedance value across the entire length of the transmission line, electrical performance can be preserved and crosstalk can be reduced.

[0085] Although the conductor band is Figure 6A and 6B While depicted as a generally straight line, the conductor strip structure can have any other shape / geometry suitable for serving as a signal line conductor in a microstrip line. For example, the conductor strip can have various shapes, such as a generally straight line, a line with bends (e.g., a curved line or a line including one or more loop portions), or any other construction suitable for a particular integrated circuit design.

[0086] The package substrates disclosed herein may be included in any suitable electronic device. Figures 7-9 illustrate various examples of devices that may be included in one or more of any package substrates disclosed herein, or that may include one or more of any package substrates disclosed herein.

[0087] Figure 7A -B is a top view of wafer 701 and die 705 that may be included in an IC package along with any packaging substrate disclosed herein. Wafer 701 may be made of semiconductor material and may include one or more dies 705 having IC elements formed on the surface of wafer 701. Each of the dies 705 may be a repeating unit of a semiconductor product including any suitable IC. After the semiconductor product is manufactured, wafer 701 may undergo a unitization process in which each die 705 is separated from each other to provide discrete “chips” of the semiconductor product. Die 705 may include one or more transistors (e.g., Figure 7C Some of the transistors 740 (as described below) and / or support circuitry for wiring electrical signals to the transistors and any other IC components. In some embodiments, die 701 or die 705 may include memory devices (e.g., static random access memory (SRAM) devices), logic devices (e.g., AND, OR, NAND, NOR, NOR gates), or any other suitable circuit elements. Many of these devices may be combined on a single die 705. For example, a memory array formed by multiple memory devices may be formed in conjunction with a processing device (e.g., Figure 9 The die 705 is the same as the processing device 902 or other logic unit configured to store information in a memory device or execute instructions stored in a memory array. In some embodiments, as described above, after the die 705 is coupled to the package substrate, the die 705 may include circuitry coupled to and interacting with circuitry provided by integrated devices in the package substrate.

[0088] Figure 7C This is a cross-sectional side view of an IC device 700 that can be included in a die that can be coupled to any package substrate disclosed herein. Specifically, one or more of the IC devices 700 can be included in one or more dies. The IC device 700 can be formed on a substrate 702 (e.g., Figure 7A The chip 701) can be on and may be included in the die (e.g., Figure 7B In the die 705). The substrate 702 can be a semiconductor substrate composed of a semiconductor material system, including, for example, an N-type or P-type material system. The substrate 702 can include, for example, a crystalline substrate formed using bulk silicon or a silicon-on-insulator substructure. In some embodiments, the substrate 702 can be formed using alternative materials that may or may not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as Group II-VI, Group III-V, or Group IV can also be used to form the substrate 702. Although several examples of materials that can form the substrate 702 are described herein, any material that can serve as the basis of the IC device 700 can be used. The substrate 702 can be a monolithic die (e.g., Figure 7B The 705 die or chip (e.g., Figure 7A The chip 701 is part of it.

[0089] IC device 700 may include one or more device layers 704 disposed on substrate 702. Device layer 704 may include features of one or more transistors 740 (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) formed on substrate 702. Device layer 704 may include, for example, one or more source and / or drain (S / D) regions 720, a gate 722 for controlling current in the transistor 740 between the S / D regions 720, and one or more S / D contacts 724 for wiring electrical signals to / from the S / D regions 720. Transistor 740 may include additional features not depicted for clarity, such as device isolation regions, gate contacts, etc. Transistor 740 is not limited to... Figure 7CThe types and configurations described herein may include a variety of other types and configurations, such as planar transistors, non-planar transistors, or combinations thereof. Non-planar transistors may include FinFET transistors, such as dual-gate or tri-gate transistors, and all-around or fully-around gate transistors, such as nanoribbon and nanowire transistors.

[0090] Each transistor 740 may include a gate 722 formed of at least two layers (a gate dielectric layer and a gate electrode layer). The gate dielectric layer may include a single layer or a stack of layers. One or more layers may include silicon oxide, silicon dioxide, and / or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be performed on the gate dielectric layer to improve its quality when using high-k materials.

[0091] The gate electrode layer may be formed on the gate dielectric layer and may include at least one P-type work function metal or an N-type work function metal, depending on whether the transistor 740 is a PMOS or NMOS transistor. In some embodiments, the gate electrode layer may be composed of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers, and at least one metal layer is a filler metal layer. Other metal layers, such as barrier layers, may be included for other purposes. For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide). For NMOS transistors, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide).

[0092] In some embodiments, when considered as a cross-section of the transistor 740 along the source-channel-drain direction, the gate electrode may be formed of a U-shaped structure, the U-shaped structure including a bottom portion generally parallel to the substrate surface and two sidewall portions generally perpendicular to the top surface of the substrate. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer, generally parallel to the top surface of the substrate and excluding the sidewall portions generally perpendicular to the top surface of the substrate. In other embodiments, the gate electrode may be formed of a combination of U-shaped and planar non-U-shaped structures. For example, the gate electrode may be formed of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0093] In some embodiments, pairs of sidewall spacers may be formed on opposite sides of the gate stack to clamp the gate stack. The sidewall spacers may be formed of materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming the sidewall spacers are well known in the art and generally include deposition and etching steps. In some embodiments, multiple pairs of spacers may be used; for example, two, three, or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.

[0094] The S / D region 720 can be formed within the substrate 702, adjacent to the gate 722 of each transistor 740. For example, the S / D region 720 can be formed using an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic can be ion-implanted into the substrate 702 to form the S / D region 720. Following the ion implantation process, an annealing process can be performed, which activates the dopants and allows them to diffuse further into the substrate 702. In the latter process, the substrate 702 can first be etched to form a depression at the location of the S / D region 720. An epitaxial deposition process can then be performed to fill the depression with the material used to fabricate the S / D region 720. In some embodiments, the S / D region 720 can be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy can be in-situ doped using dopants such as boron, arsenic, or phosphorus. In some embodiments, one or more alternative semiconductor materials, such as germanium or group III-V materials or alloys, may be used to form the S / D region 720. In other embodiments, one or more layers of metal and / or metal alloys may be used to form the S / D region 720.

[0095] One or more interconnect layers can be disposed on device layer 704 (in Figure 7C The interconnect layers (shown as interconnect layers 706-710) are used to route electrical signals, such as power signals and / or input / output (I / O) signals, to and from the transistor 740 of the device layer 704. For example, conductive features of the device layer 704 (e.g., gate 722 and S / D contact 724) may be electrically coupled to the interconnect structure 728 of the interconnect layers 706-710. One or more interconnect layers 706-710 may form an interlayer dielectric (ILD) stack 719 of the IC device 700.

[0096] Interconnect structure 728 can be arranged within interconnect layers 706-710 for electrical signal routing according to various designs (specifically, this arrangement is not limited to...). Figure 7C The specific construction of the interconnect structure 728 shown. Although Figure 7CThe disclosure depicts a specific number of interconnect layers 706-710, but embodiments of the present disclosure include IC devices having more or fewer interconnect layers than depicted.

[0097] In some embodiments, the interconnect structure 728 may include trench structures 728a (sometimes referred to as “lines”) and / or via structures 728b (sometimes referred to as “vias”) filled with a conductive material such as metal. The trench structure 728a may be arranged to route electrical signals in a direction generally parallel to the plane of the surface of the device layer 704 formed on the substrate 702. For example, the trench structure 728a may be positioned to enter and exit… Figure 7C The direction of the perspective view of the page is for electrical signal routing. The via structure 728b can be arranged to route electrical signals in a direction generally perpendicular to the plane of the surface of the device layer 704 of the substrate 702. In some embodiments, the via structure 728b can electrically couple the trench structures 728a of different interconnect layers 706-710 together.

[0098] Interconnect layers 706-710 may include dielectric material 726 disposed between interconnect structures 728, such as Figure 7C As shown. In some embodiments, the dielectric material 726 disposed between interconnect structures 728 in different interconnect layers 706-710 may have different compositions; in other embodiments, the composition of the dielectric material 726 between different interconnect layers 706-710 may be the same.

[0099] A first interconnect layer 706 (referred to as metal 1 or "M1") may be formed directly on device layer 704. In some embodiments, the first interconnect layer 706 may include trench structures 728a and / or via structures 728b, as shown. The trench structure 728a of the first interconnect layer 706 may be coupled to a contact portion (e.g., S / D contact 724) of device layer 704.

[0100] The second interconnect layer 708 (referred to as metal 2 or "M2") may be formed directly on the first interconnect layer 706. In some embodiments, the second interconnect layer 708 may include a via structure 728b to couple the trench structure 728a of the second interconnect layer 708 to the trench structure 728a of the first interconnect layer 706. Although for clarity, the trench structure 728a and the via structure 728b are structurally illustrated using lines within each interconnect layer (e.g., within the second interconnect layer 708), in some embodiments, the trench structure 728a and the via structure 728b may be structurally and / or materially continuous (e.g., simultaneously filled during a bimetallic damascene process).

[0101] A third interconnect layer 710 (referred to as metal 3 or “M3”) (and additional interconnect layers, as needed) can be formed on the second interconnect layer 708 using similar techniques and constructions as described in conjunction with the second interconnect layer 708 or the first interconnect layer 706.

[0102] IC device 700 may include solder resist material 734 (e.g., polyimide or similar material) and one or more bonding pads 736 formed on interconnect layers 706-710. For example, bonding pads 736 may provide contacts for coupling to a first-level interconnect. Bonding pads 736 may be electrically coupled to interconnect structure 728 and configured to route electrical signals of transistor 740 to other external devices. For example, solder joints may be formed on one or more bonding pads 736 to mechanically and / or electrically couple a chip including IC device 700 to another component (e.g., a circuit board). IC device 700 may have other alternative configurations for routing electrical signals from interconnect layers 706-710 as depicted in other embodiments. For example, bonding pads 736 may be replaced by other similar features (e.g., pillars) or may also include said other similar features that route electrical signals to external components.

[0103] Figure 8 This is a cross-sectional side view of an IC device assembly 800 that may include any embodiment of the package substrate disclosed herein. The IC device assembly 800 includes a number of components disposed on a circuit board 802. The IC device assembly 800 may include components disposed on a first surface 840 and an opposing second surface 842 of the circuit board 802; typically, components may be disposed on one or both of surfaces 840 and 842.

[0104] In some embodiments, circuit board 802 may be a printed circuit board (PCB) comprising multiple metal layers separated from each other by dielectric material layers and interconnected by conductive vias. Any one or more of the metal layers may be formed with a desired circuit pattern to route electrical signals between components coupled to circuit board 802 (optionally, in conjunction with other metal layers). In other embodiments, circuit board 802 may be a non-PCB substrate.

[0105] Figure 8 The IC device assembly 800 shown includes an interposer-on-package structure 836 coupled to a first side 840 of a circuit board 802 via a coupling member 816. The coupling member 816 electrically and mechanically couples the interposer-on-package structure 836 to the circuit board 802 and may include solder balls (such as...). Figure 8 (as shown), the male and female parts of the socket, adhesive, bottom filler material and / or any other suitable electrical and / or mechanical coupling structure.

[0106] The on-package structure 836 of the interposer may include an IC package 820 coupled to the interposer 804 via a coupling member 818. The coupling member 818 may take any suitable form for the application, such as the form discussed above with reference to coupling member 816. For example, the coupling member 818 may be a second-level interconnect. Although... Figure 8 A single IC package 820 is shown, but multiple IC packages can be coupled to interposer 804; in fact, additional interposers can be coupled to interposer 804. Interposer 804 can provide an intermediary substrate for bridging circuit board 802 and IC package 820. For example, IC package 820 may be or include a die ( Figure 7B 705 chips), IC devices (e.g., Figure 7C The IC package 820 can be any embodiment of the IC package substrate disclosed herein, and may include a package substrate having an internal ground plane, a microstrip signal layer as a top transmission line layer, and a surface conductive layer electrically connected to the internal ground plane. Typically, the interposer 804 can extend the connection to a wider pitch or rewire the connection to a different connection. For example, the interposer 804 can couple the IC package 820 (e.g., a die) to the ball grid array (BGA) of the coupling member 816 for coupling to the board 802. Figure 8 In the illustrated embodiment, the IC package 820 and the circuit board 802 are attached to opposite sides of the interposer 804; in other embodiments, the IC package 820 and the circuit board 802 may be attached to the same side of the interposer 804. In some embodiments, three or more components may be interconnected via the interposer 804.

[0107] The interposer 804 may be formed of epoxy resin, glass fiber reinforced epoxy resin, ceramic materials, or polymeric materials such as polyimide. In some embodiments, the interposer 804 may be formed of alternative rigid or flexible materials, which may include the same materials used in semiconductor substrates, such as silicon, germanium, and other group III-V and IV materials. The interposer 804 may include metal interconnects 808 and vias 810, including but not limited to through-silicon vias (TSVs) 806. The interposer 804 may also include embedded devices 814, including passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices, such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices, may also be formed on the interposer 804. The on-interposer package structure 836 may take the form of any on-interposer package structure known in the art.

[0108] IC device assembly 800 may include an IC package 824 coupled to a first side 840 of circuit board 802 via coupling member 822. Coupling member 822 may take the form of any embodiment discussed above with reference to coupling member 816, and IC package 824 may take the form of any embodiment discussed above with reference to IC package 820. Specifically, IC package 824 may take the form of any embodiment of the IC package disclosed herein and may include a package substrate having an internal ground plane, a microstrip signal layer as a top transmission line layer, and a surface conductive layer electrically connected to the internal ground plane.

[0109] Figure 8 The IC device assembly 800 shown includes a stacked package structure 834 coupled to a second side 842 of a circuit board 802 via a coupling member 828. The stacked package structure 834 may include IC packages 826 and 832 coupled together via a coupling member 830, such that IC package 826 is disposed between the circuit board 802 and IC package 832. The coupling members 828 and 830 may take the form of any embodiment of the coupling member 816 discussed above, and IC packages 826 and 832 may take the form of any embodiment of the IC package 820 discussed above. Specifically, IC packages 826 and 832 may take the form of any embodiment of the IC package substrate disclosed herein, having an internal ground plane, a microstrip signal layer as a top transmission line layer, and a surface conductive layer electrically connected to the internal ground plane.

[0110] Figure 9 This is a block diagram of an exemplary computing device 900 that may include one or more of the package substrates disclosed herein. For example, any suitable component of the computing device 900 may include or be included in an IC package according to any embodiment of the embodiments disclosed herein, the IC package having a package substrate having an internal ground plane, a microstrip signal layer as a top transmission line layer, and a surface conductive layer electrically connected to the internal ground plane. Figure 9 Several components are illustrated as included in computing device 900, but any one or more of these components may be omitted or repeated to suit the application. In some embodiments, some or all of the components included in computing device 900 may be attached to one or more motherboards. In some embodiments, some or all of these components are manufactured onto a single system-on-a-chip (SoC) die.

[0111] Furthermore, in various embodiments, computing device 900 may include interface circuitry for coupling to one or more components. For example, computing device 900 may not include display device 906, but may include display device interface circuitry (e.g., connector and driver circuitry) to which display device 906 may be coupled. In another set of examples, computing device 900 may not include audio input device 924 or audio output device 908, but may include audio input or output device interface circuitry (e.g., connector and support circuitry) to which audio input device 924 or audio output device 908 may be coupled.

[0112] Computing device 900 may include processing device 902 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory to convert that electronic data into other electronic data that can be stored in registers and / or memory. Processing device 902 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (dedicated processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing device. Computing device 900 may include memory 904, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or hard disk drives. In some embodiments, memory 904 may include memory that shares a die with processing device 902. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0113] In some embodiments, computing device 900 may include communication chip 912 (e.g., one or more communication chips). For example, communication chip 912 may be configured to manage wireless communication for transmitting data to and from computing device 900. The term "wireless" and its derivatives can be used to describe circuits, apparatuses, systems, methods, techniques, communication channels, etc., that can transmit data over a non-solid-state medium using modulated electromagnetic radiation. This term does not imply that the associated apparatus does not contain any wires, although in some embodiments they may not contain wires.

[0114] The 912 communication chip can implement any of several wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 5302.11 series), IEEE 5302.16 standards (e.g., IEEE 5302.16-2005 revision), the Long Term Evolution (LTE) initiative along with any of its modifications, updates, and / or revisions (e.g., Advanced LTE initiative, Ultra Mobile Broadband (UMB) initiative (also known as “3GPP2”), etc.). Broadband Wireless Access (BWA) networks compliant with IEEE 5302.16 are generally referred to as WiMAX networks, an abbreviation for Global Microwave Access Interoperability, which is a mark of product certification for passing conformance and interoperability testing of the IEEE 5302.16 standard. The 912 communication chip can operate according to Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE networks. The communication chip 912 can operate according to Enhanced Data Rate GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-LJTRAN). The communication chip 912 can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolved Data Optimization (EV-DO) and its derivatives, and any other wireless protocols designated as 3G, 4G, 5G, and higher. In other embodiments, the communication chip 912 can operate according to other wireless protocols. The computing device 900 may include an antenna 922 to facilitate wireless communication and / or receiving other wireless communications (e.g., AM or FM radio transmissions).

[0115] In some embodiments, the communication chip 912 can manage wired communication, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, the communication chip 912 may include multiple communication chips. For example, a first communication chip 912 may be dedicated to short-range wireless communication, such as Wi-Fi and Bluetooth, and a second communication chip 912 may be dedicated to long-range wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc. In some embodiments, the first communication chip 912 may be dedicated to wireless communication, and the second communication chip 912 may be dedicated to wired communication.

[0116] The computing device 900 may include a battery / power circuit 914. The battery / power circuit 914 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of the computing device 900 to a power source (e.g., AC line power) independent of the computing device 900.

[0117] The computing device 900 may include a display device 906 (or a corresponding interface circuit, as described above). The display device 906 may include any visual indicator, such as a head-up display, computer monitor, projector, touch screen display, liquid crystal display (LCD), light-emitting diode display, or flat panel display.

[0118] The computing device 900 may include an audio output device 908 (or a corresponding interface circuit, as described above). The audio output device 908 may include any device that generates an audible indicator, such as a speaker, headphones, or earphones.

[0119] The computing device 900 may include an audio input device 924 (or a corresponding interface circuit, as described above). The audio input device 924 may include any means of generating a signal representing sound, such as a microphone, microphone array, or digital instrument (e.g., an instrument with a Musical Instrument Digital Interface (MIDI) output).

[0120] The computing device 900 may include a Global Positioning System (GPS) device 918 (or a corresponding interface circuit, as described above). The GPS device 918 may communicate with a satellite-based system and may receive the location of the computing device 900, as is known in the art.

[0121] The computing device 900 may include other output devices 910 (or corresponding interface circuitry, as described above). Examples of other output devices 910 may include audio codecs, video codecs, printers, wired or wireless transmitters for providing information to other devices, or additional storage devices.

[0122] The computing device 900 may include other input devices 920 (or corresponding interface circuitry, as described above). Examples of other input devices 920 may include an accelerometer, a gyroscope, a compass, an image capturing device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a barcode reader, a quick-response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0123] The computing device 900 can have any desired form factor, such as a handheld or mobile computing device (e.g., a cellular phone, smartphone, mobile internet device, music player, tablet computer, laptop computer, netbook computer, ultrabook computer, personal digital assistant (PDA), super mobile personal computer, etc.), desktop computing device, server or other networked computing component, printer, scanner, monitor, set-top box, entertainment control unit, vehicle control unit, digital camera, digital video camera, or wearable computing device. In some embodiments, the computing device 900 can be any other electronic device that processes data.

[0124] The following examples relate to other embodiments. Various features of different embodiments can be combined with some of the included features and other features can be excluded in various ways to suit a variety of different applications.

[0125] Example 1 is an integrated circuit package substrate, comprising: an inner ground plane layer; a dielectric layer on the inner ground plane; a microstrip signal layer on the dielectric layer, wherein the microstrip signal layer is a top transmission line layer; a solder resist layer on the microstrip signal layer; and a surface conductive layer on the solder resist layer, wherein the surface conductive layer is electrically connected to the inner ground plane.

[0126] Example 2 may include the subject matter of Example 1, and may further specify that the surface conductive layer material includes one or more of copper, nickel, palladium, aluminum, silver and gold.

[0127] Example 3 may include the subject matter of any of Examples 1-2, and may further specify that the surface conductive layer exhibits electroless plating properties.

[0128] Example 4 may include the subject matter of any of Examples 1-3, and may also specifically specify that the surface conductive layer covers the entire exposed surface of the package substrate.

[0129] Example 5 may include the subject matter of any of Examples 1-3, and may also specifically specify that the surface conductive layer covers a portion of the exposed surface of the package substrate.

[0130] Example 6 may include the subject matter of Example 5, and may further specify that the line geometry of the microstrip signal layer is altered to match the impedance value of the region covered by the surface conductive layer with the impedance value of the region not covered by the surface conductive layer.

[0131] Example 7 may include the subject matter of Example 6, and may further specify that the line geometry of the microstrip signal layer is narrower in the region covered by the surface conductive layer than in the region not covered by the surface conductive layer.

[0132] Example 8 may include the subject matter of any of Examples 1-7, and may also specifically specify one or more vias forming an electrical connection between the surface conductive layer and the internal ground layer.

[0133] Example 9 may include the subject matter of any of Examples 1-8, and may also specifically specify that the thickness of the solder resist layer is greater than the thickness of the dielectric layer.

[0134] Example 10 is a method for manufacturing an integrated circuit package substrate, the method comprising: forming an internal ground layer on the substrate; forming a dielectric layer on the internal ground layer; forming a microstrip signal layer on the dielectric layer; forming a solder resist layer on the microstrip signal layer; forming a surface conductive layer on the solder resist layer; and forming an electrical connection between the surface conductive layer and the internal ground layer.

[0135] Example 11 may include the subject matter of Example 10, and may further specify that the surface conductive layer material includes one or more of copper, nickel, palladium, aluminum, silver and gold.

[0136] Example 12 may include the subject matter of any of Examples 10-11, and may also specifically specify the deposition of a surface conductive layer by electroless plating.

[0137] Example 13 may include the subject matter of any of Examples 10-12, and may also specifically specify that the surface conductive layer covers the entire exposed surface of the package substrate.

[0138] Example 14 may include the subject matter of any of Examples 10-12, and may also specifically specify that the surface conductive layer covers a portion of the exposed surface of the package substrate.

[0139] Example 15 may include the subject matter of Example 14, and may also specifically specify that the line geometry of the microstrip signal layer is changed so that the impedance value of the region covered by the surface conductive layer matches the impedance value of the region not covered by the surface conductive layer.

[0140] Example 16 may include the subject matter of Example 15, and may further specify that forming a microstrip signal layer also includes: narrowing the microstrip line width so that the impedance value of the region covered by the surface conductive layer matches the impedance value of the region not covered by the surface conductive layer.

[0141] Example 17 may include the subject matter of any of Examples 10-16, and may also specifically specify one or more vias forming an electrical connection between the surface conductive layer and the internal ground layer.

[0142] Example 18 may include the subject matter of any of Examples 10-17, and may also specifically specify that the thickness of the solder resist layer is greater than the thickness of the dielectric layer.

[0143] Example 19 is an integrated circuit package including: a die; a first-level interconnect; a second-level interconnect; and a package substrate including: an inner ground plane layer; a dielectric layer on the inner ground plane; a microstrip signal layer on the dielectric layer, wherein the microstrip signal layer is a top transmission line layer; a solder resist layer on the microstrip signal layer; and a surface conductive layer on the solder resist layer, wherein the surface conductive layer is electrically connected to the inner ground plane.

[0144] Example 20 may include the subject matter of Example 19, and may further specify that the surface conductive layer material includes one or more of copper, nickel, palladium, aluminum, silver and gold.

[0145] Example 21 may include the subject matter of any of Examples 19-20, and may further specify that the surface conductive layer exhibits electroless plating properties.

[0146] Example 22 may include the subject matter of any of Examples 19-21, and may also specifically specify that the surface conductive layer covers the entire exposed surface of the package substrate.

[0147] Example 23 may include the subject matter of any of Examples 19-21, and may also specifically specify that the surface conductive layer covers a portion of the exposed surface of the package substrate.

[0148] Example 24 may include the subject matter of Example 23, and may also specify that the line geometry of the microstrip signal layer is changed so that the impedance value of the region covered by the surface conductive layer matches the impedance value of the region not covered by the surface conductive layer.

[0149] Example 25 may include the subject matter of Example 24, and may further specify that the line geometry of the microstrip signal layer is narrower in the region covered by the surface conductive layer than in the region not covered by the surface conductive layer.

[0150] Example 26 may include the subject matter of any of Examples 19-25, and may also specifically specify one or more vias forming an electrical connection between the surface conductive layer and the internal ground layer.

[0151] Example 27 may include the subject matter of any of Examples 19-26, and may also specifically specify that the thickness of the solder resist layer is greater than the thickness of the dielectric layer.

[0152] Example 28 is a computing device comprising: a circuit board; and an integrated circuit package coupled to the circuit board, wherein the integrated circuit package includes: a die; a first-level interconnect; a second-level interconnect; and a package substrate including: an internal ground layer; a dielectric layer on the internal ground layer; a microstrip signal layer on the dielectric layer, wherein the microstrip signal layer is a top transmission line layer; a solder resist layer on the microstrip signal layer; and a surface conductive layer on the solder resist layer, wherein the surface conductive layer is electrically connected to the internal ground layer.

[0153] Example 29 may include the subject matter of Example 28, and may further specify that the surface conductive layer material includes one or more of copper, nickel, palladium, aluminum, silver and gold.

[0154] Example 30 may include the subject matter of any of Examples 28-29, and may further specify that the surface conductive layer exhibits electroless plating properties.

[0155] Example 31 may include the subject matter of any of Examples 28-30, and may also specifically specify that the surface conductive layer covers the entire exposed surface of the package substrate.

[0156] Example 32 may include the subject matter of any of Examples 28-30, and may also specifically specify that the surface conductive layer covers a portion of the exposed surface of the package substrate.

[0157] Example 33 may include the subject matter of Example 32, and may also specifically specify that the line geometry of the microstrip signal layer is changed so that the impedance value of the region covered by the surface conductive layer matches the impedance value of the region not covered by the surface conductive layer.

[0158] Example 34 may include the subject matter of Example 33, and may further specify that the line geometry of the microstrip signal layer is narrower in the region covered by the surface conductive layer than in the region not covered by the surface conductive layer.

[0159] Example 35 may include the subject matter of any of Examples 28-34, and may also specifically specify one or more vias forming an electrical connection between the surface conductive layer and the internal ground layer.

[0160] Example 36 may include the subject matter of any of Examples 28-35, and may also specifically specify that the thickness of the solder resist layer is greater than the thickness of the dielectric layer.

Claims

1. An integrated circuit packaging substrate, comprising: Internal grounding layer; The dielectric layer on the internal grounding layer; The microstrip signal layer on the dielectric layer, wherein the microstrip signal layer is the top transmission line layer; The solder resist layer on the microstrip signal layer, wherein the solder resist layer includes a die attachment region and a non-die attachment region; and A surface conductive layer on the solder resist layer in the non-die attachment region, wherein the surface conductive layer is electrically connected to the internal ground layer. The surface conductive layer at least partially covers the non-die attachment area on the solder resist layer. The linear geometry of the microstrip signal layer has a first width in a first region covered by the surface conductive layer, and a second width different from the first width in a second region not covered by the surface conductive layer. Wherein, the first width is smaller than the second width.

2. The integrated circuit packaging substrate according to claim 1, wherein, The surface conductive layer includes one or more of copper, nickel, palladium, aluminum, silver, and gold.

3. The integrated circuit packaging substrate according to claim 1, wherein, The surface conductive layer exhibits electroplating-free properties.

4. The integrated circuit packaging substrate according to any one of claims 1-3, wherein, The surface conductive layer completely covers the non-die attachment area on the solder resist layer.

5. The integrated circuit packaging substrate according to any one of claims 1-3, wherein, One or more vias form an electrical connection between the surface conductive layer and the internal ground layer.

6. The integrated circuit packaging substrate according to any one of claims 1-3, wherein, The thickness of the solder resist layer is greater than the thickness of the dielectric layer.

7. A method for manufacturing an integrated circuit package substrate, the method comprising: An internal grounding layer is formed on the substrate; A dielectric layer is formed on the internal grounding layer; A microstrip signal layer is formed on the dielectric layer; A solder resist layer is formed on the microstrip signal layer, wherein the solder resist layer includes a die attachment region and a non-die attachment region; A surface conductive layer is formed on the solder resist layer in the non-die attachment area; and This forms an electrical connection between the surface conductive layer and the internal ground layer. The surface conductive layer at least partially covers the non-die attachment area on the solder resist layer. The linear geometry of the microstrip signal layer has a first width in a first region covered by the surface conductive layer, and a second width different from the first width in a second region not covered by the surface conductive layer. Wherein, the first width is smaller than the second width.

8. The method according to claim 7, wherein, The surface conductive layer includes one or more of copper, nickel, palladium, aluminum, silver, and gold.

9. The method according to claim 7, wherein, The surface conductive layer is deposited by electroless plating.

10. The method according to any one of claims 7-9, wherein, The surface conductive layer completely covers the non-die attachment area on the solder resist layer.

11. The method according to any one of claims 7-9, wherein, One or more vias form the electrical connection between the surface conductive layer and the internal ground layer.

12. The method according to any one of claims 7-9, wherein, The thickness of the solder resist layer is greater than the thickness of the dielectric layer.

13. An integrated circuit package, comprising: The packaging substrate includes: Internal grounding layer The dielectric layer on the internal grounding layer The microstrip signal layer on the dielectric layer, wherein the microstrip signal layer is the top transmission line layer. The solder resist layer on the microstrip signal layer includes a die attachment region and a non-die attachment region, and A surface conductive layer on the solder resist layer in the non-die attachment region, wherein the surface conductive layer is electrically connected to the internal ground layer; Die, wherein the die is attached to the package substrate in the die attachment region; and The first-level interconnect, wherein the die is electrically coupled to the package substrate via the first-level interconnect. The surface conductive layer at least partially covers the non-die attachment area on the solder resist layer. The linear geometry of the microstrip signal layer has a first width in a first region covered by the surface conductive layer, and a second width different from the first width in a second region not covered by the surface conductive layer. Wherein, the first width is smaller than the second width.

14. The integrated circuit package according to claim 13, wherein, The surface conductive layer includes one or more of copper, nickel, palladium, aluminum, silver, and gold.

15. The integrated circuit package according to claim 13, wherein, The surface conductive layer exhibits electroplating-free properties.

16. The integrated circuit package according to any one of claims 13-15, wherein, The surface conductive layer completely covers the non-die attachment area on the solder resist layer.

17. The integrated circuit package according to any one of claims 13-15, wherein, One or more vias form an electrical connection between the surface conductive layer and the internal ground layer.

18. The integrated circuit package according to any one of claims 13-15, wherein, The thickness of the solder resist layer is greater than the thickness of the dielectric layer.

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