Shared memory for intelligent network interface cards

Abstract

The present invention relates to a system and method for a shared memory for an intelligent network interface card. In an example, a host fabric interface (HFI) is disclosed, including: an interconnect interface for communicatively coupling the HFI to an interconnect; a network interface for communicatively coupling the HFI to a network; a network interface logic for providing communication between the interconnect and the network; a coprocessor configured to provide an offload function for the network; a memory; and a cache agent configured to: designate a region of the memory as a shared memory between the HFI and a core communicatively coupled to the HFI via the interconnect; receive a memory operation for the shared memory; and issue a memory instruction to the memory according to the memory operation.

Description

Technical Field

[0001] The present disclosure relates generally to the field of cloud computing, and more particularly, but not exclusively, to a system and method for shared memory for smart network interface cards. Background Art

[0002] Contemporary computing practices have moved away from hardware-specific computing and toward "network as a device." Contemporary networks may include data centers that host a large number of general-purpose hardware server devices, such as contained in server racks and controlled by hypervisors. Each hardware device may run one or more instances of a virtual device, such as a workload server or a virtual desktop.

[0003] In some cases, virtualized networks may also include network function virtualization (NFV), which provides certain network functions as virtual devices. These functions may be referred to as virtual network functions (VNFs). In the past, the functions provided by these VNFs may have been provided by custom hardware service devices.

[0004] Thus, in contemporary "cloud" architectures, both network endpoints and network infrastructure may be provided, at least in part, in a virtualization layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The present disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, various features are not necessarily drawn to scale, but are used for illustration purposes only. Where scale is shown explicitly or implicitly, it only provides an illustrative example. In other embodiments, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0006] Figure 1a is a block diagram of a network according to one or more examples of the present Specification.

[0007] Figure 1b is a block diagram of selected components of a data center in a network according to one or more examples of the present Specification.

[0008] Figure 2 is a block diagram of selected components of an end-user computing device according to one or more examples of the present Specification.

[0009] Figure 3 is a high-level block diagram of a server according to one or more examples of the present specification.

[0010] Figure 4a is a block diagram of a software defined network (SDN) according to one or more examples of the present specification.

[0011] Figure 4bis a block diagram of network function virtualization (NFV) according to one or more examples of the present specification.

[0012] Figure 5 is a block diagram of a platform architecture according to one or more examples of the present specification.

[0013] Figure 6 is a block diagram of a processor according to one or more examples of the present Description.

[0014] Figure 7 is a block diagram of a computing architecture 700 according to one or more examples of the present Description.

[0015] Figure 8 is a block diagram of a computing architecture according to one or more examples of the present specification.

[0016] Fig. 9 is a block diagram of a data center according to one or more examples of the present Specification.

[0017] Fig.10 A read flow according to one or more examples of the present specification is illustrated.

[0018] Fig.11 A signal flow for write-back according to one or more examples of the present specification is illustrated.

[0019] Fig.12 A snoop flow according to one or more examples of the present specification is illustrated. DETAILED DESCRIPTION

[0020] The following disclosure provides many different embodiments or examples for realizing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be restrictive. Further, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed. Different embodiments may have different advantages, and no particular advantage is necessarily required by any embodiment.

[0021] In modern computing, and especially in enterprise computing, it is sometimes said that "the data center is the machine." In a data center, a large number of identical or nearly identical rack-mount or blade servers may be deployed, with each server being considered a line replaceable unit. If a particular device fails, it is often more economical to simply replace it than to attempt to repair it.

[0022] In this modern computing paradigm, data latency and data bandwidth are key performance indicators that greatly impact the ability of a data center to meet its QoS and SLA requirements or goals. This becomes even more of a concern as many data center resources are offloaded to specific high-capacity devices. As an illustrative example, a processor may have some local cache, rather than local DRAM, that can interface with and write to the memory of an Intel® 3D Crosspoint (3DXP) memory server that provides persistent memory at near DRAM speeds, which memory may be located locally, or on a dedicated memory server. Similarly, while the storage may be local to the device, it may also be possible to offload the storage to a storage pool, such as RAID, RAIN, or other similar storage architectures.

[0023] In this case, the interconnection between various devices becomes increasingly important. To this end, a high-speed fabric can be provided to communicatively couple various devices. The fabric can be a high-speed switching fabric, such as Intel® OmniPath, or it can be a more traditional network, such as high-speed Ethernet or InfiniBand technology. Throughout this specification, the term "fabric" should be understood to refer to any suitable structure, interconnection or bus between various components of a data center.

[0024] Thus, in a data center, the fabric and its associated network interfaces can be an integral part of the data center "machines," as opposed to an all-in-one device where the network interfaces simply provide a medium for different machines to communicate with each other. Throughout this specification, a "network interface" should be understood to include any device that couples a computing resource to the fabric, such as a network interface card (NIC), a host fabric interface (HFI), or a similar device.

[0025] In modern architectures, the network interface can be tightly coupled with the processor. In fact, in many cases, the network interface is provided as an integrated on-die component to ensure that the processor and the network interface achieve very high-speed communication to increase bandwidth and reduce latency. In other embodiments, a separate HFI chip can be provided as a peripheral device of the processor core.

[0026] Another improvement in data center architecture is the so-called "smart NIC," in which a coprocessor is added to the network interface to provide some computationally intensive and repetitive network functions. Providing a coprocessor on the NIC can be an advantageous factor for improving the performance of the NIC and reducing the total cost of ownership (TCO). As a non-limiting example, the task performed by the coprocessor can be encryption, IP security (IPsec), compression, or some other highly repetitive task.

[0027] The coprocessor itself may take the form of an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a dedicated IP block, or some other tightly coupled hardware and / or software solution that offloads these repetitive tasks from the CPU. As used throughout this specification, a "coprocessor" as applied to a NIC should be understood to include any dedicated hardware, software, firmware, or combination of those solutions that offloads tasks from the CPU.

[0028] Although the NIC itself realizes benefits to the architecture, the NIC still maintains a peripheral role relative to the CPU. When the programmer encodes the algorithm into the CPU, the programmer is still keenly aware of when certain computational processes require communication across the NIC. Because the programmer is still aware of this, he may need to decompose the computation into certain non-streamlined operations, which can be divided into behaviors such as sending, receiving, handshaking, polling, scheduling, exception handling, or similar operations. These strict boundaries between computational operations and communication operations inhibit the flexibility and performance of the program. As mentioned above, in the specific example of the data center, latency and bandwidth are performance metrics that system designers may try to optimize.

[0029] Therefore, it is advantageous to extend the role of the NIC so that its operations are streamlined into the flow of the CPU's operations, thereby bringing the NIC logically closer to the CPU than provided by existing architectures. Rather than issuing network operations like "send" and "receive," the programmer can simply read and write from a fast memory block while the communication occurs in the background.

[0030] To increase the value of NIC, this specification provides systems and methods that can streamline computing and communication tasks into cooperative operations without interfering with the architectural flexibility of the physical arrangement of NIC logic. In one example, this is achieved by augmenting the intelligent NIC with the additional ability to provide shared memory space to the CPU.

[0031] Specifically, the NIC of the present specification provides a memory range in the system address space of the computing node. The addresses in this range are mapped to a portion of the DRAM memory of the coprocessor for the NIC. The NIC coprocessor exposes these memory addresses to the computing host so that they can have shared access.

[0032] At a high level, this allows direct memory-based communication between the coprocessor and the CPU. Therefore, when the algorithm is executing software in the CPU, or conversely, when the coprocessor is providing a data stream, they can share those data and signal events via a shared memory area. It should be noted that the shared memory space is actually hosted in the DRAM of the coprocessor, so that when the cache agent (CA) of the computing host writes to or reads from the shared memory space, a transaction occurs in which the read or write is transmitted to the shared memory space via the interconnection between the two. This can be via a dedicated channel in the NIC on the die, or it can be via a PCIe (Peripheral Component Interconnect Express) channel in the case where the NIC is offloaded from the core. It should be noted that the example in the figure below illustrates an example in which the interconnection between the NIC and the core is an example of a PCIe interface, but this is a non-limiting example. As used throughout this specification and claims, the interconnection can be any suitable interconnection, including an on-die interconnection.

[0033] The coherence of the shared memory space can be managed by a cache agent provided on the NIC. When a core in the computing host issues a memory operation to the shared address space, the cache agent for the core issues a request to the cache agent for the coprocessor via the interconnect. The cache agent on the NIC can then process the memory operation.

[0034] In terms of CPU architecture, the CPU's local cache agent sees and treats the docked NIC as just another QPI or PCIe agent. Thus, in some embodiments, no changes may be made to the cache agent on the core or to the core itself. Instead, the PCIe agent tunnels memory access requests to the NIC's shared memory via a unique address range through a PCIe channel dedicated to tunneling consistent traffic to the NIC. Thus, changes may be made to the PCIe interface as well as to the cache agent on the NIC.

[0035] When a memory request arrives at the host PCIe interface in the NIC, the interface directs the shared memory access request to a cache agent of the coprocessor of the NIC. This cache agent is communicatively coupled to a memory controller that manages the shared DRAM. This cache agent manages the lines within the shared DRAM and controls who "owns" these lines (e.g., CPU cache or coprocessor). The cache agent also manages the state of each memory location, which can follow protocols such as MESI (Modify / Exclusive / Shared / Invalid). MESI is a known cache consistency protocol improved on MSI (MESI without exclusivity), which substantially reduces the number of memory transactions required. Other examples can use, for example, MSI, MOSI (Modify / Own / Shared / Invalid), or MOESI (MOSI with exclusivity).

[0036] When a memory operation occurs, the cache agent processes the request and takes appropriate actions to maintain coherency between the core and the coprocessor. This may include, for example, granting ownership of the line to the CPU, snooping on demand, reading data from the memory controller on demand, sending the data back to the requesting node along with the status, or other similar actions.

[0037] Note that in this example, one cache agent and one dedicated PCIe lane are depicted for simplicity of illustration, but in practice, the number of cache agents and PCIe lanes implemented may be driven by performance, power, and cost considerations of a particular deployment.

[0038] Note that in some examples, shared memory can be federated across multiple NICs. In this case, a system address decoder (SAD) can be added to the PCIe agent of the compute node. This SAD lets the agent federate NIC-based shared DRAM into the host memory space for seamless access. The PCIe agent will initiate memory accesses from anywhere in the system and target memory blocks in a specific NIC to that NIC. Therefore, each NIC can access the shared DRAM of the peer NIC and use it to coordinate the flow of events and perform communication and notification tasks autonomously, thereby bypassing any intervention from the CPU, which would require other control paths for control, exception, and error handling. In the case of multiple NICs sharing memory, a hash function can be used to attribute specific memory operations.

[0039] In an embodiment, a novel snoop filter and cache agent scheme located in the NIC and integrated into the PCIe node agent may also be provided to optimize the traffic to perform consistent communication between the two types of agents.

[0040] Note that this architecture can be used to create a consistent address space not only between the CPU and the NIC, but also between different NICs connected through a PCIe node agent. In this case, the address space can be split between different NICs, and the PCIe node agent reroutes requests from the NICs and CPUs to the corresponding NIC that owns the particular address space. This enables novel use cases where memory addresses are shared between multiple NICs and multiple CPUs.

[0041] The system and method for a shared memory for an intelligent network interface card will now be described in more detail with reference to the accompanying drawings. It should be noted that in all of the accompanying drawings, certain reference numerals may be repeated to indicate that a particular device or block is completely or substantially consistent across these figures. However, this is not intended to imply any particular relationship between the various embodiments disclosed. In some examples, a class of elements may be referred to by a specific reference numeral ("widget 10"), while individual species or examples of the class may be referred to by hyphenated numbers ("first specific widget 10-1" and "second specific widget 10-2").

[0042] Figure 1a 1 is a network-level diagram of a network 100 of a cloud service provider (CSP) 102 according to one or more examples of the present specification. Figure 1a In the example of FIG. 1 , the network 100 can be configured to enable one or more enterprise clients 130 to provide services or data to one or more end users 120, which can operate user devices 110 to access information or services via external networks 172. This example contemplates an embodiment in which the cloud service provider 102 itself is an enterprise that provides a third-party "network as a service" (NaaS) to the enterprise clients 130. However, this example is non-limiting. In appropriate embodiments, the enterprise clients 130 and CSP 102 may also be the same or related entities.

[0043] The enterprise network 170 can be any suitable network or combination of one or more networks operating on one or more suitable networking protocols, including, for example, a fabric, a local area network, an intranet, a virtual network, a wide area network, a wireless network, a cellular network, or the Internet (optionally accessed via a proxy, a virtual machine, or other similar security mechanism) as non-limiting examples. The enterprise network 170 can also include one or more servers, firewalls, routers, switches, security devices, antivirus servers, or other useful network devices, which can be virtualized within the data center 142 in the example. In this illustration, the enterprise network 170 is shown as a single network for simplicity, but in some embodiments, the enterprise network 170 can include a large number of networks, such as one or more enterprise intranets connected to the Internet, and can include data centers in multiple geographic locations. The enterprise network 170 can also provide access to external networks (such as the Internet) via an external network 172. The external network 172 can similarly be any suitable type of network.

[0044] The data center 142 may be provided, for example, as a virtual cluster running in a hypervisor on multiple rack blade servers or as a cluster of physical servers. The data center 142 may provide one or more server functions, one or more VNFs, or one or more "micro-clouds" to one or more tenants in one or more hypervisors. For example, a virtualized environment such as vCenter may provide the ability to define multiple "tenants," each of which is functionally separated from each other tenant, and each tenant operates as a single-purpose micro-cloud. Each micro-cloud may serve as a unique function and may include multiple virtual machines (VMs) of many different styles. In some embodiments, the data center 142 may also provide multi-tenancy, in which a single instance of a function may be provided to multiple tenants, while the data for each tenant is isolated from the data for each other tenant.

[0045] It should also be noted that certain functionality of the user equipment (UE) 110 may also be provided via the data center 142. For example, a micro cloud may provide a remote desktop management program such as Citrix Workspace that allows end users 120 to remotely log into a remote enterprise desktop and access enterprise applications, workspaces, and data. In that case, the UE 110 may be a "thin client" such as a Google Chromebook that only runs a stripped-down operating system and still provide the user 120 with useful access to enterprise resources.

[0046] One or more computing devices configured as a management console 140 may also operate on the enterprise network 170. The management console 140 may be a special case of a user device and may provide a user interface for the security administrator 150 to define enterprise security and network policies that the management console 140 may implement on the enterprise network 170 and across the client devices 110 and the data center 142. In an example, the management console 140 may run a server-class operating system such as Linux, Unix, or Windows Server. In another case, the management console 140 may be provided as a web interface, on a desktop-class machine, or via a VM provided within the data center 142.

[0047] The network 100 can communicate with an external network 172 across an enterprise boundary 104. The enterprise boundary 104 can represent a physical, logical, or other boundary. The external network 172 can include, for example, websites, servers, network protocols, and other network-based services. The CSP 102 can also contract with a third-party security service provider 190 (such as McAfee® or another security service company) to provide security services to the network 100.

[0048] The goal of an enterprise client may be to securely provide network services to end users 120 via a data center 142 such as hosted by CSP 102. To this end, CSP 102 may provide certain contractual quality of service (QoS) guarantees and / or service level agreements (SLAs). QoS may be a measure of resource performance and may include factors such as availability, jitter, bit rate, throughput, error rate, and latency, to name a few. An SLA may be a contractual agreement that may include QoS factors as well as factors such as "mean time to recovery" (MTTR) and mean time between failures (MTBF). In general, an SLA may be a higher-level agreement that is more related to the overall experience, whereas QoS may be used to measure the performance of individual components. However, this should not be understood to imply a strict division between QoS metrics and SLA metrics.

[0049] Steering Figure 1b In order to meet contractual QoS and SLA requirements, CSP 102 may provide a certain number of workload clusters 118. In this example, two workload clusters 118-1 and 118-2 are shown, each providing up to 16 rack servers 146 in chassis 148. These server racks may be collocated in a single data center, or may be located in different geographic data centers. Depending on contractual agreements, some servers 146 may be specifically dedicated to certain enterprise clients or tenants, while other servers may be shared.

[0050] Selecting a number of servers to provision in a data center is a traditional practice for CSPs 102. CSPs 102 may want to ensure that there are enough servers to handle network capacity and provide for expected equipment failures over time. However, provisioning too many servers 146 can be expensive both in terms of hardware costs and in terms of power consumption. Therefore, ideally, CSPs 102 provision enough servers 146 to serve all of their enterprise clients 130 and meet contractual QoS and SLA benchmarks, but without wasting capacity.

[0051] Various devices in the data center 142 can be connected to each other via a switching fabric. "Fabric" is often referred to and treated as a single entity, but it should be understood that in some embodiments, the fabric is a high-level label for multiple devices that can operate together to form the fabric. For example, the fabric may include one or more high-speed routing and / or switching devices 174. In some cases, the switching devices 174 may be hierarchical, with, for example, switch 174-1 processing workload cluster 118-1, switch 174-2 processing workload cluster 118-2, and switch 174-3. This simple hierarchy is shown to illustrate the principles of a hierarchical switching fabric, but it should be noted that this may be significantly simplified compared to real-life deployments. In many cases, the hierarchy of the switching fabric 174 may be multi-layered and more involved. Common network architectures include hub-and-spoke architectures and leaf-and-spine architectures.

[0052] The fabric itself can be implemented through Intel® OmniPath TM 、TrueScale TM , Ultra Path Interconnect (UPI) (formerly known as QPI or KTI), STL, Ethernet, PCI or PCIe, etc. Some of these will be more suitable for certain types of deployments than others, and choosing the appropriate fabric for the application at hand is a matter of routine skill.

[0053] Figure 2 It is a block diagram of a client device 200 according to one or more examples of this specification. The client device 200 can be any suitable computing device. In various embodiments, as a non-limiting example, a "computing device" can be or include a computer, a workstation, a server, a mainframe, a virtual machine (whether simulated or on a "bare metal" hypervisor), an embedded computer, an embedded controller, an embedded sensor, a personal digital assistant, a laptop computer, a cellular phone, an IP phone, a smart phone, a tablet computer, a dual-purpose tablet computer, a computing device, a network device, a receiver, a wearable computer, a handheld calculator, or any other electronic, microelectronic or micro-electromechanical device for processing and transmitting data. Any computing device can be designated as a host on a network. Each computing device can refer to itself as a "local host", but any computing device outside it can be designated as a "remote host". In a specific example, the client device 200 is a virtual machine configured for RDMA (remote direct memory access) as described herein.

[0054] The client device 200 includes a processor 210 connected to a memory 220 in which executable instructions for providing at least the software portion of an operating system 222 and a client agent 224 are stored. Other components of the client device 200 include a storage 250, a network interface 260, and a peripheral device interface 240. This architecture is provided only as an example and is intended to be non-exclusive and non-limiting. In addition, the various parts disclosed are intended to be logically divided only and do not necessarily represent physically separated hardware and / or software components. Some computing devices provide, for example, a main memory 220 and a storage 250 in a single physical memory device, while in other cases, the memory 220 and / or the storage 250 are functionally distributed across many physical devices, such as in the case of a data center storage pool or storage server. In the case of a virtual machine or hypervisor, all or part of the functionality may be provided in the form of software or firmware running on a virtualization layer to provide the disclosed logical functions. In other examples, a device such as a network interface 260 may provide only the minimum hardware interface necessary to perform its logical operations, and may rely on a software driver to provide additional necessary logic. Therefore, each logic block disclosed herein is broadly intended to include one or more logic elements configured and operable to provide the disclosed logical operations of the block.

[0055] As used throughout this specification, "logic elements" may include hardware (including, for example, programmable software, ASICs, or FPGAs), external hardware (digital, analog, or mixed signal), software, reciprocating software, services, drivers, interfaces, components, modules, algorithms, sensors, components, firmware, microcode, programmable logic, or objects that can be coordinated to implement logical operations. In addition, some logic elements are provided by tangible non-temporary computer-readable media on which executable instructions for instructing a processor to perform a task are stored. As non-limiting examples, such non-temporary media may include, for example, hard disks, solid-state memory or disks, read-only memories (ROMs), persistent fast memory (PFMs) (e.g., Intel® 3D crosspoints), external storage, redundant arrays of independent disks (RAIDs), redundant arrays of independent nodes (RAINs), network attached storage (NASs), optical storage, tape drives, backup systems, cloud storage, or any combination thereof. Such media may also include instructions programmed into FPGAs or encoded in hardware or processors on ASICs.

[0056] In an example, the processor 210 is communicatively coupled to the memory 220 via a memory bus 270-3, which may be, for example, a direct memory access (DMA) bus, although other memory architectures are possible, including architectures in which the memory 220 communicates with the processor 210 via the system bus 270-1 or some other bus. In a data center environment, the memory bus 270-3 may be or may include a fabric.

[0057] The processor 210 may be communicatively coupled to other devices via the system bus 270-1. As used throughout this specification, a "bus" includes any wired or wireless interconnect, network, connection, structure, bundle, single bus, multiple buses, crossbar network, single-stage network, multi-stage network, or other conductive medium operable to carry data, signals, or power between portions of a computing device or between computing devices. It should be noted that these uses are disclosed only as non-limiting examples, and some embodiments may omit one or more of the above-described buses, while other embodiments may employ additional or different buses.

[0058] In various examples, a "processor" may include any combination of logic elements operable to execute instructions (whether loaded from memory or implemented directly in hardware), including, as non-limiting examples, a microprocessor, a digital signal processor (DSP), a field programmable gate array (FPGA), a graphics processing unit (GPU), a programmable logic array (PLA), an application specific integrated circuit (ASIC), or a virtual machine processor (VMP). In some architectures, a multi-core processor may be provided, in which case, as the case may be, the processor 210 may be treated as only one core of the multi-core processor, or may be treated as the entire multi-core processor. In some embodiments, one or more coprocessors may also be provided for specialized or support functions.

[0059] The processor 210 may be connected to the memory 220 via the bus 270-3 in a DMA configuration. To simplify the present disclosure, the memory 220 is disclosed as a single logical block, but in a physical embodiment, may include one or more blocks of any suitable volatile or non-volatile memory technology, including, for example, double data rate random access memory (DDRRAM), static random access memory (SRAM), dynamic random access memory (DRAM), persistent fast memory (PFM) such as Intel® 3D Crosspoint (3DXP), cache, L1 or L2 memory, on-chip memory, registers, flash memory, read-only memory (ROM), optical media, virtual memory area, magnetic or tape storage, or the like. The memory 220 may be provided locally, or the memory 220 may be provided elsewhere, such as in the case of a data center with a 3DXP memory server. In some embodiments, the memory 220 may include a relatively low-latency volatile main memory, while the storage 250 may include a relatively high-latency non-volatile memory. However, the memory 220 and the storage 250 do not have to be physically separate devices, and in some examples may simply represent a logical separation of functions. These lines can be particularly blurred where the only long term memory is battery backed RAM or main memory is provided as PFM.It should also be noted that although DMA is disclosed as a non-limiting example, DMA is not the only protocol consistent with this specification and other memory architectures are available.

[0060] An operating system 222 may be provided, but it is not required in all embodiments. For example, some embedded systems operate on a "bare metal" for speed, efficiency, and resource conservation. However, in contemporary systems, even minimalist embedded systems typically include some kind of operating system. In the case where it is provided, operating system 222 may include any appropriate operating system, such as Microsoft Windows, Linux, Android, Mac OSX, Apple iOS, Unix, or similar operating systems. Some of the above may be used more often on a type of device than another. For example, a desktop computer or an engineering workstation may be more likely to use one of Microsoft Windows, Linux, Unix, or Mac OSX. A portable computer, which is typically a portable finished device with fewer customization options, may be more likely to run Microsoft Windows or Mac OSX. A mobile device may be more likely to run Android or iOS. Embedded devices often use embedded Linux or a dedicated embedded operating system (OS) such as VxWorks. However, these examples are not intended to be restrictive.

[0061] Storage 250 may be any kind of memory 220, or may be a separate non-volatile memory device. Storage 250 may include one or more non-transitory computer-readable media, including as non-limiting examples a hard drive, a solid-state drive, an external storage, a redundant array of independent disks (RAID), a redundant array of independent nodes (RAIN), a network attached storage, an optical storage, a tape drive, a backup system, a cloud storage, or any combination of the above. Storage 250 may be or may include one or more databases stored in other configurations, and may include a stored copy of operating software such as an operating system 222 and software portions of a client agent 224. In some examples, storage 250 may be a non-transitory computer-readable storage medium including hardware instructions or logic encoded as processor instructions or on an ASIC. Many other configurations are also possible and are intended to be included within the broad scope of this specification.

[0062] A network interface 260 may be provided to communicatively couple the client device 200 to a wired or wireless network. As used throughout this specification, a "network" may include any communication platform or medium operable to exchange data or information within or between computing devices, including, as non-limiting examples, Ethernet, WiFi, fabric, ad hoc local networks, an Internet architecture that provides computing devices with the ability to interact electronically, a plain old telephone system (POTS) that computing devices may use to perform transactions (wherein the transactions may be facilitated by a human operator or wherein the transactions may be manually keyed into a telephone or other suitable electronic device), any packet data network (PDN) that provides a communication interface or exchange between any two nodes in the system, or any local area network (LAN), metropolitan area network (MAN), wide area network (WAN), wireless local area network (WLAN), virtual private network (VPN), intranet, or any other suitable architecture or system that facilitates communication in a network or telephony environment. Note that in some embodiments, the network interface 260 may be or may include a host fabric interface (HFI).

[0063] The client agent 224 can be a client application that accesses functions (such as search services) provided by a data center. In one example, the client agent 224 is operable to perform a computer-implemented method as described in this specification. The client agent 224 may include one or more tangible non-temporary computer-readable media having executable instructions stored thereon, the executable instructions being operable to instruct a processor to provide the client agent 224. The client agent 224 may also include a processor having corresponding memory instructions that instruct the processor to execute the desired method. As used throughout this specification, an "engine" includes any combination of one or more logical elements of similar or dissimilar types that are operable for and configured to execute one or more methods or functions of the engine. In some cases, the client agent 224 may include a dedicated integrated circuit designed to execute a method or a portion thereof, and may also include software instructions that are operable to instruct a processor to execute the method. In some cases, the client agent 224 may run as a "daemon" process. A "daemon" may include a series of executable instructions or any program, whether implemented in hardware, software, firmware, or any combination thereof, that runs as a background process, a terminate-and-stay-resident program, a service, a system extension, a control panel, a boot program, a basic input / output system (BIOS) subroutine, or any similar program that operates without direct user interaction. In some embodiments, the daemon process may run with elevated privileges in a "driver space" associated with ring 0, 1, or 2 in a protection ring architecture. It should also be noted that the client agent 224 may also include other hardware and software, including, as non-limiting examples, configuration files, registry entries, and interactive or user-mode software.

[0064] In one example, the client agent 224 includes executable instructions stored on a non-transitory medium operable to perform methods according to the present specification. At an appropriate time, such as when the client device 200 is booted, or when a command comes from the operating system 222 or the user 120, the processor 210 can retrieve a copy of the instructions from the storage 250 and load it into the memory 220. The processor 210 can then iteratively execute the instructions of the client agent 224 to provide the desired method.

[0065] The peripheral device interface 240 can be configured to interface with any auxiliary device that is connected to the client device 200 but is not necessarily part of the core architecture of the client device 200. The peripheral device can be operable to provide extended functionality to the client device 200, and may or may not be completely dependent on the client device 200. In some cases, the peripheral device itself can be a computing device. As non-limiting examples, the peripheral device can include input and output devices such as a display, a terminal, a printer, a keyboard, a mouse, a modem, a data port (e.g., serial, parallel, universal serial bus (USB), Firewire (Firewire) or the like), a network controller, an optical medium, an external storage, a sensor, a transducer, an actuator, a controller, a data acquisition bus, a camera, a microphone, a speaker, or an external storage.

[0066] In one example, peripherals include display adapter 242, audio driver 244, and input / output (I / O) driver 246. Display adapter 242 can be configured to provide human-readable visual output, such as command line interface (CLI) or graphical desktop such as Microsoft Windows, Apple OSX desktop or desktop based on Unix / Linux "x" Windows system. As a non-limiting example, display adapter 242 can provide output in any suitable format, such as coaxial output, composite video, component video, video graphics array (VGA), or digital output such as digital video interface (DVI) or high-definition multimedia interface (HDMI). In some examples, display adapter 242 can include hardware graphics card, which can have its own memory and its own graphics processing unit (GPU). Audio driver 244 can provide an interface for audible sound, and can include hardware sound card in some examples. As non-limiting examples, sound output may be provided in analog (such as a 3.5 mm stereo jack), component ("RCA") stereo, or in a digital audio format such as Sony / Philips Digital Interface Format (S / PDIF), Audio Engineering Society-3 (AES3), Audio Engineering Society-47 (AES47), HDMI, USB, Bluetooth, or Wi-Fi audio. Note that in embodiments where client device 200 is a virtual machine, peripherals may be provided remotely via a device for accessing the virtual machine.

[0067] Figure 3 is a block diagram of a server-type device 300 according to one or more examples of the present specification. Figure 2 As described, server 300 may be any suitable computing device. In general, unless otherwise specifically stated, Figure 2 The definitions and examples may be considered to apply equally to Figure 3 Server 300 is described herein separately to illustrate that in certain embodiments, logical operations may be divided along a client-server model, with client device 200 providing certain localized tasks and server 300 providing certain other centralized tasks.

[0068] Note that, Figure 3 The server 300 of FIG. 300 particularly illustrates the classic "von Neumann architecture" aspects of the server 300 with a focus on functional blocks. Other figures in this document (e.g., the following Figure 4a , Figure 4b and Figure 5 ) may illustrate other aspects of client or server devices with a greater focus on virtualization aspects. These illustrated embodiments are not intended to be mutually exclusive or to infer necessary distinctions. Instead, the various views and diagrams are intended to illustrate different perspectives and aspects of these devices.

[0069] In a particular example, server device 300 may be a memory server as illustrated herein.

[0070] The server 300 includes a processor 310 connected to a memory 320 having stored therein executable instructions for providing at least software portions of an operating system 322 and a server engine 324. The server engine 324 may provide data center functionality, such as a search service. Other components of the server 300 include storage 350 and a host architecture interface 360. Figure 2 As described in , each logic block may be provided by one or more similar or dissimilar logic elements.

[0071] In an example, processor 310 is communicatively coupled to memory 320 via a memory bus 370-3, which may be, for example, a direct memory access (DMA) bus. Processor 310 may be communicatively coupled to other devices via system bus 370-1.

[0072] Processor 310 may be connected to memory 320 via DMA bus 370-3 in a DMA configuration, or via any other suitable memory configuration. Figure 2 As discussed in , memory 320 may include one or more logic elements of any suitable type. Memory 320 may include persistent fast memory, such as 3DXP or the like.

[0073] As combined Figure 2As described above, storage 350 may be any type of memory 320, or may be a separate device. Storage 350 may be or may include one or more databases stored in other configurations, and may include storage copies of operating software such as operating system 322 and software portions of server engine 324.

[0074] A host fabric interface (HFI) 360 may be provided to communicatively couple the server 300 to a wired or wireless network including a host fabric. The host fabric may include a switch interface for communicatively coupling nodes in a cloud or cloud-like environment. HFI 360 is used here as an example, but any other suitable network interface (as discussed in conjunction with network interface 260) may be used.

[0075] The server engine 324 is as follows Figure 2 The engine described in and, in one example, includes one or more logic elements operable to perform the computer-implemented methods described in this specification. The software portion of the server engine 324 may run as a daemon process.

[0076] The server engine 324 may include one or more non-transitory computer-readable media having executable instructions stored thereon that are operable to instruct the processor to provide the server engine 324. At an appropriate time, such as when the server 300 is booted or when a command comes from the operating system 322 or a user 120 or a security administrator 150, the processor 310 may retrieve a copy of the server engine 324 (or its software portion) from storage 350 and load it into memory 320. The processor 310 may then iteratively execute the instructions of the server engine 324 to provide the desired method.

[0077] Figure 4a 4 is a block diagram of a software defined network 400. In software defined networking (SDN), the data plane is separated from the control plane to achieve certain advantages. SDN is just one flavor of virtualization, shown here to illustrate one option for network setup.

[0078] Figure 4bThe network function virtualization (NFV) illustrated in is the second non-restrictive style of network virtualization, often regarded as an addition or improvement to SDN, but sometimes regarded as a separate entity. NFV was originally conceived as a method for providing reduced capital expenditures (Capex) and operating expenses (Opex) for telecommunications services, which rely heavily on fast, single-purpose service equipment. An important feature of NFV is to replace proprietary dedicated hardware devices with virtual devices running on commercial off-the-shelf (COTS) hardware within a virtualized environment. In addition to Capex and Opex savings, NFV also provides a more agile and adaptive network. As network loads change, virtual network functions (VNFs) can be provided ("spun up") or removed ("spun down") to meet network needs. For example, at high loads, more load balancer VNFs can be increased to distribute services to more workload servers (which can themselves be virtual machines). When experiencing more suspicious services, additional firewalls or deep packet inspection (DPI) devices may be required.

[0079] Because NFV was originally a telecom feature, many NFV instances focus on telecom. However, NFV is not limited to telecom services. In a broad sense, NFV includes one or more VNFs running within a network function virtualization infrastructure (NFVI). Often, VNFs are inline service functions that are separated from workload servers or other nodes (in many cases, workload type functions have been virtualized for a long time). These VNFs can be linked together into a service chain, which can be defined by a virtual subnet and can include a series of network services that provide behind-the-scenes work such as security, logging, billing, and the like. In one example, an incoming packet passes through a chain of services in a service chain, where one or more services are provided by VNFs, but historically each of those functions may have been provided by custom hardware in a physical service device. Because NFV can be adjusted up and down to meet demand, the allocation of hardware and other resources can be made more efficient. Processing resources can be allocated to meet the maximum demand, but with physical service devices, any unused capacity on the device is simply wasted, and increasing capacity to meet demand requires insertion in physical (expensive) custom service devices.

[0080] Figure 4a and Figure 4b The diagram of FIG. 400 may be considered more practical, whereas the diagram of FIG. 1 may be more of a high-level logical layout of the network. However, it should be understood that SDN 400 ( Figure 4a )、NFVI 404 ( Figure 4b ) and the enterprise network 100 may be the same network, or may be separate networks.

[0081] exist Figure 4a 1 , SDN 400 may include an SDN controller 410, a plurality of network devices 430, and a plurality of host devices 440. Some or all of SDN controller 410, network devices 430, and host devices 440 may be embodied within workload cluster 142 of FIG. 1 , or may otherwise form part of enterprise network 170.

[0082] The SDN 400 is controlled by an SDN controller 410. The SDN controller 410 is communicatively coupled to a plurality of network devices 430. Specifically, ND1 430-1, ND2 430-2, and ND5 430-5 are directly communicatively coupled to the SDN controller 410. The network devices as well as ND3 430-3 and ND4 430-4 are not directly coupled to the SDN controller 410, but are instead coupled via intermediate devices such as ND2 430-2 and ND5 430-5.

[0083] Some of the network devices 430 are also directly communicatively coupled to the host devices 440. Specifically, network device ND1 is directly coupled to host A 440-1 having an IP address of 10.0.0.10 and a MAC address of FA:16:3:01:61:8. Network device ND2 430-2 is directly coupled to host B 440-2 having an IP address of 10.0.0.20 and a MAC address of FA:16:3:01:63:B3. Network device ND5 430-5 is directly coupled to host D 440-3 having an IP address of 10.0.0.30 and a MAC address of FA:16:3:01:54:83.

[0084] Network devices 430 may be configured to perform various network functions, such as load balancing, firewall, deep packet inspection (DPI), DNS, antivirus, or any other suitable network function, as non-limiting examples. The specific arrangement of interconnections between network devices 430 and from network devices 430 to host devices 440 may be determined by the specific network configuration and needs. Thus, Figure 4a The specific configurations shown should be understood as merely illustrative examples.

[0085] Each network device 430 may have multiple ingress and / or egress interfaces, such as physical Ethernet or fabric ports. In an example, each interface may have a label or new name, such as P1, P2, P3, P4, P5, etc. Therefore, certain aspects of the network layout may be determined by examining which devices are connected on which interface. For example, network device ND1 430-1 has an ingress interface for receiving instructions and communicating with SDN controller 410. ND1 430-1 also has an interface P1 that is communicatively coupled to host A 440-1. ND1 430-1 has an interface P2 that is communicatively coupled to ND2 430-2. In the case of ND2 430-2, it is also coupled to ND1 430-1 on its own interface P2, and is coupled to host B 440-2 via interface P1. ND2 430-2 is communicatively coupled to intermediate devices ND3 430-3 and ND4 430-4 via interfaces P3 and P4, respectively. Additional interface definitions are visible throughout the diagram.

[0086] When traffic flows from one interface to another, a flow table may be defined for the traffic. This flow table is used so that a network device such as ND2 430-2, after receiving a packet, can determine where to send it next.

[0087] For example, the following flow tables may be defined for ND1 430 - 1 to ND4 430 - 4 .

[0088] Entrance I / F Source MAC Destination Mac Source IP Destination IP action P1 any fa:16:3e:01:54:a3 any 10.0.0.30 P2

[0089] Table 1. ND1 flow table.

[0090] Entrance I / F Source MAC Destination Mac Source IP Destination IP action P2 any fa:16:3e:01:54:a3 any 10.0.0.30 P4

[0091] Table 2. ND2 flow table.

[0092] Entrance I / F Source MAC Destination Mac Source IP Destination IP action P1 any fa:16:3e:01:54:a3 any 10.0.0.30 P3

[0093] Table 3. ND3 flow table.

[0094] Entrance I / F Source MAC Destination Mac Source IP Destination IP action P3 any fa:16:3e:01:54:a3 any 10.0.0.30 P1

[0095] Table 4. ND4 flow table.

[0096] Figure 4b is a block diagram of a network function virtualization (NFV) architecture according to one or more examples of the present specification. Like SDN, NFV is a subset of network virtualization. Therefore, instead of or in addition to Figure 4a In addition to the network, you can also define Figure 4b In other words, some parts of the network may rely on SDN, while other parts (or the same parts) may rely on NFV.

[0097] exist Figure 4b In the example of FIG4 , an NFV orchestrator 402 manages many VNFs running on NFVI 404. NFV requires non-trivial resource management, such as allocating a very large pool of computing resources between the appropriate number of instances of each VNF, managing connections between VNFs, determining how many instances to allocate for each VNF, and managing memory, storage, and network connections. This may require complex software management, thus requiring an NFV orchestrator 402.

[0098] Note that the NFV coordinator 402 itself is typically virtualized (rather than a dedicated hardware device). The NFV coordinator 402 can be integrated into an existing SDN system, where an operations support system (OSS) manages the SDN. This can interact with a cloud resource management system (e.g., OpenStack) to provide NVF coordination. There are many commercially available, off-the-shelf, proprietary, and open source solutions for NFV coordination and management (sometimes referred to as NFVMANO). In addition to the NFV coordinator 402, the NFVMANO can also include functions such as virtualized infrastructure management (VIM) and VNF managers.

[0099] NFVI 404 may include hardware, software, and other infrastructure that enables VNFs to run. This may include, for example, one or more racks of blade or socket servers (including, for example, processors, memory, and storage), one or more data centers, other hardware resources distributed across one or more geographic locations, hardware switches, or network interfaces. NFVI 404 may also include a software architecture that enables hypervisors to run and is managed by NFV coordinator 402. NFVI 402 may include NFVI points of presence (NFVI-Pops) where operators deploy VNFs.

[0100] Running on the NFVI 404 are a number of virtual machines, each of which in this example is a VNF providing a virtual service appliance. As non-limiting and illustrative examples, these include VNF 1 410 as a firewall, VNF 2 412 as an intrusion detection system, VNF 3 414 as a load balancer, VNF 4 416 as a router, VNF 5 418 as a session border controller, VNF 6 420 as a deep packet inspection (DPI) service, VNF 7 422 as a network address translation (NAT) module, VNF 8 424 providing call security associations, and VNF 9 426 as a second load balancer that is turned up to meet the increased demand.

[0101] Firewall 410 is a security device that monitors and controls traffic (both incoming and outgoing) based on matching the traffic to a list of "firewall rules". Firewall 410 can be a barrier between a relatively trusted (e.g., internal) network and a relatively untrusted network (e.g., the Internet). Once a communication has passed inspection by firewall 410, it can be forwarded to other parts of the network.

[0102] Intrusion detection 412 monitors the network for malicious activity or policy violations. Events can be reported to security administrator 150, or collected and analyzed by a security information and event management (SIEM) system. In some cases, intrusion detection 412 may also include anti-virus or anti-malware scanners.

[0103] Load balancers 414 and 426 can farm out traffic to a set of substantially identical workload servers to distribute the work in a fair manner. In one example, the load balancer provides many "buckets" of traffic and assigns each bucket to a workload server. Incoming traffic is assigned to buckets based on factors such as a hash of the source IP address. Because the hash is assumed to be fairly evenly distributed, each workload server receives a reasonable amount of traffic.

[0104] Router 416 forwards packets between networks or subnetworks. For example, router 416 may include one or more ingress interfaces and multiple egress interfaces, where each egress interface is associated with a resource, subnetwork, virtual private network, or other partition. When traffic enters on an ingress interface, router 416 determines what destination it should go to and routes the packet to the appropriate egress interface.

[0105] Session border controller 418 controls Voice over IP (VoIP) signaling and media flows to establish, conduct, and terminate calls. In this context, a "session" refers to a communication event (e.g., a "call"). A "border" refers to the boundary between two different parts of a network (similar to a firewall).

[0106] DPI device 420 provides deep packet inspection, including inspecting not only the header of a packet, but also the content of the packet to search for potentially unwanted content (PUC), such as protocol non-compliances, malware, viruses, spam, or intrusions.

[0107] NAT module 422 provides network address translation services to remap one IP address space to another IP address space (eg, mapping addresses within a private subnet to the larger Internet).

[0108] Call security association 424 creates a security association for a call or other session (see session border controller 418 above). Maintaining this security association may be critical because the call may be dropped if the security association is broken.

[0109] 4 illustrates that a number of VNFs have been provisioned and exist within the NFVI 404. This diagram does not necessarily illustrate any relationship between the VNFs and the larger network.

[0110] Figure 5 A block diagram of components of a computing platform 500 according to one or more examples of the present specification is illustrated. In the depicted embodiment, the computer platform 500 includes multiple platforms 502 and a system management platform 506 coupled together by a network 508. In other embodiments, the computer system may include any suitable number of (i.e., one or more) platforms. In some embodiments (e.g., when the computer system includes only a single platform), all or part of the system management platform 506 may be included on the platform 502. The platform 502 may include a platform logic 510 having one or more central processing units (CPUs) 512, a memory 514 (which may include any number of different modules), a chipset 516, a communication interface 518, and any other suitable hardware and / or software to execute a hypervisor 520 or other operating system capable of executing workloads associated with applications running on the platform 502. In some embodiments, the platform 502 may act as a host platform for one or more client systems 522 that invoke these applications. Platform 500 may represent any suitable computing environment, such as a high performance computing environment, a data center, a communications service provider infrastructure (e.g., one or more portions of an evolved packet core), an in-memory computing environment, a computing system in a vehicle (e.g., an automobile or an aircraft), an Internet of Things environment, an industrial control system, other computing environments, or combinations thereof.

[0111] In various embodiments of the present disclosure, the accumulated stress and / or stress rate accumulated to multiple hardware resources (e.g., cores and non-cores) are monitored and the entities of the computer platform 500 (e.g., the system management platform 506, the hypervisor 520, or other operating system) can assign the hardware resources of the platform logic 510 to execute the workload in accordance with the stress information. For example, the system management platform 506, the hypervisor 520, or other operating system or the CPU 512 can determine to schedule the workload to one or more cores above based on the stress information. In some embodiments, the self-diagnostic capability can be combined with stress monitoring to more accurately determine the health of the hardware resources. Such embodiments can allow optimization in deployment aspects including network function virtualization (NFV), software defined networking (SDN), or mission-critical applications. For example, stress information can be consulted during the initial placement of a VNF (virtual network function) or in order to migrate from one platform to another in order to improve reliability and capacity utilization.

[0112] Each platform 502 may include platform logic 510. Platform logic 510 includes one or more CPUs 512, memory 514, one or more chipsets 516, and communication interfaces 518, in addition to other logic that enables the functionality of platform 502. Although three platforms are illustrated, computer platform 500 may include any suitable number of platforms. In various embodiments, platform 502 may reside on a circuit board mounted in a chassis, rack, or other suitable structure that includes multiple platforms coupled together by a network 508 (which may include, for example, a rack or backplane switch).

[0113] The CPUs 512 may each include any suitable number of processor cores and supporting logic (e.g., uncores). The cores may be coupled to each other, to memory 514, to at least one chipset 516, and / or to communication interface 518 via one or more controllers resident on the CPU 612 and / or chipset 516. In certain embodiments, the CPUs 612 are embodied within a socket that is permanently or removably coupled to the platform 502. In conjunction with the following Figure 2 CPU 612 is described in further detail. Although four CPUs are shown, platform 502 may include any suitable number of CPUs.

[0114] Memory 514 may include any form of volatile or non-volatile memory, including but not limited to magnetic media (e.g., one or more tape drives), optical media, random access memory (RAM), read-only memory (ROM), flash memory, removable media, or one or more other suitable local or remote memory components. Memory 514 may be used by platform 502 for short-term, medium-term, and / or long-term storage. Memory 514 may store any suitable data or information utilized by platform logic 510, including software embedded in a computer-readable medium and / or coded logic (e.g., firmware) incorporated in hardware or otherwise stored. Memory 514 may store data used by the core of CPU 512. In some embodiments, memory 514 may also include storage for instructions that may be executed by the core of CPU 512 or other processing elements (e.g., logic residing on chipset 516) to provide functionality associated with manageability engine 526 or other components of platform logic 510. Additionally or alternatively, chipset 516 may each include a memory that may have any of the characteristics described herein with respect to memory 514. The memory 514 may also store results and / or intermediate results of various calculations and determinations performed by the CPU 512 or processing elements on the chipset 516. In various embodiments, the memory 514 may include one or more modules of system memory coupled to the CPU 512 through a memory controller (which may be external to the CPU 512 or integrated with the CPU 512). In various embodiments, one or more particular modules of the memory 514 may be dedicated to a particular CPU 512 or other processing device, or may be shared across multiple CPUs 512 or other processing devices.

[0115] In various embodiments, memory 514 may store stress information, such as cumulative stress values ​​associated with hardware resources of platform logic 510, in non-volatile memory so that when power is lost, the cumulative stress values ​​are maintained. In particular embodiments, a hardware resource may include non-volatile memory (e.g., on the same die as the particular hardware resource) for storing cumulative stress values ​​for the hardware resource.

[0116] The platform 502 may also include one or more chipsets 516 that contain any suitable logic for supporting the operation of the CPU 512. In various embodiments, the chipset 516 may reside on the same die or package as the CPU 612 or on one or more different dies or packages. Each chipset may support any suitable number of CPUs 512. The chipset 516 may also include one or more controllers for coupling other components of the platform logic 510 (e.g., a communication interface 518 or memory 514) to the one or more CPUs. Additionally or alternatively, the CPU 512 may include an integrated controller. For example, the communication interface 518 may be directly coupled to the CPU 512 via an integrated I / O controller resident on each CPU.

[0117] In the depicted embodiment, each chipset 516 also includes a manageability engine 526. The manageability engine 526 may include any suitable logic for supporting the operation of the chipset 516. In particular embodiments, the manageability engine 526 (which may also be referred to as an innovation engine) is capable of collecting real-time telemetry data from the chipset 516, the CPU(s) 512 and / or memory 514 managed by the chipset 516, other components of the platform logic 510, and / or various connections between components of the platform logic 510. In various embodiments, the collected telemetry data includes the stress information described herein.

[0118] In various embodiments, the manageability engine 526 operates as an out-of-band asynchronous computing agent that is capable of interfacing with various elements of the platform logic 510 to collect telemetry data with no or minimal disruption to processes running on the CPU 512. For example, the manageability engine 526 may include a dedicated processing element (e.g., a processor, controller, or other logic) on the chipset 516 that provides the functionality of the manageability engine 526 (e.g., by executing software instructions), thereby preserving processing cycles of the CPU 512 for operations associated with the workload performed by the platform logic 510. Furthermore, the dedicated logic for the manageability engine 526 may operate asynchronously with respect to the CPU 512 and may gather at least some of the telemetry data without increasing the load on the CPU.

[0119] The manageability engine 526 can process the telemetry data that it collects (specific examples of the processing of stress information will be provided herein). In various embodiments, the manageability engine 526 reports the data that it collects and / or the results of its processing to other elements in the computer system, such as one or more hypervisors 520 or other operating systems and / or system management software (which can run on any suitable logic such as the system management platform 506). In some embodiments, the telemetry data is periodically updated and reported to one or more of these entities. In certain embodiments, critical events such as a core that has accumulated excessive stress can be reported in advance of the normal interval for reporting telemetry data (e.g., a notification can be sent immediately upon detection).

[0120] In various embodiments, manageability engine 526 may include programmable code that may be configured to set which CPU(s) 512 a particular chipset 516 will manage and / or which telemetry data will be collected.

[0121] The chipsets 516 also each include a communication interface 528. The communication interface 528 can be used for communication of signaling and / or data between the chipset 516 and one or more I / O devices, one or more networks 508, and / or one or more devices coupled to the network 508 (e.g., the system management platform 506). For example, the communication interface 528 can be used to send and receive network services such as data packets. In a particular embodiment, the communication interface 528 includes one or more physical network interface controllers (NICs), also known as network interface cards or network adapters. The NIC may include electronic circuits for communicating using any suitable physical layer and data link layer standards such as Ethernet (e.g., as defined by the IEEE 802.3 standard), Fibre Channel, InfiniBand technology, Wi-Fi, or other suitable standards. The NIC may include one or more physical ports that can be coupled to a cable (e.g., an Ethernet cable). The NIC may enable communication between any suitable element of the chipset 516 (e.g., the manageability engine 526 or the switch 530) and another device coupled to the network 508. In some embodiments, network 508 may include a switch with bridging and / or routing functionality that is external to platform 502 and operable to couple various NICs distributed throughout computer platform 500 (e.g., on different platforms) to each other. In various embodiments, the NICs may be integrated with the chipset (i.e., may be on the same integrated circuit or circuit board as the rest of the chipset logic) or may be on a different integrated circuit or circuit board that is electromechanically coupled to the chipset.

[0122] In particular embodiments, communication interface 528 may allow communication of data associated with management and monitoring functions performed by manageability engine 526 (e.g., between manageability engine 526 and system management platform 506). In various embodiments, manageability engine 526 may utilize elements of communication interface 528 (e.g., one or more NICs) to report telemetry data (e.g., to system management platform 506) in order to preserve the use of the NICs of communication interface 518 for operations associated with workloads performed by platform logic 510. In some embodiments, communication interface 528 may also allow I / O devices (e.g., disk drives, other NICs, etc.) that are integrated with the platform or external to the platform to communicate with the CPU cores.

[0123] Switch 530 may be coupled to various ports of communication interface 528 (e.g., provided by a NIC) and may exchange data between these ports and various components of chipset 516 (e.g., one or more Peripheral Component Interconnect Express (PCIe) lanes coupled to CPU 512). Switch 530 may be a physical or virtual (i.e., software) switch.

[0124] The platform logic 510 may include an additional communication interface 518. Similar to the communication interface 528, the communication interface 518 may be used for communication of signaling and / or data between the platform logic 510 and one or more networks 508 and one or more devices coupled to the network 508. For example, the communication interface 518 may be used to send and receive network services such as data packets. In a particular embodiment, the communication interface 518 includes one or more physical NICs. These NICs may enable communication between any suitable element of the platform logic 510 (e.g., CPU 512 or memory 514) and another device coupled to the network 508 (e.g., an element of another platform or remote computing device coupled to the network 508 via one or more networks). In a particular embodiment, the communication interface 518 may allow devices external to the platform (e.g., disk drives, other NICs, etc.) to communicate with the CPU core. In various embodiments, the NIC of the communication interface 518 may be coupled to the CPU via an I / O controller (which may be external to the CPU 512 or integrated with the CPU 512).

[0125] The platform logic 510 may receive and execute any suitable type of workload. The workload may include any request to utilize one or more resources of the platform logic 510, such as one or more cores or associated logic. For example, the workload may include a request to instantiate a software component, such as an I / O device driver 524 or a client system 522; a request to process a network packet received from a virtual machine 532 or a device external to the platform 502, such as a network node coupled to the network 508; a request to execute a process or thread associated with the client system 522, an application running on the platform 502, the hypervisor 520, or other operating system running on the platform 502; or other suitable processing request.

[0126] In various embodiments, the platform 502 can execute any number of client systems 522. A client system can include a single virtual machine (e.g., virtual machine 532a or 532b) or multiple virtual machines operating together (e.g., virtual network function (VNF) 534 or service function chain (SFC) 536). As depicted, various embodiments can include various types of client systems 522 present on the same platform 502.

[0127] Virtual machine 532 may emulate a computer system with its own dedicated hardware. Virtual machine 532 may run a guest operating system on top of hypervisor 520. Components of platform logic 510 (e.g., CPU 512, memory 514, chipset 516, and communication interface 518) may be virtualized so that to the guest operating system it appears that virtual machine 532 has its own dedicated components.

[0128] Virtual machine 532 can include virtualized NIC (vNIC) used by virtual machine as its network interface. vNIC can be assigned media access control (MAC) address or other identifier, thereby allowing multiple virtual machines 532 to be individually addressable in the network.

[0129] In some embodiments, the virtual machine 532b may be paravirtualized. For example, the virtual machine 532b may include an enhanced driver (e.g., a driver that provides higher performance or has a higher bandwidth interface to the underlying resources or capabilities provided by the hypervisor 520). For example, the enhanced driver may have a faster interface to the underlying virtual switch 538 than the default driver to obtain higher network performance.

[0130] The VNF 534 may include a software implementation of functional building blocks with defined interfaces and behaviors that can be deployed in a virtualized infrastructure. In a particular embodiment, the VNF 534 may include one or more virtual machines 532 that collectively provide specific functionality (e.g., wide area network (WAN) optimization, virtual private network (VPN) termination, firewall operation, load balancing operation, security functions, etc.). The VNF 534 running on the platform logic 510 may provide the same functionality as traditional network components implemented by dedicated hardware. For example, the VNF 534 may include components for executing any suitable NFV workload, such as a virtualized evolved packet core (vEPC) component, a mobility management entity (MME), a third generation partnership project (3GPP) control and data plane components, etc.

[0131] SFC 536 is a group of VNFs 534 organized as a chain to perform a series of operations (such as network packet processing operations). Service function chaining can provide the ability to define an ordered list of network services (e.g., firewall, load balancer) that are stitched together in the network to create a service chain.

[0132] Hypervisor 520 (also referred to as a virtual machine monitor) may include logic for creating and running guest systems 522. Hypervisor 520 may present a virtual operating platform to guest operating systems run by virtual machines (i.e., it appears to the virtual machines that they are running on separate physical nodes when the guest operating systems are actually consolidated onto a single hardware platform) and manage the execution of guest operating systems through platform logic 510. The services of hypervisor 520 may be provided through virtualization in software or through hardware-assisted resources that require minimal software intervention, or both. Multiple instances of various guest operating systems may be managed by hypervisor 520. Each platform 502 may have a separate instantiation of hypervisor 520.

[0133] Hypervisor 520 may be a local or bare metal hypervisor that runs directly on platform logic 510 to control the platform logic and manage guest operating systems. Alternatively, hypervisor 520 may be a hosted hypervisor that runs on a host operating system and abstracts the guest operating systems from the host operating system. Various embodiments may include one or more non-virtualized platforms 502, in which case any suitable features or functions of hypervisor 520 described herein may be applied to the operating system of the non-virtualized platform.

[0134] Hypervisor 520 may include a virtual switch 538 that may provide virtual switching and / or routing functionality to the virtual machines of client system 522. Virtual switch 538 may include a logical switching fabric that couples the vNICs of virtual machines 532 to each other, thereby creating a virtual network through which the virtual machines may communicate with each other. Virtual switch 538 may also be coupled to one or more networks (e.g., network 508) via the physical NICs of communication interface 518 to allow communication between virtual machines 532 and one or more network nodes external to platform 502 (e.g., virtual machines running on different platforms 502 or nodes coupled to platform 502 via the Internet or other networks). Virtual switch 538 may include software elements that are executed using components of platform logic 510. In various embodiments, the hypervisor 520 can communicate with any suitable entity (e.g., an SDN controller) that can cause the hypervisor 520 to reconfigure parameters of the virtual switch 538 in response to changing conditions in the platform 502 (e.g., the addition or removal of virtual machines 532 or the identification of optimizations that can be made to enhance the performance of the platform).

[0135] Hypervisor 520 may also include resource allocation logic 544, which may include logic for determining allocation of platform resources based on telemetry data (which may include stress information). Resource allocation logic 544 may also include logic for communicating with various components of the platform logic 510 entity of platform 502, such as components of platform logic 502, to implement such optimizations. For example, resource allocation logic 544 may direct which hardware resources of platform logic 510 are to be used to execute a workload based on stress information.

[0136] Any suitable logic may make one or more of these optimization decisions. For example, system management platform 506; resource allocation logic 544 of hypervisor 520 or other operating system; or other logic of platform 502 or computer platform 500 that may be capable of making such decisions (alone or in conjunction with other elements of platform 502). In particular embodiments, system management platform 506 may communicate with hypervisor 520 (using in-band or out-of-band communications) to specify optimizations that should be used to satisfy policies stored at the system management platform.

[0137] In various embodiments, the system management platform 506 may receive telemetry data from the multiple platforms 502 and manage workload placement across the multiple platforms 502. The system management platform 506 may communicate with the hypervisor 520 (e.g., in an out-of-band manner) or with other operating systems of the various platforms 502 to implement workload placement directed by the system management platform.

[0138] The elements of platform logic 510 may be coupled together in any suitable manner. For example, a bus may couple any components together. The bus may include any known interconnect, such as a multi-drop bus, a mesh interconnect, a ring interconnect, a point-to-point interconnect, a serial interconnect, a parallel bus, a coherent (e.g., cache coherent) bus, a layered protocol architecture, a differential bus, or a GTL bus.

[0139] The elements of computer platform 500 can be coupled together in any suitable manner such as through one or more networks 508. Network 508 can be any suitable network or a combination of one or more networks operated using one or more suitable networking protocols. A network can represent a series of nodes, points and interconnected communication paths for receiving and sending information packets propagated through a communication system. For example, a network can include one or more firewalls, routers, switches, security devices, antivirus servers or other useful network devices. The network provides a communication interface between a source and / or a host, and can include any local area network (LAN), wireless local area network (WLAN), metropolitan area network (MAN), intranet, extranet, Internet, wide area network (WAN), virtual private network (VPN), cellular network, or any other appropriate architecture or system that promotes communication in a network environment. The network can include any number of hardware or software elements that are coupled to each other (and communicate with each other) through a communication medium. In various embodiments, client system 522 can communicate with nodes outside computer platform 500 through network 508.

[0140] Figure 6 A block diagram of a central processing unit (CPU) 612 in accordance with certain embodiments is illustrated. Although CPU 612 depicts a particular configuration, the core and other components of CPU 612 may be arranged in any suitable manner. CPU 612 may include any processor or processing device, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, an application processor, a coprocessor, a system on a chip (SOC), or other device for executing code. In the depicted embodiment, CPU 612 includes four processing elements (core 630 in the depicted embodiment), which may include asymmetric processing elements or symmetric processing elements. However, CPU 612 may include any number of processing elements that may be symmetric or asymmetric.

[0141] In one embodiment, processing element refers to hardware or logic for supporting software threads. Examples of hardware processing elements include: thread units, thread slots, threads, process units, contexts, context units, logical processors, hardware threads, cores and / or any other element that can keep the state of a processor (such as an execution state or an architecture state). In other words, processing element refers to any hardware that can be independently associated with code (such as a software thread, an operating system, an application or other code) in one embodiment. A physical processor (or processor socket) generally refers to an integrated circuit, which potentially includes any number of other processing elements, such as cores or hardware threads.

[0142] A core may refer to logic located on an integrated circuit capable of maintaining an independent architectural state, wherein each independently maintained architectural state is associated with at least some dedicated execution resources. A hardware thread may refer to any logic located on an integrated circuit capable of maintaining an independent architectural state, wherein the independently maintained architectural states share access to execution resources. As can be seen, the line between the nomenclature of hardware threads and cores overlaps when certain resources are shared and other resources are dedicated to an architectural state. Typically, cores and hardware threads are viewed by an operating system as separate logical processors, wherein the operating system is able to schedule operations on each logical processor separately.

[0143] The physical CPU 612 may include any suitable number of cores. In various embodiments, the cores may include one or more out-of-order processor cores or one or more in-order processor cores. However, the cores may be individually selected from any type of core, such as a native core, a software-managed core, a core adapted to execute a native instruction set architecture (ISA), a core adapted to execute a translated ISA, a co-designed core, or other known core. In a heterogeneous core environment (i.e., an asymmetric core), some form of translation (such as binary translation) may be utilized to schedule or execute code on one or both cores.

[0144] In the depicted embodiment, core 630A includes an out-of-order processor with a front end unit 670 for pre-fetching incoming instructions, performing various processing (e.g., caching, decoding, branch prediction, etc.), and passing the instructions / operations onward to an out-of-order (OOO) engine 680. The OOO engine 680 performs further processing on the decoded instructions.

[0145] The front end 670 may include a decoding module coupled to the prefetch logic to decode the prefetched elements. In one embodiment, the prefetch logic includes a separate sequencer associated with the thread slot of the core 630. Typically, the core 630 is associated with a first ISA that defines / specifies instructions that can be executed on the core 630. Typically, a machine code instruction that is part of the first ISA includes a portion of the instruction (called an opcode) that references / specifies the instruction or operation to be performed. The decoding module may include circuits that recognize these instructions from their opcodes and pass the decoded instructions to the pipeline for processing as defined by the first ISA. For example, in one embodiment, the decoder may include logic designed or adapted to recognize specific instructions (such as transaction instructions). As a result of the recognition by the decoder, the architecture of the core 630 takes specific predefined actions to perform tasks associated with the appropriate instructions. It is important to note that any of the tasks, blocks, operations, and methods described herein may be performed in response to a single or multiple instructions; some of which may be new or old instructions. In one embodiment, the decoders of the core 630 recognize the same ISA (or a subset thereof). Alternatively, in a heterogeneous core environment, the decoders of one or more cores (eg, core 630B) may recognize a second ISA (a subset of the first ISA or a different ISA).

[0146] In the depicted embodiment, the out-of-order engine 680 includes a dispatch unit 682 to receive decoded instructions, which may be in the form of one or more microinstructions or μops, from the front end unit 670 and dispatch them to appropriate resources, such as registers, etc. Next, the instructions are provided to a reservation station 684, which reserves resources and schedules them for execution on one of a plurality of execution units 686A-686N. There may be various types of execution units, including, for example, an arithmetic logic unit (ALU), a load and store unit, a vector processing unit (VPU), a floating point execution unit, etc. The results from these different execution units are provided to a re-order buffer (ROB) 688, which takes the out-of-order results and returns them to the correct program order.

[0147] In the depicted embodiment, both the front end unit 670 and the out-of-order engine 680 are coupled to different levels of the memory hierarchy. Specifically shown is an instruction level cache 672, which is in turn coupled to a mid-level cache 676, which is in turn coupled to a final level cache 695. In one embodiment, the final level cache 695 is implemented in an on-chip (sometimes referred to as an uncore) unit 690. The uncore 690 can communicate with a system memory 699, which is implemented via embedded DRAM (eDRAM) in the illustrated embodiment. The various execution units 686 within the out-of-order engine 680 communicate with a first level cache 674 that also communicates with the mid-level cache 676. Additional cores 630B-630D can also be coupled to the final level cache 695.

[0148] In various embodiments, uncore 690 (sometimes referred to as a system agent) may include any suitable logic that is not part of core 630. For example, uncore 690 may include one or more of a last level cache, a cache controller, an on-die memory controller coupled to system memory, a processor interconnect controller (e.g., a Hyperpath interconnect or similar controller), an on-die I / O controller, or other suitable on-die logic.

[0149] In certain embodiments, the non-core 690 may be in a voltage domain and / or frequency domain that is separate from the voltage domain and / or frequency domain of the core. That is, the non-core 690 may be powered by a different supply voltage than the supply voltage used to power the core and / or may operate at a different frequency than the operating frequency of the core.

[0150] The CPU 612 may also include a power control unit (PCU) 640. In various embodiments, the PCU 640 may control the power supply voltage and operating frequency applied to each core (on a per-core basis) and to the uncores. The PCU 640 may also instruct a core or uncore to enter an idle state (where voltage and clocks are not supplied) when no workload is being executed.

[0151] In various embodiments, the PCU 640 may detect one or more stress characteristics of hardware resources (such as cores and uncores). The stress characteristic may include an indication of the amount of stress being placed on the hardware resource. As an example, the stress characteristic may be a voltage or frequency applied to the hardware resource; a power level, current level, or voltage level sensed at the hardware resource; a temperature sensed at the hardware resource; or other suitable measurements. In various embodiments, when a stress characteristic is sensed at a particular moment, multiple measurements of a particular stress characteristic may be performed (e.g., at different locations). In various embodiments, the PCU 640 may detect stress characteristics at any suitable interval.

[0152] In various embodiments, PCU 640 may include a microcontroller that executes embedded firmware to perform various operations associated with stress monitoring described herein. In one embodiment, PCU 640 uses hardware to perform some or all of the PCU functions described herein without executing software instructions. For example, PCU 640 may include fixed and / or programmable logic for performing the functions of the PCU.

[0153] In various embodiments, PCU 640 is a separate component from core 630. In certain embodiments, PCU 640 runs at a clock frequency that is different from the clock frequency used by core 630. In some embodiments where the PCU is a microcontroller, PCU 640 executes instructions according to an ISA that is different from the ISA used by core 630.

[0154] In various embodiments, the CPU 612 may also include non-volatile memory 650 to store stress information associated with the core 630 or the uncore 690 (such as stress characteristics, incremental stress values, cumulative stress values, stress accumulation rates, or other stress information) so that the stress information is maintained when power is lost.

[0155] Figure 7 700 is a block diagram of a computing architecture 700 according to one or more examples of the present specification. In this example, a processing block 702 and a NIC 704 are provided. In this case, the processing block 702 includes a plurality of cores 710, specifically cores 710-1, 710-2, 710-3, and 710-4. Each core 710 includes its own cache agent 720. Specifically, core 710-1 has a cache agent 720-1. Core 710-2 has a cache agent 720-2. Core 710-3 has a cache agent 720-3. And core 710-4 has a cache agent 710-4. Note that the inclusion of four cores and four cache agents in this example is intended to illustrate the principle of operation. In practice, the processing block 702 may include one core with one cache agent, or it may include many cores with many cache agents. In modern data centers, individual nodes may have as many as 64 to 128 cores.

[0156] In this example, processing block 702 interfaces with NIC 704 via PCIe interface 776. Thus, NIC 704 includes a host PCIe interface 772. Note that the PCIe interconnect is used herein as a non-limiting example. In other embodiments, the interconnect may be any suitable interconnect or bus, including an on-die interconnect for an on-die NIC. Thus, host PCIe interface 772 may be more generally referred to as an interconnect interface, which may include an interface for communicatively coupling to any suitable interconnect.

[0157] NIC 704 also includes NIC logic 706, coprocessor 708, and NIC memory 714. Finally, NIC 704 includes a network interface 770, which is provided to communicatively couple NIC 704 to a network or fabric, such as an Intel® OmniPath Fabric or an Ethernet network.

[0158] NIC logic 706 may include general logic for executing network interfaces according to known functions. This includes converting traffic from interface 772 and directing the traffic to network interface 770, and vice versa.

[0159] Similarly, network interface 770 may in some embodiments be a simple network interface providing general interconnection to a network or fabric.

[0160] As described above, the coprocessor 708 provides processing services that offload certain intensive and repetitive tasks from the core 710. As non-limiting examples, these may include security, compression, encryption, or other repetitive tasks. The coprocessor 708 may be an FPGA, an ASIC, a programmable processor with associated software, a firmware device, or some other combination of programmable logic. The coprocessor 708 is provided with a NIC memory 714, which is a block of memory used by the coprocessor 708 to perform its functions. The NIC 804 includes a NIC memory 814, which includes both a shared memory 830 and a dedicated memory 832.

[0161] Figure 8 800 is a block diagram of a computing architecture 800 according to one or more examples of the present specification. In this example, a processing block 802 and a NIC 804 are provided. The processing block 802 includes cores 710-1, 710-2, 710-3, and 710-4. These operate with cache agents 720-1, 720-2, 720-3, and 720-4, respectively. Figure 7 The same numbers are used to illustrate that in some embodiments, no architectural changes may need to be made to the cores 710 - 1 to 710 - 4 and cache agents 720 - 1 to 720 - 4 . Instead, these may simply be programmed or configured to map certain address spaces to the shared memory 830 .

[0162] Similarly, NIC 804 includes NIC logic 706, network interface 770, and coprocessor 708. As before, the same Figure 7 The same numbers are used to illustrate that in some embodiments, these can be Figure 7 The blocks provided in NIC 704 are the same or substantially similar.

[0163] In this example, the NIC memory 814 is divided into a shared memory 830 and a dedicated memory 832. The NIC memory 814 is managed by a cache agent 822.

[0164] In this case, the cache agent 720-1 maps the upper region of the DRAM to the normal DRAM address space 840. The cache agent 720-1 maps the lower region of the DRAM to the shared memory 830.

[0165] As a non-limiting example, an application running on core 710-1 (e.g., Figure 2 The same client engine 224 provides services as in Figure 3 The server engine 324 (same as in the example above) can write to a memory location in the shared memory 830 and generate a network or fabric request. The network or fabric request can be sent to the NIC 804 via a PCIe channel. The host PCIe interface 872 can then sink the request to the NIC.

[0166] Next, the coprocessor 708 may process the request. During this processing, conflicting memory operations may occur, such as the NIC logic 706 trying to write to the same memory location. In some cases, the cache agent 822 may generate snoops to maintain cache coherence in order to resolve conflicts.

[0167] In one embodiment, once a transaction occurs, the transaction may be copied to the shared memory 830. At the same time, an application on the NIC 804 may generate a request that targets a NIC memory range cached in the host. In this case, the cache agent in the NIC may follow the implemented coherence protocol (MESIF, MESI, etc.) to generate a snoop to the compute element that caches that particular memory range.

[0168] Finally, the request is sent to the fabric via network interface 770, if necessary.

[0169] The host PCIe interface 872 may be extended to understand that one or more dedicated virtual channels or channels may be used to tunnel memory traffic to and from the shared memory 830. Traffic from those channels or channels may be forwarded to the cache agent 822. The cache agent 822 handles requests from within the core 710 and from within the coprocessor 708. Note that this architecture may also work with multiple NICs 804, which may be connected via multiple PCIe buses 776. Requests from other NICs may be tunneled by the PCIe node agent to the corresponding NIC 804. Based on the request, the cache agent 822 may generate a read request to local memory, a snoop to the coprocessor 708, or a snoop to the CPU-side cache.

[0170] The PCIe interface 870 may also be extended to include a system address decoder (SAD) 824 that maps a given address range to each NIC 804. The shared memory addresses of a peer NIC may be accessed by a NIC 804 by accessing a specific address range. The PCIe node agent may reroute requests to a given NIC when the address range is owned by that specific NIC. This architecture may work substantially transparently, as from the core 710 perspective, each access is simply a read to or write from a memory address.

[0171] In some embodiments, and particularly in embodiments where multiple cache agents provide shared NIC memory, the SAD 824 may include decoding rules that map the shared memory 830 into the shared DRAM address range 842. The cache agents 720 and 822 forward requests for these to the shared memory 830 via the PCIe bus 776. Advantageously, in some embodiments, no additional architectural changes are required to the processing block 802. Existing DRAM decoding rules in the cache agent 720 may be used instead. The cache agent 720 forwards memory requests within the range of the NIC shared DRAM 842 in a QPI or KTI format via the PCIe bus 776.

[0172] In some examples, the PCIe bus 776 may be augmented with one or more dedicated lanes for tunneling memory requests between the cache agent 720-1 and the cache agent 822. These additional lanes may also be responsible for forwarding requests (such as snoops) from the coprocessor 708 cache agent 822 to the appropriate core 710 within the processing block 802. Note that while one cache agent 822 is illustrated in this example, multiple cache agents may be included to increase throughput. A hash function on the address may be used to determine the cache agent 822 to which a given address belongs.

[0173] Fig. 9 is a block diagram of a data center 900 illustrating one example application of the teachings of the present specification.

[0174] exist Fig. 9In the example of , a processing block 802 is provided, wherein the processing block 802 is communicatively coupled to a plurality of NICs 804, specifically NIC 804-1, NIC 804-2, NIC 804-3, and NIC 804-4. NIC 804-1 is communicatively coupled to the processing block 802 via PCIe interface 776-1, NIC 804-2 is communicatively coupled to the processing block 802 via PCIe interface 776-2, the processing block 802 is communicatively coupled to the NIC 804-3 via PCIe interface 776-3, and the processing block 802 is communicatively coupled to the NIC 804-4 via PCIe interface 776-4.

[0175] Each NIC 804 receives incoming traffic. For example, data center 900 may be providing a search service, so that each NIC 804 receives a large number of incoming search requests. Each NIC 804 also performs traffic analysis offload. This relieves the CPU or core of processing block 802 from having to perform traffic analysis.

[0176] NIC 804 - 1 and NIC 804 - 3 both include a store for shared metadata 950 - 1 , while NIC 804 - 2 and NIC 804 - 4 have a store for shared metadata 950 - 2 .

[0177] Data center 900 presents network-intensive applications, such as servers for search services. In this case, in addition to servicing CPU-intensive Web requests, data center 900 also needs to put the search into context and perform and maintain business analysis (e.g., how many users of a given demographic access a given set of objects or services). Because NIC 804 is performing business analysis, this function is offloaded from the CPU, freeing up many CPU cycles.

[0178] However, even the task of coordinating with the NIC 804 and switching back and forth between servicing requests and transacting with the NIC 804 to send and receive can consume a large number of CPU cycles and can force cache miss rates to rise. Therefore, the data center 901 adopts the shared memory architecture of the present specification. With this shared memory architecture, the CPU within the processing block 802 directly coordinates with the NIC 804 via a shared DRAM area. This frees up CPU cycles that can be used to provide higher server throughput. This also reduces the latency of processing packets because the CPU and NIC 804 only wait for real dependencies, rather than waiting for completion and wakeup. Therefore, overall, this architecture streamlines computing and communications and improves TCO and performance.

[0179] Fig.10 , Fig.11 and Fig.12820 , PCIe agent 870 , host PCIe interface 872 , cache agent 822 , and shared memory space 830 .

[0180] Fig.10 A read flow (MESI Read For Ownership (RFO)) according to one or more examples of the present specification is illustrated. In this example, the RFO may be generated by an application running on core 710 .

[0181] In this example, core 710 issues a read stream to cache agent 720. Cache agent 720 then assigns the PCIe agent as the SAD home for the read stream.

[0182] The cache agent 720 issues the read stream to the PCIe agent 870. The PCIe agent 870 tunnels the read stream to the PCIe host interface 872. The PCIe host interface 872 may detunnel the read stream and issue it to the cache agent 822.

[0183] The cache agent 822 issues a read instruction to the shared memory space 830. The shared memory 830 then returns the data to the cache agent 822.

[0184] The cache agent 822 issues the data plus a read return (MESI GOE) to the PCIe interface 872 .

[0185] The PCIe interface 872 sends the tunneled data plus the GOE to the PCIe agent 870. The PCIe agent 870 may de-tunnel the data plus the GOE and send it to the cache agent 720. Finally, the cache agent 720 sends the data plus the GOE to the core 710.

[0186] Fig.11 The signal flow for write-back according to one or more examples of the present specification is illustrated. The write-back (WB) naming convention is used in conjunction with evictions in a core or last level cache (LLC). However, this can also include other types of write-backs to memory, such as flush flows. Conceptually, this flow can cover data being sent back to shared memory 830 from one of the cores 710.

[0187] Core 710 issues the write back to cache agent 720. Cache agent 720 attributes the write back to the PCIe agent. Cache agent 720 then issues the write back to PCIe agent 870.

[0188] The PCIe agent 870 tunnels the write-back and issues the tunneled write-back to the PCIe interface 872 .

[0189] The PCIe interface 872 tunnels the write-back and issues it to the cache agent 822. The cache agent 822 then issues a write instruction to the shared memory 830.

[0190] The shared memory 830 sends an acknowledgement (ACK) to the cache agent 822. The cache agent 822 sends the ACK plus a MESI GOI to the PCIe interface 872.

[0191] The PCIe interface 872 tunnels the ACK plus the GOI and sends it to the PCIe agent 870 .

[0192] The PCIe agent 870 tunnels the ACK plus the GOI and sends it to the cache agent 720. Finally, the cache agent 720 sends the ACK plus the GOI to the core 710.

[0193] Fig.12 A snoop flow according to one or more examples of the present specification is illustrated.

[0194] A "snooping" cache is one that performs bus validation for cache coherence. When memory addresses or data are shared by multiple caches, it may be necessary to ensure that the caches remain consistent. When an agent makes a change to the shared data, the change is propagated outward to the other caches. Each cache may employ a "bus snooper," and each bus snooper monitors every transaction on the bus. When a transaction occurs that modifies shared data, all snoopers check to see if their corresponding caches have the same copy of the shared data. If a cache has the correct shared data, its snooper issues an action to ensure cache coherence, such as a refresh or invalidation of a cache block. A snooper may also invalidate a cache block as appropriate.

[0195] A snoop may occur when a given line accessed by a core is currently in use by a coprocessor 708. The cache agent 822 may therefore invalidate the line and send the data back to the core 710. The same process may also be used in the case where a coprocessor 708 requests access to a line that is currently in use by one of the cores 710 in the processing block 804. In this case, the cache agent 822 may use PCIe tunneling to issue a snoop to the core of the node.

[0196] As an example, core 710 issues an RFO to cache agent 720. Cache agent 720 attributes the RFO to PCIe agent 870. Cache agent 720 then issues the RFO to PCIe agent 870. PCI agent 870 tunnels the RFO and delivers it to PCIe interface 872.

[0197] The PCIe interface 872 tunnels the RFO and issues it to the cache agent 822. In this case, the cache agent 822 determines that the line being accessed is currently in use by the coprocessor 708 and issues a snoop. Therefore, the cache agent 822 issues a MESI FWD GO2I to the shared memory 830.

[0198] The shared memory 830 sends an ACK plus the data to the cache agent 822 .

[0199] The cache agent 822 sends the data plus the GOE back to the PCIe interface 872.

[0200] The PCIe interface 872 tunnels the data plus the GOE and sends it to the PCIe agent 870 .

[0201] The PCIe agent 870 issues the data plus the GOE to the cache agent 720. Finally, the cache agent 720 issues the data plus the GOE to the core 710.

[0202] The features of several embodiments are summarized above so that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art should appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same purpose and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

[0203] All or part of any hardware element disclosed herein can be easily provided in a system on chip (SoC) including a central processing unit (CPU) package. SoC represents an integrated circuit (IC) that integrates the components of a computer or other electronic system into a single chip. Thus, for example, a client device or a server device can be provided in whole or in part in a SoC. The SoC can include digital, analog, mixed signal, and radio frequency functions, all of which can be provided on a single chip substrate. Other embodiments may include a multi-chip module (MCM), in which multiple chips are located in a single electronic package and are configured to interact closely with each other through the electronic package. In various other embodiments, the computing functionality disclosed herein can be implemented in one or more silicon cores in application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), and other semiconductor chips.

[0204] It should also be noted that in certain embodiments, some components may be omitted or combined. In a general sense, the arrangement depicted in the figure may be more logical in its representation, and the physical architecture may include various permutations, combinations and / or mixtures of these elements. It must be noted that countless possible design configurations may be used to achieve the operational goals outlined herein. Therefore, the associated infrastructure has a large number of alternative arrangements, design options, equipment possibilities, hardware configurations, software implementations and equipment options.

[0205] In a general sense, any processor configured appropriately can execute any type of instruction associated with data to implement the operation detailed herein. Any processor disclosed herein can transform an element or article (e.g., data) from one state or thing to another state or thing. In another example, some activities outlined herein can be implemented with fixed logic or programmable logic (e.g., software and / or computer instructions executed by a processor), and the elements identified herein can be a certain type of programmable processor, programmable digital logic (e.g., field programmable gate array (FPGA), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)), including digital logic, software, code, ASIC of electronic instructions, flash memory, optical disk, CD-ROM, DVD ROM, magnetic card or optical card, other types of machine-readable media suitable for storing electronic instructions, or any suitable combination thereof.

[0206] In operation, the storage may store information in any suitable type of tangible non-transitory storage medium (e.g., random access memory (RAM), read-only memory (ROM), field programmable gate array (FPGA), erasable programmable read-only memory (EPROM), electrically erasable programmable ROM (EEPROM), etc.), software, hardware (e.g., processor instructions or microcode), or, where appropriate and based on specific needs, in any other suitable component, device, element, or object. In addition, information tracked, sent, received, or stored in the processor can be provided in any database, register, table, cache, queue, control list, or storage structure based on specific needs and implementations, all of which can be referenced in any suitable time table. Any of the memory or storage elements disclosed herein should be interpreted as being included in the broad terms "memory" and "storage", as appropriate. The non-transitory storage medium herein is explicitly intended to include any non-transitory dedicated or programmable hardware configured to provide the disclosed operations or cause the processor to perform the disclosed operations.

[0207] The computer program logic that realizes all or part of the functionality described herein is specifically implemented in various forms, including but not limited to source code form, computer executable form, machine instructions or microcode, programmable hardware and various intermediate forms (e.g., forms generated by assemblers, compilers, linkers or locators). In an example, the source code includes a series of computer program instructions implemented in various programming languages ​​(such as object code, assembly language) or high-level languages ​​such as OpenCL, FORTRAN, C, C++, JAVA or HTML for various operating systems or operating environments, or hardware description languages ​​such as Spice, Verilog and VHDL. The source code can define and use various data structures and communication messages. The source code can be in a computer executable form (e.g., via an interpreter), or the source code can be converted (e.g., via a translator, assembler or compiler) into a computer executable form, or converted into an intermediate form such as a byte code. Where appropriate, any of the above can be used to construct or describe an appropriate discrete or integrated circuit, whether sequential, combined, state machine or otherwise.

[0208] In an example embodiment, any number of circuits of the figure can be implemented on a board of an associated electronic device. The board can be a general circuit board that can hold various components of the internal electronic system of the electronic device, and further, provide connectors for other peripheral devices. More specifically, the board can provide an electrical connection through which other components of the electrical connection system can communicate electrically. Any suitable processor and memory can be suitably coupled to the board based on specific configuration requirements, processing requirements, and computing design. Other components such as external storage, additional sensors, controllers for audio / video display, and peripherals can be attached to the board as plug-in cards via cables, or integrated into the board itself. In another example, the circuit of the figure can be implemented as an independent module (e.g., a device with circuits and associated components configured to perform specific applications or functions), or implemented as a plug-in module in the dedicated hardware of the electronic device.

[0209] It is noted that, using many examples provided herein, interaction can be described in terms of two, three, four or more electronic components. However, this is only done for the purpose of clarity and example. It should be appreciated that the system can be merged or reconfigured in any suitable manner. Along similar design alternatives, any of the illustrated components, modules and elements of these figures can be combined according to various possible configurations, all of which are within the broad scope of this specification. In some cases, it may be easier to describe one or more functionalities of a given set of processes by only citing a limited number of electrical components. It should be appreciated that the circuits of the figures and their teachings are easy to expand and can accommodate a large number of components and more complex / precise arrangements and configurations. Therefore, the examples provided should not limit the scope or suppress the broad teachings of the circuits that can potentially be applied to a large number of other architectures.

[0210] Numerous other changes, substitutions, variations, alterations, and modifications may be ascertained by those skilled in the art, and it is intended that the present disclosure encompass all such changes, substitutions, variations, alterations, and modifications as fall within the scope of the appended claims. To assist the United States Patent and Trademark Office (USPTO), and otherwise any reader of any patent issued in this application, in interpreting the appended claims, applicants wish to note that applicants: (a) do not intend for any of the appended claims to invoke the sixth paragraph (6) of section 112 of title 35, United States Code (pre-AIA) or paragraph (f) of the same section (post-AIA) as it existed on the filing date thereof unless the words “means for” or “step for” are specifically used in a particular claim; and (b) do not intend for any statement in this specification to limit the present disclosure in any manner not otherwise expressly reflected in the appended claims.

[0211] Example Implementations

[0212] An example of a host fabric interface (HFI) is disclosed, comprising: an interconnect interface for communicatively coupling the HFI to an interconnect; a network interface for communicatively coupling the HFI to a network; network interface logic for providing communication between the interconnect and the network; a coprocessor configured to provide offload functionality for the network; a memory; and a cache agent configured to: designate a region of the memory as shared memory between the HFI and a core communicatively coupled to the HFI via the interconnect; receive a memory operation for the shared memory; and issue a memory instruction to the memory based on the memory operation.

[0213] An example is also disclosed wherein the memory operation is received from the core.

[0214] An example is also disclosed wherein the memory operations are tunneled and wherein the interconnect interface is to de-tunnel the memory operations.

[0215] An example is also disclosed wherein the memory operation is directed to the core.

[0216] An example is also disclosed wherein the interconnect interface is to tunnel the memory operations.

[0217] An example is also disclosed wherein the memory operation is a memory read.

[0218] An example is also disclosed wherein the memory operation is a memory write.

[0219] An example is also disclosed, wherein the memory operation is initiated by one of the coprocessor and the core, and wherein the cache agent is configured to determine that the memory operation is for a memory line currently in use by the other of the coprocessor and the host.

[0220] An example is also disclosed in which the caching agent will issue a snoop to invalidate the row.

[0221] An example is also disclosed wherein the cache agent implements a coherence protocol selected from the group consisting of MESI, MOSI, MOESI, and MOESIF.

[0222] An example is also disclosed, wherein the interconnect interface includes a dedicated channel for the memory operation, wherein the interconnect interface will directly route traffic from the dedicated channel to the cache agent.

[0223] An example is also disclosed wherein the memory operation includes a hash identifying a home cache agent for the memory operation.

[0224] Also disclosed are examples of a caching agent wherein the HFI comprises an integrated circuit separate from the core.

[0225] An example is also disclosed wherein the core includes a cache agent configured to maintain cache coherence in a shared region of the memory.

[0226] An example is also disclosed wherein the core includes a cache agent configured to maintain cache coherence in a shared region of the memory.

[0227] Also disclosed are examples of one or more tangible, non-transitory computer-readable storage media having instructions encoded thereon for instructing a device to: communicatively couple the device to an interconnect; communicatively couple the device to a network; provide network interface logic to provide communication between the interconnect and the network; and provide a cache agent to: designate a region of memory as shared memory between the device and a core communicatively coupled to the device via the interconnect; receive memory operations for the shared memory; and issue memory instructions to the memory based on the memory operations.

[0228] An example is also disclosed wherein the memory operation is directed to the core.

[0229] An example is also disclosed wherein the interconnect interface is to tunnel the memory operations.

[0230] An example is also disclosed wherein the memory operation is initiated by one of a coprocessor and a core, and wherein the cache agent is configured to determine that the memory operation is for a memory line currently in use by another of the coprocessor and the core.

[0231] An example is also disclosed in which the caching agent will issue a snoop to invalidate the row.

[0232] An example is also disclosed wherein the cache agent implements a coherence protocol selected from the group consisting of MESI, MOSI, MOESI, and MOESIF.

[0233] An example is also disclosed wherein the memory operation includes a hash identifying a home cache agent for the memory operation.

[0234] Also disclosed is an example of a host device, comprising: a processor; a memory; and a cache agent configured to: map a region of the memory to a shared memory of an intelligent network interface.

[0235] An example of a host device is also disclosed, further comprising: logic for providing interconnection; and logic for providing a dedicated channel, wherein the dedicated channel is used to provide communication between a host processor and a shared memory of an intelligent network interface, wherein the intelligent network interface includes network interface logic, a coprocessor, and a memory having a shared memory area, wherein the memory operations are directed to the host.

[0236] Also disclosed are examples of a host device further comprising a system address decoder configured to receive memory operations from a plurality of intelligent network interfaces and provide a hash for attributing the memory operations.

Claims

1. A host structure interface HFI, comprising: A peripheral component interconnect express (PCIe) interface for communicatively coupling the HFI to a host; a network interface for communicatively coupling the HFI to a network; Network interface logic, used to provide communication between the PCIe interface and the network; a coprocessor configured to provide offload functionality for the network; Memory; as well as A caching proxy, wherein the caching proxy is configured to: designating a region of the memory as shared memory between the coprocessor and a core of the host communicatively coupled to the HFI via the PCIe interface; receiving a memory operation for the shared memory; as well as issuing a memory instruction to the memory according to the memory operation, Wherein the memory operation is initiated by one of the coprocessor and the core, and wherein the cache agent is configured to determine that the memory operation is directed to a line within the memory currently in use by another of the coprocessor and the core.

2. The HFI of claim 1, wherein the memory operation is received from the core.

3. The HFI of claim 2, wherein the memory operations are tunneled, and wherein the PCIe interface is to de-tunnel the memory operations.

4. The HFI of claim 1, wherein the PCIe interface is to tunnel the memory operations.

5. The HFI of any one of claims 1 to 4, wherein the memory operation is a memory read.

6. The HFI of any one of claims 1 to 4, wherein the memory operation is a memory write.

7. The HFI of claim 1, wherein the caching agent is to issue a snoop to invalidate the line within the memory.

8. The HFI of any one of claims 1 to 4, wherein the cache agent implements a coherence protocol selected from the group consisting of MESI, MOSI, MOESI, and MOESIF.

9. The HFI of claim 1, wherein the PCIe interface includes a dedicated channel for the memory operations, wherein the PCIe interface is to route traffic directly from the dedicated channel to the cache agent.

10. The HFI according to any one of claims 1 to 4, wherein: The memory operation includes a hash identifying a home cache agent for the memory operation.

11. The HFI of claim 1, wherein the HFI comprises an integrated circuit separate from the core.

12. An integrated circuit comprising the HFI of claim 1 and a core, wherein the core comprises a cache agent configured to maintain cache coherence in a shared region of the memory.

13. A multi-chip package product comprising the HFI of claim 1 and a core, wherein the core comprises a cache agent configured to maintain cache coherence in a shared region of the memory.

14. One or more tangible, non-transitory computer-readable storage media having encoded thereon instructions for instructing a device to: communicatively coupling the device to a peripheral component interconnect express (PCIe) interface of a host; communicatively coupling the device to a network; providing network interface logic to provide communications between said interconnect and said network; and Provides a caching proxy to: designating a region of memory as shared memory between the device and a core of the host communicatively coupled to the device via the PCIe interface; receiving a memory operation for the shared memory; as well as issuing a memory instruction to the memory according to the memory operation, Wherein the memory operation is initiated by one of the coprocessor and the core, and wherein the cache agent is configured to determine that the memory operation is directed to a line within the memory currently in use by another of the coprocessor and the core.

15. The one or more tangible, non-transitory computer-readable storage media of claim 14, wherein the PCIe interface is to tunnel the memory operations.

16. The one or more tangible, non-transitory computer-readable storage media of claim 14, wherein the caching agent is to issue a snoop to invalidate the line within the memory.

17. The one or more tangible, non-transitory computer-readable storage media of claim 14, wherein the cache agent implements a coherence protocol selected from the group consisting of MESI, MOSI, MOESI, and MOESIF.

18. The one or more tangible, non-transitory computer-readable storage media of claim 14, wherein the memory operation includes a hash identifying a home cache agent for the memory operation.

19. A host device, comprising: processor; Memory; as well as A caching proxy, wherein the caching proxy is configured to: mapping a region of the memory to a shared memory of an intelligent network interface, wherein the shared memory is used to provide memory coherent access to an accelerator of the intelligent network interface and a core of the processor, including a memory operation initiated by one of the accelerator and the core, and wherein the cache agent is configured to determine that the memory operation is directed to a line within the memory currently in use by another of the accelerator and the core; Logic for providing PCIe interface; logic for providing a dedicated channel for providing communication between a host processor and a shared memory of an intelligent network interface including network interface logic, a coprocessor, and a memory having a shared memory region; as well as A system address decoder is configured to receive memory operations from a plurality of intelligent network interfaces and provide a hash for attributing the memory operations.

20. A computer program product comprising a computer program, characterized in that The computer program implements the following steps: communicatively coupling the device to a native Peripheral Component Interconnect Express (PCIe) interface of a host; communicatively coupling the device to a network; Providing network interface logic to provide communication between the PCIe interface and the network; and Provides a caching proxy to: designating a region of memory as shared memory between the device and a core of the host communicatively coupled to the device via the PCIe interface; receiving a memory operation for the shared memory; as well as issuing a memory instruction to the memory according to the memory operation, Wherein the memory operation is initiated by one of the coprocessor and the core, and wherein the cache agent is configured to determine that the memory operation is directed to a line within the memory currently in use by another of the coprocessor and the core.

21. The computer program product of claim 20, wherein the PCIe interface is to tunnel the memory operations.

22. The computer program product of claim 20, wherein the caching agent is to issue a snoop to invalidate the line within the memory.

23. The computer program product of claim 20, wherein the caching agent implements a coherence protocol selected from the group consisting of MESI, MOSI, MOESI, and MOESIF.

24. The computer program product of claim 20, wherein the memory operation comprises a hash identifying a home cache agent for the memory operation.

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