A method, system, device and medium for processing 360 video

Abstract

The present invention provides motion vector / mode prediction, region of interest based emission, metadata capture and format detection for 360 video. An embodiment of an electronic processing system may include a 2D frame corresponding to a projection of a 360 video space, and the following: a component predictor for predicting coded components of a first block of the 2D frame based on coded information from neighboring blocks, the neighboring blocks being adjacent to the first block of the 2D frame only in the 360 ​​video space; a prioritizer for prioritizing the emission of a second block of the 2D frame based on an identified region of interest; and / or a format detector for detecting a 360 video format of a 2D frame based on image content. A 360 video capture device may include a context tagger for tagging 360 video content with context information contemporary with the captured 360 video content. Other embodiments are disclosed and claimed.

Description

Technical Field

[0001] Embodiments generally relate to display technology, and more particularly to block-based camera updates and asynchronous displays. More particularly, embodiments relate to motion vector (MV) / mode prediction, region of interest (ROI) based emission, metadata capture, and format detection for 360 video. Background Art

[0002] In 360 video (which is also called 360-degree video, immersive video, or spherical video), video recordings may be captured from all directions simultaneously (i.e., 360 degrees in all directions) using an omnidirectional camera or a series of cameras. Upon playback, the viewer may select a viewing direction or viewport for viewing among any of the available directions. In compression / decompression (codec) systems, compression efficiency, video quality, and computational efficiency may be important performance criteria. These criteria may also be important factors in the dissemination of 360 videos and the user experience of viewing such 360 videos. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Various advantages of the embodiments will become apparent to those skilled in the art from a reading of the following description and appended claims, and from reference to the following drawings, in which:

[0004] Figure 1 is a block diagram illustrating a computer system configured to implement one or more aspects of the embodiments described herein;

[0005] Figures 2A to 2D A parallel processor component according to an embodiment is shown;

[0006] FIG. 3A to FIG. 3B is a block diagram of a graphics multiprocessor according to an embodiment;

[0007] FIG. 4A to FIG. 4F An exemplary architecture is presented in which a plurality of GPUs are communicatively coupled to a plurality of multi-core processors;

[0008] Figure 5 Demonstrating a graphics processing pipeline according to an embodiment;

[0009] Figure 6 is a block diagram of an example of an electronic processing system according to an embodiment;

[0010] Fig. 7A is a block diagram of an example of a graphics device according to an embodiment;

[0011] Figure 7B is a flowchart of an example of a method of processing 360 video according to an embodiment;

[0012] Figure 7C is a block diagram of an example of an electronic processing system according to an embodiment;

[0013] Fig.7D is a schematic diagram of an example of a two-dimensional (2D) frame having an equirectangular projection 360 video format according to an embodiment;

[0014] Fig. 7E is a schematic diagram of an example of a viewport according to an embodiment;

[0015] Figure 7F is a schematic diagram of an example of a viewport superimposed on an equirectangular format 2D frame according to an embodiment;

[0016] Figure 7G is a schematic diagram of an example of a 2D frame with a cubemap 360 video format according to an embodiment;

[0017] Figure 7H is a schematic perspective view of an example of a cube according to an embodiment;

[0018] Fig.7I is a schematic diagram of an example of a 2D frame with a compact cubemap 360 video format according to an embodiment;

[0019] Fig. 8A is a block diagram of another example of a graphics device according to an embodiment;

[0020] Figure 8B is a flowchart of another example of a method for processing a 360 video according to an embodiment;

[0021] Figure 8C is a schematic diagram of an example of a 360 video according to an embodiment;

[0022] FIG. 8D to FIG. 8E is a schematic diagram of an example of prioritized encoding / packet transmission for 360 video according to an embodiment;

[0023] Fig.9A is a block diagram of another example of a graphics device according to an embodiment;

[0024] Fig. 9B is a flowchart of another example of a method for processing a 360 video according to an embodiment;

[0025] Fig. 9C is a schematic diagram of an example of a frame having a fisheye 360 ​​video format according to an embodiment;

[0026] Fig.9D is a schematic diagram of an example of a frame having an equirectangular projection (ERP) 360 video format according to an embodiment;

[0027] Fig.9E is a schematic diagram of an example of a frame having a cubemap 360 video format according to an embodiment;

[0028] Fig.9F is a schematic diagram of an example of a frame having a packed cubemap 360 video format according to an embodiment;

[0029] Figure 9G is a block diagram of another example of a graphics device according to an embodiment;

[0030] Figure 9H is a flowchart of another example of a method for processing a 360 video according to an embodiment;

[0031] Fig. 10A is a block diagram of another example of a graphics device according to an embodiment;

[0032] Fig. 10B is a flowchart of another example of a method for processing a 360 video according to an embodiment;

[0033] Fig. 10C is a block diagram of an example of a 360 video capture device according to an embodiment;

[0034] Fig. 10D is a perspective view of an example of a 360 video camera according to an embodiment;

[0035] Fig.11 is a block diagram of an example of a display with local backlight capability according to an embodiment;

[0036] Fig. 12A is a block diagram of an example of a data processing apparatus according to an embodiment;

[0037] Fig. 12B is a demonstration of an example of distance determination according to an embodiment;

[0038] Fig.13 is a block diagram of an example of a layered display architecture according to an embodiment;

[0039] Fig.14 is a block diagram of an example of a display architecture according to an embodiment, the display architecture including a plurality of display units;

[0040] Fig.15 is a block diagram of an example of a cloud-assisted media delivery architecture according to an embodiment;

[0041] Figure 16 to Figure 18 is a block diagram of an example of an overview of a data processing system according to an embodiment;

[0042] Fig.19is a block diagram of an example of a graphics processing engine according to an embodiment;

[0043] Figure 20 to Figure 22 is a block diagram of an example of an execution unit according to an embodiment;

[0044] Fig.23 is a block diagram of an example of a graphics pipeline according to an embodiment;

[0045] FIG. 24A to FIG. 24B is a block diagram of an example of a graphics pipeline according to an embodiment;

[0046] Fig.25 is a block diagram of an example of a graphics software architecture according to an embodiment;

[0047] Fig.26 is a block diagram of an example of an intellectual property (IP) core development system according to an embodiment; and

[0048] Fig. 27 is a block diagram of an example of a system on chip integrated circuit according to an embodiment. DETAILED DESCRIPTION

[0049] In the following description, numerous specific details are set forth to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without one or more of these specific details. In other examples, well-known features are not described to avoid obscuring the present invention.

[0050] System Overview

[0051] Figure 1 1 is a block diagram illustrating a computing system 100 that is configured to implement one or more aspects of the embodiments described herein. The computing system 100 includes a processing subsystem 101 having one or more processors 102 and a system memory 104 that communicate with the system memory via an interconnect path that may include a memory hub 105. The memory hub 105 may be a separate component within a chipset component, or may be integrated within one or more processors 102. The memory hub 105 is coupled to an I / O subsystem 111 via a communication link 106. The I / O subsystem 111 includes an I / O hub 107 that may enable the computing system 100 to receive input from one or more input devices 108. Additionally, the I / O hub 107 may enable a display controller that may be included in one or more processors 102 to provide output to one or more display devices 110A. In one embodiment, the one or more display devices 110A coupled to the I / O hub 107 may include local, internal, or embedded display devices.

[0052] In one embodiment, the processing subsystem 101 includes one or more parallel processors 112, which are coupled to the memory hub 105 via a bus or other communication link 113. The communication link 113 can be one of any number of standard-based communication link technologies or protocols (such as, but not limited to, the PCI Express bus), or can be a vendor-specific communication interface or communication structure. In one embodiment, the one or more parallel processors 112 form a computationally focused parallel or vector processing system that includes a large number of processing cores and / or processing clusters (such as, for example, an integrated many-core (MIC) processor). In one embodiment, the one or more parallel processors 112 form a graphics processing subsystem that can output pixels to one of one or more display devices 110A coupled via the I / O hub 107. The one or more parallel processors 112 may also include a display controller and display interface (not shown) to enable direct connection to one or more display devices 110B.

[0053] Within the I / O subsystem 111, a system storage unit 114 may be connected to the I / O hub 107 to provide a storage mechanism for the computing system 100. An I / O switch 116 may be used to provide an interface mechanism to enable connection between the I / O hub 107 and other components, such as a network adapter 118 and / or a wireless network adapter 119 that may be integrated into the platform, and various other devices that may be added via one or more plug-in devices 120. The network adapter 118 may be an Ethernet adapter or another wired network adapter. The wireless network adapter 119 may include one or more of the following: Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more radio devices.

[0054] The computing system 100 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to the I / O hub 107. Figure 1 The communication paths interconnecting the various components in the system may be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI Express bus) or any other bus or point-to-point communication interface and / or protocol (e.g., NV-Link high-speed interconnect, or interconnect protocols known in the art).

[0055] In one embodiment, one or more parallel processors 112 include circuits optimized for graphics and video processing (including, for example, video output circuits) and constitute a graphics processing unit (GPU). In another embodiment, one or more parallel processors 112 include circuits optimized for general-purpose processing while maintaining the underlying computing architecture described in more detail herein. In yet another embodiment, the components of the computing system 100 may be integrated on a single integrated circuit along with one or more other system elements. For example, one or more parallel processors 112, memory hub 105, processor 102, and I / O hub 107 may be integrated into a system on a chip (SoC) integrated circuit. Alternatively, the components of the computing system 100 may be integrated into a single package to form a system in package (SIP) configuration. In one embodiment, at least a portion of the components of the computing system 100 may be integrated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules into a modular computing system.

[0056] It will be appreciated that the computing system 100 shown herein is illustrative and that various variations and modifications are possible. The connection topology, including the number and rows of bridges, the number of processor(s) 102, and the number of parallel processor(s) 112, may be modified as desired. For example, in some embodiments, the system memory 104 is connected to the processor(s) 102 directly rather than through a bridge, while other devices communicate with the system memory 104 via the memory hub 105 and the processor(s) 102. In other alternative topologies, the parallel processor(s) 112 are connected to the I / O hub 107 or directly to one of the one or more processors 102, rather than to the memory hub 105. In other embodiments, the I / O hub 107 and the memory hub 105 may be integrated into a single chip. Some embodiments may include two or more groups of processors 102 attached via multiple sockets, which may be coupled to two or more instances of the parallel processor(s) 112.

[0057] Some specific components shown herein are optional and may not be included in all implementations of computing system 100. For example, any number of plug-in cards or peripherals may be supported, or some components may be eliminated. In addition, some architectures may be different from those described above. Figure 1 Different terminology is used for components similar to those shown in FIG. 1. For example, in some architectures, memory hub 105 may be referred to as a north bridge, while I / O hub 107 may be referred to as a south bridge.

[0058] Figure 2AA parallel processor 200 is shown according to an embodiment. The various components of the parallel processor 200 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). According to an embodiment, the parallel processor 200 shown is Figure 1 A variation of one or more parallel processors 112 is shown in .

[0059] In one embodiment, parallel processor 200 includes parallel processing unit 202. The parallel processing unit includes an I / O unit 204, which enables communication with other devices (including other instances of parallel processing unit 202). I / O unit 204 can be directly connected to other devices. In one embodiment, I / O unit 204 is connected to other devices via the use of a hub or switch interface (e.g., memory hub 105). The connection between memory hub 105 and I / O unit 204 forms communication link 113. Within parallel processing unit 202, I / O unit 204 is connected to host interface 206 and memory crossbar 216, wherein host interface 206 receives commands related to performing processing operations and memory crossbar 216 receives commands related to performing memory operations.

[0060] When the host interface 206 receives the command buffer via the I / O unit 204, the host interface 206 can direct the work operations for executing those commands to the front end 208. In one embodiment, the front end 208 is coupled with a scheduler 210, which is configured to distribute commands or other work items to the processing cluster array 212. In one embodiment, the scheduler 210 ensures that the processing cluster array 212 is properly configured and in a valid state before the task is distributed to the processing clusters of the processing cluster array 212. In one embodiment, the scheduler 210 is implemented via firmware logic executed on a microcontroller. The microcontroller-implemented scheduler 210 can be configured to perform complex scheduling and work distribution operations at coarse and fine granularity, thereby achieving fast preemption and context switching of threads executed on the processing array 212. In one embodiment, the host software can prove the workload for scheduling on the processing array 212 via one of a plurality of image processing doorbells. The workload can then be automatically distributed across the processing array 212 by the scheduler 210 logic within the scheduler microcontroller.

[0061] The processing cluster array 212 may include up to "N" processing clusters (e.g., cluster 214A, cluster 214B, up to cluster 214N). Each cluster 214A-214N of the processing cluster array 212 may execute a large number of concurrent threads. The scheduler 210 may use various scheduling and / or work distribution algorithms to assign work to the clusters 214A-214N of the processing cluster array 212, which may vary depending on the workload generated for each type of program or calculation. Scheduling may be handled dynamically by the scheduler 210, or may be partially assisted by compiler logic during the compilation of program logic configured for execution by the processing cluster array 212. In one embodiment, different clusters 214A-214N of the processing cluster array 212 may be assigned to process different types of programs, or to perform different types of calculations.

[0062] Processing cluster array 212 may be configured to perform various types of parallel processing operations. In one embodiment, processing cluster array 212 is configured to perform general-purpose parallel computing operations. For example, processing cluster array 212 may include logic for performing processing tasks including filtering video and / or audio data, performing modeling operations (including physics operations), and performing data transformations.

[0063] In one embodiment, processing cluster array 212 is configured to perform parallel graphics processing operations. In embodiments where parallel processor 200 is configured to perform graphics processing operations, processing cluster array 212 may include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, and tessellation logic and other vertex processing logic. In addition, processing cluster array 212 may be configured to execute shader programs related to graphics processing, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. Parallel processing unit 202 may pass data from system memory via I / O unit 204 for processing. During processing, the passed data may be stored in on-chip memory (e.g., parallel processor memory 222) during processing and then written back to system memory.

[0064] In one embodiment, when the parallel processing unit 202 is used to perform graphics processing, the scheduler 210 can be configured to divide the processing workload into tasks of approximately equal size to better enable the distribution of graphics processing operations to multiple clusters 214A to 214N in the processing cluster array 212. In some embodiments, multiple portions of the processing cluster array 212 can be configured to perform different types of processing. For example, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen space operations to generate a rendered image for display. Intermediate data generated by one or more of the clusters 214A to 214N can be stored in a buffer to allow the intermediate data to be transmitted between the clusters 214A to 214N for further processing.

[0065] During operation, the processing cluster array 212 may receive processing tasks to be performed via the scheduler 210, which receives commands defining the processing tasks from the front end 208. For graphics processing operations, the processing tasks may include indices of data to be processed (e.g., surface (patch) data, primitive data, vertex data, and / or pixel data) as well as state parameters and commands defining how the data is to be processed (e.g., what program to execute). The scheduler 210 may be configured to obtain indices corresponding to the tasks, or may receive these indices from the front end 208. The front end 208 may be configured to ensure that the processing cluster array 212 is configured to a valid state before initiating a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.).

[0066] Each of the one or more instances of the parallel processing unit 202 can be coupled to a parallel processor memory 222. The parallel processor memory 222 can be accessed via a memory crossbar switch 216, which can receive memory requests from the processing cluster array 212 and the I / O unit 204. The memory crossbar switch 216 can access the parallel processor memory 222 via a memory interface 218. The memory interface 218 can include a plurality of partition units (e.g., partition unit 220A, partition unit 220B, up to partition unit 220N), each of which can be coupled to a portion of the parallel processor memory 222 (e.g., a memory unit). In one implementation, the number of partition units 220A-220N is configured to be equal to the number of memory units, such that the first partition unit 220A has a corresponding first memory unit 224A, the second partition unit 220B has a corresponding memory unit 224B, and the Nth partition unit 220N has a corresponding Nth memory unit 224N. In other embodiments, the number of partition units 220A-220N may not be equal to the number of memory devices.

[0067] In various embodiments, the memory units 224A to 224N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory (e.g., synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory). In one embodiment, the memory units 224A to 224N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). Those skilled in the art will recognize that the specific implementation of the memory units 224A to 224N may vary and may be selected from one of a variety of conventional designs. Render targets (e.g., frame buffers or texture maps) may be stored across the memory units 224A to 224N, allowing the partition units 220A to 220N to write multiple portions of each render target in parallel to efficiently use the available bandwidth of the parallel processor memory 222. In some embodiments, local instances of the parallel processor memory 222 may be excluded to facilitate utilizing a unified memory design of the system memory in conjunction with local cache memory.

[0068] In one embodiment, any of the clusters 214A-214N of the processing cluster array 212 can process data to be written to any of the memory units 224A-224N within the parallel processor memory 222. The memory crossbar 216 can be configured to pass the output of each cluster 214A-214N to any partition unit 220A-220N or another cluster 214A-214N that can perform additional processing operations on the output. Each cluster 214A-214N can communicate with the memory interface 218 through the memory crossbar 216 to read from or write to various external memory devices. In one embodiment, the memory crossbar 216 has a connection to the memory interface 218 to communicate with the I / O unit 204 and has a connection to the local instance of the parallel processor memory 222, thereby enabling the processing units within the different processing clusters 214A-214N to communicate with the system memory or other memory that is not local to the parallel processing unit 202. In one embodiment, the memory crossbar switch 216 may use virtual channels to separate traffic flows between the clusters 214A-214N and the partition units 220A-220N.

[0069] Although a single instance of parallel processing unit 202 is shown in parallel processor 200, any number of instances of parallel processing unit 202 may be included. For example, multiple instances of parallel processing unit 202 may be provided on a single plug-in card, or multiple plug-in cards may be interconnected. Different instances of parallel processing unit 202 may be configured to interoperate even if these different instances have different numbers of processing cores, different amounts of local parallel processor memory and / or other configuration differences. For example and in one embodiment, some instances of parallel processing unit 202 may include higher precision floating point units relative to other instances. The system including one or more instances of parallel processing unit 202 or parallel processor 200 may be implemented with multiple configurations and form factors, including but not limited to desktop, laptop or handheld personal computers, servers, workstations, game consoles and / or embedded systems.

[0070] Figure 2B is a block diagram of a partition unit 220 according to an embodiment. In one embodiment, the partition unit 220 is Figure 2A2 is an example of one of the partition units 220A to 220N of the memory crossbar 216. As shown, the partition unit 220 includes an L2 cache 221, a frame buffer interface 225, and an ROP 226 (raster operation unit). The L2 cache 221 is a read / write cache that is configured to perform load and store operations received from the memory crossbar switch 216 and the ROP 226. Read misses and urgent write-back requests are output by the L2 cache 221 to the frame buffer interface 225 for processing. Updates may also be sent to the frame buffer via the frame buffer interface 225 for processing. In one embodiment, the frame buffer interface 225 interfaces with one of the memory units in the parallel processor memory (e.g., the memory units 224A to 224N of FIG. 2 (e.g., within the parallel processor memory 222)).

[0071] In graphics applications, ROP 226 is a processing unit that performs raster operations such as stencil, z-test, blending, etc. ROP 226 then outputs processed graphics data that is stored in graphics memory. In some embodiments, ROP 226 includes compression logic that compresses depth or color data written to memory and decompresses depth or color data read from memory. The compression logic can be lossless compression logic that utilizes one or more of a variety of compression algorithms. The type of compression performed by ROP 226 can vary based on the statistical characteristics of the data to be compressed. For example, in one embodiment, delta color compression is performed on depth and color data on a tile-by-tile basis.

[0072] In some embodiments, ROP 226 is included within each processing cluster (e.g., clusters 214A to 214N of FIG. 2 ) rather than within partition unit 220. In such embodiments, read and write requests for pixel data rather than pixel fragment data are transmitted via memory crossbar 216. The processed graphics data may be displayed on a display device (e.g., Figure 1 100), is routed for further processing by the processor(s) 102, or is routed for processing by the processor(s) 102. Figure 2A The process is further processed by one of the processing entities within the parallel processor 200.

[0073] Figure 2CIt is a block diagram of a processing cluster 214 in a parallel processing unit according to an embodiment. In one embodiment, the processing cluster is an instance of one of the processing clusters 214A to 214N of Figure 2. The processing cluster 214 can be configured to execute many threads in parallel, wherein the term "thread" refers to an instance of a specific program executed on a set of specific input data. In some embodiments, in the case where multiple independent instruction units are not provided, a single instruction multiple data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads. In other embodiments, in the case of using a common instruction unit, a single instruction multiple thread (SIMT) technology is used to support the parallel execution of a large number of generally synchronized threads, and the common instruction unit is configured to issue instructions to a group of processing engines in each of the processing clusters. Different from the SIMD execution regime (wherein, all processing engines usually execute the same instruction), SIMT execution allows different threads to more easily pass through a given thread program along divergent execution paths. It will be understood by those skilled in the art that the SIMD processing regime represents a functional subset of the SIMT processing regime.

[0074] The operation of the processing cluster 214 can be controlled via a pipeline manager 232, which distributes processing tasks to SIMT parallel processors. The pipeline manager 232 receives instructions from the scheduler 210 of Figure 2, and manages the execution of those instructions via a graphics multiprocessor 234 and / or a texture unit 236. The graphics multiprocessor 234 shown is an exemplary instance of a SIMT parallel processor. However, various types of SIMT parallel processors with different architectures may be included in the processing cluster 214. One or more instances of the graphics multiprocessor 234 may be included in the processing cluster 214. The graphics multiprocessor 234 may process data, and a data crossbar 240 may be used to distribute the processed data to one of a plurality of possible destinations (including other shader units). The pipeline manager 232 may facilitate the distribution of the processed data by specifying the destination of the processed data to be distributed via the data crossbar 240.

[0075] Each graphics multiprocessor 234 within a processing cluster 214 may include an identical set of function execution logic (e.g., arithmetic logic units, load-store units, etc.). The function execution logic may be configured in a pipelined manner in which a new instruction may be issued before a previous instruction is completed. The function execution logic supports a wide variety of operations including integer and floating point arithmetic, comparison operations, Boolean operations, bit shifts, and calculation of various algebraic functions. In one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0076] The instructions transmitted to the processing cluster 214 constitute threads. A group of threads that are executed across a group of parallel processing engines is a thread group. A thread group executes the same program on different input data. Each thread in a thread group can be assigned to a different processing engine in the graphics multiprocessor 234. A thread group may include fewer threads than the number of processing engines in the graphics multiprocessor 234. When a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during the cycle when the thread group is being processed. A thread group may also include more threads than the number of processing engines in the graphics multiprocessor 234. When a thread group includes more threads than the number of processing engines in the graphics multiprocessor 234, processing may be performed on consecutive clock cycles. In one embodiment, multiple thread groups may be executed concurrently on the graphics multiprocessor 234.

[0077] In one embodiment, the graphics multiprocessor 234 includes an internal cache memory to perform load and store operations. In one embodiment, the graphics multiprocessor 234 can abandon the internal cache and use the cache memory (e.g., L1 cache 308) within the processing cluster 214. Each graphics multiprocessor 234 also has access to the L2 cache within the partition unit (e.g., partition units 220A to 220N of Figure 2) that is shared among all processing clusters 214 and can be used to transfer data between threads. The graphics multiprocessor 234 can also access off-chip global memory, which can include one or more of the local parallel processor memory and / or system memory. Any memory outside the parallel processing unit 202 can be used as global memory. Multiple embodiments (wherein the processing cluster 214 includes multiple instances of the graphics multiprocessor 234) can share common instructions and data, which can be stored in the L1 cache 308.

[0078] Each processing cluster 214 may include an MMU 245 (memory management unit) configured to map virtual addresses into physical addresses. In other embodiments, one or more instances of the MMU 245 may reside within the memory interface 218 of FIG. 2 . The MMU 245 includes: a set of page table entries (PTEs) for mapping virtual addresses of tiles (more on tiling) to physical addresses; and optionally a cache line index. The MMU 245 may include an address translation lookaside buffer (TLB) or cache that may reside within the graphics multiprocessor 234 or L1 cache or processing cluster 214. Physical addresses are processed to distribute surface data access locality, thereby allowing efficient request interleaving among partition units. The cache line index can be used to determine whether a request for a cache line is a hit or a miss.

[0079] In graphics and computing applications, the processing clusters 214 may be configured such that each graphics multiprocessor 234 is coupled to a texture unit 236 for performing texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. Texture data is read from an internal texture L1 cache (not shown) or in some embodiments from an L1 cache within the graphics multiprocessor 234, and retrieved from an L2 cache, local parallel processor memory, or system memory, as needed. Each graphics multiprocessor 234 outputs processed tasks to a data crossbar 240 to provide the processed tasks to another processing cluster 214 for further processing or to store the processed tasks in an L2 cache, local parallel processor memory, or system memory via a memory crossbar 216. The preROP 242 (e.g., pre-raster operation unit) is configured to receive data from the graphics multiprocessor 234, direct the data to ROP units, which may be located with partition units (e.g., partition units 220A to 220N of FIG. 2 ) as described herein. The preROP 242 unit may perform optimizations for color blending, organize pixel color data, and perform address translations.

[0080] It will be appreciated that the core architecture described herein is illustrative and that various variations and modifications are possible. Any number of processing units (e.g., graphics multiprocessor 234, texture unit 236, preROP 242, etc.) may be included within processing cluster 214. Furthermore, while only one processing cluster 214 is shown, a parallel processing unit as described herein may include any number of instances of processing cluster 214. In one embodiment, each processing cluster 214 may be configured to operate independently of other processing clusters 214 using separate and distinct processing units, L1 caches, etc.

[0081] Figure 2D A graphics multiprocessor 234 is shown according to one embodiment. In such an embodiment, the graphics multiprocessor 234 is coupled to the pipeline manager 232 of the processing cluster 214. The graphics multiprocessor 234 has an execution pipeline including, but not limited to, an instruction cache 252, an instruction unit 254, an address mapping unit 256, a register file 258, one or more general purpose graphics processing unit (GPGPU) cores 262, and one or more load / store units 266. The GPGPU cores 262 and the load / store units 266 are coupled to a cache memory 272 and a shared memory 270 via a memory and cache interconnect 268.

[0082] In one embodiment, the instruction cache 252 receives a stream of instructions to be executed from the pipeline manager 232. These instructions are cached in the instruction cache 252 and dispatched by the instruction unit 254 for execution. The instruction unit 254 can dispatch instructions into thread groups (e.g., warps), where each thread of the thread group is assigned to a different execution unit within the GPGPU core 262. Instructions can access any of the local, shared, or global address spaces by specifying an address within the unified address space. The address mapping unit 256 can be used to convert addresses in the unified address space into distinct memory addresses that can be accessed by the load / store unit 266.

[0083] The register file 258 provides a set of registers for the functional units of the graphics multiprocessor 324. The register file 258 provides temporary storage for operands for the data paths of the functional units (e.g., GPGPU core 262, load / store unit 266) connected to the graphics multiprocessor 324. In one embodiment, the register file 258 is divided between each of these functional units so that each functional unit is allocated a dedicated portion of the register file 258. In one embodiment, the register file 258 is divided between different warps executed by the graphics multiprocessor 324.

[0084] The GPGPU cores 262 may each include a floating point unit (FPU) and / or an integer arithmetic logic unit (ALU) that is used to execute instructions of the graphics multiprocessor 324. Depending on the embodiment, the GPGPU cores 262 may be similar in architecture, or may be different in architecture. For example and in one embodiment, the first portion of the GPGPU core 262 includes a single-precision FPU and an integer ALU, while the second portion of the GPGPU core includes a double-precision FPU. In one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic, or may implement variable-precision floating-point arithmetic. The graphics multiprocessor 324 may additionally include one or more fixed-function or special-function units to perform specific functions (e.g., copy rectangles or pixel blending operations). In one embodiment, one or more of the GPGPU cores may also include fixed or special-function logic.

[0085] In one embodiment, GPGPU core 262 includes SIMD logic that can execute single instruction to multiple groups of data. In one embodiment, GPGPU core 262 can physically execute SIMD4, SIMD8 and SIMD16 instructions, and logically execute SIMD1, SIMD2 and SIMD32 instructions. SIMD instructions for GPGPU core can be generated by shader compiler at compile time, or can be automatically generated when executing a program written and compiled as single program multiple data (SPMD) or SIMT architecture. Multiple threads of a program configured for SIMT execution model can be executed via a single SIMD instruction. For example, in one embodiment, eight SIMT threads performing the same or similar operation can be executed in parallel via a single SIMD8 logic unit.

[0086] The memory and cache interconnect 268 is an interconnect network that connects each of the functional units of the graphics multiprocessor 234 to the register file 258 and to the shared memory 270. In one embodiment, the memory and cache interconnect 268 is a crossbar interconnect that allows the load / store unit 266 to implement load and store operations between the shared memory 270 and the register file 258. The register file 258 can operate at the same frequency as the GPGPU core 262, so that data transfer between the GPGPU core 262 and the register file 258 is very low latency. The shared memory 270 can be used to implement communication between threads executing on the functional units within the graphics multiprocessor 234. The cache memory 272 can be used, for example, as a data cache to cache texture data communicated between the functional units and the texture unit 236. The shared memory 270 can also be used as a program-managed cache. Threads executing on the GPGPU core 262 can programmatically store data in the shared memory in addition to the automatically cached data stored in the cache memory 272.

[0087] FIG. 3A to FIG. 3B Additional graphics multiprocessors are shown according to embodiments. The graphics multiprocessors 325, 350 shown are Figure 2C The illustrated graphics multiprocessors 325, 350 may be configured as streaming multiprocessors (SMs) capable of executing a large number of execution threads simultaneously.

[0088] Figure 3A A graphics multiprocessor 325 is shown according to an additional embodiment. The graphics multiprocessor 325 is Figure 2DThe graphics multiprocessor 234 includes multiple additional instances of execution resource units. For example, the graphics multiprocessor 325 may include multiple instances of instruction units 332A to 332B, register files 334A-334B, and texture units 344A-344B. The graphics multiprocessor 325 also includes multiple groups of graphics or compute execution units (e.g., GPGPU cores 336A to 336B, GPGPU cores 337A to 337B, GPGPU cores 338A to 338B) and multiple groups of load / store units 340A to 340B. In one embodiment, the execution resource units have a common instruction cache 330, texture and / or data cache memory 342, and shared memory 346.

[0089] The various components may communicate via the interconnect structure 327. In one embodiment, the interconnect structure 327 includes one or more crossbar switches to enable communication between the various components of the graphics multiprocessor 325. In one embodiment, the interconnect structure 327 is a separate high-speed network fabric layer on which each component of the graphics multiprocessor 325 is stacked. The components of the graphics multiprocessor 325 communicate with remote components via the interconnect structure 327. For example, the GPGPU cores 336A-336B, 337A-337B, and 338A-338B may each communicate with the shared memory 346 via the interconnect structure 327. The interconnect structure 327 may arbitrate communications within the graphics multiprocessor 325 to ensure fair bandwidth allocation between components.

[0090] Figure 3B FIG. 3 shows a graphics multiprocessor 350 according to an additional embodiment. The graphics processor includes multiple sets of execution resources 356A to 356D, wherein each set of execution resources includes multiple instruction units, register files, GPGPU cores, and load storage units, such as Figure 2D and Figure 3A Execution resources 356A-356D may work in concert with texture units 360A-360D to perform texture operations while sharing instruction cache 354 and shared memory 362. In one embodiment, execution resources 356A-356D may share multiple instances of instruction cache 354 and shared memory 362 as well as texture and / or data cache memories 358A-358B. The various components may be communicated to one another via a communication protocol similar to Figure 3A The interconnect structure 327 and the interconnect structure 352 communicate with each other.

[0091] Those skilled in the art will understand that Figure 1 , FIG. 2A to FIG. 2D as well as FIG. 3A to FIG. 3BThe architecture described in is illustrative and non-limiting with respect to the scope of the present embodiments. Therefore, without departing from the scope of the embodiments described herein, the techniques described herein may be implemented on any properly configured processing unit, including but not limited to one or more mobile application processors, one or more desktop or server central processing units (CPUs) (including multi-core CPUs), one or more parallel processing units (e.g., parallel processing unit 202 of FIG. 2 ), and one or more graphics processors or special processing units.

[0092] In some embodiments, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU may be integrated on the same package or chip as these cores and communicatively coupled to these cores via an internal processor bus / interconnect (i.e., inside the package or chip). Regardless of the manner in which the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuits / logic to efficiently process these commands / instructions.

[0093] Technologies for GPU to host processor interconnect

[0094] Figure 4A An exemplary architecture is shown in which multiple GPUs 410 to 413 are communicatively coupled to multiple multi-core processors 405 to 406 via high-speed links 440 to 443 (e.g., buses, point-to-point interconnects, etc.). In one embodiment, the high-speed links 440 to 443 support 4GB / s, 30GB / s, 80GB / s, or higher communication throughput, depending on the implementation. Various interconnect protocols may be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. However, the underlying principles of the invention are not limited to any particular communication protocol or throughput.

[0095] Additionally, in one embodiment two or more of the GPUs 410 to 413 are interconnected via high-speed links 444 to 445, which may be implemented using the same or different protocols / links as used for high-speed links 440 to 443. Similarly, two or more of the multi-core processors 405 to 406 may be connected via high-speed link 433, which may be a symmetric multiprocessor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, Figure 4AAll communications between the various system components shown in can be accomplished using the same protocols / links (eg, via a common interconnect structure). However, as mentioned, the underlying principles of the invention are not limited to any particular type of interconnect technology.

[0096] In one embodiment, each multi-core processor 405-406 is communicatively coupled to processor memory 401-402 via memory interconnects 430-431, respectively, and each GPU 410-413 is communicatively coupled to GPU memory 420-423 via GPU memory interconnects 450-453, respectively. The memory interconnects 430-431 and 450-453 may utilize the same or different memory access technologies. By way of example and not limitation, the processor memory 401-402 and the GPU memory 420-423 may be volatile memory, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memory, such as 3D XPoint or nano random access memory. In one embodiment, a portion of the memory may be volatile memory and another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0097] As described below, although the various processors 405-406 and GPUs 410-413 may be physically coupled to specific memories 401-402, 420-423, respectively, a unified memory architecture may be implemented in which the same virtual system address space (also referred to as an "effective address" space) is distributed among all of the various physical memories. For example, the processor memories 401-402 may each include 64GB of system memory address space, and the GPU memories 420-423 may each include 32GB of system memory address space (yielding a total of 256GB of addressable memory in this example).

[0098] Figure 4B Additional details are shown for the interconnection between the multi-core processor 407 and the graphics acceleration module 446 according to one embodiment. The graphics acceleration module 446 may include one or more GPU chips integrated on a line card that is coupled to the processor 407 via the high-speed link 440. Alternatively, the graphics acceleration module 446 may be integrated on the same package or chip as the processor 407.

[0099] The processor 407 shown includes multiple cores 460A to 460D, each core having a translation lookaside buffer 461A to 461D and one or more caches 462A to 462D. These cores may include various other components for executing instructions and processing data, which are not shown to avoid obscuring the basic principles of the present invention (e.g., instruction acquisition units, branch prediction units, decoders, execution units, reorder buffers, etc.). Caches 462A to 462D may include level 1 (L1) and level 2 (L2) caches. In addition, one or more shared caches 426 may be included in the cache hierarchy and shared by multiple groups of cores 460A to 460D. For example, one embodiment of the processor 407 includes 24 cores, each core having its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one of the L2 and L3 caches is shared by two adjacent cores. The processor 407 and the graphics accelerator integrated module 446 are connected to the system memory 441 , which may include the processor memories 401 to 402 .

[0100] The coherence of data and instructions stored in the various caches 462A-462D, 456, and the system memory 441 is maintained via inter-core communications over the coherence bus 464. For example, each cache may have cache coherence logic / circuitry associated therewith to communicate via the coherence bus 464 in response to a detected read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented via the coherence bus 464 to snoop cache accesses. Cache snooping / coherence techniques are well understood by those skilled in the art and will not be described in detail herein to avoid obscuring the underlying principles of the present invention.

[0101] In one embodiment, the proxy circuit 425 communicatively couples the graphics acceleration module 446 to the coherence bus 464, thereby allowing the graphics acceleration module 446 to participate in the cache coherence protocol as a peer of the core. Specifically, the interface 435 provides connectivity to the proxy circuit 425 via a high-speed link 440 (e.g., a PCIe bus, NVLink, etc.), and the interface 437 connects the graphics acceleration module 446 to the link 440.

[0102] In one implementation, the accelerator integrated circuit 436 provides cache management, memory access, context management, and interrupt management services on behalf of the multiple graphics processing engines 431, 432, N of the graphics acceleration module 446. The graphics processing engines 431, 432, N may each include a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 431, 432, N may include different types of graphics processing engines within the GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a bit block transfer (blit) engine. In other words, the graphics acceleration module may be a GPU with multiple graphics processing engines 431 to 432, N, or the graphics processing engines 431 to 432, N may be individual GPUs integrated on a common package, line card, or chip.

[0103] In one embodiment, the accelerator integrated circuit 436 includes a memory management unit (MMU) 439 for performing various memory management functions, such as virtual to physical memory translation (also known as effective to real memory translation) and memory access protocols for accessing the system memory 441. The MMU 439 may also include a translation lookaside buffer (TLB) (not shown) for virtual / effective cache to physical / real address translation. In one implementation, the cache 438 stores commands and data for effective access by the graphics processing engines 431 to 432, N. In one embodiment, the data stored in the cache 438 and the graphics memory 433 to 434, N is kept consistent with the core caches 462A to 462D, 456 and the system memory 411. As mentioned, this may be accomplished via proxy circuitry 425, which participates in cache coherence mechanisms on behalf of cache 438 and memories 433 to 434, N (e.g., sending updates related to modifications / accesses to cache lines on processor caches 462A to 462D, 456 to and receiving updates from cache 438).

[0104] A set of registers 445 stores context data for threads executed by the graphics processing engines 431 to 432, N, and context management circuitry 448 manages thread contexts. For example, context management circuitry 448 may perform save and restore operations during context switching to save and restore contexts of various threads (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, upon context switching, context management circuitry 448 may store current register values ​​to a designated area in memory (e.g., identified by a context pointer). It may then restore these register values ​​upon returning to the context. In one embodiment, interrupt management circuitry 447 receives and processes interrupts received from system devices.

[0105] In one implementation, virtual / effective addresses from the graphics processing engine 431 are converted to real / physical addresses in the system memory 411 by the MMU 439. One embodiment of the accelerator integrated circuit 436 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 446 and / or other accelerator devices. The graphics accelerator module 446 may be dedicated to a single application executing on the processor 407, or may be shared between multiple applications. In one embodiment, a virtualized graphics execution environment is presented in which multiple applications or virtual machines (VMs) share the resources of the graphics processing engines 431 to 432, N. These resources may be subdivided into "slices" that are allocated to the different VMs and / or applications based on the processing requirements and priorities associated with the different VMs and / or applications.

[0106] Thus, the accelerator integrated circuit acts as a bridge to the system of graphics acceleration module 446 and provides address translation and system memory cache services. In addition, the accelerator integrated circuit 436 can provide virtualization facilities for the host processor to manage virtualization, interrupts and memory management of the graphics processing engine.

[0107] Since the hardware resources of the graphics processing engines 431-432, N are explicitly mapped to the real address space seen by the host processor 407, any host processor can directly address these resources using effective address values. In one embodiment, one function of the accelerator integrated circuit 436 is to physically separate the graphics processing engines 431-432, N so that they appear to the system as independent units.

[0108] As mentioned, in the illustrated embodiment, one or more graphics memories 433-434, M are respectively coupled to each of the graphics processing engines 431-432, N. The graphics memories 433-434, M store instructions and data processed by each of the graphics processing engines 431-432, N. The graphics memories 433-434, M may be volatile memory, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memory, such as 3D XPoint or Nano-Random Access Memory (Nano-Ram).

[0109] In one embodiment, to reduce data traffic on link 440, biasing techniques are used to ensure that the data stored in graphics memory 433-434, M is data that will be used most frequently by graphics processing engines 431-432, N and preferably not used (at least not frequently) by cores 460A-460D. Similarly, the biasing mechanism attempts to keep data needed by cores (and preferably not by graphics processing engines 431-432, N) within the caches 462A-462D, 456 of these cores and system memory 411.

[0110] Figure 4C Another embodiment is shown in which an accelerator integrated circuit 436 is integrated within the processor 407. In this embodiment, the graphics processing engines 431-432, N communicate directly to the accelerator integrated circuit 436 via the interface 437 and the interface 435 (again, these interfaces can utilize any form of bus or interface protocol) through the high-speed link 440. The accelerator integrated circuit 436 can perform operations related to Figure 4B The same operations are described, but at potentially higher throughput given their close proximity to the coherency bus 462 and caches 462A-462D, 426.

[0111] One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization). The latter may include a programming model controlled by accelerator integrated circuit 436 and a programming model controlled by graphics acceleration module 446.

[0112] In one embodiment of a dedicated process model, the graphics processing engines 431 to 432, N are dedicated to a single application or process under a single operating system. A single application can funnel other application requests to the graphics engines 431 to 432, N, thereby providing virtualization within a VM / partition.

[0113] In a dedicated process programming model, graphics processing engines 431 to 432, N can be shared by multiple VM / application partitions. The shared model requires a hypervisor to virtualize graphics processing engines 431 to 432, N to allow access by each operating system. For a single partition system without a hypervisor, graphics processing engines 431 to 432, N are owned by the operating system. In both cases, the operating system can virtualize graphics processing engines 431 to 432, N to provide access to each process or application.

[0114] For the shared programming model, the graphics acceleration module 446 or the individual graphics processing engines 431 to 432, N use the process handle to select a process element. In one embodiment, the process elements are stored in the system memory 411 and can be addressed using the effective address to real address translation techniques described herein. The process handle can be an implementation-specific value provided to the host process when registering its context with the graphics processing engine 431 to 432, N (that is, calling the system software to add the process element to the process element linked list). The lower 16 bits of the process handle can be the offset of the process element within the process element linked list.

[0115] Figure 4D An exemplary accelerator integrated slice 490 is shown. As used herein, a "slice" includes a specified portion of the processing resources of an accelerator integrated circuit 436. An application effective address space 482 within the system memory 411 stores process elements 483. In one embodiment, the process elements 483 are stored in response to a GPU call 481 from an application 480 executed on a processor 407. The process element 483 contains the process state of the corresponding application 480. The work descriptor (WD) 484 contained in the process element 483 can be a single job requested by the application, or can contain a pointer to a job queue. In the latter case, WD484 is a pointer to a job request queue in the address space 482 of the application.

[0116] Graphics acceleration module 446 and / or individual graphics processing engines 431-432, N may be shared by all processes or a subset of processes in the system. Embodiments of the present invention include infrastructure for setting process state and sending WD 484 to graphics acceleration module 446 to start a job in a virtualized environment.

[0117] In one implementation, the dedicated process programming model is implementation specific. In this model, a single process owns the graphics acceleration module 446 or individual graphics processing engine 431. Since the graphics acceleration module 446 is owned by a single process, when the graphics acceleration module 446 is assigned, the hypervisor initializes the accelerator integrated circuit 436 for the owning partition and the operating system initializes the accelerator integrated circuit 436 for the owning process.

[0118] In operation, the WD acquisition unit 491 in the accelerator integrated slice 490 acquires the next WD 484, which includes an indication of work to be completed by one of the graphics processing engines of the graphics acceleration module 446. Data from the WD 484 may be stored in registers 445 and used by the MMU 439, interrupt management circuit 447, and / or context management circuit 446 as shown. For example, one embodiment of the MMU 439 includes a segment / page walk circuit for accessing a segment / page table 486 within the OS virtual address space 485. The interrupt management circuit 447 may process an interrupt event 492 received from the graphics acceleration module 446. When performing graphics operations, the effective address 493 generated by the graphics processing engine 431 to 432, N is converted to a real address by the MMU 439.

[0119] In one embodiment, a set of identical registers 445 are replicated for each graphics processing engine 431 to 432, N, and / or graphics acceleration module 446, and these registers may be initialized by a hypervisor or operating system. Each of these replicated registers may be included in an accelerator integrated slice 490. Exemplary registers that may be initialized by a hypervisor are shown in Table 1.

[0120] Table 1 - Registers initialized by the hypervisor

[0121] 1 Slice Control Register 2 Real address (RA) dispatched process area pointer 3 Authority Mask Override Register 4 Interrupt vector table entry offset 5 Interrupt Vector Table Entry Limits 6 Status Register 7 Logical Partition ID 8 Real Address (RA) Hypervisor Accelerator Utilizing Record Pointers 9 Storage Description Register

[0122] Example registers that may be initialized by the operating system are shown in Table 2.

[0123] Table 2 - Registers initialized by the operating system

[0124] 1 Process and thread identities 2 Effective Address (EA) context save / restore pointer 3 Virtual Address (VA) Accelerator Utilizes Record Pointers 4 Virtual Address (VA) Segment Table Pointer 5 Permission Mask 6 Job Descriptor

[0125] In one embodiment, each WD 484 is specific to a particular graphics acceleration module 446 and / or graphics processing engine 431-432, N. It contains all the information needed by the graphics processing engine 431-432, N to complete its work, or it may be a pointer to a memory location where the application has set up a command queue for work to be done.

[0126] Figure 4E Additional details of one embodiment of a sharing model are presented. This embodiment includes a hypervisor real address space 498 in which a process element list 499 is stored. The hypervisor real address space 498 is accessible via a hypervisor 496 that virtualizes a graphics acceleration module engine for an operating system 495.

[0127] The shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 446. There are two programming models where the graphics acceleration module 446 is shared by multiple processes and partitions: time-sliced ​​shared and graphics directed shared.

[0128] In this model, the hypervisor 496 owns the graphics acceleration module 446 and makes its functionality available to all operating systems 495. In order for the graphics acceleration module 446 to support virtualization by the hypervisor 496, the graphics acceleration module 446 may comply with the following requirements: 1) The application's job requests must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 446 must provide a context save and restore mechanism. 2) The application's job requests must be guaranteed to be completed within a specified amount of time by the graphics acceleration module 446 (including any transition failures), or the graphics acceleration module 446 provides the ability to preempt the processing of a job. 3) When operating in a directed-sharing programming model, the graphics acceleration module 446 must be guaranteed fairness between processes.

[0129] In one embodiment, for the shared model, the application 480 is required to use the graphics acceleration module 446 type, work descriptor (WD), permission mask register (AMR) value and context save / restore region pointer (CSRP) to make an operating system 495 system call. The graphics acceleration module 446 type describes the target acceleration function for the system call. The graphics acceleration module 446 type can be a system-specific value. The WD is formatted specifically for the graphics acceleration module 446 and can be in the form of a graphics acceleration module 446 command, an effective address pointer to a user-defined structure, an effective address pointer to a command queue, or any other data structure for describing the work to be completed by the graphics acceleration module 446. In one embodiment, the AMR value is the AMR state to be used for the current process. The value passed to the operating system is similar to the application of setting the AMR. If the accelerator integrated circuit 436 and the graphics acceleration module 446 implementation do not support the user permission mask override register (UAMOR), the operating system can apply the current UAMOR value to the AMR value and then pass the AMR in the hypervisor call. Optionally, the hypervisor 496 may apply the current permission mask overwrite register (AMOR) value before placing the AMR into the process element 483. In one embodiment, the CSRP is one of the registers 445 that contains the effective address of an area in the application's address space 482 for the graphics acceleration module 446 to save and restore context state. This pointer is optional if state does not need to be saved between jobs or when a job is preempted. The context save / restore area may be pinned system memory.

[0130] Upon receiving the system call, the operating system 495 may verify that the application 480 has been registered and has been given permission to use the graphics acceleration module 446. The operating system 495 then calls the hypervisor 496 using the information shown in Table 3.

[0131] Table 3 – OS to Hypervisor call parameters

[0132] 1 Work Descriptor (WD) 2 The permission mask register (AMR) value (potentially masked) 3 Effective Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and optional thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual address of the storage segment table pointer (SSTP) 7 Logical Interrupt Service Number (LISN)

[0133] Upon receiving the hypervisor call, the hypervisor 496 verifies that the operating system 495 has been registered and has been given permission to use the graphics acceleration module 446. The hypervisor 496 then places the process element 483 into a linked list of process elements of the corresponding graphics acceleration module 446 type. The process element may include the information shown in Table 4.

[0134] Table 4 - Process element information

[0135] 1 Work Descriptor (WD) 2 The permission mask register (AMR) value (potentially masked) 3 Effective Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and optional thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual address of the storage segment table pointer (SSTP) 7 Logical Interrupt Service Number (LISN) 8 Interrupt vector table derived from hypervisor call parameters 9 Status Register (SR) Value 10 Logical Partition ID (LPID) 11 Real Address (RA) Hypervisor Accelerator Utilizing Record Pointers 12 Memory Descriptor Register (SDR)

[0136] In one embodiment, the hypervisor initializes the plurality of accelerator integrated slice 490 registers 445 .

[0137] like Figure 4F As shown in , one embodiment of the present invention employs a unified memory addressable via a common virtual memory address space for accessing physical processor memories 401-402 and GPU memories 420-423. In this implementation, operations executed on GPUs 410-413 utilize the same virtual / effective memory address space to access processor memories 401-402 and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 401, a second portion is allocated to second processor memory 402, a third portion is allocated to GPU memory 420, and so on. This allows the entire virtual / effective memory space (sometimes referred to as the effective address space) to be distributed across each of processor memories 401-402 and GPU memories 420-423, thereby allowing any processor or GPU to access any physical memory using a virtual address mapped to the memory.

[0138] In one embodiment, bias / coherency management circuits 494A-494E within one or more of MMUs 439A-439E ensure cache coherency between caches of a host processor (e.g., 405) and GPUs 410-413 and implement biasing techniques that indicate physical memory where certain types of data should be stored. Figure 4F 4. Multiple instances of bias / consistency management circuits 494A-494E are shown in , but bias / consistency circuits may be implemented within an MMU of one or more host processors 405 and / or within an accelerator integrated circuit 436.

[0139] One embodiment allows GPU-attached memory 420 to 423 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology, but without the typical performance drawbacks associated with full system cache coherence. The ability of GPU-attached memory 420 to 423 to be accessed as system memory without heavy cache coherence overhead provides a beneficial operating environment for GPU offloading. This arrangement allows host processor 405 software to set operands and access calculation results without the overhead of traditional I / O DMA data copying. Such traditional copying involves driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, which are all inefficient relative to simple memory accesses. At the same time, the ability to access GPU-attached memory 420 to 423 without cache coherence overhead can be critical to the execution time of the offloaded calculation. In the case of substantial streaming write memory traffic, for example, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPUs 410 to 413. The efficiency of operand setup, the efficiency of result access, and the efficiency of GPU calculation all play a role in determining the effectiveness of GPU offloading.

[0140] In one implementation, the selection between GPU bias and host processor bias is driven by a bias tracker data structure. A bias table may be used, for example, which may be a page granular structure including 1 or 2 bits per GPU attached memory page (i.e., controlled at the granularity of a memory page). The bias table may be implemented using stolen memory ranges of one or more GPU attached memories 420 to 423, with or without a bias cache in GPUs 410 to 413 (e.g., to cache frequently used / recently used entries of the bias table). Alternatively, the entire bias table may be maintained within the GPU.

[0141] In one implementation, the bias table entry associated with each access to GPU attached memory 420 to 423 is accessed before actually accessing the GPU memory, resulting in the following operations. First, local requests from GPUs 410 to 413 that find their pages in the GPU bias (these local requests find their pages in the GPU bias) are forwarded directly to the corresponding GPU memory 420 to 423. Local requests from the GPU (these local requests find their pages in the host bias) are forwarded to the processor 405 (e.g., via a high-speed link as discussed above). In one embodiment, the request from the processor 405 to find the requested page in the host processor bias completes a request similar to a normal memory read. Alternatively, the request for the GPU bias page can be forwarded to the GPU 410 to 413. Then, if the GPU is not currently using the page, it can transfer the page to the host processor bias.

[0142] The bias state of a page may be changed by a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited set of circumstances, a purely hardware-based mechanism.

[0143] One mechanism for changing the bias state employs an API call (e.g., OpenCL) which in turn calls the GPU's device driver which in turn sends a message (or queues a command descriptor) to the GPU instructing it to change the bias state and perform a cache flushing operation in the host for some transitions. The cache flushing operation is required for transitions from host processor 405 bias to GPU bias, but not for the reverse transition.

[0144] In one embodiment, cache coherency is maintained by temporarily rendering GPU biased pages that are not cacheable by host processor 405. To access these pages, processor 405 may request access from GPU 410, which may or may not be granted immediately, depending on the implementation. Therefore, to reduce communication between processor 405 and GPU 410, it is advantageous to ensure that GPU biased pages are those pages that are needed by the GPU but not by host processor 405 (and vice versa).

[0145] Graphics processing pipeline

[0146] Figure 5 A graphics processing pipeline 500 according to an embodiment is shown. In one embodiment, a graphics processor may implement the illustrated graphics processing pipeline 500. The graphics processor may be included in a parallel processing subsystem as described herein, such as the parallel processing subsystem 200 of FIG. 2 , which in one embodiment is Figure 1 2 . Various parallel processing systems may implement the graphics processing pipeline 500 via one or more instances of a parallel processing unit (e.g., parallel processing unit 202 of FIG. 2 ) as described herein. For example, a shader unit (e.g., graphics multiprocessor 234 of FIG. 3 ) may be configured to perform the functions of one or more of a vertex processing unit 504, a tessellation control processing unit 508, a tessellation evaluation processing unit 512, a geometry processing unit 516, and a fragment / pixel processing unit 524. The functions of the data assembler 502, the primitive assemblers 506, 514, 518, the tessellation unit 510, the rasterizer 522, and the raster operation unit 526 may also be performed by other processing engines within a processing cluster (e.g., processing cluster 214 of FIG. 3 ) and corresponding partition units (e.g., partition units 220A to 220N of FIG. 2 ). The graphics processing pipeline 500 may also be implemented using dedicated processing units for one or more functions. In one embodiment, one or more portions of graphics processing pipeline 500 may be executed by parallel processing logic within a general purpose processor (e.g., a CPU). In one embodiment, one or more portions of graphics processing pipeline 500 may access on-chip memory (e.g., such as parallel processor memory 222 in FIG. 2 ) via memory interface 528, which may be an example of memory interface 218 in FIG. 2 .

[0147] In one embodiment, data assembler 502 is a processing unit that collects vertex data for surfaces and primitives. Data assembler 502 then outputs vertex data including vertex attributes to vertex processing unit 504. Vertex processing unit 504 is a programmable execution unit that executes vertex shader programs to illuminate and transform vertex data as specified by the vertex shader programs. Vertex processing unit 504 reads data stored in cache, local or system memory for use in processing vertex data, and vertex processing unit 504 can be programmed to transform vertex data from an object-based coordinate representation to a world space coordinate space or a normalized device coordinate space.

[0148] A first instance of primitive assembler 506 receives vertex attributes from vertex processing unit 504. Primitive assembler 506 reads the stored vertex attributes as needed and builds graphics primitives for processing by tessellation control processing unit 508. Graphics primitives include triangles, line segments, points, patches, etc., which are supported by various graphics processing application programming interfaces (APIs).

[0149] The tessellation control processing unit 508 treats the input vertices as control points for the geometric patch. The control points are converted from the input representation from the patch (e.g., the basis of the patch) to a representation suitable for use in the surface evaluation by the tessellation evaluation processing unit 512. The tessellation control processing unit 508 can also calculate the tessellation factors for the edges of the geometric patch. The tessellation factors are applied to a single edge and the view-dependent detail level associated with the edge is quantized. The tessellation unit 510 is configured to receive the tessellation factors for the edges of the patch and tessellate the patch into a plurality of geometric primitives such as lines, triangles, or quadrilateral primitives, which are transmitted to the tessellation evaluation processing unit 512. The tessellation evaluation processing unit 512 operates on the parameterized coordinates of the subdivided patch to generate a surface representation and vertex attributes for each vertex associated with the geometric primitive.

[0150] A second instance of primitive assembler 514 receives vertex attributes from tessellation evaluation processing unit 512, reads stored vertex attributes as needed, and builds graphics primitives for processing by geometry processing unit 516. Geometry processing unit 516 is a programmable execution unit that executes geometry shader programs to transform graphics primitives received from primitive assembler 514 as specified by the geometry shader programs. In one embodiment, geometry processing unit 516 is programmed to subdivide a graphics primitive into one or more new graphics primitives and to compute parameters for rasterizing the new graphics primitives.

[0151] In some embodiments, the geometry processing unit 516 may add or delete elements in the geometry stream. The geometry processing unit 516 outputs parameters and vertices specifying new graphics primitives to the primitive assembler 518. The primitive assembler 518 receives the parameters and vertices from the geometry processing unit 516 and constructs graphics primitives for processing by the viewport scaling, picking, and clipping unit 520. The geometry processing unit 516 reads data stored in the parallel processor memory or the system memory for use in processing the geometry data. The viewport scaling, picking, and clipping unit 520 performs clipping, picking, and viewport scaling, and outputs the processed graphics primitives to the rasterizer 522.

[0152] The rasterizer 522 can perform depth sorting and other depth-based optimizations. The rasterizer 522 also performs scan conversion on new graphics primitives to generate fragments, and outputs those fragments and associated coverage data to the fragment / pixel processing unit 524. The fragment / pixel processing unit 524 is a programmable execution unit configured to execute a fragment shader program or a pixel shader program. The fragment / pixel processing unit 524 transforms fragments or pixels received from the rasterizer 522 as specified by the fragment or pixel shader program. For example, the fragment / pixel processing unit 524 can be programmed to perform operations to generate shaded fragments or pixels output to the raster operation unit 526, including but not limited to texture mapping, shading, blending, texture correction, and perspective correction. The fragment / pixel processing unit 524 can read data stored in a parallel processor memory or system memory for use in processing fragment data. The fragment or pixel shader program can be configured to shade with samples, pixels, tiles, or other granularity depending on the sampling rate configured for the processing unit.

[0153] Raster operations unit 526 is a processing unit that performs raster operations including, but not limited to, stenciling, z-testing, blending, etc., and outputs pixel data as processed graphics data for storage in graphics memory (e.g., parallel processor memory 222 and / or Figure 1 The raster operations unit 526 may be configured to compress the z or color data written to the memory and to decompress the z or color data read from the memory.

[0154] MV / mode prediction, ROI-based emission, metadata capture and format detection for 360 video examples

[0155] Now turn to Figure 6 , an embodiment of the electronic processing system 600 may include: a display processor 611 for generating image data for display; and a memory 612, communicatively coupled to the display processor 611 to store a two-dimensional (2D) frame corresponding to a projection from the 360 ​​video space. The system 600 may include a component predictor 613, the component predictor being communicatively coupled to the display processor 611 to predict an encoded component of a first block of the 2D frame based on encoding information from one or more neighboring blocks of the 2D frame, wherein the one or more neighboring blocks of the 2D frame include only one or more blocks that are adjacent to the first block of the 2D frame in the 360 ​​video space. For example, the encoding information may include one or more of motion vector information and mode information.

[0156] The system 600 may also include a prioritizer 614 communicatively coupled to the display processor 611 to prioritize the transmission of the grouping of the 2D frames based on the identified region of interest; and / or a format detector 615 communicatively coupled to the display processor 611 to detect a 360 video format of the 2D frame based on the image content of the 2D frame. For example, the detected 360 video format may include one or more of a fisheye format, an equirectangular projection format, a cube map format, and a packed cube map format. In some embodiments, the prioritizer 614 may be configured to prioritize the encoding of the second block of the 2D frame based on the identified region of interest.

[0157] Some embodiments of the system 600 may further include: a 360 video capture device 616 communicatively coupled to the display processor 611 to capture 360 ​​video content; and a context annotator 617 communicatively coupled to the 360 ​​video capture device 616 to annotate the 360 ​​video content with context information contemporary with the captured 360 video content. For example, the context information may include one or more of motion information, position information, speed information, acceleration information, orientation information, and direction information.

[0158] Embodiments of each of the above display processor 611, memory 612, component predictor 613, prioritizer 614, format detector 615, 360 video capture device 616, context tagger 617 and other system components can be implemented in hardware, software or any suitable combination thereof. For example, the hardware implementation may include configurable logic (such as, for example, a programmable logic array (PLA), FPGA, complex programmable logic device (CPLD)), or in fixed-function logic hardware using circuit technology (such as, for example, ASIC, complementary metal oxide semiconductor (CMOS) or transistor-transistor logic (TTL) technology), or any combination of the above two situations. Alternatively or additionally, these components can be implemented as a set of logic instructions in one or more modules, which are stored in a machine-readable or computer-readable storage medium (such as, random access memory (RAM), read-only memory (ROM), programmable ROM (PROM), firmware, flash memory, etc.) to be executed by a processor or computing device. For example, computer program code for implementing the operations of these components may be written in any combination of one or more operating system applicable / suitable programming languages ​​(including object-oriented programming languages ​​such as PYTHON, PERL, JAVA, SMALLTALK, C++, C#, etc.) and conventional procedural programming languages ​​(e.g., the "C" programming language or similar programming languages).

[0159] Component Predictor Example

[0160] Now turn to Fig. 7A , an embodiment of the graphics device 700 may include: an encoder 721 for encoding a first block of a two-dimensional (2D) frame, wherein the 2D frame corresponds to a projection of a 360 video space; and a component predictor 722, communicatively coupled to the encoder to: determine whether the first block is a neighbor of a second block of the 2D frame in the 360 ​​video space; and if the first block is determined to be a neighbor of the second block in the 360 ​​video space, then predict the encoded components of the second block based on the encoded information of the first block. For example, the component predictor 722 may be configured to: if the first block is determined to be a neighbor of the second block in the 360 ​​video space, then predict the motion vector of the second block based on the encoded motion vector information of the first block. In some embodiments, the component predictor 722 may be additionally or alternatively configured to: if the first block is determined to be a neighbor of the second block in the 360 ​​video space, then predict the mode of the second block based on the encoded mode information of the first block. For example, the mode information may include luma and chroma intra prediction mode information, merge mode information, and / or reference index information. In some embodiments, the encoder 721 may be configured to encode a second block of the 2D frame based on the predicted coded component.For example, in some embodiments, a block may include any of individual pixels, a group of adjacent pixels, or a group of pixels.

[0161] Some embodiments of the apparatus 700 may further include any of: a prioritizer communicatively coupled to the encoder 721 to prioritize the transmission of groups of 2D frames based on the identified regions of interest; a format detector communicatively coupled to the encoder 721 to detect a 360 video format of the 2D frames based on image content of the 2D frames; and / or a 360 video capture device communicatively coupled to the encoder 721 to capture 360 ​​video content and having a context annotator communicatively coupled to the 360 ​​video capture device to annotate the 360 ​​video content using context information contemporary with the captured 360 video content.

[0162] The embodiments of each of the above encoder 721, component predictor 722 and other components of the device 700 can be implemented in hardware, software or any combination thereof. For example, the hardware implementation may include configurable logic (such as, for example, PLA, FPGA, CPLD), or in fixed-function logic hardware using circuit technology (such as, for example, ASIC, CMOS or TTL technology), or any combination of the above two situations. Alternatively or in addition, these components can be implemented as a set of logic instructions in one or more modules, and the logic instructions are stored in a machine-readable or computer-readable storage medium (such as, RAM, ROM, PROM, firmware, flash memory, etc.) to be executed by a processor or computing device. For example, the computer program code for implementing the operation of these components can be written in any combination of one or more operating system applicable / suitable programming languages ​​(including object-oriented programming languages ​​such as PYTHON, PERL, JAVA, SMALLTALK, C++, C#, etc.) and conventional program programming languages ​​(such as, "C" programming language or similar programming languages).

[0163] Now turn to Figure 7B , an embodiment of the method 730 for processing 360 video may include: at block 731, encoding a first block of a two-dimensional (2D) frame, wherein the 2D frame corresponds to a projection of a 360 video space; at block 732, determining whether the first block is a neighbor of a second block of the 2D frame in the 360 ​​video space; and at block 733, if the first block is determined to be a neighbor of the second block in the 360 ​​video space, predicting an encoded component of the second block based on encoded information of the first block. The method 730 may include: at block 734, if the first block is determined to be a neighbor of the second block in the 360 ​​video space, predicting a motion vector of the second block based on encoded motion vector information of the first block. Additionally or alternatively, the method 730 may also include: at block 735, if the first block is determined to be a neighbor of the second block in the 360 ​​video space, predicting a mode of the second block based on encoded mode information of the first block. In some embodiments, the method 730 may further include, at block 736 , encoding a second block of the 2D frame based on the predicted encoding component.

[0164] Embodiments of method 730 may be implemented using a system, device, GPU, or parallel processing unit (PPU) (such as, for example, each of the above described herein). More specifically, the hardware implementation of method 730 may include configurable logic (such as, for example, PLA, FPGA, CPLD), or in fixed-function logic hardware using circuit technology (such as, for example, ASIC, CMOS, or TTL technology), or any combination of the above two situations. Alternatively or in addition, method 730 may be implemented as a set of logic instructions in one or more modules, which are stored in a machine-readable or computer-readable storage medium (such as RAM, ROM, PROM, firmware, flash memory, etc.) to be executed by a processor or computing device. For example, the computer program code for implementing the operation of these components can be written in any combination of one or more operating system applicable / suitable programming languages ​​(including object-oriented programming languages ​​such as PYTHON, PERL, JAVA, SMALLTALK, C++, C#, etc.) and conventional program programming languages ​​(such as, "C" programming language or similar programming languages). For example, method 730 may be implemented on a computer-readable medium as described below in conjunction with Examples 18-21.

[0165] For example, various embodiments or portions of method 730 may be implemented using application or driver software (e.g., via an API). Other embodiments or portions of method 730 may be implemented using specialized code (e.g., shaders) to be executed on a GPU. Other embodiments or portions of method 730 may be implemented using fixed-function logic or specialized hardware (e.g., in a GPU).

[0166] Some embodiments may advantageously provide mode / MV prediction extensions for 360 video. For example, as explained in more detail below, for 360 video in a 2D projection plane, neighboring blocks in the original 3D space may not be adjacent in 2D space. If the current block has neighboring blocks that have already been encoded in the original 3D space, some embodiments may use the neighbor information to predict the current block. Some embodiments may utilize neighbors from 3D space to improve prediction of all or most prediction components that may be affected by any discontinuities (e.g., surfaces, boundaries, etc.) caused by the 2D mapping.

[0167] In some embodiments, the bitstream may be motion vector encoded. For example, each block may have motion information, such as x-direction and y-direction. The video codec may use adjacent motion vectors to predict the current motion vector. The motion vector of the adjacent block may be similar to the motion vector of the current block. When a 3D video is mapped to 2D in a 2D map, there may be no connection between the edges of the map. However, in 3D space, the left edge and the right edge may be connected. There may be correlation between the edges, and these edges may be neighbors in a 3D sphere. Some embodiments may extend the adjacent blocks used for prediction to include adjacent blocks from 3D space in addition to the adjacent blocks in 2D space.

[0168] For example, if some pixels are neighbors in 3D space, then even if these pixels are not neighbors in 2D space, they can still be considered neighbors in 2D space and can be added to a set of neighbors that can be used for prediction (e.g., in addition to the already adjacent pixels or neighbors in 2D space). The definition of neighbors can vary based on the prediction type, processing type, and / or other factors.

[0169] Some embodiments may advantageously provide coding component prediction for 360 video. For example, coding component prediction may enable coding component prediction along the boundaries of 2D video frames and the faces of such 2D video frames, when such boundaries are continuous in the corresponding 360 video (e.g., in the corresponding 360 video sphere), the faces are discontinuous in the projected 2D plane. Specifically, in some 360 ​​video decoding contexts, 2D video frames may be provided to an encoder for encoding into a bitstream (e.g., a bitstream that complies with a standard), the 2D video frames being projections from the 360 ​​video space (e.g., projections from the 360 ​​video to the 2D plane based on a predetermined format). The bitstream may be stored or transmitted or the like, and the bitstream may be processed by a decoder. A decoder (e.g., a decoder that complies with a standard) may decode the bitstream to reconstruct a 2D video frame (e.g., a projection from a 360 video). The reconstructed 2D video frame may be processed for presentation to a user. For example, the selected viewport may be used to determine one or more portions of a reconstructed 2D video frame, which may be assembled as needed and provided to a display device for presentation to a user.

[0170] In such techniques, standard-compliant codec (encoder / decoder) techniques may include intra-frame coding component prediction for adjacent or neighboring blocks / pixels in a video frame that crosses a frame / block (e.g., macroblock, coding unit, etc.) boundary. However, in the projection from 360 video space to 2D video frame, some blocks / pixels that are neighbors in 360 video space are presented or formatted as non-adjacent blocks / pixels in 2D video frame. In some embodiments, the term non-adjacent may indicate pixels that are not spatially adjacent (e.g., in a 2D video frame) and that a number of pixel sets have no adjacent pixels between them (e.g., no pixel in a first block in a 2D video frame is spatially adjacent to any pixel in a second block). For example, such adjacent blocks / pixels in 3D video space may be on opposite boundaries of a corresponding 2D video frame, on non-adjacent boundaries of a surface projection within a corresponding 2D video frame, and so on, as further discussed herein.

[0171] In some embodiments, a group of blocks for coding component prediction may be identified within a 2D video frame (which is a projection from 360 video space) such that the group of blocks includes a first block and a second block (the two blocks are non-adjacent sets of pixels in the 2D video frame) and such that they have a first individual pixel of the first block and a second individual pixel of the second block (the two individual pixels are adjacent pixels in 360 video space). The identified group of blocks (e.g., including blocks on opposite sides of a boundary) may be encoded based on encoding information from adjacent sets of pixels. Such a technique may be repeated row by row for any or all blocks that are non-adjacent in the 2D video frame but are adjacent blocks in 360 video space to produce an encoded video frame based on individual 2D video frames.

[0172] Such block selection, matching and / or coding component prediction techniques may be implemented in any suitable encoding, decoding, video pre-processing or video post-processing context. For example, such techniques may be applied within a local encoding loop of a video encoder as pre-processing before providing a video frame to an encoder, as post-decoder processing, and the like, as further discussed herein. In addition, the discussed techniques may be used in any suitable decoding context, such as in implementations of a codec based on the H.264 / MPEG-4 Advanced Video Coding (AVC) standard, a codec based on the High Efficiency Video Coding (H.265 / HEVC) standard, a proposed video coding (H.266) codec, a codec based on the Alliance for Open Media (AOM) standard (e.g., the AV1 standard), a codec based on an MPEG standard (e.g., the MPEG-4 standard), a codec based on the VP9 standard, or any other suitable codec or extension or profile thereof. The discussed techniques reduce blocky artifacts of the decoded video displayed to the user and provide an improved 360 video experience.

[0173] Figure 7C 7 is a schematic diagram of an embodiment of a system 740 for processing 2D video frames projected from a 360 video space. The system 740 may include a 360 video source 741, a 360 to 2D projector 742, a decoder 743, a viewport generator 747, and a display 748. For example, the decoder 743 may include an encoding component predictor 744, which may further include a block selector 745 and a predictor 746.

[0174] In some embodiments, the decoder 743 may receive 2D video frames (e.g., 2D video frames projected from 360 or spherical space) from the 360-to-2D projector 742, and the decoder 743 may generate a corresponding output bitstream. Although the decoder 743 receives 2D video frames from the 360-to-2D projector 742 for display, the decoder 743 may receive 2D video frames from any suitable source (e.g., memory, another device, etc.). In some embodiments, the decoder 743 may provide encoder capabilities for the system 740. The 360 ​​video source 741 may include a suitable camera or a group of cameras that can obtain 360 video or spherical video, etc. In addition, the 360-to-2D projector 742 may receive 360 ​​video, and the 360-to-2D projector 742 may use any suitable one or more techniques to generate 2D video frames. For example, the 360 ​​to 2D projector 742 may project the 360 ​​video into 2D video frames in any suitable 2D format representing the projection from the 360 ​​video.

[0175] Other modules or components of the system 740 may also receive 2D video frames or portions thereof as needed. The system 740 may provide, for example, video compression, and the system 740 may be a video encoder implemented via a computer or computing device, etc. For example, the system 740 may generate an output bitstream that is compatible with a video compression-decompression (codec) standard such as the H.264 / MPEG-4 Advanced Video Coding (AVC) standard, the High Efficiency Video Coding (H.265 / HEVC) standard, the proposed video coding (H.266) standard, the VP8 standard, the VP9 standard, etc.

[0176] In some embodiments, the decoder 743 may receive an input bitstream that corresponds to or represents a 2D frame projected from 360 or spherical space, and the decoder 743 may generate a corresponding 2D video frame (e.g., such that the 2D frame is projected from 360 or spherical space). The input bitstream may also be received from a memory, another device, or the like. In some embodiments, the decoder 743 may provide decoder capabilities for the system 740. In some embodiments, the input bitstream may be decoded into a 2D video frame, which may be displayed to a user via a display 748 based on a selected viewport within the 2D video frame. The display 748 may be any suitable display, such as a virtual reality (VR) display, a head-mounted VR display, or the like.

[0177] Furthermore, while shown as having all of the 360 ​​video source 741, 360 to 2D projector 742, decoder 743, viewport generator 747, and display 748, the system 740 may include only some of these components. Various combinations of these components and other components may be provided for the system 740, depending on the nature of the device(s) implementing the system 740. The system 740 may be implemented via any suitable device(s), such as, for example, a server, a personal computer, a laptop, a tablet computer, a phablet, a smartphone, a digital camera, a game console, a wearable device, a display device, an all-in-one device, a two-in-one device, etc. or a flat (e.g., a mobile platform, etc.). For example, as used herein, a system, device, computer, or computing device may include any such device or platform.

[0178] As discussed, the decoder 743 may receive a 2D video frame. A 2D video frame (as well as other video frames discussed herein) may include any suitable video data at any suitable resolution, such as pixels or pixel values ​​or data, video sequences, pictures of video sequences, video frames, video pictures, a series of video frames, a group of pictures, multiple groups of pictures, video data, etc. A 2D video frame may be characterized by video, input video data, video data, raw video, etc. For example, a 2D video frame may be a video graphics array (VGA), high definition (HD), full high definition (e.g., 1080p) or 4K resolution video, etc. In addition, a 2D video frame may include any number of video frames, video frame sequences, pictures, multiple groups of pictures, etc. For clarity of presentation, the techniques discussed herein are discussed with respect to pixels and pixel values ​​of video frames. However, such video frames and / or video data may be characterized by pictures, video pictures, frames, frame sequences, video sequences, etc. As used herein, the term pixel or pixel value may include a value representing a pixel of a video frame, such as a brightness value of a pixel, a color channel value of a pixel, etc. In various examples, the 2D video frame may include original video or decoded video.Furthermore, as discussed herein, the decoder 743 may provide both encoding and decoding functions.

[0179] In some embodiments, the encoding component predictor 744 may receive a 2D video frame that includes a projection from a 360 video space. As used herein, the term projection from a 360 video space may indicate that the format of the 2D video frame may include picture or video information corresponding to a 360 space, a spherical space, and the like. For example, a 360 video may be formatted or projected to a 2D image or video frame plane, and the like, using known techniques. Such a projection (and its various advantages and disadvantages) may be similar to, for example, generating a 2D map from a globe. The format of such a 2D video frame may include any suitable format, such as, for example, an equirectangular projection (ERP) format, a cube map format, a compact cube map format, and the like.

[0180] The block selector 745 may select several groups of blocks for coding component prediction (e.g., for some or all of the 2D video frame). The block selector 745 may use any suitable one or more techniques to select such several groups of blocks for coding component prediction. In some embodiments, the block selector 745 may receive one or more indicators indicating the format type of the 2D video frame (e.g., an equirectangular format, a cube mapping format, a compact cube mapping format, etc.), and the block selector 745 may determine which groups of blocks to select for coding component prediction in response to the one or more format type indicators. Each of such a group of blocks selected for coding component prediction may include a first group of blocks and a second group of blocks, such that the first group of blocks and the second group of blocks are non-adjacent in the 2D video frame but adjacent in the 360 ​​video space. In addition, such a first group of blocks and a second group of blocks may be separated by a boundary, and coding component prediction may be applied across the boundary. The boundary may be provided by a frame boundary of a 2D video frame, a surface boundary of a projected portion of a 2D video frame, and the like. For example, the two groups of blocks may be selected and oriented / aligned for coding component prediction. As Figure 7C As shown in , such coding component prediction may be applied by predictor 746 of coding component predictor 744. The predicted coding component may be used by decoder 743 as part of encoding, decoding, pre-processing, or post-processing, as discussed further herein.

[0181] Fig.7D An example 2D video frame 750 (including a projection from a 360 video space in an ERP format) and a viewport 751 overlaying the 2D video frame 750, arranged in accordance with at least some embodiments, is shown. The 2D video frame 750 may include a projection of a 360 video in an ERP format. For example, the ERP format may project a spherical 3D image or frame onto orthogonal coordinates of a 2D image or frame. The viewport 751 may be applied with respect to the 2D video frame 750 (e.g., by the viewport generator 747) so that a user may expect to view a video corresponding to the viewport 751. The viewport 751 may surround the 2D video frame 750 so that a portion 752 of the viewport 751 is on the right side of the 2D video frame 750 and another portion 753 of the viewport 751 is on the left side of the 2D video frame 750. For example, to obtain video data of viewport 751 for presentation, portion 753 of viewport 751 must be obtained from the left side of 2D video frame 750, which overextends frame boundary 754 of 2D video frame 750. For example, assembled viewport 751 including portions 752, 753 may be presented to the user.

[0182] Fig. 7EAn embodiment of a coding component prediction arrangement within a viewport 751 is shown. To perform coding component prediction for block B5, a group of blocks B1 to B4 and B6 to B9 may be identified as neighbors of block B5. For example, blocks B3, B6, and B9 may be neighbors of block B5 in 360 video space but not in a corresponding 2D video frame projection. For example, the viewport 751 provides a continuous viewing angle in the 360 ​​video space. In addition, blocks B5 and B6 may include discontinuous, non-adjacent pixels in the 2D video frame 750 because block B5 is from the right side of the 2D video frame 750 and block B6 is from the left side of the 2D video frame 750 (see, for example, FIG. 2 ). Fig.7D ). For example, blocks B5 and B6 may be separated by boundary 754, such that boundary 754 separates blocks that are not adjacent in 2D video frame space but are adjacent in 360 or spherical space.

[0183] In a processing order from left to right and from top to bottom, blocks B1 to B4 may be encoded before B5. For other processing orders, other subsets of neighboring blocks may be processed before the currently processed block. The block selector 745 may select a subset of neighboring blocks that make previously encoded / processed information available, and provide those blocks or the information to the predictor 746. Advantageously, the subset of neighboring blocks provided to the predictor 746 may provide more encoding information to the predictor 746 for improved prediction (e.g., and / or for improving video decoding efficiency, etc.). In this example, the subset of neighbors with encoding information useful for block B5 may include 2D frame neighboring blocks B1, B2 and B4 and also neighboring block B3 from 360 space. The predictor 746 may align the blocks (e.g., place them in row or column order) or otherwise rotate and / or reorder the blocks so that 3D video space neighboring blocks may be positioned close to or near each other when necessary for performing coding component prediction.

[0184] As discussed with respect to system 740, a group of blocks B1 to B4 may be selected by block selector 745, may be aligned by block selector 745 relative to block B5 for coding component prediction, and have coding components that are predicted by predictor 746 to produce predicted coding components or parameter values, etc. for block B5. Coding component prediction may be performed for any suitable coding / processing information, including motion vector information, mode information, etc. For motion vector prediction, predictive neighboring blocks may include blocks that have been encoded in the raster direction. For left-to-right and top-to-bottom scanning, motion vector prediction for the current block may use motion vector information from previously encoded neighboring blocks that are above and to the left of the current block. Advantageously, some embodiments may increase the number of predictive neighboring blocks by including neighboring blocks from 3D space.

[0185] refer to Fig.7D, additional groups of blocks may be selected across the boundary 754 so that a group of blocks includes blocks from the right side of the 2D video frame 750 (e.g., adjacent to the right boundary or edge of the 2D video frame 750) and blocks from the left side of the 2D video frame 750 (e.g., adjacent to the left boundary or edge of the 2D video frame 750), respectively. For example, in the equirectangular format, all leftmost pixels and corresponding rightmost pixels of the 2D video frame 750 are adjacent in the 360 ​​video space, but are non-adjacent (non-contiguous) in the 2D video frame 750. The coded component prediction may be extended for some or all groups of blocks including blocks from the left and right sides of the 2D video frame 750.

[0186] Figure 7F An embodiment of a 2D video frame 760 is shown, the 2D video frame including selected blocks arranged for coding component prediction. The 2D video frame 760 may include a projection of a 360 video in an equirectangular format. The selected blocks may include a first group of blocks G1 and a second group of blocks G2, which are selected for coding component prediction. For example, for coding component prediction, block 761 may be aligned to the right of block 762, and coding component prediction may be performed. Group G2 may include block 763 and block 764, such that for coding component prediction, block 763 may be inverted and aligned to the top of block 764 (or vice versa), and coding component prediction may be performed.

[0187] Blocks 761 and 762 are not adjacent in 2D video frame 760 (e.g., no pixels in block 761 are continuous or adjacent to any pixels in block 762 in 2D video frame 760). However, in 360 video space, pixels of block 761 at frame boundary 766 are neighbors of pixels of block 762 at frame boundary 767. In addition, blocks 761, 762 may be separated by an equal distance (d2) from bottom frame boundary 769 (and top frame boundary 768). Figure 7F , in the equirectangular format, for any block adjacent to the left frame boundary 766, a corresponding block adjacent to the right frame boundary 767 (equally spaced from the bottom frame boundary 769 or the top frame boundary 768) can be found, such that groups of blocks are non-adjacent in the 2D video frame 760 but are adjacent in the 360 ​​video space. Similar determinations can be made to identify Fig. 7E A set of neighboring blocks corresponding to a set of neighboring blocks B1 to B9 in . The identified neighboring blocks can also be used for coding component prediction.

[0188] Group G2 may include block 763 and block 764 for coding component prediction. For example, to perform coding component prediction, block 763 may be inverted and aligned to the top of block 764 (or block 764 may be inverted and aligned to the top of block 763), and coding component prediction may be performed. Block 763 and block 764 are non-adjacent in 2D video frame 760, and they may be neighbors in 360 video space. For example, blocks 763 and 764 may be equidistant from center line 765 of 2D video frame 760 (i.e., both are separated by a distance d1). For any block adjacent to top frame boundary 768 (except for pixels exactly on center line 765, if any), a corresponding block may be found that is also adjacent to top frame boundary 768 and is equidistant to center line 765, so that these blocks are non-adjacent in 2D video frame 760 but adjacent in 360 video space. Similarly, for any block adjacent to the bottom frame boundary 769, a corresponding block can be found that is also adjacent to the bottom frame boundary 769 and is equidistant from the center line 765, such that these blocks are non-adjacent in the 2D video frame 760 but are adjacent in the 360 ​​video space. Similar determinations can be made to identify blocks that are adjacent to the bottom frame boundary 769. Fig. 7E A set of neighboring blocks corresponding to a set of neighboring blocks B1 to B9 in . The identified neighboring blocks can also be used for coding component prediction.

[0189] The block selection and coding component prediction techniques described for a 2D video frame (which is a projection from a 360 video space) may be performed for any format of projection. For example, the 2D video frame may be an equirectangular frame projected from a 360 video space (e.g., FIG. 7D to FIG. 7F and elsewhere in this paper), cubemap formats projected from 360 video space (as discussed in Figure 7G and elsewhere in this paper), compact cubemap formats projected from 360 video space (as discussed in Fig.7I and discussed elsewhere herein), mapped to environments of any shape, geometric meshes of any 3D shape, etc. For example, a cube map format may project a 360 video space onto the sides of a cube, which may be unfolded or arranged in a 2D video frame.

[0190] Figure 7GAn embodiment of a 2D video frame 770 is shown, which includes projections from a 360 video space in a cube map format and blocks selected for coding component prediction. For example, a group of blocks G3 may include blocks 771 and blocks 772, which may be aligned for coding component prediction. A group of blocks G4 may include blocks 773 and blocks 774, which may be rotated and aligned as needed for coding component prediction. As discussed herein, other combinations of blocks may be identified as neighbors and aligned into several groups of blocks for coding component prediction. The 2D video frame 770 may include a left frame boundary 776, a right frame boundary 777, a top frame boundary 778, and a bottom frame boundary 779. In addition, the 2D video frame 770 may include blank pixel areas R1, R2, which are shown as hatched lines in the 2D video frame 770 but may include any suitable color or pixel value (e.g., black). Blocks 771 and 772 may be identified as neighbors in 360 video space because they may be separated by an equal distance (d1) from bottom frame boundary 779 (and top frame boundary 778). Blocks 773 and 774 may be identified as neighbors in 360 video space because they may be equidistant from the corners of face C and face B (i.e., both are separated by a distance d2). Similar determinations may be made to identify neighbors with respect to face C and face B. Fig. 7E A set of neighboring blocks corresponding to a set of neighboring blocks B1 to B9 in . The identified neighboring blocks can also be used for coding component prediction.

[0191] Figure 7H An embodiment of a cube 780 for receiving projections from a 3D video space is shown. The cube 780 may have six faces (labeled A through F, such that A is the back, B is the front, C is the top, D is the bottom, E is the right side, and F is the left side). For example, a 3D video (e.g., a frame or picture) may be projected onto the cube 780 such that each face of the cube 780 includes a portion of the 3D video or sphere. Figure 7G In a cube map format, each face of the cube 780 may be spread across the 2D video frame 770 in a border-connected manner. For example, the 2D video frame 770 may include a geometric mesh of cubes 780. Although shown as having faces in a side-T format, any suitable format may be used, such as described below with reference to Fig.7I The compact cube format is discussed further.

[0192] like Figure 7HAs shown in , block 773 and block 774 may be connected at the boundary between faces B and C relative to cube 780. For example, pixels of block 773 at the boundary and pixels of block 774 at the boundary are adjacent pixels projected onto cube 780 in 3D video space. As discussed further below, group G4 including block 773 and block 774 may be selected for coding component prediction. Similarly, corresponding groups of blocks that share boundaries between adjacent faces may be selected for coding component prediction. For example, such groups of blocks may be formed between: a shared boundary between faces C and face B, a shared boundary between faces C and face E, a shared boundary between faces A and face F (as discussed with respect to Figure 7G ), and so on.

[0193] With respect to faces A through F, each face may have a left boundary, a right boundary, a top boundary, and a bottom boundary. Such boundaries may be shared with another face, a blank pixel region, or a frame boundary as shown. Figure 7H As discussed, several groups of blocks at right angles to the following surface boundaries may be selected / matched and rotated / aligned for coding component prediction: the top boundary of surface B and the right boundary of surface C, the bottom boundary of surface B and the right boundary of surface D, the top boundary of surface E and the top boundary of surface C, the bottom boundary of surface E and the bottom boundary of surface D, the top boundary of surface A and the left boundary of surface C, the right boundary of surface A and the left boundary of surface F, and the bottom boundary of surface A and the left boundary of surface D.

[0194] Fig.7I An embodiment of a 2D video frame 790 is shown, which may include a projection from a 360 video space in a compact cube map format and several groups of blocks G5, G6 selected for coding component prediction. For example, group G5 may include blocks 791 and 792, which may be rotated and / or aligned for coding component prediction. Group G6 may include blocks 793 and 794, which may also be rotated and / or aligned for coding component prediction. Other combinations of blocks may also be aligned into several groups of blocks for coding component prediction. For example, any group of blocks having blocks that share boundaries between adjacent faces may be selected for coding component prediction.

[0195] refer to Figure 7H and Fig.7I , in a compact cube map format, each face of a cube 780 may be provided within a 2D video frame 790 as shown. Figure 7G , faces A, B, E and F may have the same alignment, while faces C' and D' may be rotated 180°. Although shown in a particular compact cube format, any suitable format may be used for prediction from 360 video space.

[0196] 2D video frame 790 includes left frame boundary 796, right frame boundary 797, top frame boundary 798 and bottom frame boundary 799. In addition, as shown with respect to planes A, B, C', D', E, F, each plane may have a left plane boundary, a right plane boundary, a top plane boundary and a bottom plane boundary. Such boundaries may be shared with another plane or frame boundary as shown. For example, blocks at right angles to the following plane boundaries may be selected / matched and rotated / aligned for coding component prediction: top boundary of plane B with left boundary of plane C', bottom boundary of plane B with left boundary of plane D', top boundary of plane E with bottom boundary of plane C', bottom boundary of plane E with top boundary of plane D', top boundary of plane A with right boundary of plane C', right boundary of plane A with left boundary of plane F, bottom boundary of plane A with right boundary of plane D'.

[0197] Block 791 and block 792 are non-adjacent in 2D video frame 790, but are adjacent in 360 video space (e.g., based on the left boundary of surface D' being shared with the bottom boundary of surface B). Block 793 and block 794 are non-adjacent in 2D video frame 790, but are adjacent in 360 video space (e.g., based on the top boundary of surface B being shared with the left boundary of surface C'). Similar determinations may be made to identify Fig. 7E A set of neighboring blocks corresponding to a set of neighboring blocks B1 to B9 in . The identified neighboring blocks can also be used for coding component prediction.

[0198] As discussed, the block selection and coding component prediction techniques discussed herein may be used in any suitable 3D video encoding, decoding, pre-processing, or post-processing context.

[0199] Prioritizer Example

[0200] Now turn to Fig. 8A, embodiments of the graphics device 800 may include: a region identifier 821 for identifying a region of interest in a 2D frame, wherein the 2D frame corresponds to a projection of a 360 video; and a prioritizer 822, communicatively coupled to the region identifier 821 to prioritize the transmission of packets of the 2D frame based on the identified region of interest. For example, the region of interest may be identified as corresponding to a user-selected viewport. In some embodiments, the prioritizer 822 may also be configured to prioritize the encoding of one or more blocks of the 2D frame based on the identified region of interest. Some embodiments of the device 800 may also include: an encoder 823, communicatively coupled to the prioritizer 822 to encode the prioritized one or more blocks of the 2D frame; a packetizer 824, communicatively coupled to the encoder 823 to assemble prioritized packets from the encoded prioritized one or more blocks of the 2D frame; and / or a transmitter 825, communicatively coupled to the packetizer 824 to transmit the prioritized packets.

[0201] In some embodiments, the device 800 may further include any of the following: a format detector, communicatively coupled to the encoder 823 to detect the 360 ​​video format of the 2D frame based on the image content of the 2D frame; and / or a 360 video capture device, communicatively coupled to the encoder 823 to capture the 360 ​​video content and having a context tagger, which is communicatively coupled to the 360 ​​video capture device to annotate the 360 ​​video content using context information contemporary with the captured 360 video content.

[0202] The above embodiments of each of the region identifier 821, the prioritizer 822, the encoder 823, the packer 824, the transmitter 825 and other components of the device 800 can be implemented in hardware, software or any combination thereof. For example, the hardware implementation may include configurable logic (such as, for example, PLA, FPGA, CPLD), or in fixed-function logic hardware using circuit technology (such as, for example, ASIC, CMOS or TTL technology), or any combination of the above two situations. Alternatively or in addition, these components can be implemented as a set of logical instructions in one or more modules, and the logical instructions are stored in a machine-readable or computer-readable storage medium (such as RAM, ROM, PROM, firmware, flash memory, etc.) to be executed by a processor or computing device. For example, the computer program code for implementing the operation of these components can be written in any combination of one or more operating system applicable / suitable programming languages ​​(including object-oriented programming languages ​​such as PYTHON, PERL, JAVA, SMALLTALK, C++, C#, etc.) and conventional program programming languages ​​(such as "C" programming language or similar programming languages).

[0203] Now turn to Figure 8B , an embodiment of the method 830 for processing 360 video may include: identifying a region of interest in a 2D frame at block 831, wherein the 2D frame corresponds to a projection of the 360 ​​video; and prioritizing the transmission of packets of the 2D frame based on the identified region of interest at block 832. The method 830 may also include: prioritizing the encoding of one or more blocks of the 2D frame based on the identified region of interest at block 833. In some embodiments, the method 830 may further include any of the following: encoding the prioritized one or more blocks of the 2D frame at block 834; assembling the prioritized packets from the encoded prioritized one or more blocks of the 2D frame at block 835; and transmitting the prioritized packets at block 836. In some embodiments, the region of interest may be identified as corresponding to a user-selected viewport.

[0204] Embodiments of method 830 may be implemented using a system, device, GPU, or parallel processing unit (PPU) (such as, for example, each of the above described herein). More specifically, the hardware implementation of method 830 may include configurable logic (such as, for example, PLA, FPGA, CPLD), or in fixed-function logic hardware using circuit technology (such as, for example, ASIC, CMOS, or TTL technology), or any combination of the above two situations. Alternatively or in addition, method 830 may be implemented as a set of logic instructions in one or more modules, which are stored in a machine-readable or computer-readable storage medium (such as RAM, ROM, PROM, firmware, flash memory, etc.) to be executed by a processor or computing device. For example, the computer program code for implementing the operation of these components can be written in any combination of one or more operating system applicable / suitable programming languages ​​(including object-oriented programming languages ​​such as PYTHON, PERL, JAVA, SMALLTALK, C++, C#, etc.) and conventional program programming languages ​​(such as, "C" programming language or similar programming languages). For example, method 830 may be implemented on a computer-readable medium as described below in conjunction with Examples 36-39.

[0205] For example, application or driver software may be employed to implement various embodiments or portions of method 830 (e.g., via an API). Other embodiments or portions of method 830 may be implemented using specialized code (e.g., shaders) to be executed on a GPU. Other embodiments or portions of method 830 may be implemented using fixed-function logic or specialized hardware (e.g., in a GPU).

[0206] Advantageously, some embodiments may reorder 360 video packets for low latency viewing. For example, based on the viewer's viewpoint, packets belonging to a region of interest (ROI) may be encoded and transmitted before the rest of the packets (e.g., the packets have been reordered compared to traditional raster scan order). Some embodiments may be used for offline encoding and / or on-the-fly encoding.

[0207] Now turn to Figure 8C , the 360 ​​video 840 can be viewed by the user. When viewing the 360 ​​video 840, the user views a portion of the 360 ​​video 840 (sometimes referred to as a viewport 842). For example, the user can manually select the viewport 842 (e.g., with cursor keys, mouse movement, touch screen gestures such as sliding, etc.). With a suitably configured headset, the user can select the viewport 842 by moving their head or body (e.g., or using gestures or eye tracking). In the 2D frame, the user can see the mountain portion of the 360 ​​video 840. To see the sun, the user can move their head and then see a portion of the 360 ​​video 840 in the 2D frame. Regardless of the method used by the user to select the viewport, the viewport information can then be communicated to the graphics system as a region of interest to process the video and display the viewport to the user.

[0208] Now turn to Fig.8D , in some cases, the complete 360 ​​video 840 may be sent to the viewing device. In other cases, only a portion 844 of the 360 ​​video 840 may be sent (e.g., the viewport 842, or the viewport 842 plus a certain overdrawn portion). The traditional raster scan order may start at the upper left of the 360 ​​video for encoding and transmitting the 360 ​​video horizontally and processing the 360 ​​video in sequence, line by line. Some embodiments may advantageously prioritize the region of interest corresponding to the viewport 842, and reorder the encoding and / or transmission of the packets in the region of interest. For example, the graphics system may first transmit packet 851, and then proceed from left to right for each row of packets in the region of interest. After the last packet 853 in the region of interest is transmitted, the graphics system may continue to transmit in a raster scan order (starting from the upper left packet 855 and continuing to the last packet 857). The graphics system may skip previously transmitted packets 851 to 853, or may retransmit these packets.

[0209] Now turn to Fig. 8E, in some embodiments, the graphics system may reorder the scan by selecting a starting row 861 corresponding to the top row of the region of interest, and then continuing from left to right for each row. For example, row 863 may continue after row 861, and continue to the bottom row 865. Top row 867 may continue after bottom row 865, and continue to the last row 869. Advantageously, the earlier the region of interest is emitted, the better, so that it will only have minor changes to the encoding and / or emission logic for traditional raster scanning. Some embodiments may fully encode the 360 ​​video and only apply prioritization / reordering to the emission based on the identified region of interest. Some embodiments may also prioritize and / or reorder encoding based on the region of interest.

[0210] For network transmission (including cloud services), a large amount of bandwidth may be required to send a full 360 video. Some embodiments may prioritize the encoding / transmission of a head-mounted display (HMD) based on the region of interest. For example, based on the orientation of the HMD, the system may prioritize the encoding / transmission to process blocks in that area first. The system may encode one block at a time and may include multiple encoded blocks in a packet. The viewing area may be encoded and sent over the network first, while other parts may be encoded and sent later in regular raster order. In some embodiments, if sending later packets causes too much latency, then these later packets may be skipped or discarded. For example, if packets begin to be discarded, then some embodiments may restart drawing at the region of interest. Some embodiments may cut the packets into a desired order and provide slice-based encoding.

[0211] Format Detector Example

[0212] Now turn to Fig.9A, an embodiment of the graphics device 900 may include: a decoder 921 for decoding a 2D frame, wherein the 2D frame corresponds to a projection of a 360 video; a format detector 922, communicatively coupled to the decoder 921 to detect the format of the 360 ​​video based on the image content of the 2D frame; and a mapper 923, communicatively coupled to the decoder 921 and the format detector 922 to map the decoded 2D frame based on the detected 360 video format. For example, the format detector 922 may be configured to detect a fisheye format based on an identified blank area of ​​the 2D frame, wherein the identified blank area is outside an identified non-blank circular area of ​​the 2D frame. The format detector 922 may be further configured to detect an equirectangular projection format based on one or more of an identified warping near a 2D frame pole, an identified discontinuity at an edge of the 2D frame, and an identified object segmentation between a left edge and a right edge of the 2D frame. The format detector 922 may also be configured to detect a cube map format based on one or more of an identified blank rectangular area of ​​the 2D frame and an identified T-shape of a non-blank area of ​​the 2D frame. For example, the format detector 922 may detect a packed cube map format based on one or more of an identified number of edges in the 2D frame, an identified commonality among edges in the 2D frame, and an identified discontinuity along an edge of the 2D frame.

[0213] In some embodiments, the apparatus 900 may further include a 360 video capture device communicatively coupled to the decoder 921 to capture 360 ​​video content and having a context tagger communicatively coupled to the 360 ​​video capture device to tag the 360 ​​video content with contextual information contemporary with the captured 360 video content.

[0214] The embodiments of each of the above decoder 921, format detector 922, mapper 923 and other components of device 900 can be implemented in hardware, software or any combination thereof. For example, the hardware implementation may include configurable logic (such as, for example, PLA, FPGA, CPLD), or in fixed-function logic hardware using circuit technology (such as, for example, ASIC, CMOS or TTL technology), or any combination of the above two situations. Alternatively or in addition, these components can be implemented as a set of logic instructions in one or more modules, and the logic instructions are stored in a machine-readable or computer-readable storage medium (such as, RAM, ROM, PROM, firmware, flash memory, etc.) to be executed by a processor or computing device. For example, the computer program code for implementing the operation of these components can be written in any combination of one or more operating systems applicable / suitable programming languages ​​(including object-oriented programming languages ​​such as PYTHON, PERL, JAVA, SMALLTALK, C++, C#, etc.) and conventional program programming languages ​​(such as, "C" programming language or similar programming languages).

[0215] Now turn to Fig. 9B , an embodiment of the method 930 for processing a 360 video may include: at box 931, decoding a 2D frame, wherein the 2D frame corresponds to a projection of the 360 ​​video; at box 932, detecting a format of the 360 ​​video based on image content of the 2D frame; and at box 933, mapping the decoded 2D frame based on the detected 360 video format. For example, method 930 may include any of the following: at box 934, detecting a fisheye format based on an identified blank area of ​​the 2D frame, wherein the identified blank area is outside an identified non-blank circular area of ​​the 2D frame; at box 935, detecting an equirectangular projection format based on one or more of an identified deformation near the poles of the 2D frame, an identified discontinuity at the edge of the 2D frame, and an identified object segmentation between the left edge and the right edge of the 2D frame; at box 936, detecting a cube map format based on one or more of an identified blank rectangular area of ​​the 2D frame and an identified T-shape of the non-blank area of ​​the 2D frame; and / or at box 937, detecting a packed cube map format based on one or more of an identified number of edges in the 2D frame, an identified commonality among the edges in the 2D frame, and an identified discontinuity along the edge of the 2D frame.

[0216] The embodiment system of method 930 can be implemented using a device, GPU or parallel processing unit (PPU) (such as, for example, the above described herein). More specifically, the hardware implementation of method 930 may include configurable logic (such as, for example, PLA, FPGA, CPLD), or in fixed-function logic hardware using circuit technology (such as, for example, ASIC, CMOS or TTL technology), or any combination of the above two situations. Alternatively or in addition, method 930 can be implemented as a set of logic instructions in one or more modules, and the logic instructions are stored in a machine-readable or computer-readable storage medium (such as RAM, ROM, PROM, firmware, flash memory, etc.) to be executed by a processor or computing device. For example, the computer program code for implementing the operation of these components can be written in any combination of one or more operating system applicable / suitable programming languages ​​(including object-oriented programming languages ​​such as PYTHON, PERL, JAVA, SMALLTALK, C++, C#, etc.) and conventional program programming languages ​​(such as "C" programming language or similar programming languages). For example, method 930 may be implemented on a computer-readable medium as described below in conjunction with Examples 55-59.

[0217] For example, application or driver software may be employed to implement various embodiments or portions of method 930 (e.g., via an API). Other embodiments or portions of method 930 may be implemented using specialized code (e.g., shaders) to be executed on a GPU. Other embodiments or portions of method 930 may be implemented using fixed-function logic or specialized hardware (e.g., in a GPU).

[0218] Some embodiments may advantageously provide automatic detection of 360 video projection formats. When a 360 video is provided for viewing, it may include or be accompanied by metadata or tags that can identify the format of the 360 ​​video. Non-limiting example formats may include fisheye formats, ERP formats, cube map formats, and compact cube map formats. However, metadata or tags may sometimes not be provided, may not be recognized, or may be incorrect. Some embodiments may perform image processing on the image content itself to detect the format of the 360 ​​video. For example, a format detector may be included in an encoder to detect and / or correct the type of 360 video to achieve correct encoding. The format detector may analyze pixel data to detect the format of the 360 ​​video. The content and the detected information may be provided to a mapper for mapping and viewpoint generation of a viewport based on the determined format.

[0219] Now turn to Fig. 9C, an embodiment of a 2D frame 940 may include a projection from a 360 video having a fisheye format. The fisheye format may be characterized by active content in a circle 941 surrounded by an inactive background 942. To automatically detect fisheye, a format detector may analyze the pixel data to detect a circle surrounded by black (e.g., using image processing).

[0220] Now turn to Fig.9D , an embodiment of a 2D frame 945 may include a projection from a 360 video having an ERP format. The ERP format may be characterized by object 946 or scene segmentation across the left and right edges of the frame and / or deformations at the image poles (e.g., see line 947). The poles may correspond to the top and bottom center areas of the 2D frame. To automatically detect the ERP format, the format detector may analyze the pixel data to identify straight lines at the poles, which become curved during the distortion mapping process. To identify objects or scenes that may be segmented across the left and right edges, the format detector may analyze the pixel data near those edges. If a significant amount of pixel data from the left is vertically correlated with pixel data from the right, then this may indicate that the scene is segmented across those edges. In some embodiments, a weighted value may be determined to represent how many of the pixels from the left are vertically correlated with the pixels from the right.

[0221] Now turn to Fig.9E , an embodiment of 2D frame 960 may include a projection from a 360 video in a cube map format having cube faces A through F. The cube map format may be characterized by one or more blank rectangular or box-shaped regions (e.g., regions R1 through R4). To automatically detect the cube map format, a format detector may analyze the pixel data to identify those blank regions.

[0222] Now turn to Fig.9F, an embodiment of the 2D frame 965 may include a projection from a 360 video in a packed cube map format (e.g., sometimes also referred to as a compact cube map format) having cube faces A to F. The packed cube map format may be characterized by discontinuities along edges, where a face is moved and not in its original continuous position. To automatically detect the packed cube map format, a format detector may analyze the pixel data to identify edges with 90 degree angles corresponding to the outline of a cube face. For example, if a change in pixel data occurs along a line, then the line may be identified as an edge of a cube face. Those lines that cross or intersect at a 90 degree angle may identify the outline of a cube face. Some embodiments may align the cube map projection based on the size of the 2D frame to identify candidate edges and find matches. Some embodiments may look for similarities across all possible pairs and try to minimize them. For a packed or compact cube map format, the format detector may also look for edge commonality (edge ​​matching) or continuity across blocks. Additionally or alternatively, some embodiments may look for discontinuities along edges (edge ​​mismatches) or discontinuities across blocks.

[0223] For either the cube map format or the packed cube map format, the faces in the 2D frame may need to be identified relative to their original positions in the 360 ​​video space for subsequent correct processing. For the cube map format, identifying the original positions can be relatively straightforward because each face retains at least one original continuous edge (e.g., see Figure 7G and Fig.9E ). For the packed cubemap format, the original positions can be rearranged. For example, in Fig.9F In the example above, faces C, D, and E may all be contiguous, but faces A, B, and F may have been moved. There may be a variety of ways to pack a 2D frame, and individual blocks may occupy other locations in the packed frame. For a packed cube map format, a format detector may first determine the format, and then may determine the correct mapping (e.g., which faces are A, B, C, D, E, and F). For example, the format detector may analyze the pixel data to line up the edges for each face.

[0224] Now turn to Figure 9G, an embodiment of the graphics device 970 may include N format detectors (e.g., where N>0), including a first format detector 971, a second format detector 972, through an Nth format detector 973, which are communicatively coupled to a format selector 974. For example, a 2D frame may be provided to each of the first format detector 971 through the Nth format detector 973, and each format detector may respectively determine whether the 2D frame has a format corresponding to the detector. The format detectors may provide a binary result (true or false), or the format detectors may provide a result indicating a suitable probability (low / medium / high, percentage, weighted value, etc.) that the 2D frame has a format corresponding to the detector. The format selector 974 may receive the results from each of the first format detector 981 through the Nth format detector to select an output value indicating the most likely value for the 2D frame. In some embodiments, metadata or other format identification information from the 2D frame may also be provided to the format selector 974 (e.g., the format selector 974 may take the metadata or other format identification information into account when weighting the various probabilities). For example, format selector 974 may include logic for selecting the most likely format based on the output of each detector. Table 5 shows a sample decision process:

[0225] Table 5 - Format selection logic

[0226] Detector 1 Results Detector 2 Results Detector 3 results Selected format Fake Fake Fake Inconclusive Fake Fake real Format 3 Fake real Fake Format 2 Fake real real Format 2 real Fake Fake Format 1 real Fake real Format 1 real real Fake Format 1 real real real Inconclusive

[0227] Now turn to Figure 9H , a method for detecting a 360 video format may include: at block 981, determining whether a 2D frame has a circular outline; and if so, then fisheye may be selected for the detected format at block 982, and the detected format may be indicated at block 992. If the 2D frame does not have a circular outline at block 981, then the 2D frame may be analyzed at 983 to determine whether the 2D frame has one or more blank square-shaped areas. If so. Then a cube map may be selected for the detected format at block 984, faces of the cube map may be extracted at block 985, and the detected format may be indicated at block 992.

[0228] If there are no empty boxes at block 986, the 2D frame may then be analyzed at block 986 to determine if there are multiple edges with 90 degree angles. If there are edges with 90 degree angles, a packed cube map may be selected for the detected format at block 987, faces may be extracted at block 985, and the detected format may be indicated at block 992. If there are no 90 degree edges at block 986, the 2D frame may be analyzed at block 988 to determine if the scene appears to be segmented across the edge of the frame. If so, an ERP may be selected for the detected format at block 989, and the detected format may be indicated at block 992. Otherwise, the format may be considered at block 991, and an inconclusive format may be indicated at block 992.

[0229] 360 video capture device with contextual tagger example

[0230] Now turn to Fig. 10A , an embodiment of the graphics device 1000 may include: a 360 video capture device 1021 for capturing 360 video content; and a context tagger 1022, communicatively coupled to the 360 ​​video capture device 1021 to tag the 360 ​​video content with context information contemporary with the captured 360 video content. For example, the context information may include one or more of motion information, position information, speed information, acceleration information, orientation information, and direction information. In some embodiments of the device 1000, the context tagger 1022 may be configured to tag the 360 ​​video content with metadata of the context information, and the 360 ​​video capture device 1021 may be configured to encode the captured 360 video content using the metadata.

[0231] The embodiments of each of the above 360 ​​video capture device 1021, context tagger 1022 and other components of the device 1000 can be implemented in hardware, software or any combination thereof. For example, the hardware implementation may include configurable logic (such as, for example, PLA, FPGA, CPLD), or in fixed-function logic hardware using circuit technology (such as, for example, ASIC, CMOS or TTL technology), or any combination of the above two situations. Alternatively or in addition, these components can be implemented as a set of logic instructions in one or more modules, and the logic instructions are stored in a machine-readable or computer-readable storage medium (such as RAM, ROM, PROM, firmware, flash memory, etc.) to be executed by a processor or computing device. For example, the computer program code for implementing the operation of these components can be written in any combination of one or more operating system applicable / suitable programming languages ​​(including object-oriented programming languages ​​such as PYTHON, PERL, JAVA, SMALLTALK, C++, C#, etc.) and conventional program programming languages ​​(such as "C" programming language or similar programming languages).

[0232] Now turn to Fig. 10B , an embodiment of a method 1030 for processing 360 video may include: at block 1031, capturing 360 video content; and at block 1032, annotating the 360 ​​video content with contextual information contemporary with the captured 360 video content. For example, at block 1033, the contextual information may include one or more of motion information, position information, speed information, acceleration information, orientation information, and direction information. In some embodiments, the method 1030 may further include: at block 1034, annotating the 360 ​​video content with metadata of the contextual information; and at block 1035, encoding the captured 360 video content using the metadata.

[0233] Embodiments of method 1030 may be implemented using a system, device, GPU, or parallel processing unit (PPU) (such as, for example, each of the above described herein). More specifically, the hardware implementation of method 1030 may include configurable logic (such as, for example, PLA, FPGA, CPLD), or in fixed-function logic hardware using circuit technology (such as, for example, ASIC, CMOS, or TTL technology), or any combination of the above two situations. Alternatively or in addition, method 1030 may be implemented as a set of logic instructions in one or more modules, which are stored in a machine-readable or computer-readable storage medium (such as RAM, ROM, PROM, firmware, flash memory, etc.) to be executed by a processor or computing device. For example, the computer program code for implementing the operation of these components can be written in any combination of one or more operating system applicable / suitable programming languages ​​(including object-oriented programming languages ​​such as PYTHON, PERL, JAVA, SMALLTALK, C++, C#, etc.) and conventional program programming languages ​​(such as, "C" programming language or similar programming languages). For example, method 1030 may be implemented on a computer-readable medium as described below in conjunction with Examples 73-76.

[0234] For example, application or driver software may be employed to implement various embodiments or portions of method 1030 (e.g., via an API). Other embodiments or portions of method 1030 may be implemented using specialized code (e.g., shaders) to be executed on a GPU. Other embodiments or portions of method 1030 may be implemented using fixed-function logic or specialized hardware (e.g., in a GPU).

[0235] Some embodiments may advantageously add position and orientation information to the 360 ​​video to enhance the experience. Other sensor information may be added at the time of capture, and the 360 ​​video may be embedded with the sensor information. In some embodiments, the information is added while the 360 ​​video is being captured, and the information is encoded with the video data. For example, some embodiments may annotate video frames with one or more of camera position, camera speed, global positioning satellite (GPS) information, and orientation. In some embodiments, each frame may be annotated with the information. In some embodiments, the annotated information may be added every N frames, where N>1. In some embodiments, the annotated information may be added asynchronously (e.g., whenever the information changes). These tags may be used later to enhance the user experience.

[0236] Now turn to Fig. 10C, the 360 ​​video capture device 1040 may include: a processor 1041; a persistent storage medium 1042, communicatively coupled to the processor 1041; a video capture engine 1043, communicatively coupled to the processor 1040; and a sensing engine 1044, communicatively coupled to the video capture engine 1043. For example, the video capture engine 1043 may capture video information from multiple cameras to capture 360 ​​video and record the 360 ​​video frames to the persistent storage medium 1042. During video capture, the sensing engine 1044 may provide additional information (e.g., position, direction, speed, acceleration, orientation, etc.) to the video capture engine 1043, and the capture engine 1043 may add the information as metadata to the recorded 360 video frames. Later during viewing, the information may be extracted to enhance the viewing experience (e.g., a four-dimensional (4D) experience).

[0237] For example, if a 360 video is captured in a car, the car may accelerate during the capture. Device 1040 may capture acceleration information and save it with the 360 ​​video. When the HMD is worn and the video is played back, tactile feedback may be added based on the acceleration information added to the video, for example, during playback. For example, a gaming chair may have a tactile feedback device to enhance the user experience. For example, the chair may move backwards based on acceleration information captured simultaneously with the 360 ​​video, thereby enhancing the user's perception of acceleration. The connected audio system may add sound effects, change the intensity of the sound track, etc. based on metadata added simultaneously. A properly configured gaming chair may bounce the user based on a sudden vertical acceleration. If the added metadata indicates the direction of the camera change, the chair may also rotate to match the camera direction.

[0238] Now turn to Fig. 10D , the 360 ​​video camera 1050 may include a housing 1051, wherein a plurality of cameras 1052 are mounted to the housing 1051, including cameras 1052a, 1052b, 1052c, 1052d, etc. (other cameras are not shown, and more or fewer cameras may be provided in some embodiments). The camera 1050 may be configured in a manner similar to the device 1040 and include a sensing engine 1053. For example, the sensing engine 1053 may include information obtained from sensors, content, services, and / or other sources to provide sensing information. The sensing information may include, for example, image information, audio information, motion information, depth information, temperature information, biometric information, GPU information, etc. When capturing video data, the camera 1050 may encode metadata corresponding to the various sensing information along with one or more of the 360 ​​video data.

[0239] For example, the sensing engine 1053 may include a sensor hub that is communicatively coupled to a two-dimensional (2D) camera, a three-dimensional (3D) camera, a depth camera, a gyroscope, an accelerometer, an inertial measurement unit (IMU), a location service, a microphone, a proximity sensor, a thermometer, a biometric sensor, etc. and / or a combination of multiple sources. The sensor hub may be distributed across multiple devices. Information from the sensor hub may include input data from a user's device, or may be combined with input data from a user's device.

[0240] For example, the user's device(s) may also include a gyroscope, accelerometer, IMU, location services, thermometer, biometric sensors, etc. For example, the user may carry a smartphone (e.g., in the user's pocket) and / or a wearable device (e.g., such as a smart watch, activity monitor, and / or fitness tracker). The user's device(s) may also include a microphone that can be used to detect whether the user is talking, making a phone call, talking to another person nearby, etc. The sensor hub may include interfaces to some or all of the user's various devices (which are capable of capturing information related to the user's actions or activities) (e.g., including input / output (I / O) interfaces of the user's device, which can capture keyboard / mouse / touch activities). The sensor hub may obtain information directly from a capture device in the user's device (e.g., wired or wireless), or the sensor hub may be able to integrate information from a server or service of the device (e.g., information can be uploaded from a fitness tracker to a cloud service so that the sensor hub can download it).

[0241] Display Technology

[0242] Now turn to Fig.11, showing a performance-enhanced computing system 1100. In the example shown, the processor 1110 is coupled to a display 1120. The processor 1110 may generally generate an image to be displayed on an LCD panel 1150 of the display 1120. In one example, the processor 1110 includes a communication interface, such as, for example, a video graphics array (VGA), a display port (DP) interface, an embedded display port (eDP) interface, a high-definition multimedia interface (HDMI), a digital visual interface (DVI), and the like. The processor 1110 may be a graphics processor (e.g., a graphics processing unit / GPU) that processes graphics data and generates an image (e.g., a video frame, a still image) displayed on the LCD panel 1150. In addition, the processor 1110 may include one or more image processing pipelines that generate pixel data. The image processing pipeline may conform to the OPENGL architecture or other suitable architectures. In addition, the processor 1110 may be connected to a host processor (e.g., a central processing unit / CPU), wherein the host processor executes one or more device drivers that control the processor 1100 and / or interact with the processor 1110.

[0243] The illustrated display 1120 includes a timing controller (TCON) 1130 that can address different pixels on an LCD panel 1150 individually and update each individual pixel on the LCD panel 1150 on a refresh cycle by refresh cycle. In this regard, the LCD panel 1150 can include a plurality of liquid crystal elements, such as, for example, liquid crystals and integrated color filters. Each pixel of the LCD panel 1150 can include a triplet of liquid crystal elements having red, green, and blue filters, respectively. The LCD panel 1150 can arrange pixels in a two-dimensional (2D) array that is controlled via a row driver 1152 and a column driver 1154 to update an image being displayed by the LCD panel 1150. Thus, the TCON 1130 can drive the row driver 1152 and the column driver 1154 to address a specific pixel of the LCD panel 1150. The TCON 1130 can also adjust the voltage provided to the liquid crystal element in the pixel to change the light intensity passing through each of the three liquid crystal elements, and thus change the color of the pixel displayed on the surface of the LCD panel 1150.

[0244] The backlight 1160 may include a plurality of light emitting elements, such as, for example, light emitting diodes (LEDs), arranged at the edges of the LCD panel 1150. Accordingly, the light generated by the LEDs may be dispersed through the LCD panel 1150 by a diffuser (not shown). In another example, the LEDs are arranged in a 2D array directly behind the LCD panel 1150 in a configuration that is sometimes referred to as a direct backlight because each LED disperses light through one or more corresponding pixels of the LCD panel 1150 positioned in front of the LED. The light emitting elements may also include compact fluorescent lamps (CFLs) arranged along one or more edges of the LCD panel 1150. To eliminate multiple edges, the combination of edges may be altered to achieve selective illumination of an area, where less than a full set of lighting elements are used with less power.

[0245] The light emitting element may also include one or more sheets of electroluminescent material placed behind the LCD panel 1150. In such cases, light from the surface of the sheet may be dispersed through the pixels of the LCD panel 1150. In addition, the sheet may be divided into multiple regions, such as, for example, quadrants. In one example, each region is individually controlled to illuminate only a portion of the LCD panel 1150. Other backlight solutions may also be used.

[0246] The illustrated display 1120 also includes a backlight controller (BLC) 1140 that provides voltage to the light emitting elements of the backlight 1160. For example, the BLC 1140 may include a pulse width modulation (PWM) driver (not shown) to generate a PWM signal that activates at least a portion of the light emitting elements of the backlight 1160. The duty cycle and frequency of the PWM signal may dim the light generated by the light emitting elements. For example, a 100% duty cycle may correspond to a light emitting element being fully turned on, while a 0% duty cycle may correspond to a light emitting element being fully turned off. Thus, intermediate duty cycles (e.g., 25%, 50%) typically cause the light emitting elements to be turned on for a portion of the cycle that is proportional to the percentage of the duty cycle. The cycle may be fast enough that the flickering of the light emitting elements is not noticeable to the human eye. In addition, the impact on the user may be that the level of light emitted by the backlight 1160 is lower than when the backlight 1160 is fully activated. The BLC 1140 may be separate from the TCON 1130, or may be incorporated into the TCON 1130.

[0247] Alternatively, an emissive display system may be used, where the LCD panel 1150 would be replaced by an emissive display panel (e.g., organic light emitting diode / OLED), the backlight 1160 would be omitted, and the row driver 1152 and column driver 1154 could be used to directly modulate pixel color and brightness, respectively.

[0248] Display resolution based on distance

[0249] Fig. 12A A scenario is shown in which a user 1218 interacts with a data processing device 1200 that includes a display unit 1228. The display processing device 1200 may include, for example, a notebook computer, a desktop computer, a tablet computer, a convertible tablet, a mobile Internet device (MID), a personal digital assistant (PDA), a wearable device (e.g., a head mounted display / HMD), a media player, etc., or any combination of the above. The data processing device 1200 shown includes a processor 1224 (e.g., an embedded controller, a microcontroller, a host processor, a graphics processor) coupled to a memory 1222, which may include storage locations addressable by the processor 1224. As will be discussed in more detail, the distance sensor 1210 can enable a display resolution based on distance relative to the display unit 1228.

[0250] The illustrated memory 1222 includes display data 1226 to be rendered on a display unit 1228. In one example, the processor 1224 performs data conversion on the display data 1226 before presenting the display data 1226 on the display unit 1228. The post-processing engine 1214 may be executed on the processor 1224 to receive the display data 1226 and the output of the distance sensor 1210. The post-processing engine 1214 may modify the display data 1226 to enhance the readability of the screen content on the display unit 1228, reduce power consumption in the data processing device 1200, etc., or may perform any combination of the above operations.

[0251] The memory 1222 is shown storing display resolution settings 1216 in addition to the operating system 1212 and the applications 1220. The display resolution settings 1216 may specify the number of pixels of the display data 1226 to be presented on the display unit 1228 along the length dimension and the width dimension. If the display data 1226 as generated by the applications 1220 is not compatible with the format of the display unit 1228, the processor 1224 may configure the scaling of the display data 1226 to match the format of the display unit 1228. In this regard, the display resolution settings 1216 may be associated with and / or may be incorporated into configuration data defining other settings of the display unit 1228. Furthermore, the display resolution settings 1216 may be defined in terms of unit distance or area (e.g., pixels per inch / PPI) or other suitable parameters.

[0252] The application 1220 can generate a user interface, wherein the user 1218 can interact with the user interface to select the display resolution setting 1216 from one or more options provided through the user interface, enter the display resolution setting 1216 as a requested value, etc. Thus, the display data 1226 can be resized to fit the display resolution setting 1216 before being rendered on the display unit 1228.

[0253] The distance sensor 1210 may track the distance between the user 1218 and the display unit 1228, wherein the distance sensing may be triggered by a physical button associated with the data processing device 1200 / display unit 1228, by a user interface provided by the loading of the application 1220 and / or the operating system 1220, etc. For example, during booting of the data processing device 1200, the operating system 1212 may execute an automatic process to trigger distance sensing in the background or foreground. The distance sensing may be performed periodically or continuously.

[0254] Fig. 12B An example of a distance sensing scenario is shown. In the example shown, the distance sensor 1210 uses a transceiver 1208 to transmit an electromagnetic beam 1202 in the direction of a user 1218. Thus, the transceiver 1202 may be located at a data processing device 1200 ( Fig. 12A ). Electromagnetic beam 1202 may impact user 1218 and may be reflected / scattered from user 1218 as return electromagnetic beam 1204. Return electromagnetic beam 1204 may be processed by, for example, processor 1224 ( Fig. 12A ) and / or post-processing engine 1214 ( Fig. 12A ) analysis to determine that the user 1218 and the display unit 1228 ( Fig. 12A ) between the two images 1206. The distance 1206 can be used to adjust the display resolution setting 1216.

[0255] Display Layer

[0256] Now turn to Fig.13 , a display system 1300 is shown in which cascaded display layers 1361, 1362, and 1363 are used to implement spatial / temporal super-resolution in a display component 1360. In the example shown, the processor 1310 provides raw graphics data 1334 (e.g., video frames, still images) to the system 1300 via a bus 1320. The cascaded display program 1331 can be stored in a memory 1330, where the cascaded display program 1331 can be part of a display driver associated with the display component 1360. The illustrated memory 1330 also includes the raw graphics data 1334 and the decomposed graphics data 1335. In one example, the cascaded display program 1331 includes a temporal decomposition component 1332 and a spatial decomposition component 1333. The temporal decomposition component 1332 can perform temporal decomposition calculations, and the spatial decomposition component can perform spatial decomposition calculations. The cascaded display program 331 may derive decomposed graphics data 1335 for presentation on each display layer 1361 , 1362 , and 1363 based on the user configuration and the original graphics data 1334 .

[0257] The display assembly 1360 may be implemented as an LCD (liquid crystal display) used in, for example, head mounted display (HMD) applications. More specifically, the display assembly 1360 may include a stack of LCD panels, interface boards, lens attachments, etc. Each panel can operate at, for example, a native resolution of 1280*1280 and a refresh rate of 60 Hz. Other native resolutions, refresh rates, display panel technologies, and / or layer configurations may be used.

[0258] Multiple display units

[0259] Fig.14 A graphical display system 1400 is shown that includes a set of display units 1430 (1430a-1430n) that are generally operable to output a widescreen (e.g., panoramic) presentation 1440 that includes coordinated content in a cohesive and structured topological form. In the illustrated example, a data processing device 1418 includes a processor 1415 that applies a logic function 1424 to hardware profile data 1402 received from the set of display units 1430 via a network 1420. When no match is found between the hardware profile data and a set of settings in a hardware profile lookup table 1412, applying the logic function 1424 to the hardware profile data 1402 may create a set of automatic topology settings 1406. The illustrated set of automatic topology settings 1406 is transmitted from the display processing device 1418 to the display unit 1430 via the network 1420.

[0260] The processor 1415 may execute and run the logic function 1424 after receiving the logic function 1424 from the display driver 1410. In this regard, the display driver 1410 may include an automatic topology module 1408 that automatically configures and builds the topology of the display unit 1432 to create the presentation 1440. In one example, the display driver 1410 is a set of instructions that, when executed by the processor 1415, causes the data processing device 1418 to communicate with the display unit 1430, a video card, etc., and perform automatic topology generation operations.

[0261] Data processing device 1418 may include, for example, a server, a desktop, a notebook computer, a tablet computer, a convertible tablet, a MID, a PDA, a wearable device, a media player, and the like. Thus, display processing device 1418 may include hardware control module 1416, storage device 1414, random access memory (RAM, not shown), controller cards including one or more video controller cards, and the like. In one example, display unit 1430 is a flat panel display (e.g., liquid crystal, active matrix, plasma, etc.), HMD, video projection device, and the like that cooperate with each other to generate presentation 1440. In addition, presentation 1440 may be generated based on media files stored in storage device 1414, where the media files may include, for example, movies, video clips, animations, advertisements, and the like, or any combination thereof.

[0262] The term "topology" may be considered to be the number, scaling, shape, and / or other configuration parameters of the first display unit 1430a, the second display unit 1430b, the third display unit 1430n, and the like. Accordingly, the topology of the display units 1430 may enable the presentation 1440 to be visually presented consistently, such that the various segments of the presentation 1440 are proportional and compatible with the original scale and range of the media being played through the display units 1430. Thus, the topology may constitute spatial relationships and / or geometric properties that are not affected by continuous changes in the shape or size of the content rendered in the presentation 1440. In one example, the automatic topology module 1408 includes a timing module 1426, a control module 1428, a signal monitor module 1432, and a signal display module 1434. The timing module 1426 may designate a particular display unit in a set of display units 1430 as a sample display unit. In such cases, the timing module 1426 may designate the remaining display modules 1430 as additional display units. In one example, the timing module 1426 automatically sets the form factor to be compatible with the hardware profile data 1402 , where the presentation 1440 is automatically initiated by the sequence 1422 of graphical signals.

[0263] In one example, the control module 1428 modifies the set of automatic topology settings 1406. In addition, the signal monitor module 1432 can automatically monitor the sequence of graphic signals 1422 and trigger the storage device 1414 to associate the set of automatic topology settings 1406 with the hardware profile lookup table 1412. In addition, the signal monitor module 1432 can automatically detect changes in the set of display units 1430 according to a set of change criteria and automatically generate a new topology profile corresponding to the changes in the set of display units 1430. Thus, the new topology profile can be applied to the set of display units 1430. If the sequence of graphic signals 1422 fails to meet the set of criteria, the signal monitor module 1432 can also trigger the signal display module 1434 to reapply the set of automatic topology settings 1406. If the hardware profile data 1402 does not support automatic topology display of the sequence of graphic signals 1422, the data processing device 1418 can report an error and record the error in the error log 1413.

[0264] Cloud-assisted media delivery

[0265] Now turn to Fig.15 , the cloud gaming system 1500 includes a client 1540 coupled to a server 1520 via a network 1510. The client 1540 may generally be a consumer of graphics (e.g., games, virtual reality / VR, augmented reality / AR) content that is hosted, processed, and rendered on the server 1520. The scalable server 1520 shown has the capacity to provide graphics content to multiple clients simultaneously (e.g., by utilizing parallel and shared processing and rendering resources). In one example, the scalability of the server 1520 is limited by the capacity of the network 1510. Accordingly, there may be a threshold number of clients, beyond which service to all clients is degraded.

[0266] In one example, server 1520 includes a graphics processor (e.g., GPU) 1530, a host processor (e.g., CPU) 1524, and a network interface card (NIC) 1552. NIC 1522 may receive requests for graphics content from clients 1540. Requests from clients 1540 may cause graphics content to be retrieved from memory via applications executed on host processor 1524. Host processor 1524 may perform high-level operations such as, for example, determining the position, collision, and motion of objects in a given scene. Based on these high-level operations, host processor 1524 may generate rendering commands that are combined with scene data and executed by graphics processor 1530. Rendering commands may cause graphics processor 1530 to define scene geometry, shading, lighting, motion, textures, camera parameters, etc. for a scene to be rendered via client 1540.

[0267] More specifically, the illustrated graphics processor 1530 includes a graphics renderer 1532 that performs a rendering process based on rendering commands generated by the host processor 1524. The output of the graphics renderer 1532 may be a raw video frame stream that is provided to a frame capturer 1534. The illustrated frame capturer 1534 is coupled to an encoder 1536 that may compress / format the raw video stream for transmission over the network 1510. The encoder 1536 may use various video compression algorithms, such as, for example, the H.264 standard from the International Telecommunication Union Telecommunication Standardization Sector (ITUT), the MPEG4 Advanced Video Coding (AVC) standard from the International Organization for Standardization / International Electrotechnical Commission (ISO / IEC), and the like.

[0268] The client 1540 shown (which may be a desktop computer, notebook computer, tablet computer, convertible computer, wearable device, MID, PDA, media player, etc.) includes a NIC 1542 to receive the transmitted video stream from the server 1520. The NIC 1522 may include the basis of the physical layer and software layer of the network interface in the client 1540 to facilitate communication over the network 1510. The client 1540 may also include a decoder 1544 that employs the same formatting / compression scheme as the encoder 1536. Thus, the decompressed video stream may be provided from the decoder 1544 to a video renderer 1546. The video renderer 1546 shown is coupled to a display 1548 that visually presents the graphical content.

[0269] As already noted, the graphical content may include gaming content. In this regard, the client 1540 may perform real-time interactive streaming involving collecting user input from the input device 1550 and delivering the user input to the server 1520 via the network 1510. This real-time interactive portion of cloud gaming may present challenges regarding latency.

[0270] Additional System Overview Examples

[0271] Fig.16 1 is a block diagram of a processing system 1600 according to an embodiment. In various embodiments, the system 1600 includes one or more processors 1602 and one or more graphics processors 1608, and may be a single-processor desktop computer system, a multi-processor workstation system, or a server system with a large number of processors 1602 or processor cores 1607. In one embodiment, the system 1600 is a processing platform included in a system-on-chip (SoC) for use in a mobile device, a handheld device, or an embedded device.

[0272] Embodiments of system 1600 may include or may be included in the following: a server-based game platform, a game console (including game and media consoles), a mobile game console, a handheld game console, or an online game console. In some embodiments, system 1600 is a mobile phone, a smart phone, a tablet computing device, or a mobile Internet device. Data processing system 1600 may also include, be coupled with, or be integrated in: a wearable device, such as a smart watch wearable device, a smart glasses device, an augmented reality device, or a virtual display device. In some embodiments, data processing system 1600 is a television or set-top box device having one or more processors 1602 and a graphics interface generated by one or more graphics processors 1608.

[0273] In some embodiments, one or more processors 1602 each include one or more processor cores 1607 for processing instructions, which when executed perform the operation of the system and user software. In some embodiments, each of the one or more processor cores 1607 is configured to process a specific instruction set 1609. In some embodiments, the instruction set 1609 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction words (VLIW). Multiple processor cores 1607 can each process different instruction sets 1609, and the instruction set may include instructions for facilitating emulation of other instruction sets. The processor core 1607 may also include other processing devices, such as a digital signal processor (DSP).

[0274] In some embodiments, the processor 1602 includes a cache memory 1604. Depending on the architecture, the processor 1602 may have a single internal cache or multiple levels of internal cache. In some embodiments, the cache memory is shared among various components of the processor 1602. In some embodiments, the processor 1602 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC) (not shown), which may be shared between the processor cores 1607 using known cache coherence techniques. A register file 1606 is additionally included in the processor 1602, which may include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. Some registers may be general purpose registers, while other registers may be specific to the design of the processor 1602.

[0275] In some embodiments, the processor 1602 is coupled to a processor bus 1610 to transmit communication signals (e.g., address, data, or control signals) between the processor 1602 and other components in the system 1600. In one embodiment, the system 1600 uses an exemplary 'hub' system architecture, including a memory controller hub 1616 and an input-output (I / O) controller hub 1630. The memory controller hub 1616 facilitates communication between memory devices and other components of the system 1600, while the I / O controller hub (ICH) 1630 provides connections to the I / O devices via a local I / O bus. In one embodiment, the logic of the memory controller hub 1616 is integrated within the processor.

[0276] Memory device 1620 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or some other memory device having suitable properties to act as process memory. In one embodiment, memory device 1620 may operate as system memory for system 1600 to store data 1622 and instructions 1621 for use when one or more processors 1602 execute applications or processes. Memory controller hub 1616 is also coupled to an optional external graphics processor 1612, which may be coupled to graphics processor 1608 in processor 1602 to perform graphics and media operations.

[0277] In some embodiments, the ICH 1630 enables peripheral devices to be connected to the memory device 1620 and the processor 1602 via a high-speed I / O bus. The I / O peripheral devices include, but are not limited to, an audio controller 1646, a firmware interface 1628, a wireless transceiver 1626 (e.g., Wi-Fi, Bluetooth), a data storage device 1624 (e.g., a hard drive, flash memory, etc.), and a traditional I / O controller 1640 for coupling traditional (e.g., Personal System 2 (PS / 2)) devices to the system. One or more Universal Serial Bus (USB) controllers 1642 connect input devices (e.g., a keyboard and mouse 1644 combination). A network controller 1634 may also be coupled to the ICH 1630. In some embodiments, a high-performance network controller (not shown) is coupled to the processor bus 1610. It will be appreciated that the system 1600 shown is exemplary and not limiting, as other types of data processing systems configured in different ways may also be used. For example, the I / O controller hub 1630 may be integrated within the one or more processors 1602 , or the memory controller hub 1616 and the I / O controller hub 1630 may be integrated within a discrete external graphics processor (such as the external graphics processor 1612 ).

[0278] Fig.17 is a block diagram of an embodiment of a processor 1700 having one or more processor cores 1702A- 1702N, an integrated memory controller 1714, and an integrated graphics processor 1708. Fig.17 Those elements having the same reference numbers (or names) as those of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited thereto. Processor 1700 may include additional cores up to and including additional core 1702N represented by a dashed box. Each of processor cores 1702A to 1702N includes one or more internal cache units 1704A to 1704N. In some embodiments, each processor core is also capable of accessing one or more shared cache units 1706.

[0279] Internal cache units 1704A to 1704N and shared cache unit 1706 represent a cache memory hierarchy within processor 1700. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared intermediate level caches (e.g., level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache), where the highest level cache in front of external memory is classified as LLC. In some embodiments, cache coherence logic maintains coherence between the various cache units 1706 and 1704A to 1704N.

[0280] In some embodiments, the processor 1700 may further include a set of one or more bus controller units 1716 and a system agent core 1710. The one or more bus controller units 1716 manage a set of peripheral buses, such as one or more peripheral component interconnect buses (e.g., PCI, PCI Express buses). The system agent core 1710 provides management functions for various processor components. In some embodiments, the system agent core 1710 includes one or more integrated memory controllers 1714, which are used to manage access to various external memory devices (not shown).

[0281] In some embodiments, one or more of the processor cores 1702A to 1702N include support for simultaneous multithreaded processing. In such embodiments, the system agent core 1710 includes components for coordinating and operating the cores 1702A to 1702N during multithreaded processing. The system agent core 1710 may additionally include a power control unit (PCU) that includes logic and components for regulating the power state of the processor cores 1702A to 1702N and the graphics processor 1708.

[0282] In some embodiments, the processor 1700 further includes a graphics processor 1708 for performing graphics processing operations. In some embodiments, the graphics processor 1708 is coupled with a set of shared cache units 1706 and the system agent core 1710 including one or more integrated memory controllers 1714. In some embodiments, a display controller 1711 is coupled with the graphics processor 1708 to drive the graphics processor output to one or more coupled displays. In some embodiments, the display controller 1711 can be a separate module coupled to the graphics processor via at least one interconnect, or can be integrated within the graphics processor 1708 or the system agent core 1710.

[0283] In some embodiments, a ring-based interconnect unit 1712 is used to couple the internal components of the processor 1700. However, alternative interconnect units may be used, such as point-to-point interconnects, switched interconnects, or other technologies, including those well known in the art. In some embodiments, the graphics processor 1708 is coupled to the ring interconnect 1712 via an I / O link 1713.

[0284] Exemplary I / O links 1713 represent at least one of a variety of I / O interconnects, including an on-package I / O interconnect that facilitates communication between various processor components and high-performance embedded memory modules 1718, such as eDRAM modules. In some embodiments, each of processor cores 1702 to 1702N and graphics processor 1708 use embedded memory modules 1718 as a shared last-level cache.

[0285] In some embodiments, processor cores 1702A to 1702N are homogeneous cores that execute the same instruction set architecture. In another embodiment, processor cores 1702A to 1702N are heterogeneous in terms of instruction set architecture (ISA), wherein one or more of processor cores 1702A to 1702N execute a first instruction set, while at least one of the other cores executes a subset of the first instruction set or a different instruction value. In one embodiment, processor cores 1702A to 1702N are heterogeneous in terms of microarchitecture, wherein one or more cores with relatively higher power consumption are coupled with one or more power cores with lower power consumption. In addition, processor 1700 can be implemented on one or more chips or as a SoC integrated circuit having the components shown in addition to other components.

[0286] Fig.181 is a block diagram of a graphics processor 1800, which may be a discrete graphics processing unit, or may be a graphics processor integrated with multiple processing cores. In some embodiments, the graphics processor communicates with memory via a mapped I / O interface to registers on the graphics processor and using commands placed in processor memory. In some embodiments, the graphics processor 1800 includes a memory interface 1814 for accessing memory. The memory interface 1814 may be an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory.

[0287] In some embodiments, the graphics processor 1800 also includes a display controller 1802 for driving display output data to a display device 1820. The display controller 1802 includes hardware for one or more overlapping planes of the display and a composition of multiple layers of video or user interface elements. In some embodiments, the graphics processor 1800 includes a video codec engine 1806 for encoding, decoding, or media transcoding to, from, or between one or more media encoding formats, including but not limited to: Moving Picture Experts Group (MPEG) formats (such as MPEG-2), Advanced Video Coding (AVC) formats (such as H.264 / MPEG-4 AVC), and Society of Motion Picture & Television Engineers (SMPTE) 421M / VC-1, and Joint Photographic Experts Group (JPEG) formats (such as JPEG, and Motion JPEG (MJPEG) formats).

[0288] In some embodiments, graphics processor 1800 includes a block image transfer (BLIT) engine 1804 for performing two-dimensional (2D) rasterizer operations, including, for example, bit boundary block transfers. However, in one embodiment, 2D graphics operations are performed using one or more components of a graphics processing engine (GPE) 1810. In some embodiments, graphics processing engine 1810 is a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0289] In some embodiments, GPE 1810 includes a 3D pipeline 1812 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that act on 3D primitive shapes (e.g., rectangles, triangles, etc.). 3D pipeline 1812 includes programmable and fixed function elements that perform various tasks within the elements and / or generated execution threads to 3D / media subsystem 1815. Although 3D pipeline 1812 can be used to perform media operations, embodiments of GPE 1810 also include a media pipeline 1816 that is specifically used to perform media operations, such as video post-processing and image enhancement.

[0290] In some embodiments, the media pipeline 1816 includes fixed-function or programmable logic units for performing one or more specialized media operations, such as video decoding acceleration, video deinterlacing, and video encoding acceleration, instead of or on behalf of the video codec engine 1806. In some embodiments, the media pipeline 1816 additionally includes a thread generation unit to generate threads for execution on the 3D / media subsystem 1815. The generated threads perform calculations for media operations on one or more graphics execution units included in the 3D / media subsystem 1815.

[0291] In some embodiments, the 3D / media subsystem 1815 includes logic for executing threads generated by the 3D pipeline 1812 and the media pipeline 1816. In one embodiment, the pipeline sends thread execution requests to the 3D / media subsystem 1815, which includes thread dispatch logic for arbitrating and dispatching each request to available thread execution resources. The execution resources include an array of graphics execution units for processing 3D and media threads. In some embodiments, the 3D / media subsystem 1815 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory (including registers and addressable memory) to share data between threads and store output data.

[0292] 3D / Media Processing

[0293] Fig.19 is a block diagram of a graphics processing engine 1910 of a graphics processor according to some embodiments. In one embodiment, GPE 1910 is Fig.18 A version of the GPE 1810 shown in . Fig.19 Elements in FIG. 1 having the same reference number (or name) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited thereto.

[0294] In some embodiments, the GPE 1910 is coupled to a command stream converter 1903, which provides a command stream to the 3D pipeline 1912 and the media pipeline 1916 of the GPE. In some embodiments, the command stream converter 1903 is coupled to a memory, which may be a system memory, or may be one or more of an internal cache memory and a shared cache memory. In some embodiments, the command stream converter 1903 receives commands from the memory and sends the commands to the 3D pipeline 1912 and / or the media pipeline 1916. The commands are instructions obtained from a ring buffer storing commands for the 3D pipeline 1912 and the media pipeline 1916. In one embodiment, the ring buffer may further include a batch command buffer storing multiple batches of multiple commands. The 3D pipeline 1912 and the media pipeline 1916 process the commands by performing operations via logic within the respective pipelines or by dispatching one or more execution threads to the execution unit array 1914. In some embodiments, execution unit array 1914 is scalable such that the array includes a variable number of execution units based on the target power and performance level of GPE 1910 .

[0295] In some embodiments, sampling engine 1930 is coupled to a memory (e.g., cache memory or system memory) and execution unit array 1914. In some embodiments, sampling engine 1930 provides a memory access mechanism for execution unit array 1914 that allows execution array 1914 to read graphics and media data from memory. In some embodiments, sampling engine 1930 includes logic for performing specialized image sampling operations for media.

[0296] In some embodiments, the specialized media sampling logic in the sampling engine 1930 includes a denoising / de-interlacing module 1932, a motion estimation module 1934, and an image scaling and filtering module 1936. In some embodiments, the denoising / de-interlacing module 1932 includes logic for performing one or more of a denoising or de-interlacing algorithm on the decoded video data. The de-interlacing logic combines the alternating lengths of the interlaced video content into a single frame of video. The denoising logic reduces or removes data noise from the video and image data. In some embodiments, the denoising and de-interlacing logic is motion adaptive and uses spatial or temporal filtering based on the amount of motion detected in the video data. In some embodiments, the denoising / de-interlacing module 1932 includes specialized motion detection logic (e.g., within the motion estimation engine 1934).

[0297] In some embodiments, the motion estimation engine 1934 provides hardware acceleration of video operations by performing video acceleration functions (such as motion vector estimation and prediction) on video data. The motion estimation engine determines motion vectors that describe image data transformations between consecutive video frames. In some embodiments, the graphics processor media codec uses the video motion estimation engine 1934 to perform operations on macroblock-level video that may otherwise be too computationally intensive to perform using a general-purpose processor. In some embodiments, the motion estimation engine 1934 may be generally available to the graphics processor component to assist in video decoding and processing functions that are sensitive or adaptive to the direction or magnitude of motion within the video data.

[0298] In some embodiments, the image scaling and filtering module 1936 performs image processing operations to improve the visual quality of the generated images and videos. In some embodiments, the scaling and filtering module 1936 processes the image and video data during a sampling operation before providing the data to the execution unit array 1914.

[0299] In some embodiments, GPE 1910 includes a data port 1944 that provides an additional mechanism for enabling the graphics subsystem to access memory. In some embodiments, data port 1944 facilitates memory access for operations including render target writes, constant buffer reads, temporary memory space reads / writes, and media surface accesses. In some embodiments, data port 1944 includes a cache memory space for caching accesses to memory. The cache memory can be a single data cache, or separated into multiple caches (e.g., render buffer caches, constant buffer caches, etc.) for multiple subsystems that access memory via data ports. In some embodiments, threads executing on execution units in execution unit array 1914 communicate with the data port by exchanging messages via a data distribution interconnect that couples each subsystem of GPE 1910.

[0300] Execution Unit

[0301] Fig. 20 is a block diagram of another embodiment of a graphics processor 2000 . Fig. 20 Elements in FIG. 1 having the same reference number (or name) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited thereto.

[0302] In some embodiments, graphics processor 2000 includes ring interconnect 2002, pipeline front end 2004, media engine 2037, and graphics cores 2080A to 2080N. In some embodiments, ring interconnect 2002 couples the graphics processor to other processing units, including other graphics processors or one or more general-purpose processor cores. In some embodiments, the graphics processor is one of multiple processors integrated into a multi-core processing system.

[0303] In some embodiments, the graphics processor 2000 receives batches of commands via the ring interconnect 2002. The incoming commands are translated by the command stream converter 2003 in the pipeline front end 2004. In some embodiments, the graphics processor 2000 includes scalable execution logic for performing 3D geometry processing and media processing via the graphics cores 2080A to 2080N. For 3D geometry processing commands, the command stream converter 2003 supplies the commands to the geometry pipeline 2036. For at least some media processing commands, the command stream converter 2003 supplies the commands to the video front end 2034, which is coupled to the media engine 2037. In some embodiments, the media engine 2037 includes a video quality engine (VQE) 2030 for video and image post-processing and a multi-format encoding / decoding (MFX) 2033 engine for providing hardware accelerated media data encoding and decoding. In some embodiments, the geometry pipeline 2036 and the media engine 2037 each generate an execution thread, which is used for thread execution resources provided by at least one graphics core 2080A.

[0304] In some embodiments, the graphics processor 2000 includes scalable thread execution resources featuring modular cores 2080A to 2080N (sometimes referred to as core slices), each modular core having multiple sub-cores 2050A to 2050N, 2060A to 2060N (sometimes referred to as core sub-slices). In some embodiments, the graphics processor 2000 can have any number of graphics cores 2080A to 2080N. In some embodiments, the graphics processor 2000 includes a graphics core 2080A, which has at least a first sub-core 2050A and a second sub-core 2060A. In other embodiments, the graphics processor is a low-power processor with a single sub-core (e.g., 2050A). In some embodiments, the graphics processor 2000 includes multiple graphics cores 2080A to 2080N, each graphics core including a group of first sub-cores 2050A to 2050N and a group of second sub-cores 2060A to 2060N. Each of the group of first sub-cores 2050A to 2050N includes at least a first group of execution units 2052A to 2052N and a media / texture sampler 2054A to 2054N. Each of the group of second sub-cores 2060A to 2060N includes at least a second group of execution units 2062A to 2062N and a sampler 2064A to 2064N. In some embodiments, each sub-core 2050A to 2050N, 2060A-2060N shares a group of shared resources 2070A to 2070N. In some embodiments, these shared resources include shared cache memory and pixel operation logic. Other shared resources may also be included in various embodiments of the graphics processor.

[0305] Fig.21 Threadable execution logic 2100 is shown, including an array of processing elements employed in some embodiments of a GPE. Fig.21 Those elements in FIG. 1 having the same reference numbers (or names) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited thereto.

[0306] In some embodiments, the thread execution logic 2100 includes a pixel shader 2102, a thread dispatcher 2104, an instruction cache 2106, a scalable execution unit array, including multiple execution units 2108A to 2108N, a sampler 2110, a data cache 2112, and a data port 2114. In one embodiment, these included components are interconnected via an interconnect structure that is linked to each of these components. In some embodiments, the thread execution logic 2100 includes one or more connections to a memory (e.g., a system memory or a cache memory) through the instruction cache 2106, the data port 2114, the sampler 2110, and one of the execution unit arrays 2108A to 2108N. In some embodiments, each execution unit (e.g., 2108A) is an individual vector processor capable of executing multiple simultaneous threads and processing multiple data elements in parallel for each thread. In some embodiments, the execution unit arrays 2108A to 2108N include any number of individual execution units.

[0307] In some embodiments, execution unit arrays 2108A to 2108N are primarily used to execute "shader" programs. In some embodiments, the execution units in arrays 2108A to 2108N execute an instruction set that includes native support for many standard 3D graphics shader instructions, so that shader programs from graphics libraries (e.g., Direct 3D and OpenGL) are executed with minimal conversion. The execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general processing (e.g., compute and media shaders).

[0308] Each execution unit in the execution unit array 2108A to 2108N operates on an array of data elements. The number of data elements is the "execution size" or number of lanes for the instruction. An execution lane is a logical execution unit used for data element access, masking, and flow control within an instruction. The number of lanes may be independent of the number of physical arithmetic logic units (ALUs) or floating point units (FPUs) for a particular graphics processor. In some embodiments, execution units 2108A to 2108N support integer and floating point data types.

[0309] The execution unit instruction set includes single instruction multiple data (SIMD). Various data elements can be stored in registers as compressed data types, and the execution unit will process these elements based on the data size of various elements. For example, when operating on a 256-bit wide vector, the 256-bit vector is stored in a register, and the execution unit operates on the vector as four independent 64-bit compressed data elements (data elements of quadruple word length (QW) size), eight independent 32-bit compressed data elements (data elements of double word length (DW) size), sixteen independent 16-bit compressed data elements (data elements of word length (W) size), or thirty-two independent 8-bit data elements (data elements of byte (B) size). However, different vector widths and register sizes are possible.

[0310] One or more internal instruction caches (e.g., 2106) are included in the thread execution logic 2100 to cache thread instructions for the execution unit. In some embodiments, one or more data caches (e.g., 2112) are included to cache thread data during thread execution. In some embodiments, a sampler 2110 is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, the sampler 2110 includes a specialized texture or media sampling function to process texture or media data during the sampling process before providing the sampled data to the execution unit.

[0311] During execution, the graphics pipeline and the media pipeline send thread initiation requests to the thread execution logic 2100 via the thread generation and dispatch logic. In some embodiments, the thread execution logic 2100 includes a local thread dispatcher 2104 that arbitrates thread initiation requests from the graphics pipeline and the media pipeline and instantiates the requested threads on one or more execution units 2108A to 2108N. For example, the geometry pipeline (e.g., Fig. 20 2036) dispatches vertex processing, tessellation or geometry processing threads to thread execution logic 2100 ( Fig.21 ). In some embodiments, thread dispatcher 2104 may also process runtime thread generation requests from executing shader programs.

[0312] Once a set of geometric objects has been processed and rasterized into pixel data, the pixel shader 2102 is called to further calculate output information and cause the results to be written to the output surface (e.g., color buffer, depth buffer, stencil buffer, etc.). In some embodiments, the pixel shader 2102 calculates the value of each vertex attribute, which is interpolated across the rasterized object. In some embodiments, the pixel shader 2102 then executes a pixel shader program supplied by an application programming interface (API). In order to execute the pixel shader program, the pixel shader 2102 dispatches threads to execution units (e.g., 2108A) via a thread dispatcher 2104. In some embodiments, the pixel shader 2102 uses texture sampling logic in a sampler 2110 to access texture data in a texture map stored in a memory. Arithmetic operations performed on the texture data and the input geometry calculate pixel color data for each geometric fragment, or discard one or more pixels for further processing.

[0313] In some embodiments, data port 2114 provides a memory access mechanism for thread execution logic 2100 to output processed data to memory for processing on the graphics processor output pipeline. In some embodiments, data port 2114 includes or is coupled to one or more cache memories (e.g., data cache 2112) to cache data via the data port for memory access.

[0314] Fig. 22 is a block diagram of a schematic graphics processor instruction format 2200 according to some embodiments. In one or more embodiments, the graphics processor execution unit supports an instruction set having instructions in multiple formats. Solid line boxes show components that are typically included in execution unit instructions, while dashed lines include components that are optional or included only in a subset of instructions. In some embodiments, the instruction format 2200 described and illustrated are macroinstructions because they are instructions supplied to the execution unit, as opposed to micro-operations generated from instruction decoding (once the instruction is processed).

[0315] In some embodiments, the graphics processor execution unit natively supports instructions in 128-bit format 2210. 64-bit compact instruction format 2230 can be used for some instructions based on the selected instruction, instruction options and the number of operands. Native 128-bit format 2210 provides access to all instruction options, while some options and operations are restricted in 64-bit format 2230. The native instructions available in 64-bit format 2230 vary according to the embodiment. In some embodiments, instructions are partially compacted using a set of index values ​​in index field 2213. The execution unit hardware references a set of compression tables based on these index values, and uses the compression table output to reconstruct the native instructions in 128-bit format 2210.

[0316] For each format, the instruction opcode 2212 defines the operation to be performed by the execution unit. The execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an addition instruction, the execution unit executes simultaneous addition operations across each color channel representing a texture element or a picture element. By default, the execution unit executes each instruction across all data channels of the operand. In some embodiments, the instruction control field 2214 enables control of certain execution options, such as channel selection (e.g., prediction) and data channel sorting (e.g., mixing). For 128-bit instructions 2210, the execution size field 2216 limits the number of data channels that will be executed in parallel. In some embodiments, the execution size field 2216 is not available for 64-bit compact instruction format 2230.

[0317] Some execution unit instructions have up to three operands, including two source operands src0 2220, src1 2222, and one destination 2218. In some embodiments, the execution unit supports dual destination instructions, where one of the destinations is implicit. Data manipulation instructions may have a third source operand (e.g., SRC2 2224), where the instruction opcode 2212 determines the number of source operands. The last source operand of an instruction may be an immediate (e.g., hard-coded) value passed by the instruction.

[0318] In some embodiments, the 128-bit instruction format 2210 includes access / address mode information 2226, which specifies, for example, whether direct register addressing mode or indirect register addressing mode is used. When direct register addressing mode is used, the register address of one or more operands is provided directly by bits in the instruction 2210.

[0319] In some embodiments, the 128-bit instruction format 2210 includes an access / address mode field 2226 that specifies the address mode and / or access mode of the instruction. In one embodiment, the access mode defines the data access alignment of the instruction. Some embodiments support access modes including a 16-byte aligned access mode and a 1-byte aligned access mode, wherein the byte alignment of the access mode determines the access alignment of the instruction operand. For example, when in a first mode, the instruction 2210 may use byte-aligned addressing for source operands and destination operands, and when in a second mode, the instruction 2210 may use 16-byte aligned addressing for all source operands and destination operands.

[0320] In one embodiment, the address mode portion of the access / address mode field 2226 determines whether the instruction will use direct addressing or indirect addressing. When direct register addressing mode is used, the bits in the instruction 2210 directly provide the register address of one or more operands. When indirect register addressing mode is used, the register address of one or more operands can be calculated based on the address register value and the address immediate field in the instruction.

[0321] In some embodiments, instructions are grouped based on the opcode 2212 bit field to simplify opcode decoding 2240. For 8-bit opcodes, bits 4, 5, and 6 allow the execution unit to determine the type of opcode. The precise opcode grouping shown is exemplary only. In some embodiments, the move and logic opcode group 2242 includes data movement and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, the move and logic group 2242 shares five most significant bits (MSBs), wherein the move (mov) instruction adopts the form of 0000xxxxb, and the logic instruction adopts the form of 0001xxxxb. The flow control instruction group 2244 (e.g., call (call), jump (jmp)) includes instructions in the form of 0010xxxxb (e.g., 0x20). The miscellaneous instruction group 2246 includes a mixture of instructions, which include synchronization instructions (e.g., wait, send) in the form of 0011xxxxb (e.g., 0x30). The parallel math instruction group 2248 includes component-wise arithmetic instructions (e.g., add, mul) in the form of 0100xxxxb (e.g., 0x40). The parallel math group 2248 performs arithmetic operations in parallel across data lanes. The vector math group 2250 includes arithmetic instructions (e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic such as dot product calculations on vector operands.

[0322] Graphics Pipeline

[0323] Fig.23 is a block diagram of another embodiment of a graphics processor 2300 . Fig.23 Elements in FIG. 1 having the same reference number (or name) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited thereto.

[0324] In some embodiments, the graphics processor 2300 includes a graphics pipeline 2320, a media pipeline 2330, a display engine 2340, a thread execution logic 2350, and a rendering output pipeline 2370. In some embodiments, the graphics processor 2300 is a graphics processor within a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or by commands issued to the graphics processor 2300 via the ring interconnect 2302. In some embodiments, the ring interconnect 2302 couples the graphics processor 2300 to other processing components, such as other graphics processors or general-purpose processors. Commands from the ring interconnect 2302 are translated by a command stream converter 2303, which supplies instructions to individual components of the graphics pipeline 2320 or the media pipeline 2330.

[0325] In some embodiments, the command stream converter 2303 directs the operation of the vertex fetcher 2305, which reads vertex data from memory and executes vertex processing commands provided by the command stream converter 2303. In some embodiments, the vertex fetcher 2305 provides the vertex data to the vertex shader 2307, which performs coordinate space transformation and lighting operations on each vertex. In some embodiments, the vertex fetcher 2305 and the vertex shader 2307 execute the vertex processing instructions by dispatching execution threads to the execution units 2352A, 2352B via the thread dispatcher 2331.

[0326] In some embodiments, execution units 2352A, 2352B are arrays of vector processors with instruction sets for performing graphics and media operations. In some embodiments, execution units 2352A, 2352B have an additional L1 cache 2351 specific for each array or shared between arrays. The cache can be configured as a data cache, an instruction cache, or a single cache that is partitioned to contain data and instructions in different partitions.

[0327] In some embodiments, the graphics pipeline 2320 includes a tessellation component for performing hardware accelerated tessellation of 3D objects. In some embodiments, a programmable hull shader 2311 configures the tessellation operation. A programmable domain shader 2317 provides back-end evaluation of the tessellation output. The tessellation 2313 operates at the direction of the hull shader 2311 and contains dedicated logic for generating a detailed set of geometric objects based on a coarse geometric model that is provided as input to the graphics pipeline 2320. In some embodiments, if tessellation is not used, the tessellation components 2311, 2313, 2317 can be bypassed.

[0328] In some embodiments, the complete geometric object may be processed by the geometry shader 2319 via one or more threads dispatched to the execution units 2352A, 2352B, or may proceed directly to the clipper 2329. In some embodiments, the geometry shader operates on entire geometric objects (rather than vertices or vertex patches as in previous stages of the graphics pipeline). If tessellation is disabled, the geometry shader 2319 receives input from the vertex shader 2307. In some embodiments, the geometry shader 2319 may be programmed by a geometry shader program to perform geometry tessellation when the tessellation unit is disabled.

[0329] Prior to rasterization, the clipper 2329 processes the vertex data. The clipper 2329 can be a fixed function clipper or a programmable clipper with clipping and geometry shader functions. In some embodiments, a rasterizer 2373 (e.g., a depth test component) in the render output pipeline 2370 dispatches a pixel shader to convert geometric objects into their pixel-by-pixel representations. In some embodiments, the pixel shader logic is included in the thread execution logic 2350. In some embodiments, the application can bypass the rasterizer 2373 and access the unrasterized vertex data via the outflow unit 2323.

[0330] The graphics processor 2300 has an interconnect bus, interconnect structure, or some other interconnect mechanism that allows data and messages to be passed among the main components of the processor. In some embodiments, the execution units 2352A, 2352B and associated cache(s) 2351, texture and media samplers 2354, and texture / sampler cache 2358 are interconnected via data ports 2356 to perform memory accesses and communicate with the rendering output pipeline components of the processor. In some embodiments, the samplers 2354, caches 2351, 2358, and execution units 2352A, 2352B each have separate memory access paths.

[0331] In some embodiments, the rendering output pipeline 2370 includes a rasterizer 2373 that converts vertex-based objects into associated pixel-based representations. In some embodiments, the rasterizer logic includes a windower / masker unit for performing fixed-function triangle and line rasterization. An associated rendering cache 2378 and depth cache 2379 are also available in some embodiments. The pixel operation component 2377 performs pixel-based operations on data, although in some examples, pixel operations associated with 2D operations (e.g., bit block image transfers and blending) are performed by the 2D engine 2341, or replaced by a display controller 2343 using overlapping display planes at display time. In some embodiments, a shared L3 cache 2375 can be used for all graphics components, allowing data to be shared without using main system memory.

[0332] In some embodiments, the graphics processor media pipeline 2330 includes a media engine 2337 and a video front end 2334. In some embodiments, the video front end 2334 receives pipeline commands from the command stream converter 2303. In some embodiments, the media pipeline 2330 includes a separate command stream converter. In some embodiments, the video front end 2334 processes the media commands before sending the commands to the media engine 2337. In some embodiments, the media engine 2337 includes a thread generation function for generating threads for dispatching to the thread execution logic 2350 via the thread dispatcher 2331.

[0333] In some embodiments, the graphics processor 2300 includes a display engine 2340. In some embodiments, the display engine 2340 is external to the processor 2300 and is coupled to the graphics processor via the ring interconnect 2302, or some other interconnect bus or structure. In some embodiments, the display engine 2340 includes a 2D engine 2341 and a display controller 2343. In some embodiments, the display engine 2340 includes dedicated logic that can operate independently of the 3D pipeline. In some embodiments, the display controller 2343 is coupled to a display device (not shown), which can be a system-integrated display device (such as in a laptop computer), or can be an external display device attached via a display device connector.

[0334] In some embodiments, graphics pipeline 2320 and media pipeline 2330 can be configured to perform operations based on multiple graphics and media programming interfaces, and are not specific to any one application programming interface (API). In some embodiments, the driver software of the graphics processor converts the API dispatch specific to a specific graphics or media library into a command that can be processed by the graphics processor. In some embodiments, the open graphics library (OpenGL) and open computing language (OpenCL) from Khronos Group, the Direct 3D library from Microsoft Corporation provide support, or both OpenGL and D3D can be provided. It is also possible to provide support for the open source computer vision library (OpenCV). If it is possible to map the pipeline called from the future API to the pipeline of the graphics processor, then the future API with a compatible 3D pipeline will also be supported.

[0335] Graphics Pipeline Programming

[0336] Fig.24A is a block diagram of a schematic diagram of a processor command format 2400 according to some embodiments. Fig. 24B is a block diagram illustrating a schematic diagram of a processor command sequence 2410 according to an embodiment. Fig.24A The solid-line boxes in show components that are typically included in a graphics command, while the dashed lines include components that are optional or included only in a subset of graphics commands. Fig.24A The exemplary graphics processor command format 2400 includes data fields for identifying the target client 2402 of the command, a command operation code (opcode) 2404, and command related data 2406. In some commands, a sub-opcode 2405 and a command size 2408 are also included.

[0337] In some embodiments, client 2402 specifies the client unit of the graphics device that processes the command data. In some embodiments, the graphics processor command parser checks the client field of each command to adjust the further processing of the command and routes the command data to the appropriate client unit. In some embodiments, the graphics processor client unit includes a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline for processing commands. Once the command is received by the client unit, the client unit reads the opcode 2404 and (if present) the sub-opcode 2405 to determine the operation to be performed. The client unit uses the information in the data field 2406 to execute the command. For some commands, an explicit command size 2408 is expected to specify the size of the command. In some embodiments, the command parser automatically determines the size of at least some of the commands in the command based on the command opcode. In some embodiments, the commands are aligned via multiples of the double word length.

[0338] Fig. 24B An exemplary graphics processor command sequence 2410 is shown in the flowchart of FIG. In some embodiments, software or firmware of a data processing system featuring an embodiment of a graphics processor uses a version of the command sequence shown to initiate, execute, and terminate a set of graphics operations. The sample command sequence is shown and described for exemplary purposes only, as embodiments are not limited to these particular commands or this command sequence. In addition, the commands may be issued as a batch of commands in a command sequence so that the graphics processor will process the command sequence in an at least partially simultaneous manner.

[0339] In some embodiments, the graphics processor command sequence 2410 may begin with a pipeline dump clear command 2412 to cause any active graphics pipeline to complete the currently pending commands of the pipeline. In some embodiments, the 3D pipeline 2422 and the media pipeline 2424 are not operating at the same time. The pipeline dump clear is performed to cause the active graphics pipeline to complete any pending commands. In response to the pipeline dump clear, the command parser of the graphics processor will suspend command processing until the active drawing engine completes the pending operation and the associated read cache is invalidated. Optionally, any data marked as 'dirty' in the rendering cache can be dumped to memory. In some embodiments, the pipeline dump clear command 2412 can be used for pipeline synchronization or before placing the graphics processor in a low power state.

[0340] In some embodiments, when a command sequence requires the graphics processor to explicitly switch between pipelines, a pipeline select command 2413 is used. In some embodiments, a pipeline select command 2413 is only required once in an execution context before issuing pipeline commands, unless the context is to issue commands for both pipelines. In some embodiments, a pipeline flush command is 2412 is required immediately before a pipeline switch is made via a pipeline select command 2413.

[0341] In some embodiments, pipeline control commands 2414 configure the graphics pipeline for operation and are used to program 3D pipeline 2422 and media pipeline 2424. In some embodiments, pipeline control commands 2414 configure the pipeline state of the active pipeline. In one embodiment, pipeline control commands 2414 are used for pipeline synchronization and for clearing data from one or more cache memories within the active pipeline before processing a batch of commands.

[0342] In some embodiments, a set of return buffers for the corresponding pipeline to write data is configured using return buffer state commands 2416. Some pipeline operations require the allocation, selection, or configuration of one or more return buffers into which these operations write intermediate data during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform cross-thread communication. In some embodiments, return buffer state 2416 includes selecting the size and number of return buffers to use for a set of pipeline operations.

[0343] The remaining commands in the command sequence differ based on the active pipeline for operation. Based on pipeline determination 2420 , the command sequence is customized according to a 3D pipeline 2422 , which starts at 3D pipeline state 2430 , and a media pipeline 2424 , which starts at media pipeline state 2440 .

[0344] The commands for 3D pipeline state 2430 include 3D state setting commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables that will be configured before processing 3D primitive commands. The values ​​of these commands are determined based at least in part on the specific 3D API in use. In some embodiments, the 3D pipeline state 2430 commands can also selectively disable or bypass specific pipeline elements if those elements will not be used.

[0345] In some embodiments, 3D primitive 2432 commands are used to submit 3D primitives to be processed by 3D pipeline. The commands and associated parameters passed to the graphics processor via 3D primitive 2432 are forwarded to the vertex acquisition function in the graphics pipeline. The vertex acquisition function uses 3D primitive 2432 command data to generate vertex data structure. The vertex data structure is stored in one or more return buffers. In some embodiments, 3D primitive 2432 commands are used to perform vertex operations on 3D primitives via vertex shaders. In order to process vertex shaders, 3D pipeline 2422 dispatches shader execution threads to the graphics processor execution unit.

[0346] In some embodiments, the 3D pipeline 2422 is triggered via an execution 2434 command or event. In some embodiments, a register write triggers the command execution. In some embodiments, the execution is triggered via a 'go' or 'kick' command in a command sequence. In one embodiment, the command execution is triggered using a pipeline synchronization command to dump and clear the command sequence through the graphics pipeline. The 3D pipeline will perform geometry processing for 3D primitives. Once the operation is completed, the resulting geometric object is rasterized, and the pixel engine colors the resulting pixels. Additional commands for controlling pixel shading and pixel backend operations may also be included for those operations.

[0347] In some embodiments, when performing media operations, the graphics processor command sequence 2410 follows the media pipeline 2424 path. Generally, the specific purpose and programming of the media pipeline 2424 depends on the media or computing operation to be performed. During media decoding, specific media decoding operations can be offloaded to the media pipeline. In some embodiments, the media pipeline can also be bypassed, and the media decoding can be performed in whole or in part using resources provided by one or more general processing cores. In one embodiment, the media pipeline also includes elements for general purpose graphics processor unit (GPGPU) operations, wherein the graphics processor is used to perform SIMD vector operations using compute shader programs, and the compute shader programs are not explicitly related to the rendering of graphics primitives.

[0348] In some embodiments, the media pipeline 2424 is configured in a similar manner to the 3D pipeline 2422. A set of media pipeline state commands 2440 are dispatched or placed into a command queue prior to the media object commands 2442. In some embodiments, the media pipeline state commands 2440 include data for configuring the media pipeline elements that will be used to process the media objects. This includes data for configuring the video decoding and video encoding logic within the media pipeline (such as encoding or decoding modes). In some embodiments, the media pipeline state commands 2440 also support the use of one or more pointers to an "indirect" state element that contains a batch of state settings.

[0349] In some embodiments, media object commands 2442 supply pointers to media objects for processing by the media pipeline. The media object includes a memory buffer containing video data to be processed. In some embodiments, all media pipeline states must be valid before issuing media object commands 2442. Once the pipeline state is configured and media object commands 2442 are queued, media pipeline 2424 is triggered via an execute command 2444 or an equivalent execution event (e.g., a register write). The output from media pipeline 2424 can then be post-processed by operations provided by 3D pipeline 2422 or media pipeline 2424. In some embodiments, GPGPU operations are configured and executed in a manner similar to media operations.

[0350] Graphics software architecture

[0351] Fig.25 An exemplary graphics software architecture of a data processing system 2500 according to some embodiments is shown. In some embodiments, the software architecture includes a 3D graphics application 2510, an operating system 2520, and at least one processor 2530. In some embodiments, processor 2530 includes a graphics processor 2532 and one or more general purpose processor cores 2534. Graphics application 2510 and operating system 2520 are each executed in a system memory 2550 of the data processing system.

[0352] In some embodiments, the 3D graphics application 2510 includes one or more shader programs that include shader instructions 2512. The shader language instructions may be in a high-level shader language, such as High-Level Shader Language (HLSL) or OpenGL Shader Language (GLSL). The application also includes executable instructions 2514 in a machine language suitable for execution by a general purpose processor core 2534. The application also includes geometric objects 2516 defined by vertex data.

[0353] In some embodiments, operating system 2520 is from Microsoft Corporation Operating system, proprietary UNIX-like operating system using a variant of the Linux kernel, or an open source UNIX-like operating system. When the Direct3D API is in use, the operating system 2520 uses a front-end shader compiler 2524 to compile any shader instructions 2512 in HLSL into a low-level shader language. The compilation can be a just-in-time (JIT) compilation, or the application can execute shader pre-compilation. In some embodiments, during the compilation of the 3D graphics application 2510, the high-order shader is compiled into a low-order shader.

[0354] In some embodiments, the user mode graphics driver 2526 includes a backend shader compiler 2527 that is used to convert shader instructions 2512 into hardware specific representations. When the OpenGL API is in use, the shader instructions 2512 in the GLSL high-level language are passed to the user mode graphics driver 2526 for compilation. In some embodiments, the user mode graphics driver 2526 uses operating system kernel mode functions 2528 to communicate with the kernel mode graphics driver 2529. In some embodiments, the kernel mode graphics driver 2529 communicates with the graphics processor 2532 to dispatch commands and instructions.

[0355] IP core implementation

[0356] One or more aspects of at least one embodiment may be implemented by representative code stored on a machine-readable medium, which represents and / or defines logic within an integrated circuit (e.g., a processor). For example, a machine-readable medium may include instructions representing the various logics within a processor. When read by a machine, the instructions may cause the machine to manufacture logic for performing the techniques described herein. Such representations (referred to as "IP cores") are reusable units of logic for an integrated circuit, which may be stored on a tangible, machine-readable medium as a hardware model describing the structure of the integrated circuit. The hardware model may be supplied to each consumer or manufacturing facility that loads the hardware model on a manufacturing machine that manufactures the integrated circuit. The integrated circuit may be manufactured so that the circuit performs the operations described in association with any of the embodiments described herein.

[0357] Fig.26 2600 is a block diagram showing an IP core development system according to an embodiment, and the IP core development system can be used to manufacture an integrated circuit to perform operations. The IP core development system 2600 can be used to generate a modular, reusable design that can be incorporated into a larger design or used to build an entire integrated circuit (e.g., a SOC integrated circuit). The design facility 2630 can use a high-level programming language (e.g., C / C++) to generate a software simulation 2610 for the IP core design. The software simulation 2610 can be used to design, test and verify the behavior of the IP core. Then the register transfer level (RTL) design can be created or synthesized by the simulation model 2600. The RTL design 2615 is an abstraction of the behavior of an integrated circuit (including associated logic executed using the modeled digital signals) that models the flow of digital signals between hardware registers. In addition to the RTL design 2615, a lower level design at a logic level or transistor level can also be created, designed or synthesized. Thus, the specific details of the initial design and simulation can change.

[0358] The RTL design 2615 or equivalent may be further synthesized by the design facility into a hardware model 2620, which may be in a hardware description language (HDL) or some other representation of physical design data. The HDL may be further simulated or tested to verify the IP core design. The IP core design may be stored using a non-volatile memory 2640 (e.g., a hard disk, flash memory, or any non-volatile storage medium) for delivery to a third-party manufacturing facility 2665. Alternatively, the IP core design may be transmitted (e.g., via the Internet) via a wired connection 2650 or a wireless connection 2660. The manufacturing facility 2665 may then manufacture an integrated circuit based at least in part on the IP core design. The manufactured integrated circuit may be configured to perform operations according to at least one embodiment described herein.

[0359] Fig. 27 2700, which can be manufactured using one or more IP cores. The exemplary integrated circuit includes one or more application processors 2705 (e.g., CPUs), at least one graphics processor 2710, and may additionally include an image processor 2715 and / or a video processor 2720, any of which may be modular IP cores from the same or multiple different design facilities. The integrated circuit includes peripheral or bus logic, including a USB controller 2725, a UART controller 2730, an SPI / SDIO controller 2735, an I 2 S / I 2 The integrated circuit may include a display device 2745 coupled to one or more of a high-definition multimedia interface (HDMI) controller 2750 and a mobile industry processor interface (MIPI) display interface 2755. Storage may be provided by a flash memory subsystem 2760 (including flash memory and a flash memory controller). A memory interface may be provided via a memory controller 2765 for accessing SDRAM or SRAM memory devices. Some integrated circuits additionally include an embedded security engine 2770.

[0360] Additionally, other logic and circuitry may be included in the processor of integrated circuit 2700 , including additional graphics processors / cores, peripheral interface controllers, or general purpose processor cores.

[0361] Advantageously, any of the above systems, processors, graphics processors, devices and / or methods may be integrated or configured with any of the various embodiments described herein (e.g., or portions thereof), including, for example, those described in the following additional notes and examples.

[0362] Additional Notes and Examples

[0363] Example 1 may include an electronic processing system comprising: a display processor to generate image data for display; a memory communicatively coupled to the display processor for storing a two-dimensional (2D) frame corresponding to a projection from a 360 video space; a component predictor communicatively coupled to the display processor for predicting an encoded component of a first block of the 2D frame based on encoded information from one or more neighboring blocks of the 2D frame, wherein the one or more neighboring blocks of the 2D frame include one or more blocks that are adjacent to the first block of the 2D frame only in the 360 ​​video space; a prioritizer communicatively coupled to the display processor for prioritizing transmission of groups of the 2D frame based on identified regions of interest; and a format detector communicatively coupled to the display processor for detecting a 360 video format of the 2D frame based on image content of the 2D frame.

[0364] Example 2 may include the system as described in Example 1, further comprising: a 360 video capture device, communicatively coupled to the display processor for capturing 360 video content; and a context tagger, communicatively coupled to the 360 ​​video capture device for tagging the 360 ​​video content using context information contemporary with the captured 360 video content.

[0365] Example 3 may include the system of Example 2, wherein the context information includes one or more of motion information, position information, speed information, acceleration information, orientation information, and direction information.

[0366] Example 4 may include a system as described in Example 1, wherein the encoding information includes one or more of motion vector information and mode information.

[0367] Example 5 may include the system of Example 1, wherein the prioritizer is further for prioritizing encoding of a second block of the 2D frame based on the identified region of interest.

[0368] Example 6 may include the system of Example 1, wherein the detected 360 video format includes one or more of a fisheye format, an equirectangular projection format, a cube map format, and a packed cube map format.

[0369] Example 7 may include a graphics device comprising: an encoder to encode a first block of a two-dimensional (2D) frame, wherein the 2D frame corresponds to a projection of a 360 video space; and a component predictor, communicatively coupled to the encoder to determine whether the first block is a neighbor of a second block of the 2D frame in the 360 ​​video space, and to predict an encoded component of the second block based on encoding information of the first block if the first block is determined to be the neighbor of the second block in the 360 ​​video space.

[0370] Example 8 may include the apparatus of Example 7, wherein the component predictor is further configured to predict a motion vector of the second block based on encoded motion vector information of the first block if the first block is determined to be the neighbor of the second block in the 360 ​​video space.

[0371] Example 9 may include the apparatus of Example 7, wherein the component predictor is further configured to predict a mode of the second block based on encoded mode information of the first block if the first block is determined to be the neighbor of the second block in the 360 ​​video space.

[0372] Example 10 may include the apparatus of Example 7, wherein the encoder is further configured to encode the second block of the 2D frame based on the predicted coding component.

[0373] Example 11 may include the apparatus of Example 7, further comprising a prioritizer communicatively coupled to the encoder for prioritizing transmission of the groupings of the 2D frames based on the identified regions of interest.

[0374] Example 12 may include the apparatus of Example 7, further comprising a format detector communicatively coupled to the encoder for detecting a 360 video format of the 2D frame based on image content of the 2D frame.

[0375] Example 13 may include the apparatus of Example 7, further comprising: a 360 video capture device communicatively coupled to the encoder for capturing 360 video content; and a context tagger communicatively coupled to the 360 ​​video capture device for tagging the 360 ​​video content using context information contemporary with the captured 360 video content.

[0376] Example 14 may include a method of processing a 360° video, the method comprising: encoding a first block of a two-dimensional (2D) frame, wherein the 2D frame corresponds to a projection of a 360° video space; determining whether the first block is a neighbor of a second block of the 2D frame in the 360° video space; and if the first block is determined to be the neighbor of the second block in the 360° video space, predicting an encoding component of the second block based on encoding information of the first block.

[0377] Example 15 may include the method of Example 14, further comprising: if the first block is determined to be the neighbor of the second block in the 360 ​​video space, predicting the motion vector of the second block based on the encoded motion vector information of the first block.

[0378] Example 16 may include the method of Example 14, further comprising predicting the mode of the second block based on the encoded mode information of the first block if the first block is determined to be the neighbor of the second block in the 360 ​​video space.

[0379] Example 17 may include the method of Example 14, further comprising encoding the second block of the 2D frame based on the predicted coding component.

[0380] Example 18 may include at least one computer-readable medium comprising a set of instructions that, when executed by a computing device, cause the computing device to: encode a first block of a two-dimensional (2D) frame, wherein the 2D frame corresponds to a projection of a 360 video space; determine whether the first block is a neighbor of a second block of the 2D frame in the 360 ​​video space; and if the first block is determined to be the neighbor of the second block in the 360 ​​video space, predict an encoding component of the second block based on encoding information of the first block.

[0381] Example 19 may include at least one computer-readable medium as described in Example 18, comprising an additional set of instructions that, when executed by a computing device, cause the computing device to: if the first block is determined to be the neighbor of the second block in the 360 ​​video space, predict the motion vector of the second block based on the encoded motion vector information of the first block.

[0382] Example 20 may include at least one computer-readable medium as described in Example 18, comprising an additional set of instructions that, when executed by a computing device, cause the computing device to: if the first block is determined to be the neighbor of the second block in the 360 ​​video space, predict the mode of the second block based on the encoded mode information of the first block.

[0383] Example 21 may include at least one computer-readable medium as described in Example 18, comprising a further set of instructions that, when executed by a computing device, cause the computing device to encode the second block of the 2D frame based on the predicted encoding component.

[0384] Example 22 may include a graphics device comprising: a device for encoding a first block of a two-dimensional (2D) frame, wherein the 2D frame corresponds to a projection of a 360 video space; a device for determining whether the first block is a neighbor of a second block of the 2D frame in the 360 ​​video space; and a device for predicting an encoding component of the second block based on encoding information of the first block if the first block is determined to be the neighbor of the second block in the 360 ​​video space.

[0385] Example 23 may include the apparatus of Example 22, further comprising: means for predicting a motion vector of the second block based on encoded motion vector information of the first block if the first block is determined to be the neighbor of the second block in the 360 ​​video space.

[0386] Example 24 may include the apparatus of Example 22, further comprising: means for predicting a mode of the second block based on encoded mode information of the first block if the first block is determined to be the neighbor of the second block in the 360 ​​video space.

[0387] Example 25 may include the apparatus of Example 22, further comprising: means for encoding the second block of the 2D frame based on the predicted coding component.

[0388] Example 26 may include a graphics device comprising: a region identifier for identifying a region of interest in a 2D frame, wherein the 2D frame corresponds to a projection of a 360 video; and a prioritizer communicatively coupled to the region identifier for prioritizing the transmission of groups of the 2D frame based on the identified region of interest.

[0389] Example 27 may include the apparatus of Example 26, wherein the prioritizer is further for prioritizing encoding of one or more blocks of the 2D frame based on the identified region of interest.

[0390] Example 28 may include the apparatus of Example 27, further comprising: an encoder communicatively coupled to the prioritizer for encoding the prioritized one or more blocks of the 2D frame; and a packetizer communicatively coupled to the encoder for assembling the prioritized groups from the encoded prioritized one or more blocks of the 2D frame.

[0391] Example 29 may include the apparatus of Example 28, further comprising: a transmitter communicatively coupled to the packetizer for transmitting the prioritized packets.

[0392] Example 30 may include the apparatus of Example 27, further comprising: a format detector communicatively coupled to the encoder for detecting a 360 video format of the 2D frame based on image content of the 2D frame.

[0393] Example 31 may include the apparatus of Example 27, further comprising: a 360 video capture device communicatively coupled to the encoder for capturing 360 video content; and a context tagger communicatively coupled to the 360 ​​video capture device for tagging the 360 ​​video content using context information contemporary with the captured 360 video content.

[0394] Example 32 may include a method of processing a 360 video, the method comprising: identifying a region of interest in a 2D frame, wherein the 2D frame corresponds to a projection of the 360 ​​video; and prioritizing transmission of groups of the 2D frames based on the identified region of interest.

[0395] Example 33 may include the method of Example 32, further comprising prioritizing encoding of one or more blocks of the 2D frame based on the identified region of interest.

[0396] Example 34 may include the method of Example 33, further comprising: encoding one or more prioritized blocks of a coded 2D frame; and assembling the prioritized groups from the encoded one or more prioritized blocks of the 2D frame.

[0397] Example 35 may include the method of Example 34, further comprising transmitting the prioritized packets.

[0398] Example 36 may include at least one computer-readable medium comprising a set of instructions that, when executed by a computing device, cause the computing device to: identify a region of interest in a 2D frame, wherein the 2D frame corresponds to a projection of a 360 video; and prioritize transmission of groups of the 2D frames based on the identified region of interest.

[0399] Example 37 may include at least one computer-readable medium as described in Example 36, comprising an additional set of instructions that, when executed by a computing device, cause the computing device to prioritize encoding of one or more blocks of the 2D frame based on the identified region of interest.

[0400] Example 38 may include at least one computer-readable medium as described in Example 37, comprising an additional set of instructions that, when executed by a computing device, cause the computing device to: encode one or more prioritized blocks of the 2D frame; and assemble the prioritized groups from the encoded one or more prioritized blocks of the 2D frame.

[0401] Example 39 may include at least one computer-readable medium as described in Example 38, comprising an additional set of instructions that, when executed by a computing device, cause the computing device to transmit the prioritized packets.

[0402] Example 40 may include a graphics device comprising: means for identifying a region of interest in a 2D frame, wherein the 2D frame corresponds to a projection of a 360 video; and means for prioritizing transmission of groups of the 2D frame based on the identified region of interest.

[0403] Example 41 may include the apparatus of Example 40, further comprising: means for prioritizing encoding of one or more blocks of the 2D frame based on the identified region of interest.

[0404] Example 42 may include an apparatus as described in Example 40, further comprising: a device for encoding one or more prioritized blocks of the 2D frame; and a device for assembling prioritized groups from the encoded one or more prioritized blocks of the 2D frame.

[0405] Example 43 may include the apparatus of Example 40, further comprising means for transmitting the prioritized packets.

[0406] Example 44 may include a graphics device comprising: a decoder to decode a 2D frame, wherein the 2D frame corresponds to a projection of a 360 video; a format detector communicatively coupled to the decoder for detecting a format of the 360 ​​video based on image content of the 2D frame; and a mapper communicatively coupled to the decoder and the format detector for mapping the decoded 2D frame based on the detected 360 video format.

[0407] Example 45 may include the apparatus of Example 44, wherein the format detector is further for detecting the fisheye format based on an identified blank area of ​​the 2D frame, the identified blank area being outside of the identified non-blank circular area of ​​the 2D frame.

[0408] Example 46 may include an apparatus as described in Example 44, wherein the format detector is further used to: detect the equirectangular projection format based on one or more of the identified deformation near the poles of the 2D frame, the identified discontinuity at the edges of the 2D frame, and the identified object segmentation between the left edge and the right edge of the 2D frame.

[0409] Example 47 may include the apparatus of Example 44, wherein the format detector is further for detecting a cube map format based on one or more of an identified blank rectangular region of the 2D frame and an identified T-shape of a non-blank region of the 2D frame.

[0410] Example 48 may include a device as described in Example 44, wherein the format detector is further used to: detect a packed cube map format based on one or more of the number of identified edges in the 2D frame, the identified commonality among the edges in the 2D frame, and the identified discontinuity along the edges of the 2D frame.

[0411] Example 49 may include the apparatus of Example 44, further comprising: a 360 video capture device communicatively coupled to the decoder to capture 360 ​​video content; and a context tagger communicatively coupled to the 360 ​​video capture device to tag the 360 ​​video content using context information contemporary with the captured 360 video content.

[0412] Example 50 may include a method of processing a 360 video, the method comprising: decoding a 2D frame, wherein the 2D frame corresponds to a projection of the 360 ​​video; detecting a format of the 360 ​​video based on image content of the 2D frame; and mapping the decoded 2D frame based on the detected 360 video format.

[0413] Example 51 may include the method of Example 50, further comprising detecting a fisheye format based on an identified blank area of ​​the 2D frame, the identified blank area being outside of the identified non-blank circular area of ​​the 2D frame.

[0414] Example 52 may include the method of Example 50, further comprising detecting an equirectangular projection format based on one or more of identified deformations near poles of the 2D frame, identified discontinuities at edges of the 2D frame, and identified object segmentation between left and right edges of the 2D frame.

[0415] Example 53 may include the method of Example 50, further comprising detecting a cube map format based on one or more of an identified blank rectangular region of the 2D frame and an identified T-shape of a non-blank region of the 2D frame.

[0416] Example 54 may include the method as described in Example 50, further comprising: detecting a packed cube map format based on one or more of the number of identified edges in the 2D frame, the identified commonality among the edges in the 2D frame, and the identified discontinuity along the edges of the 2D frame.

[0417] Example 55 may include at least one computer-readable medium comprising a set of instructions that, when executed by a computing device, cause the computing device to: decode a 2D frame, wherein the 2D frame corresponds to a projection of a 360 video; detect a format of the 360 ​​video based on image content of the 2D frame; and map the decoded 2D frame based on the detected 360 video format.

[0418] Example 56 may include at least one computer-readable medium as described in Example 55, comprising an additional set of instructions that, when executed by a computing device, cause the computing device to: detect a fisheye format based on an identified blank area of ​​the 2D frame, wherein the identified blank area is outside an identified non-blank circular area of ​​the 2D frame.

[0419] Example 57 may include at least one computer-readable medium as described in Example 55, comprising an additional set of instructions that, when executed by a computing device, cause the computing device to: detect an equirectangular projection format based on one or more of identified deformations near the poles of the 2D frame, identified discontinuities at the edges of the 2D frame, and identified object segmentation between the left and right edges of the 2D frame.

[0420] Example 58 may include at least one computer-readable medium as described in Example 55, comprising an additional set of instructions that, when executed by a computing device, cause the computing device to: detect a cube mapping format based on one or more of the identified blank rectangular areas of the 2D frame and the identified T-shapes of the non-blank areas of the 2D frame.

[0421] Example 59 may include at least one computer-readable medium as described in Example 55, comprising an additional set of instructions that, when executed by a computing device, cause the computing device to: detect a packed cube map format based on one or more of the number of identified edges in the 2D frame, the identified commonality among the edges in the 2D frame, and the identified discontinuity along the edges of the 2D frame.

[0422] Example 60 may include a graphics device comprising: a device for decoding a 2D frame, wherein the 2D frame corresponds to a projection of a 360 video; a device for detecting a format of the 360 ​​video based on image content of the 2D frame; and a device for mapping the decoded 2D frame based on the detected 360 video format.

[0423] Example 61 may include the apparatus of Example 60, further comprising: means for detecting a fisheye format based on an identified blank area of ​​the 2D frame, the identified blank area being outside of the identified non-blank circular area of ​​the 2D frame.

[0424] Example 62 may include an apparatus as described in Example 60, further comprising: a device for detecting an equirectangular projection format based on one or more of identified deformations near the poles of the 2D frame, identified discontinuities at the edges of the 2D frame, and identified object segmentation between the left and right edges of the 2D frame.

[0425] Example 63 may include the apparatus of Example 60, further comprising means for detecting a cube map format based on one or more of the identified blank rectangular regions of the 2D frame and the identified T-shapes of the non-blank regions of the 2D frame.

[0426] Example 64 may include an apparatus as described in Example 60, further comprising: a device for detecting a packed cube map format based on one or more of the number of identified edges in the 2D frame, the identified commonality among the edges in the 2D frame, and the identified discontinuity along the edges of the 2D frame.

[0427] Example 65 may include a graphics device further comprising: a 360 video capture device to capture 360 ​​video content; and a context tagger communicatively coupled to the 360 ​​video capture device to tag the 360 ​​video content with context information contemporary with the captured 360 video content.

[0428] Example 66 may include the device of Example 65, wherein the context information includes one or more of motion information, position information, speed information, acceleration information, orientation information, and direction information.

[0429] Example 67 may include the apparatus of Example 65, wherein the context tagger is further for tagging the 360 ​​video content using metadata of the context information.

[0430] Example 68 may include the apparatus of Example 67, wherein the 360 ​​video capture device is further for encoding the captured 360 video content using the metadata.

[0431] Example 69 may include a method of processing 360 video, the method comprising: capturing 360 video content; and annotating the 360 ​​video content using contextual information contemporary with the captured 360 video content.

[0432] Example 70 may include the method of Example 69, wherein the context information includes one or more of motion information, position information, speed information, acceleration information, orientation information, and direction information.

[0433] Example 71 may include the method of Example 70, further comprising annotating the 360 ​​video content using metadata of the context information.

[0434] Example 72 may include the method of Example 71, further comprising encoding the captured 360 video content using the metadata.

[0435] Example 73 may include at least one computer-readable medium comprising a set of instructions that, when executed by a computing device, cause the computing device to: capture 360 ​​video content; and annotate the 360 ​​video content using contextual information contemporary with the captured 360 video content.

[0436] Example 74 may include at least one computer-readable medium as described in Example 73, wherein the context information includes one or more of motion information, position information, velocity information, acceleration information, orientation information, and direction information.

[0437] Example 75 may include at least one computer-readable medium as described in Example 74, comprising an additional set of instructions that, when executed by a computing device, cause the computing device to annotate the 360 ​​video content with metadata of the contextual information.

[0438] Example 76 may include at least one computer-readable medium as described in Example 75, comprising a further set of instructions that, when executed by a computing device, cause the computing device to encode the captured 360 video content using the metadata.

[0439] Example 77 may include a graphics device comprising: means for capturing 360 video content; and means for annotating the 360 ​​video content with contextual information contemporary with the captured 360 video content.

[0440] Example 78 may include the device of Example 77, wherein the context information comprises one or more of motion information, position information, speed information, acceleration information, orientation information, and direction information.

[0441] Example 79 may include the apparatus of Example 78, further comprising means for annotating the 360 ​​video content using metadata of the context information.

[0442] Example 80 may include the apparatus of Example 79, further comprising means for encoding the captured 360 video content using the metadata.

[0443] Embodiments are applicable for use with all types of semiconductor integrated circuit ("IC") chips. Examples of these ICs include, but are not limited to, processors, controllers, chipset components, programmable logic arrays (PLA), memory chips, network chips, systems on chips (SoC), SSD / NAND controller ASICs, and the like. In addition, in some of the drawings, signal conductor lines are represented by lines. Some may be different to indicate more signal paths; have digital labels to indicate the number of signal paths that are formed, and / or have arrows at one or more ends to indicate the main direction of information flow. However, this should not be interpreted in a limiting sense. Instead, such additional details may be used in conjunction with one or more exemplary embodiments to facilitate easier understanding of the circuit. Regardless of whether there is additional information, any signal line represented may actually include one or more signals that can travel in multiple directions, and may be implemented with any suitable type of signal scheme, such as digital or analog lines implemented with differential pairs, fiber optic lines, and / or single-ended lines.

[0444] Example size / model / value / range may be given, but the embodiment is not limited thereto. As manufacturing technology (e.g., photolithography) matures over time, it is expected that a device with a smaller size can be manufactured. In addition, the well-known power / ground connection to the IC chip and other components may be shown or not shown in the figure, which is for the simplicity of display and discussion and in order not to obscure certain aspects of the embodiment. In addition, some arrangements can be shown in the form of block diagrams to avoid obscuring the embodiment, and it is also considered that the details of the implementation of such block diagram arrangements are highly dependent on the fact that the level of the internal embodiment to be implemented, that is, such details should be well within the authority of those skilled in the art. In the case of stating specific details (e.g., circuits) in order to describe exemplary embodiments, it should be apparent to those skilled in the art that the embodiment can be practiced without these specific details or with variations of these specific details. Therefore, this specification will be regarded as illustrative rather than restrictive.

[0445] The term "coupled" may be used herein to refer to any type of relationship, direct or indirect, between the components in question, and may apply to electrical, mechanical, fluid, optical, electromagnetic, electromechanical or other connections. In addition, the terms "first", "second", etc. may be used herein only to facilitate discussion, and unless otherwise indicated, do not convey any specific temporal or temporal significance. In addition, it should be understood that the indefinite article "a" or "an" carries the meaning of "one or more" or "at least one".

[0446] As used in this application and in the claims, a list of items described by the term "one or more" may mean any combination of the listed items. For example, the phrase "at least one of A, B, and C" means A, B, C; A and B; A and C; B and C; or A, B, and C.

[0447] Embodiments have been described above with reference to specific embodiments. However, it will be appreciated by those skilled in the art that various modifications and changes may be made thereto without departing from the broader spirit and scope of the embodiments as set forth in the appended claims. The foregoing description and drawings are therefore considered to be illustrative rather than restrictive.

Claims

1. An electronic processing system comprising: A display processor for generating image data for display; a memory, communicatively coupled to the display processor, for storing two-dimensional (2D) frames corresponding to projections from a 360 video space; a component predictor, communicatively coupled to the display processor, for predicting an encoded component of a first block of the 2D frame based on encoded information from one or more neighboring blocks of the 2D frame, wherein the one or more neighboring blocks of the 2D frame include one or more blocks that are adjacent to the first block of the 2D frame only in the 360 ​​video space; a prioritizer, communicatively coupled to the display processor, for prioritizing transmission of the groups of 2D frames based on the identified regions of interest; and a format detector, communicatively coupled to the display processor, for detecting a 360 video format of the 2D frame based on image content of the 2D frame, The first block of the 2D frame and the one or more adjacent blocks of the 2D frame are equidistant from a same point in the 2D frame, and the same point is a corner of two surfaces of the 2D frame.

2. The system of claim 1, further comprising: a 360 video capture device, communicatively coupled to the display processor, for capturing 360 video content; as well as A context tagger is communicatively coupled to the 360 ​​video capture device and is configured to tag the 360 ​​video content with context information contemporary with the captured 360 video content.

3. The system of claim 2, wherein: The context information includes one or more of motion information, position information, speed information, acceleration information, orientation information, and direction information.

4. The system of claim 1, wherein: The encoding information includes one or more of motion vector information and mode information.

5. The system of claim 1, wherein: The prioritizer is further configured to prioritize encoding of a second block of the 2D frame based on the identified region of interest.

6. The system of claim 1, wherein: The detected 360 video formats include one or more of a fisheye format, an equirectangular projection format, a cube map format, and a packed cube map format.

7. A graphics device comprising: An encoder configured to encode a first block of a two-dimensional (2D) frame, wherein the 2D frame corresponds to a projection of a 360 video space; and a component predictor, communicatively coupled to the encoder, for determining whether the first block is a neighbor of a second block of the 2D frame in the 360 ​​video space, and for predicting an encoded component of the second block based on the encoded information of the first block if the first block is determined to be the neighbor of the second block in the 360 ​​video space, The first block and the second block are equidistant from a same point in the 2D frame, and the same point is a corner of two surfaces of the 2D frame.

8. The device of claim 7, wherein: The component predictor is further configured to predict a motion vector of the second block based on the encoded motion vector information of the first block if the first block is determined to be the neighbor of the second block in the 360 ​​video space.

9. The device of claim 7, wherein: The component predictor is further configured to predict a mode of the second block based on the encoded mode information of the first block if the first block is determined to be the neighbor of the second block in the 360 ​​video space.

10. The device of claim 7, wherein: The encoder is further configured to encode the second block of the 2D frame based on the predicted coding component.

11. The apparatus of claim 7, further comprising: A prioritizer, communicatively coupled to the encoder, is configured to prioritize transmission of packets of the 2D frame based on the identified regions of interest.

12. The apparatus of claim 7, further comprising: A format detector is communicatively coupled to the encoder and is configured to detect a 360 video format of the 2D frame based on image content of the 2D frame.

13. The apparatus of claim 7, further comprising: a 360 video capture device, communicatively coupled to the encoder, for capturing 360 video content; as well as A context tagger is communicatively coupled to the 360 ​​video capture device and is configured to tag the 360 ​​video content with context information contemporary with the captured 360 video content.

14. A method for processing 360 video, the method comprising: Encoding a first block of a two-dimensional (2D) frame, wherein the 2D frame corresponds to a projection of a 360 video space; determining whether the first block is a neighbor of a second block of the 2D frame in the 360 ​​video space; and If the first block is determined to be the neighbor of the second block in the 360 ​​video space, predicting a coding component of the second block based on the coding information of the first block, The first block and the second block are equidistant from a same point in the 2D frame, and the same point is a corner of two surfaces of the 2D frame.

15. The method of claim 14, further comprising: If the first block is determined to be the neighbor of the second block in the 360 ​​video space, a motion vector of the second block is predicted based on the encoded motion vector information of the first block.

16. The method of claim 14, further comprising: If the first block is determined to be the neighbor of the second block in the 360 ​​video space, a mode of the second block is predicted based on the encoded mode information of the first block.

17. The method of claim 14, further comprising: The second block of the 2D frame is encoded based on the predicted coded component.

18. A graphics device comprising: Means for encoding a first block of a two-dimensional (2D) frame, wherein the 2D frame corresponds to a projection of a 360 video space; means for determining whether the first block is a neighbor of a second block of the 2D frame in the 360 ​​video space; and means for predicting a coding component of the second block based on the coding information of the first block if the first block is determined to be the neighbor of the second block in the 360 ​​video space, The first block and the second block are equidistant from a same point in the 2D frame, and the same point is a corner of two surfaces of the 2D frame.

19. The apparatus of claim 18, further comprising: Means for predicting a motion vector of the second block based on the encoded motion vector information of the first block if the first block is determined to be the neighbor of the second block in the 360 ​​video space.

20. The apparatus of claim 18, further comprising: Means for predicting a mode of the second block based on the encoded mode information of the first block if the first block is determined to be the neighbor of the second block in the 360 ​​video space.

21. The apparatus of claim 18, further comprising: Means for encoding the second block of the 2D frame based on the predicted coding component.

22. A graphics device comprising: a region identifier for identifying a region of interest in a 2D frame corresponding to a projection of the 360 ​​video; and a prioritizer, communicatively coupled to the region identifier, for prioritizing transmission of the groups of 2D frames based on the identified regions of interest, The neighboring blocks of the 2D frame can be found based on corners of two surfaces of the 2D frame, wherein the neighboring blocks of the 2D frame are equidistant from the corners.

23. The apparatus of claim 22, wherein: The prioritizer is further configured to prioritize encoding of one or more blocks of the 2D frame based on the identified region of interest.

24. The apparatus of claim 23, further comprising: an encoder, communicatively coupled to the prioritizer, for encoding the prioritized one or more blocks of the 2D frame; as well as A packetizer, communicatively coupled to the encoder, is configured to assemble the prioritized packets from the encoded prioritized one or more blocks of the 2D frame.

25. The apparatus of claim 24, further comprising: A transmitter, communicatively coupled to the packetizer, is configured to transmit the prioritized packets.

26. A computer readable medium having stored thereon instructions which, when executed by a computer processor, cause the processor to perform the method of any one of claims 14 to 17.

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