Exploiting Dense Digital Arithmetic Circuits for Fixed-Point Machine Learning

Abstract

Systems and methods are directed to improving the throughput of a neural network in an integrated circuit by combining values ​​in operands to increase computational density. The system includes an integrated circuit (IC) having a multiplier circuit. The IC receives a first value and a second value in a first operand. The IC performs a multiplication operation on the first operand and the second operand via the multiplier circuit to produce a first multiplied product based at least in part on the first value and a second multiplied product based at least in part on the second value.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is a non-provisional application claiming priority to U.S. Provisional Patent Application No. 62 / 488,636, filed on April 21, 2017, entitled “Lower Precision Neural Network Systems and Methods,” the entire contents of which are incorporated by reference for all purposes. Background Art

[0003] The present disclosure generally relates to efficient utilization of arithmetic circuits (e.g., multiply-accumulate circuits and / or digital signal processor (DSP) circuits) in integrated circuits for machine learning.

[0004] This section is intended to introduce the reader to various aspects of the art that may be related to the various aspects of the present disclosure described and / or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Therefore, it is understood that these statements should be read in this light and not as prior art.

[0005] Integrated circuits, such as field programmable gate arrays (FPGAs), can include circuitry for performing various mathematical operations. For example, a deep learning neural network can be implemented in one or more integrated circuit devices for machine learning applications. The integrated circuit devices can perform several operations to output results for the neural network. However, in some instances, the throughput of the mathematical operations in the neural network may be limited by the hardware of the integrated circuit. Due to these limitations, the neural network may execute at a slower rate than desired. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure may be better understood upon reading the following detailed description and upon reference to the accompanying drawings, in which:

[0007] Figure 1 is a block diagram of a data processing system that performs machine learning via machine learning circuitry according to an embodiment;

[0008] Figure 2 According to the embodiment Figure 1 Block diagram of the machine learning circuit;

[0009] Figure 3 According to an embodiment, Figure 1 A network diagram of a neural network where a machine learning circuit performs a task;

[0010] Figure 4 According to the embodiment Figure 1A flowchart of the process performed by the machine learning circuit;

[0011] Figure 5 According to an embodiment, Figure 1 A diagram of another neural network whose machine learning circuit performs a task;

[0012] Figure 6 According to the embodiment Figure 1 A block diagram of the data structure for the multiplication operation performed by the machine learning circuit;

[0013] Figure 7 is a method for performing a multiplication operation according to an embodiment Figure 1 Block diagram of the machine learning circuit;

[0014] Figure 8 According to the embodiment Figure 1 A block diagram of a generalized data structure for a multiplication operation performed by a machine learning circuit;

[0015] Figure 9 is a method for performing a generalized multiplication operation according to an embodiment Figure 1 Block diagram of the machine learning circuit;

[0016] Figure 10 According to the embodiment Figure 1 A block diagram of another data structure for performing a multiplication operation on a machine learning circuit; and

[0017] Figure 11 According to the embodiment Figure 1 Flowchart of a process performed by machine learning circuitry to perform multiplication operations for a neural network. DETAILED DESCRIPTION

[0018] One or more specific embodiments will be described below. In order to provide a concise description of these embodiments, not all features of the actual implementation are described in the specification. It will be appreciated that in the development of any such actual implementation (as in any engineering or design project), several implementation-specific decisions must be made to achieve the developer's specific goals, for example, to meet system-related constraints and business-related constraints, which may vary from one implementation to another. Furthermore, it will be appreciated that such development efforts may be complex and time-consuming, but nonetheless will be a routine task of design, fabrication, and manufacturing for those of ordinary skill in the art who benefit from this disclosure.

[0019] Machine learning is used in various settings to perform tasks through the use of examples. For example, a neural network can be used to perform a task without requiring task-specific programming. That is, a neural network can be trained from previous data to classify or infer information from current data. For example, training data can be used to identify images containing an object by analyzing other images that contain the object and those that do not. While images are used as examples, this is meant to be illustrative only, and any suitable neural network task can be performed in the embodiments described below.

[0020] Configurable devices, such as programmable logic devices (PLDs), can perform one or more operations to perform tasks via machine learning. For example, an integrated circuit (IC), such as a field programmable gate array (FPGA), can include one or more digital signal processing (DSP) blocks or DSP circuits, each with one or more specialized processing blocks to perform arithmetic operations on data received by the DSP blocks. One type of specialized processing block within a DSP block may be a multiply-accumulate (MAC) block or MAC circuit, which includes one or more multiplier circuits and / or one or more accumulator circuits. For example, in some FPGAs, a MAC block may be a hardened intellectual property (IP) block with specialized multiplication circuits coupled to specialized adder circuits. Examples of operations performed by a MAC block include dot products, vector multiplications, and the like. As described below, one or more multipliers of a DSP block can be used to perform neural network arithmetic operations during the classification or inference phases. However, the throughput of a digital signal processor (DSP) may be limited by the IC's hardware. For example, the number of MAC blocks may limit the IC's performance (e.g., speed) in performing neural network arithmetic operations.

[0021] Some arithmetic operations in a neural network may not involve the same precision as that designed to be processed in a MAC block. For example, a MAC block may include circuitry to process 18-bit operands, but a neural network may involve multiplying lower-precision 6-bit operands. The systems and methods described below improve neural network performance in an IC by better utilizing operand capacity in multiplication operations. By combining more than one quantity into each operand of a multiplication operation, the speed of MAC operations (e.g., weighting and summing) performed by a MAC block of an IC in a neural network application can be increased. For example, two or more quantities can be packed into a first operand received by a multiplier circuit. Two or more quantities can be packed into a second operand received by the multiplier circuit. The multiplier circuit can then perform a multiplication operation between the first operand and the second operand to determine the product between each of the corresponding quantities. The multiplier circuit can then output each of the products to be accumulated. To prevent multiplication overflow, a gap can be included between each of the quantities combined in the operand.

[0022] Furthermore, to reduce the likelihood of accumulation overflow, the accumulator circuit of the MAC block can be bypassed to a soft logic accumulator. That is, the multiplication of the MAC operation can be performed in a hardened multiplier dedicated to performing multiplication and accumulation, and the accumulation of the MAC operation can be performed in soft logic to prevent overflow due to accumulating several products output from the multiplication.

[0023] Taking the above into consideration, Figure 1 A block diagram of a data processing system 10 that can be used to perform one or more tasks via machine learning is shown. Data processing system 10 may include a processor 12 operably coupled to a memory 14. Processor 10 may execute one or more instructions stored on memory 14 to perform one or more tasks. Data processing system 10 may include a network interface 16 to send and / or receive data via a network to communicate with other electronic devices. Data processing system 10 may include one or more input / output (I / O) 18 that may be used to receive data via I / O devices such as a keyboard, mouse, display, buttons, or other controls. Data processing system 10 may include machine learning circuitry 20 that uses machine learning methods and techniques to perform one or more tasks. Machine learning circuitry 20 may include a PLD, such as an FPGA. Each of processor 12, memory 14, network interface 16, I / O 18, and machine learning circuitry 20 may be communicatively coupled to one another via interconnect circuitry 22, such as a communication bus.

[0024] The hardware of the machine learning circuit 20 may perform one or more tasks using the neural networks 100 and 138. Turning now to a more detailed discussion of an example of the machine learning circuit 20, Figure 2An IC 30 is shown, which may be a programmable logic device, such as a field programmable gate array (FPGA) 32. For the purposes of this example, the device is referred to as IC 30, but it should be understood that the device may be any suitable type of device that may be used (e.g., an application specific standard product). As shown, IC 30 may have input / output circuitry 34 for driving signals out of IC 30 and receiving signals from other devices via input / output pins 36. Interconnect resources 38 (e.g., global and local, vertical and horizontal wires and buses) may be used to route signals on IC 30. In addition, interconnect resources 38 may include fixed interconnects (wires) and programmable interconnects (i.e., programmable connections between corresponding fixed interconnects). Programmable logic 40 may include combinational and sequential logic circuits. For example, programmable logic 40 may include lookup tables, registers, and multiplexers. In various embodiments, programmable logic 40 may be configured to perform custom logic functions. The programmable interconnects associated with the interconnect resources may be considered part of programmable logic 40. IC 30 may include a programmable element 42 having programmable logic 40. Programmable elements 42 may be based on any suitable programmable technology, such as fuses, antifuses, electrically programmable read-only memory technology, random access memory cells, mask-programmed elements, and the like.

[0025] The circuitry of IC 30 may be organized using any suitable architecture. As an example, the logic of IC 30 may be organized in a series of rows and columns of larger programmable logic regions, each of which may have multiple smaller logic regions. The logic resources of IC 30 may be interconnected via interconnect resources 38, such as associated vertical and horizontal conductors. For example, in some embodiments, these conductors may include global wires that span substantially all of IC 30, fractional wires such as half-wires or quarter-wires that span portions of IC 30, staggered wires of a specific length (e.g., sufficient to interconnect several logic regions), smaller local wires, or any other suitable arrangement of interconnect resources. Furthermore, in other embodiments, the logic of IC 30 may be arranged in more hierarchies or layers, where multiple large regions are interconnected to form larger logic sections. Furthermore, other device arrangements may use logic that is not arranged in a manner other than rows and columns. As explained below, machine learning circuitry 20 may use the hardware of IC 30 to perform one or more tasks. For example, machine learning circuitry 20 may utilize arithmetic logic circuitry to perform arithmetic operations used in machine learning methods and techniques.

[0026] Figure 31 is a network diagram of an example of a machine learning network (e.g., neural network 100) that can be used to perform one or more tasks on machine learning circuitry 20. Although neural network 100 is described in detail as an example, any suitable machine learning methods and techniques can be used. Neural network 100 includes a set of inputs 102, 103, 104, and 106, a set of weights 108, 109, 110, and 112, a set of sums 114 and 115, and a result value 116. Each of inputs 102, 103, 104, and 106 is weighted using a corresponding weight to determine a corresponding weighted value 108, 109, 110, and 112. Weighted values ​​108 and 109 can be summed at sum 114, and weighted values ​​110 and 112 can be summed at sum 115. Result value 116 can be output from sums 114 and 115 and used to perform one or more tasks from previous data. While four inputs and two sums are shown, this is intended to be illustrative, and any suitable combination of inputs, weights, sums, and connections therebetween may be used.

[0027] Figure 4 is a flow diagram of a process 130 that may be performed on IC 30 in conjunction with neural network 100. At block 132, IC 30 may perform training, wherein weight values ​​108, 109, 110, and 112 are determined and / or adjusted so that the weights applied to inputs 102, 103, 104, and 106 indicate the likelihood that the respective inputs 102, 103, 104, and 106 predict an outcome value 116.

[0028] When training neural network 100, IC 30 may perform deduction and / or classification on new data at block 134. In an example involving, for example, image recognition, neural network 100 may be trained using images of shapes (e.g., circles, triangles, squares), where the shapes in the images are known. Then, after adjusting the weights based on the training data, IC 30 may use neural network 100 to classify the shapes of new data. By adjusting the weights applied to inputs 102, 103, 104, and 106 based on the training data, weights may be obtained that, when applied to a new image, reflect the likelihood that the corresponding input of the new image includes a particular shape. In some embodiments, continuous learning may occur, where new data is then validated and the weights are continuously adjusted. Each of blocks 134 may be performed via machine learning circuitry 20, and / or some operations in each of blocks 134 may be performed via processor 12.

[0029] Figure 51 is a network diagram of an example of a neural network 138 having an input layer 140, one or more computational layers 142, and an output layer 144. The illustrated embodiment may be referred to as a deep neural network due to having more than one computational layer 142 (also referred to as a hidden layer). As the number of computational layers 142 increases, the complexity and processing of the inputs increases. In the illustrated embodiment, each input is weighted and summed at four sums, and then each corresponding sum is weighted and summed at three sums, which are then used to output a result value.

[0030] As explained below, the circuitry of IC 30 may also include one or more DSP blocks. The DSP blocks may include one or more (multiply-accumulate) MAC blocks or MAC circuits. Each MAC block may include hardened circuitry (e.g., multiplier circuitry and accumulator circuitry) designed and specialized for performing multiplication and accumulation operations. While a MAC block may include circuitry that performs multiplication and accumulation on inputs with a specific amount of precision, neural network 100 may have inputs 102, 103, 104, and 106 and weights with lower precision than the circuitry of the MAC block. For example, while neural network 100 may utilize weights and inputs 102, 103, 104, and 106 with six bits of precision, the MAC block may include circuitry designed to process eighteen-bit inputs. By combining more than one value from neural network 100 into the same operand of a MAC block, each multiplication of the MAC block may process additional values ​​associated with neural network 100, thereby increasing the throughput of neural network 100.

[0031] Figure 6 206. The IC 30 may combine a first value 204 and a second value 206 into a first operand 208. That is, the IC 30 may pack each bit of the first value 204 and each bit of the second value 206 into the first operand 208. For example, a first component of the first operand 208 (e.g., a first group of bits) may represent the first value 204, and a second component of the first operand 208 (e.g., a second group of bits) may represent the second value 206. Furthermore, the operand 208 may include a gap between the first value 204 and the second value 206 to prevent overflow. For example, the gap 210 may be at least the number of bits of the first value 204 or the second value 206. The first value 204 may be the first input 102, and the second value 206 may be the second input 104.

[0032] Similarly, IC 30 may combine third value 212 and fourth value 214 into a second operand 216. Second operand 216 may include a gap 218 between third value 212 and fourth value 214 to prevent overflow. Gap 218 may be at least the number of bits of third value 212 or fourth value 214. In the example described above where neural network 100 utilizes six bits of precision, first value 204, second value 206, third value 212, fourth value 214, and gaps 210 and 218 may each be six bits. Third value 212 may be a first weight to be applied to first input 102, and fourth value 106 may be a second weight to be applied to second input 104.

[0033] IC 30 can perform a multiplication operation on first operand 208 and second operand 216 such that multiplied product 230 includes first product 232 of first value 204 multiplied by third value 212 and second product 234 of second value 206 multiplied by fourth value 214 from the same multiplication operation. That is, by combining or packing more than one value into each operand 208 and 216 with sufficient gaps 210 and 218 between the values, multiplied product 230 can include each corresponding product without overflow. For example, in neural network 100, first product 232 can be weighted value 108 from applying a first weight to first input 102, and second product 234 can be second weighted value 110 from applying a second weight to second input 104. By combining values ​​from neural network 100 into each operand 208 and 216, result value 116 can be determined at a faster rate due to increased throughput.

[0034] Each of the first product 232 and the second product 234 can then be split from the multiplied product 230 and accumulated. Because accumulation can be a faster operation than multiplication, the performance of the neural network 100 can be improved by using more available precision in the hardened multiplier circuitry of the IC 30 to determine more than one product from a single multiplication operation. In addition, the hardened circuitry of the MAC block in the IC 30 can be dedicated to performing multiplications to determine the weight values ​​108, 109, 110, and 112 at a faster rate than circuitry that performs multiplications in soft logic due to the specialization of the hardened circuitry.

[0035] Figure 7 Is the implementation of Figure 61 is a block diagram of circuitry of IC 30 for performing arithmetic operations as described herein. IC 30 may include a DSP block 250 having a first input circuit 252 and a second input circuit 254 that receive a first operand 208 and a second operand 216, respectively. DSP block 250 may include a MAC block 260 having a multiplier circuit 262 that multiplies first operand 208 and second operand 216 and outputs the product. That is, multiplier circuit 262 may be designed or hardened using circuitry that performs multiplication operations on operands of a particular precision. By including more than one value having a lower precision than the designed operand precision in the operands before performing the multiplication operation, more than one product may be determined from the multiplication operation.

[0036] In some embodiments, MAC block 260 may include adder circuitry 264 that may add the products from multiplier circuitry 262. Upon completing the MAC operation, MAC block 260 may output the result via output circuitry 268. In the embodiment shown, IC 30 may include more than one DSP block 250 (e.g., 2, 3, 4, 5, or more), and each DSP block may include more than one MAC block 252 (e.g., 2, 3, 4, 5, 10, 20, 50, or more).

[0037] MAC block 252 may include a bypass circuit 270 (e.g., a multiplexer) to bypass adder 264 and provide the multiplied product 230 to soft logic 274 of IC 30. Furthermore, IC 30 may then perform the sums 114 and 115 of the neural network in the soft logic 274 of IC 30. Soft logic 274 may refer to programmed instructions (e.g., code) stored in memory on IC 30 for performing operations of IC 30. IC 30 may be programmed to execute instructions to split first product 232 and second product 234 from the multiplied product 230. IC 30 may then execute instructions to accumulate 276 the first product (e.g., first weighted value 108) with one or more other products (e.g., weighted values ​​108) to determine a total based on sum 114. IC 30 may execute an instruction to accumulate 278 the second product (e.g., weighted value 110) with one or more other products (e.g., weighted value 112). For example, the first product (e.g., weighted value 108) may be retained at block 282. IC 30 may then perform another multiplication to determine third and fourth products (e.g., weighted values ​​109 and 112) by combining the fifth and sixth values ​​(e.g., inputs 103 and 106) into a third operand and combining the seventh and eighth values ​​(e.g., weights of the respective inputs) into a fourth operand. The third and fourth products (e.g., weighted values ​​109 and 112) are then added to each of the respective retained totals (282 and 284). By implementing the accumulator in soft logic 274, more accumulation operations can be performed with less or no risk of overflow. By moving to a neural network with less precision than the six-bit example, IC 30 can obtain additional products in each multiplication operation.

[0038] Figure 8 is a more generalized example of a data structure 300 used when performing a multiplication operation in neural network 100 on IC 30. IC 30 can group values ​​A[0] through A[n] into a first operand. Similarly, IC 30 can group values ​​B[0] through B[n] into a second operand. Each of values ​​302 and 306 can be separated from the other values ​​302 and 306 by gaps 304 and 308 to prevent overflow.

[0039] When performing a multiplication operation, the product of the multiplication 310 may include a set of multiplied values ​​312 C[0] through C[n] from multiplying each corresponding value of A through B. The lower level of precision of the neural network may allow for the inclusion of additional values ​​in each multiplication operation. For example, in an 18-bit multiplication operation, the following table may reflect the level of precision with respect to the number of values ​​in each operand:

[0040] Precision (bits) Calculation improvements (low precision - 18 bits) 1 9x 2 5x 3 3x 4 2x 5 2x 6 2x

[0041] This relationship can be further generalized according to the following equation:

[0042]

[0043] Among them, num comp Refers to the number of values ​​that can be included in each operand, Width Mult refers to the number of bits in each operand, and precision refers to the number of bits used in operations in neural network 100.

[0044] Figure 9 is used Figure 8 Data structure execution Figure 3 A generalized block diagram of the circuit of IC 30 for performing arithmetic operations on a neural network. IC 30 includes circuits related to Figure 7 Furthermore, an additional accumulator (eg, in code) may be used for each of the values ​​312 in the multiplied product 310 .

[0045] Figure 10 Can be combined with about Figure 9 A block diagram of another data structure 324 used by the described circuitry is shown. Data structure 324 includes a first operand having N values ​​326 A[0] through A[n] with gaps 328 between each of the values ​​326. Data structure 324 includes a second operand having a single value B[0] 330 and padding 332 throughout the remainder of the first operand. The single value B[0] may have the same precision as each of the N values ​​of the first operand. When performing a multiplication operation, IC 30 may determine a first multiplied product 334 by multiplying the first value A[0] of the first operand by B[0] 330. IC 30 may determine a second multiplied product 334 by multiplying the second value A[1] of the first operand by B[0] 330. That is, B[0] 330 may be multiplied by each of the N values ​​326 of the first operand.

[0046] Figure 11 It is a combination Figure 5 and Figure 6 100 to perform an arithmetic operation of the neural network 100 to output a result value 116. At block 342, the IC 30 may combine (e.g., pack) the first value and the second value into a first operand. In some embodiments, the IC 30 may combine (e.g., pack) the third value and the fourth value into a second operand. As described above with respect to Figure 8 and Figure 9 As mentioned, additional values ​​may be included in each of the first operand and the second operand. Figure 10In the particular embodiment described, IC 30 may have only a single value in the second operand. At block 344, IC 30 may multiply the first operand with the second operand to determine a first multiplied product based at least in part on the first value and a second multiplied product based at least in part on the second value. In examples where the second operand includes a third value and a fourth value, for example, the first multiplied product may be the first value multiplied by the third value, and the second multiplied product may be the second value multiplied by the fourth value. In this manner, more than one multiplied product may be determined from the same multiplication operation performed by the hardened multiplier circuit. In some embodiments, the multiplication operation may be performed in the hardened multiplier circuit, and a result of the multiplication including both the first multiplied product and the second multiplied product may be output to soft logic, where the first multiplied product and the second multiplied product may be separated from each other.

[0047] In some embodiments, at block 346, the IC 30 may perform a correction operation (e.g., in soft logic) to correct for any conflicts in the multiplication operations. For example, if the product of the first multiplication overlaps with the product of the second multiplication due to overflow, the IC 30 may perform an exclusive OR (XOR) operation, a masking operation, etc. to correct for the overlapping values. At block 348, the IC 30 may then add the product of the first multiplication, the product of the second multiplication, or both to at least one sum. For example, the product of the first multiplication and the product of the second multiplication may be added to the same sum 114, or each product may be added to a different sum 114 and 115, respectively. At block 350, the IC 30 may output a result value based at least in part on the at least one sum. That is, the result value may come from the sum of the two sums 114 and 115 (as in Figure 3 ), or the resulting value can be determined after several computation layers (as in Figure 5 Result value 116 may be output (e.g., via I / O pin 36) to control the operation of IC 30. In some embodiments, result value 116 may be displayed to a user. In other embodiments, result value 116 may be sent to another electronic device. By combining lower-precision values ​​into operands having a greater design precision than the lower-precision values, throughput through the neural network may be increased.

[0048] Although the embodiments described in this disclosure may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and described in detail herein. However, it will be understood that the disclosure is not intended to be limited to the specific forms disclosed. The disclosure encompasses all modifications, equivalents, and alternatives falling within the spirit and scope of the disclosure as defined by the appended claims.

Claims

1. An integrated circuit device comprising: a first input circuit of a hardened multiplier, wherein the first input circuit is configured to receive a first operand, wherein a first component of the first operand comprises a first value and a second component of the first operand comprises a second value; a second input circuit of the hardened multiplier, wherein the second input circuit is configured to receive a second operand, wherein a first component of the second operand comprises a third value; multiplication circuitry of the hardened multiplier, wherein the multiplication circuitry is configured to multiply the first operand and the second operand in a single multiplication operation to produce a product, the product comprising a plurality of results equal to corresponding plurality of different multiplication operations, wherein the product comprises a first component comprising a first result of the plurality of results, wherein the first result is equal to a first multiplication operation based on the first value, and wherein the product comprises a second component comprising a second result of the plurality of results, wherein the second result is equal to a second multiplication operation based on the second value, wherein the integrated circuit device comprises soft logic circuitry configured to determine a first accumulated value based at least in part on the first result and a second accumulated value based at least in part on the second result; and A bypass circuit is configured to bypass the hardened adder circuit of the integrated circuit device to the soft logic circuit.

2. The integrated circuit device according to claim 1, wherein The multiplication circuit is configured to perform the multiplication operation via a digital signal processing (DSP) circuit.

3. The integrated circuit device according to claim 1 or 2, wherein: The first value and the second value each have a lower precision than a precision of the first operand and the second operand.

4. The integrated circuit device according to claim 1 or 2, wherein: The first value has a single bit of precision.

5. The integrated circuit device according to claim 1 or 2, wherein: The first result comprises a weighted value of a neural network, wherein the first value comprises an input to the neural network and the third value comprises a weight of the neural network.

6. The integrated circuit device according to claim 1 or 2, wherein: The first operand includes a gap between the first value and the second value to prevent or reduce overflow in the first multiplied value or the second multiplied value.

7. The integrated circuit device according to claim 1 or 2, wherein: The integrated circuit device is configured to perform a correction operation to correct any conflicts caused by the multiplication operation, wherein the correction operation includes an exclusive-OR (XOR) operation, a masking operation, or any combination thereof.

8. An integrated circuit comprising: A hardened multiplier configured as: receiving a first operand comprising one or more bits associated with a first value and one or more bits associated with a second value; and multiplying the first operand and a second operand to determine a first multiplied product based at least in part on the first value and a second multiplied product based at least in part on the second value, wherein the second operand includes one or more bits associated with a third value and one or more bits associated with a fourth value; A soft logic circuit configured to: receiving a product of the first multiplication and a product of the second multiplication; accumulating a first total based at least in part on the products of the first multiplications; accumulating a second total based at least in part on the product of the second multiplication; and outputting the first total and the second total; and A hardened accumulator is provided, wherein the hardened accumulator is bypassed to the soft logic circuit via a bypass circuit.

9. The integrated circuit according to claim 8, wherein: The first value and the second value of the first operand are spaced sufficiently far apart in the operation of the hardened multiplier to reduce the likelihood of overflow.

10. An integrated circuit according to claim 8 or 9, comprising digital signal processing (DSP) circuitry having the hardened multiplier and the hardened accumulator.

11. The integrated circuit according to claim 8 or 9, wherein: The soft logic circuit is configured to output a signal indicative of the first total, the second total, or both via an I / O pin of the integrated circuit.

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