Coordination and increased utilization of a graphics processor during inference

Abstract

Describe a mechanism for promoting inference coordination and processing utilization of machine learning at an autonomous machine. As described herein, one method of an embodiment includes: detecting, during training, information related to one or more tasks to be performed based on a training data set associated with a processor including a graphics processor. The method may further include: analyzing the information to determine one or more portions of the hardware associated with the processor that can support the one or more tasks; and configuring the hardware to pre-select the one or more portions to perform the one or more tasks, while other portions of the hardware remain available for other tasks.

Description

Technical Field

[0001] The embodiments described herein generally relate to data processing, and more particularly to a tool for facilitating the coordination and increased utilization of a graphics processor during inference. Background Art

[0002] Current parallel graphics data processing includes systems and methods developed for performing specific operations on graphics data, such as, for example, linear interpolation, tessellation, rasterization, texture mapping, depth testing, etc. Traditionally, graphics processors used fixed function computing units to process graphics data, however, more recently, multiple parts of graphics processors have become programmable, enabling such processors to support a wider variety of operations for processing vertex and fragment data.

[0003] To further improve performance, graphics processors typically implement processing techniques such as pipelining operations, which attempt to process as much graphics data as possible in parallel through different parts of the graphics pipeline. Parallel graphics processors with a single instruction multiple thread (SIMT) architecture are designed to maximize the amount of parallel processing in the graphics pipeline. In the SIMT architecture, multiple groups of parallel threads attempt to synchronously execute program instructions together as often as possible to improve processing efficiency. A general overview of the software and hardware for the SIMT architecture can be found in either: CUDA Programming by Shane Cook, Chapter 3, pages 37 to 51 (2013) and / or CUDA Handbook by Nicholas Wilt (A Comprehensive Guide to GPU Programming), Sections 2.6.2 to 3.1.2 (June 2013).

[0004] Machine learning has been successful in solving many kinds of tasks. The computations generated when training and using machine learning algorithms (e.g., neural networks) make them naturally amenable to efficient parallel implementation. Thus, parallel processors such as general purpose graphics processing units (GPGPUs) play an important role in the practical implementation of deep neural networks. Parallel graphics processors with a single instruction multiple thread (SIMT) architecture are designed to maximize the amount of parallel processing in the graphics pipeline. In the SIMT architecture, multiple groups of parallel threads attempt to synchronously execute program instructions together as often as possible to improve processing efficiency. The efficiency provided by the parallel implementation of machine learning algorithms allows the use of large-capacity networks and enables those networks to be trained on larger data sets.

[0005] Conventional techniques do not provide coordination between the inference output and the sensors responsible for providing the input; however, such conventional techniques do not provide the accuracy of the inference output. In addition, the use of inference on the graphics processor is quite limited, while the remaining graphics processors are not utilized. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The embodiments are shown in the drawings in an illustrative, not restrictive, manner, in which like reference numerals refer to like elements. Thus, the features described above, the more specific description briefly outlined above, may have been described with reference to embodiments, some of which are shown in the drawings. It should be noted, however, that the drawings only show typical embodiments and should not be considered as limiting their scope, as the drawings may show other equally effective embodiments.

[0007] Figure 1 is a block diagram of a computer system configured to implement one or more aspects of the embodiments described herein.

[0008] Figures 2A to 2D shows a parallel processor component according to an embodiment.

[0009] Figures 3A to 3B is a block diagram of a graphics multiprocessor according to an embodiment.

[0010] Figures 4A to 4F shows an exemplary architecture in which a plurality of graphics processing units are communicatively coupled to a plurality of multi-core processors.

[0011] Figure 5 shows a graphics processing pipeline according to an embodiment.

[0012] Figure 6 shows a computing device that hosts an inference coordination and processing utilization mechanism according to an embodiment.

[0013] Figure 7 shows an inference coordination and processing utilization mechanism according to an embodiment.

[0014] Figure 8A shows a transaction framework at an application and / or graphics processor for facilitating pre-analysis training according to an embodiment.

[0015] Figure 8B shows a graphics processor for improved processing utilization according to an embodiment.

[0016] Figure 8C shows a transaction sequence for improved coordination of inference output and sensors according to an embodiment.

[0017] Figure 8DShows a transaction sequence for inferring an output with improved coordination with a sensor, according to one embodiment.

[0018] Figure 9A And Figure 9B Shows a transaction sequence illustrating the use of a model, according to one embodiment.

[0019] Figure 9C Shows a diagram illustrating prioritization options, according to one embodiment.

[0020] Figure 10 Shows a machine learning software stack, according to an embodiment.

[0021] Figure 11 Shows a highly parallel general-purpose graphics processing unit, according to an embodiment.

[0022] Figure 12 Shows a multi-GPU computing system, according to an embodiment.

[0023] Figures 13A to 13B Shows the layers of an exemplary deep neural network.

[0024] Figure 14 Shows the training and deployment of a deep neural network.

[0025] Figure 15 Shows the training and deployment of a deep neural network.

[0026] Figure 16 Is a block diagram showing distributed learning.

[0027] Figure 17 Shows an exemplary inference chip on a system (SOC) suitable for performing inference using a trained model.

[0028] Figure 18 Is a block diagram of an embodiment of a computer system having a processor with one or more processor cores and a graphics processor.

[0029] Figure 19 Is a block diagram of an embodiment of a processor having one or more processor cores, an integrated memory controller, and an integrated graphics processor.

[0030] Figure 20 Is a block diagram of an embodiment of a graphics processor, which can be a discrete graphics processing unit or a graphics processor integrated with multiple processing cores.

[0031] Figure 21 Is a block diagram of an embodiment of a graphics processing engine for a graphics processor.

[0032] Figure 22It is a block diagram of another embodiment of a graphics processing unit.

[0033] Figure 23 It is a block diagram of thread execution logic including an array of processing elements.

[0034] Figure 24 Shows a graphics processing unit execution unit instruction format according to an embodiment.

[0035] Figure 25 It is a block diagram of another embodiment of a graphics processing unit, the graphics processing unit including a graphics pipeline, a media pipeline, a display engine, thread execution logic, and a rendering output pipeline.

[0036] Figure 26A It is a block diagram showing a graphics processing unit command format according to an embodiment.

[0037] Figure 26B It is a block diagram showing a graphics processing unit command sequence according to an embodiment.

[0038] Figure 27 Shows an exemplary graphics software architecture of a data processing system according to an embodiment.

[0039] Figure 28 It is a block diagram showing an IP core development system that can be used to fabricate an integrated circuit to perform operations according to an embodiment.

[0040] Figure 29 It is a block diagram showing an exemplary system-on-chip integrated circuit that can be fabricated using one or more IP cores according to an embodiment.

[0041] Figure 30 It is a block diagram showing an exemplary graphics processing unit of a system-on-chip integrated circuit.

[0042] Figure 31 It is a block diagram showing an additional exemplary graphics processing unit of a system-on-chip integrated circuit. Detailed Description

[0043] Embodiments provide a new technique for helping to detect frequently used data values and subsequently accelerating operations by using one or more techniques such as look-up tables, simplified mathematics, etc. Embodiments also provide a new technique for introducing a finite state machine, where, in one embodiment, this finite state machine provides pointers to the base addresses of A and B, and the output is a C+ sequence.

[0044] Note that terms or acronyms such as "convolutional neural network", "CNN", "neural network", "NN", "deep neural network", "DNN", "recurrent neural network", "RNN", etc. may be interchangeably referred to throughout this document. Additionally, terms such as "autonomous machine" or simply "machine", "autonomous vehicle" or simply "vehicle", "autonomous agent" or simply "agent", "autonomous device" or "computing device", "robot", etc. may be interchangeably referred to throughout this document.

[0045] In some embodiments, a graphics processing unit (GPU) is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU may be communicatively coupled to the host processor / core via a bus or another interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU may be integrated with the core on the same package or chip and communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside the package or chip). Regardless of how the GPU is connected, the processor core may assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0046] In the following description, numerous specific details are set forth. However, embodiments may be practiced without these specific details as described herein. In other instances, well-known circuits, structures, and techniques have not been shown in detail to avoid obscuring the understanding of this specification.

[0047] System Overview I

[0048] Figure 1is a block diagram showing a computer system 100 configured to implement one or more aspects of the embodiments described herein. The computing system 100 includes a processing subsystem 101 having one or more processors 102 and a system memory 104, the one or more processors and the system memory communicating via an interconnect path that may include a memory hub 105. The memory hub 105 may be a separate component within a chipset component or may be integrated within one or more of the processors 102. The memory hub 105 is coupled to an I / O subsystem 111 via a communication link 106. The I / O subsystem 111 includes an I / O hub 107 that enables the computing system 100 to receive input from one or more input devices 108. Additionally, the I / O hub 107 enables a display controller (which may be included within one or more of the processors 102) to provide output to one or more display devices 110A. In one embodiment, one or more of the display devices 110A coupled to the I / O hub 107 may include a local display device, an internal display device, or an embedded display device.

[0049] In one embodiment, the processing subsystem 101 includes one or more parallel processors 112 that are coupled to the memory hub 105 via a bus or other communication link 113. The communication link 113 may be one of any number of standard-based communication link technologies or protocols (such as, but not limited to, PCI Express), or may be a vendor-specific communication interface or communication fabric. In one embodiment, the one or more parallel processors 112 form a compute-centric parallel or vector processing system that includes a large number of processing cores and / or processing clusters such as an integrated many-core (MIC) processor. In one embodiment, the one or more parallel processors 112 form a graphics processing subsystem that may output pixels to one of the one or more display devices 110A coupled via the I / O hub 107. The one or more parallel processors 112 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 110B.

[0050] Within the I / O subsystem 111, the system storage unit 114 can be connected to the I / O hub 107 to provide a storage mechanism for the computing system 100. The I / O switch 116 can be used to provide an interface mechanism to enable connections between the I / O hub 107 and other components that can be integrated into the platform such as the network adapter 118 and / or the wireless network adapter 119, as well as various other devices that can be added via one or more plug-in devices 120. The network adapter 118 can be an Ethernet adapter or another wired network adapter. The wireless network adapter 119 can include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more radio devices.

[0051] The computing system 100 can include other components not explicitly shown, which include USB or other port connectors, optical storage drives, video capture devices, etc., and can also be connected to the I / O hub 107. Figure 1 The communication paths interconnecting the various components can be implemented using any suitable protocol such as a PCI (Peripheral Component Interconnect)-based protocol (e.g., PCI-Express), or any other bus or point-to-point communication interface and / or protocol such as the NV-Link high-speed interconnect or an interconnect protocol known in the art.

[0052] In one embodiment, one or more parallel processors 112 incorporate circuitry optimized for graphics and video processing, including for example video output circuitry, and the circuitry constitutes a graphics processing unit (GPU). In another embodiment, one or more parallel processors 112 incorporate circuitry optimized for general processing while retaining the underlying computing architecture described in more detail herein. In yet another embodiment, the components of the computing system 100 can be integrated with one or more other system elements on a single integrated circuit. For example, one or more parallel processors 112, the memory hub 105, the (multiple) processors 102, and the I / O hub 107 can be integrated into a system-on-chip (SoC) integrated circuit. Alternatively, the components of the computing system 100 can be integrated into a single package to form a system-in-package (SIP) configuration. In other embodiments, at least a portion of the components of the computing system 100 can be integrated into a multi-chip module (MCM), and the multi-chip module can be interconnected with other multi-chip modules to form a modular computing system.

[0053] It should be understood that the computing system 100 shown herein is illustrative and variations and modifications are possible. The connection topology can be modified as needed, which includes the number and arrangement of bridges, the number of processors 102, and the number of parallel processors 112. For example, in some embodiments, the system memory 104 is connected directly to the processors 102 rather than through a bridge, while other devices communicate with the system memory 104 via the memory hub 105 and the processors 102. In other alternative topologies, the parallel processors 112 are connected to the I / O hub 107 or directly to one of the one or more processors 102, rather than to the memory hub 105. In other embodiments, the I / O hub 107 and the memory hub 105 can be integrated into a single chip. Some embodiments can include two or more groups of processors 102 attached via multiple sockets, and these two or more groups can be coupled to two or more instances of the parallel processors 112.

[0054] Some of the specific components shown herein are optional and may not be included in all implementations of the computing system 100. For example, any number of plug-in cards or peripheral devices can be supported, or some components can be omitted. In addition, some architectures may use different terms to describe components similar to those Figure 1 shown. For example, in some architectures, the memory hub 105 can be referred to as the north bridge, while the I / O hub 107 can be referred to as the south bridge.

[0055] Figure 2A A parallel processor 200 according to an embodiment is shown. Various components of the parallel processor 200 can be implemented using one or more integrated circuit devices such as programmable processors, application specific integrated circuits (ASICs), or field programmable gate arrays (FPGAs). According to an embodiment, the shown parallel processor 200 is Figure 1 a variant of one or more of the parallel processors 112 shown.

[0056] In one embodiment, parallel processor 200 includes parallel processing unit 202. The parallel processing unit includes I / O unit 204 which enables communication with other devices including other instances of parallel processing unit 202. I / O unit 204 can be directly connected to other devices. In one embodiment, I / O unit 204 is connected to other devices via the use of a hub or switch interface such as memory hub 105. The connection between memory hub 105 and I / O unit 204 forms communication link 113. Within parallel processing unit 202, I / O unit 204 is connected to host interface 206 and memory crossbar 216, where host interface 206 receives commands related to the execution of processing operations and memory crossbar 216 receives commands related to the execution of memory operations.

[0057] When host interface 206 receives command buffers via I / O unit 204, host interface 206 can direct the work operations for the execution of those commands to front end 208. In one embodiment, front end 208 is coupled to scheduler 210 which is configured to distribute commands or other work items to processing cluster array 212. In one embodiment, scheduler 210 ensures that processing cluster array 212 is properly configured and in an active state before distributing tasks to the processing clusters within processing cluster array 212.

[0058] Processing cluster array 212 can include up to “N” processing clusters (e.g., cluster 214A, cluster 214B, up to cluster 214N). Each of the clusters 214A through 214N of processing cluster array 212 can execute a large number of concurrent threads. Scheduler 210 can use various scheduling and / or work distribution algorithms to assign work to the clusters 214A through 214N of processing cluster array 212, and these algorithms can vary depending on the workload caused by each type of program or computation. Scheduling can be handled dynamically by scheduler 210 or can be assisted in part by compiler logic during the compilation of program logic configured to be executed by processing cluster array 212.

[0059] In one embodiment, different clusters 214A through 214N of processing cluster array 212 can be assigned to process different types of programs or to perform different types of computations.

[0060] Processing cluster array 212 can be configured to perform various types of parallel processing operations. In one embodiment, processing cluster array 212 is configured to perform general purpose parallel computing operations. For example, processing cluster array 212 can include logic for performing processing tasks including filtering of video and / or audio data, performing modeling operations including physical operations, and performing data transformations.

[0061] In one embodiment, the processing cluster array 212 is configured to perform parallel graphics processing operations. In embodiments in which the parallel processors 200 are configured to perform graphics processing operations, the processing cluster array 212 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. Additionally, the processing cluster array 212 may be configured to execute shader programs related to graphics processing, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. The parallel processing units 202 may transfer data from the system memory via the I / O unit 204 for processing. During processing, the transferred data may be stored in on-chip memory (e.g., the parallel processor memory 222) during processing and then written back to the system memory.

[0062] In one embodiment, when the parallel processing units 202 are used to perform graphics processing, the scheduler 210 may be configured to divide the processing workload into tasks of approximately equal size to better enable the distribution of graphics processing operations to the multiple clusters 214A through 214N of the processing cluster array 212. In some embodiments, portions of the processing cluster array 212 may be configured to perform different types of processing. For example, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations to produce a rendered image for display. Intermediate data generated by one or more of the clusters 214A through 214N may be stored in a buffer to allow the intermediate data to be transferred between the clusters 214A through 214N for further processing.

[0063] During operation, the processing cluster array 212 may receive processing tasks to be executed via the scheduler 210, which receives commands defining the processing tasks from the front end 208. For graphics processing operations, the processing tasks may include data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, as well as indices defining state parameters and commands (e.g., which program to execute) for how to process the data. The scheduler 210 may be configured to obtain the indices corresponding to the tasks or may receive the indices from the front end 208. The front end 208 may be configured to ensure that the processing cluster array 212 is configured in a valid state before the workload specified by the incoming command buffer (e.g., batch buffer, push buffer, etc.) is initiated.

[0064] Each of one or more instances of the parallel processing unit 202 may be coupled to the parallel processor memory 222. The parallel processor memory 222 may be accessed via a memory crossbar 216, which may receive memory requests from the array of processing clusters 212 and the I / O unit 204. The memory crossbar 216 may access the parallel processor memory 222 via a memory interface 218. The memory interface 218 may include a plurality of partitioning units (e.g., partitioning unit 220A, partitioning unit 220B, up to partitioning unit 220N), each of which may be coupled to a portion (e.g., a memory unit) of the parallel processor memory 222. In one implementation, the number of partitioning units 220A to 220N is configured to be equal to the number of memory units, such that the first partitioning unit 220A has a corresponding first memory unit 224A, the second partitioning unit 220B has a corresponding memory unit 224B, and the Nth partitioning unit 220N has a corresponding Nth memory unit 224N. In other embodiments, the number of partitioning units 220A to 220N may not be equal to the number of memory devices.

[0065] In various embodiments, the memory units 224A to 224N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In one embodiment, the memory units 224A to 224N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). Those skilled in the art will understand that the specific implementation of the memory units 224A to 224N may vary and may be selected from one of various conventional designs. Rendering targets such as frame buffers or texture maps may be stored on the memory units 224A to 224N, allowing the partitioning units 220A to 220N to write portions of each rendering target in parallel to efficiently utilize the available bandwidth of the parallel processor memory 222. In some embodiments, to support a unified memory design that utilizes system memory along with local cache memory, local instances of the parallel processor memory 222 may be excluded.

[0066] In one embodiment, any one of clusters 214A through 214N of processing cluster array 212 can process data to be written to any one of memory cells 224A through 224N within parallel processor memory 222. Memory crossbar 216 can be configured to pass the output of each of clusters 214A through 214N to any of partition units 220A through 220N or to another one of clusters 214A through 214N, which can perform additional processing operations on the output. Each of clusters 214A through 214N can communicate with memory interface 218 via memory crossbar 216 for read or write operations to various external memory devices. In one embodiment, memory crossbar 216 can be connected to memory interface 218 to communicate with I / O unit 204 and can be connected to a local instance of parallel processor memory 222 such that processing units within different processing clusters 214A through 214N can communicate with system memory or other memory that is not local to parallel processing unit 202. In one embodiment, memory crossbar 216 can use virtual channels to separate traffic flows between clusters 214A through 214N and partition units 220A through 220N.

[0067] Although a single instance of parallel processing unit 202 is shown within parallel processor 200, any number of instances of parallel processing unit 202 can also be included. For example, multiple instances of parallel processing unit 202 can be provided on a single plug-in card, or multiple plug-in cards can be interconnected. Different instances of parallel processing unit 202 can be configured to interoperate even if they have different numbers of processing cores, different amounts of local parallel processor storage, and / or other configuration differences. For example, and in one embodiment, some instances of parallel processing unit 202 can include floating-point units of higher precision relative to other instances. Systems incorporating one or more instances of parallel processing unit 202 or parallel processor 200 can be implemented in a variety of configurations and form factors, including but not limited to desktop computers, laptop computers or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0068] Figure 2B is a block diagram of partition unit 220 according to an embodiment. In one embodiment, partition unit 220 is Figure 2AAn example of one of the partition units 220A to 220N. As shown, the partition unit 220 includes an L2 cache 221, a frame buffer interface 225, and a ROP 226 (raster operation unit). The L2 cache 221 is a read / write cache configured to perform load and store operations received from the memory crossbar 216 and the ROP 226. Read hit misses and urgent writeback requests are output by the L2 cache 221 to the frame buffer interface 225 for processing. Dirty updates can also be sent via the frame buffer interface 225 to the frame buffer for opportunistic processing. In one embodiment, the frame buffer interface 225 interfaces with one of the memory cells in the parallel processor memory, such as, Figure 2A the memory cells 224A to 224N (e.g., within the parallel processor memory 222).

[0069] In a graphics application, the ROP 226 is a processing unit that performs raster operations such as stencil printing, z-testing, blending, etc. The ROP 226 then outputs the processed graphics data, which is stored in the graphics memory. In some embodiments, the ROP 226 includes compression logic for compressing z or color data written to memory and decompressing z or color data read from memory. In some embodiments, the ROP 226 is included within each processing cluster (e.g., Figure 2A the clusters 214A to 214N), rather than within the partition unit 220. In such embodiments, read and write requests for pixel data are transmitted via the memory crossbar 216 rather than pixel fragment data.

[0070] The processed graphics data can be displayed on one of one or more display devices 110 such as Figure 1 routed by the (one or more) processors 102 for further processing, or routed by Figure 2A one of the processing entities within the parallel processor 200 for further processing.

[0071] Figure 2C is a block diagram of a processing cluster 214 within a parallel processing unit according to an embodiment. In one embodiment, the processing cluster is Figure 2AAn instance of one of the processing clusters 214A - 214N. The processing clusters 214 can be configured to execute multiple threads in parallel, where the term "thread" refers to an instance of a particular program executing on a particular input data set. In some embodiments, single instruction multiple data (SIMD) instruction issue techniques are used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In other embodiments, single instruction multiple thread (SIMT) techniques are used to support the parallel execution of a large number of substantially synchronous threads using a common instruction unit configured to issue instructions to a set of processing engines within each of the processing clusters. Unlike SIMD execution mechanisms where all processing engines typically execute the same instruction, SIMT execution allows different threads to more easily follow divergent execution paths through a given thread program. Those skilled in the art will understand that the SIMD processing mechanism represents a functional subset of the SIMT processing mechanism.

[0072] The operation of the processing cluster 214 can be controlled via a pipeline manager 232 that distributes processing tasks to the SIMT parallel processors. The pipeline manager 232 receives instructions from Figure 2A a scheduler 210 and manages the execution of those instructions via a graphics multiprocessor 234 and / or a texture unit 236. The illustrated graphics multiprocessor 234 is an exemplary instance of a SIMT parallel processor. However, various types of SIMT parallel processors of different architectures can be included within the processing cluster 214. One or more instances of the graphics multiprocessor 234 can be included within the processing cluster 214. The graphics multiprocessor 234 can process data, and a data crossbar 240 can be used to distribute the processed data to one of a number of possible destinations including other shading units. The pipeline manager 232 can facilitate the distribution of the processed data by specifying a destination for the data to be distributed via the data crossbar 240.

[0073] Each graphics multiprocessor 234 within the processing cluster 214 can include the same set of functional execution logic (e.g., arithmetic logic units, load store units, etc.). The functional execution logic can be configured in a pipelined manner where new instructions can be issued before the completion of previous instructions. The functional execution logic can be provided. The functional logic supports a variety of operations including integer and floating point arithmetic, comparison operations, boolean operations, shift operations, and the calculation of various algebraic functions. In one embodiment, the same functional unit hardware can be used to perform different operations, and any combination of functional units can exist.

[0074] Instructions transmitted to processing cluster 214 constitute threads. A set of threads executed on a set of parallel processing engines is a thread group. The thread group executes the same program on different input data. Each thread within the thread group can be assigned to a different processing engine within graphics multiprocessor 234. The thread group can include fewer threads than the number of processing engines within graphics multiprocessor 234. When the thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during the cycles of processing the thread group. The thread group can also include more threads than the number of processing engines within graphics multiprocessor 234. When the thread group includes more threads than the number of processing engines within graphics multiprocessor 234, processing can be executed on consecutive clock cycles. In one embodiment, multiple thread groups can be executed simultaneously on graphics multiprocessor 234.

[0075] In one embodiment, graphics multiprocessor 234 includes an internal cache memory for performing load and store operations. In one embodiment, graphics multiprocessor 234 can forego the internal cache and instead use the cache memory (e.g., L1 cache 308) within processing cluster 214. Each graphics multiprocessor 234 can also access the L2 cache within the partition units (e.g., Figure 2A partition units 220A through 220N) shared among all processing clusters 214 and can be used to transfer data between threads. Graphics multiprocessor 234 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. Any memory external to parallel processing unit 202 can be used as global memory. Embodiments in which processing cluster 214 includes multiple instances of graphics multiprocessor 234 can share common instructions and data that can be stored in L1 cache 308.

[0076] Each processing cluster 214 can include an MMU 245 (memory management unit) configured to map virtual addresses to physical addresses. In other embodiments, one or more instances of MMU 245 can reside in Figure 2A memory interface 218. MMU 245 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles (more on tiling) and optionally cache line indices. MMU 245 can include an address translation lookaside buffer (TLB) or cache that can reside within graphics multiprocessor 234 or L1 cache or processing cluster 214. The physical addresses are processed to distribute surface data locality to enable efficient request interleaving among partition units. The cache line index can be used to determine whether a request to a cache line is a hit or a miss.

[0077] In graphics and computing applications, the processing cluster 214 can be configured such that each graphics multiprocessor 234 is coupled to a texture unit 236 to perform texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. The texture data is read from an internal texture L1 cache (not shown) or, in some embodiments, from an L1 cache within the graphics multiprocessor 234, and is fetched from the L2 cache, local parallel processor memory, or system memory as needed. Each graphics multiprocessor 234 outputs processed tasks to the data crossbar 240 to provide the processed tasks to another processing cluster 214 for further processing or to store the processed tasks in the L2 cache, local parallel processor memory, or system memory via the memory crossbar 216. The preROP 242 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 234 and direct the data to ROP units, which can be located with partitioning units (e.g., Figure 2A partitioning units 220A through 220N as described herein). The preROP 242 unit can optimize color blending, organize pixel color data, and perform address translation.

[0078] It should be understood that the core architectures described herein are exemplary and variations and modifications are possible. For example, any number of processing units, such as the graphics multiprocessor 234, texture unit 236, preROP 242, etc., can be included within the processing cluster 214. Additionally, although only one processing cluster 214 is shown, the parallel processing units as described herein can include any number of instances of the processing cluster 214. In one embodiment, each processing cluster 214 can be configured to operate independently of other processing clusters 214 using separate and distinct processing units, L1 caches, etc.

[0079] Figure 2D A graphics multiprocessor 234 is shown in accordance with one embodiment. In such an embodiment, the graphics multiprocessor 234 is coupled to a pipeline manager 232 of the processing cluster 214. The graphics multiprocessor 234 has an execution pipeline that includes, but is not limited to, an instruction cache 252, an instruction unit 254, an address mapping unit 256, a register file 258, one or more general-purpose graphics processing unit (GPGPU) cores 262, and one or more load / store units 266. The GPGPU cores 262 and load / store units 266 are coupled to a cache memory 272 and a shared memory 270 via a memory and cache interconnect 268.

[0080] In one embodiment, the instruction cache 252 receives a stream of instructions to be executed from the pipeline manager 232. These instructions are cached in the instruction cache 252 and dispatched for execution by the instruction unit 254. The instruction unit 254 may dispatch instructions as a thread group (e.g., a warp), and each thread of the thread group is assigned to a different execution unit within the GPGPU core 262. Instructions can access any one of the local, shared, or global address spaces by specifying an address within the unified address space. The address mapping unit 256 can be used to convert an address in the unified address space into a different memory address accessible by the load / store unit 266.

[0081] The register file 258 provides a set of registers for the functional units of the graphics multiprocessor 324. The register file 258 provides temporary storage for the operands of the data paths of the functional units (e.g., the GPGPU core 262, the load / store unit 266) connected to the graphics multiprocessor 324. In one embodiment, the register file 258 is partitioned among each of the functional units such that each functional unit is assigned a dedicated portion of the register file 258. In one embodiment, the register file 258 is partitioned among different warps being executed by the graphics multiprocessor 324.

[0082] The GPGPU cores 262 may each include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing the instructions of the graphics multiprocessor 324. According to an embodiment, the architectures of the GPGPU cores 262 may be similar or different. For example, and in one embodiment, a first portion of the GPGPU core 262 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In one embodiment, the FPU may implement the IEEE 754-2008 floating-point arithmetic standard or enable variable-precision floating-point arithmetic. Additionally, the graphics multiprocessor 324 may also include one or more fixed-function or special-function units for performing specific functions such as copy rectangle or pixel blend operations. In one embodiment, one or more of the GPGPU cores may also contain fixed or special-function logic.

[0083] The memory and cache interconnect 268 is an interconnect network that connects each of the functional units of the graphics multiprocessor 324 to the register file 258 and the shared memory 270. In one embodiment, the memory and cache interconnect 268 is a crossbar interconnect that allows the load / store unit 266 to perform load and store operations between the shared memory 270 and the register file 258. The register file 258 can operate at the same frequency as the GPGPU core 262, so data transfer between the GPGPU core 262 and the register file 258 has very low latency. The shared memory 270 can be used to implement communication between threads executing on the functional units within the graphics multiprocessor 234. For example, the cache memory 272 can be used as a data cache to cache texture data communicated between the functional units and the texture unit 236. The shared memory 270 can also be used as a cached managed program. In addition to the automatically cached data stored in the cache memory 272, threads executing on the GPGPU core 262 can also programmatically store data in the shared memory.

[0084] Figures 3A to 3B Additional graphics multiprocessors according to embodiments are shown. The illustrated graphics multiprocessors 325, 350 are Figure 2C variants of the graphics multiprocessor 234. The illustrated graphics multiprocessors 325, 350 can be configured as streaming multiprocessors (SMs) capable of simultaneously executing a large number of execution threads.

[0085] Figure 3A A graphics multiprocessor 325 according to an additional embodiment is shown. The graphics multiprocessor 325 includes multiple additional instances of execution resource units relative to Figure 2D the graphics multiprocessor 234. For example, the graphics multiprocessor 325 can include multiple instances of instruction units 332A to 332B, register files 334A to 334B, and (multiple) texture units 344A to 344B. The graphics multiprocessor 325 also includes multiple sets of graphics or compute execution units (e.g., GPGPU cores 336A to 336B, GPGPU cores 337A to 337B, GPGPU cores 338A to 338B) and multiple sets of load / store units 340A to 340B. In one embodiment, the execution resource units have a common instruction cache 330, a texture and / or data cache memory 342, and a shared memory 346. The various components can communicate via an interconnect fabric 327. In one embodiment, the interconnect fabric 327 includes one or more crossbars to enable communication between the components of the graphics multiprocessor 325.

[0086] Figure 3B A graphics multiprocessor 350 according to an additional embodiment is shown. AsFigure 2D and Figure 3A As shown in Figure 3A , the graphics processor includes multiple sets of execution resources 356A through 356D, where each set of execution resources includes multiple instruction units, register files, GPGPU cores, and load / store units. The execution resources 356A through 356D can work with (multiple) texture units 360A through 360D to perform texture operations while sharing the instruction cache 354 and the shared memory 362. In one embodiment, the execution resources 356A through 356D can share the instruction cache 354 and the shared memory 362 as well as multiple instances of texture and / or data cache memories 358A through 358B. Various components can communicate via an interconnect structure 352 similar to the interconnect structure 327 of Figure 3A .

[0087] Those skilled in the art will understand that Figure 1 、 Figures 2A to 2D and Figures 3A to 3B the architectures described in Figure 2A are descriptive and do not limit the scope of the embodiments of the present invention. Thus, the techniques described herein can be implemented on any suitably configured processing unit, including but not limited to: one or more mobile application processors; one or more desktop computers or server central processing units (CPUs), including multi-core CPUs; one or more parallel processing units such as Figure 2A the parallel processing unit 202; and one or more graphics processors or specialized processing units without departing from the scope of the embodiments described herein.

[0088] In some embodiments, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU can be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., within the package or chip). Regardless of how the GPU is connected, the processor core can allocate work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. Then, the GPU uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0089] Techniques for GPU-to-Host Processor Interconnect

[0090] Figure 4AAn exemplary architecture is shown in which multiple GPUs 410 to 413 are communicatively coupled to multiple multi-core processors 405 to 406 via high-speed links 440 to 443 (e.g., buses, point-to-point interconnects, etc.). In one embodiment, high-speed links 440 to 443 support a communication throughput of 4 GB / s, 30 GB / s, 80 GB / s, or higher, depending on the implementation. Various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. However, the basic principles of the present invention are not limited to any particular communication protocol or throughput.

[0091] Furthermore, in one embodiment, two or more of GPUs 410 to 413 are interconnected via high-speed links 444 to 445, which can be implemented using the same or different protocols / links as those used for high-speed links 440 to 443. Similarly, two or more of multi-core processors 405 to 406 can be connected via high-speed link 433, which can be a symmetric multi-processor (SMP) bus operating at a speed of 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, Figure 4A all communications between the various system components shown can be accomplished using the same protocol / link (e.g., via a common interconnect structure). However, as mentioned, the basic principles of the present invention are not limited to any particular type of interconnect technology.

[0092] In one embodiment, each multi-core processor 405 to 406 is communicatively coupled to processor memories 401 to 402 via memory interconnects 430 to 431, respectively, and each GPU 410 to 413 is communicatively coupled to GPU memories 420 to 423 via GPU memory interconnects 450 to 453, respectively. Memory interconnects 430 to 431 and 450 to 453 can utilize the same or different memory access technologies. By way of example and not limitation, processor memories 401 to 402 and GPU memories 420 to 423 can be volatile memories such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or can be non-volatile memories such as 3D XPoint or Nano-Ram. In one embodiment, a portion of the memory can be volatile memory while another portion can be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0093] As described below, although each of the various processors 405 to 406 and GPUs 410 to 413 can be physically coupled to specific memories 401 to 402, 420 to 423 respectively, a unified memory architecture can be implemented, in which the same virtual system address space (also referred to as the "effective address" space) is distributed across all the various physical memories. For example, each of the processor memories 401 to 402 can include 64 GB of system memory address space, and each of the GPU memories 420 to 423 can include 32 GB of system memory address space (resulting in a total of 256 GB of addressable storage space in the example).

[0094] Figure 4B Additional details of the interconnection between a multi-core processor 407 and a graphics acceleration module 446 according to one embodiment are shown. The graphics acceleration module 446 can include one or more GPU chips integrated on a line card coupled to the processor 407 via a high-speed link 440. Alternatively, the graphics acceleration module 446 can be integrated on the same package or chip as the processor 407.

[0095] The illustrated processor 407 includes multiple cores 460A to 460D, each having a translation lookaside buffer 461A to 461D and one or more caches 462A to 462D. These cores can include various other components for executing instructions and processing data not shown so as not to obscure the basic principles of the present invention (e.g., instruction fetch unit, branch prediction unit, decoder, execution unit, reorder buffer, etc.). The caches 462A to 462D can include level 1 (L1) and level 2 (L2) caches. Additionally, one or more shared caches 426 can be included in the cache hierarchy and shared by groups of cores 460A to 460D. For example, one embodiment of the processor 407 includes 24 cores, each having its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one of the L2 caches and one of the L3 caches are shared by two adjacent cores. The processor 407 and the graphics accelerator integrated module 446 are connected to a system memory 441, which can include the processor memories 401 to 402.

[0096] Data and instructions stored in various caches 462A-462D, 456, and system memory 441 are kept consistent via inter-core communication through coherence bus 464. For example, each cache may have cache coherence logic / circuit associated therewith to communicate via coherence bus 464 in response to a detected read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented via coherence bus 464 to snoop cache accesses. Cache snooping / coherence techniques are well understood by those skilled in the art and will not be described in detail here so as not to obscure the basic principles of the present invention.

[0097] In one embodiment, proxy circuit 425 communicatively couples graphics acceleration module 446 to coherence bus 464, thereby allowing graphics acceleration module 446 to participate in the cache coherence protocol as a peer of the cores. Specifically, interface 435 provides connectivity to proxy circuit 425 via high-speed link 440 (e.g., PCIe bus, NVLink, etc.), and interface 437 connects graphics acceleration module 446 to link 440.

[0098] In one implementation, accelerator integrated circuit 436 provides cache management, memory access, context management, and interrupt management services on behalf of multiple graphics processing engines 431, 432, 43N of graphics acceleration module 446. Graphics processing engines 431, 432, 43N may each include a separate graphics processing unit (GPU). Alternatively, graphics processing engines 431, 432, 43N may include different types of graphics processing engines within a GPU such as graphics execution units, media processing engines (e.g., video encoder / decoder), samplers, and block image transfer engines. In other words, the graphics acceleration module may be a GPU having multiple graphics processing engines 431, 432, 43N, or graphics processing engines 431-432, 43N may be separate GPUs integrated on a common package, line card, or chip.

[0099] In one embodiment, the accelerator integrated circuit 436 includes a memory management unit (MMU) 439 that performs various memory management functions such as virtual-to-physical memory translation (also known as effective-to-real memory translation) and a memory access protocol for accessing system memory 441. The MMU 439 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective-to-physical / real address translations. In one implementation, the cache 438 stores commands and data for efficient access by the graphics processing engines 431-432, 43N. In one embodiment, data stored in the cache 438 and the graphics memories 433-434, 43N is kept coherent with the core caches 462A-462D, 456, and the system memory 411. As mentioned, this may be done via the proxy circuit 425 that participates in the cache coherence mechanism on behalf of the cache 438 and the memories 433-434, 43N (e.g., sending updates related to modifications / accesses of cache lines on the processor caches 462A-462D, 456 to the cache 438 and receiving updates from the cache 438).

[0100] A set of registers 445 stores context data for threads executed by the graphics processing engines 431-432, 43N, and the context management circuit 448 manages thread contexts. For example, the context management circuit 448 may perform save and restore operations to save and restore the contexts of various threads during a context switch (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, at context switch, the context management circuit 448 may store the current register values into a specified area in memory (e.g., identified by a context pointer). The context management circuit may restore the register values upon return to the context. In one embodiment, the interrupt management circuit 447 receives and processes interrupts received from system devices.

[0101] In one implementation, the MMU 439 translates virtual / effective addresses from the graphics processing engine 431 into real / physical addresses in the system memory 411. One embodiment of the accelerator integrated circuit 436 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 446 and / or other accelerator devices. The graphics accelerator modules 446 may be dedicated to a single application executing on the processor 407 or may be shared among multiple applications. In one embodiment, a virtual graphics execution environment is presented where the resources of the graphics processing engines 431-432, 43N are shared among multiple applications or virtual machines (VMs). The resources may be subdivided into "slices" that are allocated to different VMs and / or applications based on processing requirements and priorities associated with the VMs and / or applications.

[0102] Accordingly, the accelerator integrated circuit acts as a bridge for the system of the graphics acceleration module 446 and provides address translation and system memory cache services. Additionally, the accelerator integrated circuit 436 can provide virtualization facilities for the host processor to manage the virtualization of the graphics processing engine, interrupts, and memory management.

[0103] Since the hardware resources of the graphics processing engines 431 to 432, 43N are explicitly mapped to the actual address space seen by the host processor 407, any host processor can use valid address values to directly address these resources. In one embodiment, one function of the accelerator integrated circuit 436 is the physical separation of the graphics processing engines 431 to 432, 43N such that they appear as independent units on the system.

[0104] As mentioned, in the illustrated embodiments, one or more graphics memories 433 to 434, 43M are respectively coupled to each of the graphics processing engines 431 to 432, 43N. The graphics memories 433 to 434, 43M store the instructions and data being processed by each of the graphics processing engines 431 to 432, 43N. The graphics memories 433 to 434, 43M can be volatile memories such as DRAM (including stacked DRAM), GDDR memories (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memories such as 3D XPoint or Nano-Ram.

[0105] In one embodiment, to reduce the data traffic on the link 440, biasing techniques are used to ensure that the data stored in the graphics memories 433 to 434, 43M is the data most frequently used by the graphics processing engines 431 to 432, 43N and is preferably not used (at least not frequently) by the cores 460A to 460D. Similarly, the biasing mechanism attempts to keep the data required by the cores (and preferably not the graphics processing engines 431 to 432, 43N) within the caches 462A to 462D, 456 of the cores and the system memory 411.

[0106] Figure 4C Another embodiment is shown in which the accelerator integrated circuit 436 is integrated within the processor 407. In this embodiment, the graphics processing engines 431 to 432, 43N communicate directly with the accelerator integrated circuit 436 via the interface 437 and the interface 435 through the high-speed link 440 (which can also utilize any form of bus or interface protocol). The accelerator integrated circuit 436 can perform the same operations as described with respect to Figure 4B but may operate with higher throughput considering its close proximity to the coherence bus 462 and the caches 462A to 462D, 426.

[0107] One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization). The shared programming model can include a programming model controlled by the accelerator integrated circuit 436 and a programming model controlled by the graphics acceleration module 446.

[0108] In one embodiment of the dedicated process model, the graphics processing engines 431 to 432, 43N are dedicated to a single application or process under a single operating system. A single application can centralize other application requests to the graphics engines 431 to 432, 43N, thereby providing virtualization within the VM / partition.

[0109] In the dedicated process programming model, the graphics processing engines 431 to 432, 43N can be shared by multiple VM / application partitions. The shared model requires a hypervisor that virtualizes the graphics processing engines 431 to 432, 43N to allow access by each operating system. For a single-partition system without a hypervisor, the graphics processing engines 431 to 432, 43N are owned by the operating system. In both cases, the operating system can virtualize the graphics processing engines 431 to 432, 43N to provide access to each process or application.

[0110] For the shared programming model, the graphics acceleration module 446 or the separate graphics processing engines 431 to 432, 43N use a process handle to select process elements. In one embodiment, the process elements are stored in the system memory 411 and can be addressed using the effective address to physical address translation techniques described herein. The process handle can be a value specific to the implementation provided to the host process when registering its context with the graphics processing engines 431 to 432, 43N (i.e., calling the system software to add a process element to the process element linked list). The lower 16 bits of the process handle can be the offset of the process element within the process element linked list.

[0111] Figure 4D An exemplary accelerator integrated slice 490 is shown. As used herein, "slice" includes a specified portion of the processing resources of the accelerator integrated circuit 436. The application effective address space 482 within the system memory 411 stores process elements 483. In one embodiment, the process elements 483 are stored in response to a GPU call 481 from an application 480 executing on the processor 407. The process elements 483 contain the processing state of the corresponding application 480. The work descriptor (WD) 484 contained in the process elements 483 can be a single job requested by the application, or can contain a pointer to a job queue. In the latter case, the WD 484 is a pointer to the job request queue within the application address space 482.

[0112] The graphics acceleration module 446 and / or the separate graphics processing engines 431 to 432, 43N can be shared by all or some of the processes in the system. Embodiments of the present invention include an infrastructure for establishing a processing state and sending a WD 484 to the graphics acceleration module 446 to start a job in a virtual environment.

[0113] In one implementation, the dedicated process programming model is specific to a particular implementation. In this model, a single process owns the graphics acceleration module 446 or a separate graphics processing engine 431. Since the graphics acceleration module 446 is owned by a single process, the hypervisor initializes the accelerator integrated circuit 436 to obtain the partition to which it belongs, and the operating system initializes the accelerator integrated circuit 436 to obtain the process to which it belongs when the graphics acceleration module 446 is allocated.

[0114] In operation, the WD acquisition unit 491 in the accelerator integrated slice 490 acquires the next WD 484, which includes an indication of the work to be performed by one of the graphics processing engines of the graphics acceleration module 446. As shown, the data from the WD 484 can be stored in the register 445 and used by the MMU 439, the interrupt management circuit 447, and / or the context management circuit 446. For example, one embodiment of the MMU439 includes a segment / page walk circuit for accessing the segment / page table 486 within the OS virtual address space 485. The interrupt management circuit 447 can process the interrupt event 492 received from the graphics acceleration module 446. When performing a graphics operation, the effective address 493 generated by the graphics processing engines 431 to 432, 43N is converted to an actual address by the MMU 439.

[0115] In one embodiment, the same set of registers 445 is replicated for each of the graphics processing engines 431 to 432, 43N and / or the graphics acceleration module 446, and this set of registers can be initialized by the hypervisor or the operating system. Each of these replicated registers can be included in the accelerator integrated slice 490. Exemplary registers that can be initialized by the hypervisor are shown in Table 1.

[0116] Table 1 - Hypervisor Initialized Registers

[0117]

[0118]

[0119] Exemplary registers that can be initialized by the operating system are shown in Table 2.

[0120] Table 2 - Operating System Initialized Registers

[0121] 1 Process and Thread Identification 2 Effective Address (EA) Context Save / restore Pointer 3 Virtual Address (RA) Accelerator Utilization Record Pointer 4 Virtual Address (RA) Storage Segment Table Pointer 5 Authorization Mask 6 Work Descriptor

[0122] In one embodiment, each WD 484 is specific to a particular graphics acceleration module 446 and / or graphics processing engines 431 to 432, 43N. The WD contains all the information required for the graphics processing engines 431 to 432, 43N to do their work, or the WD can be a pointer to a memory location where the application has established a command queue of work to be done.

[0123] Figure 4E Additional details of an embodiment of the shared model are shown. The embodiment includes a hypervisor physical address space 498 in which a list of process elements 499 is stored. The hypervisor physical address space 498 can be accessed via a hypervisor 496 that virtualizes the graphics acceleration module engine of the operating system 495.

[0124] The shared programming model allows all or part of the processes from all or part of the partitions in the system to use the graphics acceleration module 446. There are two programming models in which the graphics acceleration module 446 is shared by multiple processes and partitions: time-slicing sharing and graphics direct sharing.

[0125] In this model, the system hypervisor 496 owns the graphics acceleration module 446 and makes its functionality available to all operating systems 495. To enable the graphics acceleration module 446 to support the virtualization of the system hypervisor 496, the graphics acceleration module 446 may comply with the following requirements: 1) Application job requests must be autonomous (i.e., do not need to maintain state between jobs), or the graphics acceleration module 446 must provide a context save and restore mechanism. 2) The graphics acceleration module 446 guarantees the completion of application job requests within a specified amount of time, including any translation errors, or the graphics acceleration module 446 provides the ability to preempt job processing. 3) When operating in the direct sharing programming model, fairness of the graphics acceleration module 446 in the process must be guaranteed.

[0126] In one embodiment, for a shared model, an application 480 is required to utilize a graphics acceleration module 446 type, a work descriptor (WD), an authorization mask register (AMR) value, and a context save / restore area pointer (CSRP) to make an operating system 495 system call. The graphics acceleration module 446 type describes the target acceleration function of the system call. The graphics acceleration module 446 type can be a system-specific value. The WD is specifically formatted for the graphics acceleration module 446 and can be in the form of: a graphics acceleration module 446 command; a valid address pointer to a user-defined structure; a valid address pointer to a command queue; or any other data structure for describing the work to be performed by the graphics acceleration module 446. In one embodiment, the AMR value is the AMR state for the current process. The value passed to the operating system is similar to the application that sets the AMR. If the implementation of the accelerator integrated circuit 436 and the graphics acceleration module 446 does not support the user authorization mask override register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in a hypervisor call. The hypervisor 496 can optionally apply the current authorization mask override register (AMOR) value before placing the AMR in the process element 483. In one embodiment, the CSRP is one of the registers 445 that contains a valid address of a region in the application address space 482 for the graphics acceleration module 446 to save and restore the context state. This pointer is optional if there is no need to save state between jobs or when a job is preempted. The context save / restore area can be plugged system memory.

[0127] Upon receiving the system call, the operating system 495 can verify that the application 480 is registered and authorized to use the graphics acceleration module 446. The operating system 495 then utilizes the information shown in Table 3 to call the hypervisor 496.

[0128] Table 3 - Operating System Call Parameters to the Hypervisor

[0129] 1 Work Descriptor (WD) 2 Authorization Mask Register (AMR) Value (May be Masked) 3 Effective Address (EA) Context Save / restore Region Pointer (CSRP) 4 Process ID (PID) and Optional Thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual Address of Storage Segment Table Pointer (SSTP) 7 Logical Interrupt Service Number (LISN)

[0130] Upon receiving the hypervisor call, the hypervisor 496 can verify that the operating system 495 is registered and authorized to use the graphics acceleration module 446. The hypervisor 496 then places the process element 483 into the process element linked list for the corresponding graphics acceleration module 446 type. The process element can contain the information shown in Table 4.

[0131] Table 4 - Process Element Information

[0132] 1 Work Descriptor (WD) 2 Authorization Mask Register (AMR) Value (May be Masked) 3 Effective Address (EA) Context Save / restore Region Pointer (CSRP) 4 Process ID (PID) and Optional Thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual Address of Storage Segment Table Pointer (SSTP) 7 Logical Interrupt Service Number (LISN) 8 Interrupt Vector Table, Derived from Hypervisor Call Parameters 9 Status Register (SR) Value 10 Logical Partition ID (LPID) 11 Physical Address (RA) Hypervisor Accelerator Utilization Record Pointer 12 Storage Descriptor Register (SDR)

[0133] In one embodiment, the hypervisor initializes a plurality of accelerator integrated slices 490 of register 445.

[0134] As Figure 4F shown, one embodiment of the present invention employs unified memory that can be addressed via a common virtual memory address space for accessing physical processor memories 401 to 402 and GPU memories 420 to 423. In this implementation, operations executed on GPUs 410 to 413 utilize the same virtual / effective memory address space to access processor memories 401 to 402, and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 401, a second portion is allocated to second processor memory 402, a third portion is allocated to GPU memory 420, and so on. The entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memories 401 to 402 and GPU memories 420 to 423, allowing any processor or GPU to access any physical memory having a virtual address mapped to that memory.

[0135] In one embodiment, bias / coherency management circuits 494A to 494E within one or more of MMUs 439A to 439E ensure cache coherency between the host processor (e.g., 405) and the caches of GPUs 410 to 413, and implement a biasing technique for indicating the physical memory in which certain types of data should be stored. Although Figure 4F multiple instances of bias / coherency management circuits 494A to 494E are shown, the bias / coherency circuits may also be implemented within the MMU of one or more host processors 405 and / or within accelerator integrated circuit 436.

[0136] One embodiment allows the GPU-attached memories 420-423 to be mapped as part of the system memory and accessed using shared virtual memory (SVM) techniques, without suffering the typical performance penalties associated with full-system cache coherence. The ability to access the GPU-attached memories 420-423 as system memory does not incur a heavy cache coherence overhead, which provides a favorable operating environment for GPU offloading. This arrangement allows the host processor 405 software to set operands and access computation results without the overhead of traditional I / O DMA data copies. These traditional copies involve driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are inefficient relative to simple memory accesses. At the same time, the ability to access the GPU-attached memories 420-423 without cache coherence overhead can be critical to the execution time of offloaded computations. For example, in the presence of a large amount of streaming write memory traffic, the cache coherence overhead can significantly reduce the effective write bandwidth seen by the GPUs 410-413. The efficiency of operand setting, result access, and GPU computation all play important roles in determining the effectiveness of GPU offloading.

[0137] In one implementation, the choice between GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table can be used, which can be a page-granularity structure (i.e., controlled at the granularity of memory pages) including 1 or 2 bits per GPU-attached memory page. The bias table can be implemented within the stolen memory range of one or more of the GPU-attached memories 420-423, with or without a bias cache in the GPUs 410-413 (e.g., to cache frequently / most recently used entries of the bias table). Alternatively, the entire bias table can be maintained within the GPU.

[0138] In one implementation, the bias table entry associated with each access to the GPU-attached memories 420-423 is accessed prior to actually accessing the GPU memory, enabling the following operations. First, local requests from the GPUs 410-413 that find their pages in GPU bias are forwarded directly to the corresponding GPU memories 420-423. Local requests from the GPUs that find their pages in host bias are forwarded to the processor 405 (e.g., via the high-speed link as described above). In one embodiment, requests from the processor 405 that find the requested page in host processor bias complete the request as a normal memory read. Alternatively, requests for GPU bias pages can be forwarded to the GPUs 410-413. If the GPU is not currently using the page, the GPU can transition the page to host processor bias.

[0139] The bias state of a page can be changed by a software-based mechanism, a hardware-assisted software mechanism, or, for a limited set of cases, a hardware-only mechanism.

[0140] A mechanism for changing the bias state employs an API call (e.g., OpenCL), which in turn calls the GPU device driver, which in turn sends a message to the GPU (or enqueues a command descriptor) to cause the GPU to change the bias state, and for some transitions, performs a cache dump flush operation in the host. The cache dump flush operation is necessary for the transition from host processor 405 bias to GPU bias, but not for the reverse transition.

[0141] In one embodiment, cache coherence is maintained by temporarily presenting GPU-biased pages that are non-cacheable by the host processor 405. To access these pages, processor 405 can request access from GPU 410, and the GPU may or may not immediately grant access depending on the implementation. Thus, to reduce communication between processor 405 and GPU 410, it is beneficial to ensure that GPU-biased pages are pages that are needed by the GPU but not by the host processor 405, and vice versa.

[0142] Graphics Processing Pipeline

[0143] Figure 5 A graphics processing pipeline 500 according to an embodiment is shown. In one embodiment, a graphics processor may implement the shown graphics processing pipeline 500. The graphics processor may be included in a parallel processing subsystem such as Figure 2A within parallel processor 200 as described herein. In one embodiment, the parallel processor is Figure 1 a variant of the (multiple) parallel processors 112 as described herein. As described herein, various parallel processing systems may implement the graphics processing pipeline 500 via one or more instances of a parallel processing unit (e.g., Figure 2A parallel processing unit 202 as described herein). For example, a shader unit (e.g., Figure 2D graphics multiprocessor 234 as described herein) may be configured to perform the functions of one or more of vertex processing unit 504, tessellation control processing unit 508, tessellation evaluation processing unit 512, geometry processing unit 516, and fragment / pixel processing unit 524. The functions of data assembler 502, primitive assemblers 506, 514, 518, tessellation unit 510, rasterizer 522, and raster operation unit 526 may also be performed by other processing engines and corresponding partitioning units within a processing cluster (e.g., Figure 3A processing cluster 214 as described herein), Figure 2Cis performed by partition units 220A to 220N). The graphics processing pipeline 500 may also be implemented using one or more dedicated processing units for functions. In one embodiment, one or more parts of the graphics processing pipeline 500 may be executed by parallel processing logic within a general-purpose processor (e.g., a CPU). In one embodiment, one or more parts of the graphics processing pipeline 500 may access on-chip memory (e.g., parallel processor memory 222 as shown in Figure 2A through a memory interface 528, and the memory interface may be an instance of the memory interface 218 shown in Figure 2A .

[0144] In one embodiment, the data assembler 502 is a processing unit that collects vertex data of surfaces and primitives. The data assembler 502 then outputs vertex data including vertex attributes to the vertex processing unit 504. The vertex processing unit 504 is a programmable execution unit that executes a vertex shader program to illuminate and transform vertex data as specified by the vertex shader program. The vertex processing unit 504 reads data stored in a cache, local, or system memory for processing the vertex data, and can be programmed to transform the vertex data from an object-based coordinate representation to a world space coordinate space or a normalized device coordinate space.

[0145] A first instance of the primitive assembler 506 receives vertex attributes from the vertex processing unit 504. The primitive assembler 506 reads the stored vertex attributes as needed and constructs graphics primitives for processing by the tessellation control processing unit 508. Graphics primitives include triangles, line segments, points, patches, etc. as supported by various graphics processing application programming interfaces (APIs).

[0146] The tessellation control processing unit 508 treats the input vertices as control points of a geometric patch. These control points are transformed from an input representation of the patch (e.g., the base of the patch) to a representation suitable for surface evaluation by the tessellation evaluation processing unit 512. The tessellation control processing unit 508 may also calculate tessellation factors for the edges of the geometric patch. The tessellation factors apply to individual edges and quantify view-dependent levels of detail associated with the edges. The tessellation unit 510 is configured to receive the tessellation factors for the edges of the patch and subdivide the patch into multiple geometric primitives such as line, triangle, or quadrilateral primitives, which are transmitted to the tessellation evaluation processing unit 512. The tessellation evaluation processing unit 512 operates on the parameterized coordinates of the subdivided patch to generate a surface representation and vertex attributes for each vertex associated with the geometric primitive.

[0147] A second instance of the primitive assembler 514 receives vertex attributes from the tessellation evaluation processing unit 512, reads stored vertex attributes as needed, and constructs graphics primitives for processing by the geometry processing unit 516. The geometry processing unit 516 is a programmable execution unit that executes a geometry shader program to transform the graphics primitives received from the primitive assembler 514 as specified by the geometry shader program. In one embodiment, the geometry processing unit 516 is programmed to subdivide a graphics primitive into one or more new graphics primitives and calculate parameters for rasterizing the new graphics primitives.

[0148] In some embodiments, the geometry processing unit 516 may add or delete elements in the geometry stream. The geometry processing unit 516 outputs parameters and vertices that specify new graphics primitives to the primitive assembler 518. The primitive assembler 518 receives the parameters and vertices from the geometry processing unit 516 and constructs graphics primitives for processing by the viewport scaling, culling, and clipping unit 520. The geometry processing unit 516 reads data stored in the parallel processor memory or system memory for processing geometric data. The viewport scaling, culling, and clipping unit 520 performs clipping, culling, and viewport scaling and outputs the processed graphics primitives to the rasterizer 522.

[0149] The rasterizer 522 may perform depth culling and other depth-based optimizations. The rasterizer 522 also performs scan conversion on the new graphics primitives to generate segments and outputs these segments and associated coverage data to the segment / pixel processing unit 524.

[0150] The segment / pixel processing unit 524 is a programmable execution unit configured to execute a fragment shader program or a pixel shader program. The segment / pixel processing unit 524 transforms the segments or pixels received from the rasterizer 522 as specified by the fragment or pixel shader program. For example, the segment / pixel processing unit 524 may be programmed to perform operations including but not limited to texture mapping, shading, blending, texture correction, and perspective correction to produce shaded segments or pixels output to the raster operations unit 526. The segment / pixel processing unit 524 may read data stored in the parallel processor memory or system memory for use in processing segment data. The fragment or pixel shader program may be configured to shade at a sample, pixel, tile, or other granularity according to a sampling rate configured for the processing unit.

[0151] The raster operations unit 526 is a processing unit that performs raster operations including but not limited to stencil printing, z-testing, blending, etc., and outputs pixel data as processed graphics data for storage in the graphics memory (e.g., Figure 2A the parallel processor memory 222 in Figure 1in the system memory 104 for display on one or more display devices 110 or for further processing by one or more processors 102 or one of the (multiple) parallel processors 112. In some embodiments, the raster operation unit 526 is configured to compress z or color data written to memory and decompress z or color data read from memory.

[0152] Figure 6 illustrates a computing device 600 hosting an inference coordination and processing utilization mechanism (“coordination / utilization mechanism”) 610 according to one embodiment. The computing device 600 represents a communication and data processing device, including (but not limited to) smart wearable devices, smartphones, virtual reality (VR) devices, head-mounted displays (HMDs), mobile computers, Internet of Things (IoT) devices, laptop computers, desktop computers, server computers, etc., and may be similar or identical to Figure 1 the computing device 100; thus, for brevity, clarity, and ease of understanding, many of the details described above will not be further discussed or repeated below with reference to Figures 1 to 5 stated.

[0153] The computing device 600 may also include (but not limited to) autonomous machines or artificial intelligence agents, such as, mechanical agents or machines, electronic agents or machines, virtual agents or machines, electromechanical agents or machines, etc. Examples of autonomous machines or artificial intelligence agents may include (but not limited to) robots, autonomous vehicles (e.g., self-driving cars, unmanned aerial vehicles, self-navigating ships, etc.), autonomous devices (self-operating construction vehicles, self-operating medical devices, etc.), and so on. Throughout this document, “computing device” may be interchangeably referred to as “autonomous machine” or “artificial intelligence agent” or simply “robot”.

[0154] It is contemplated that although “autonomous vehicles” and “self-driving” are referred to throughout this document, the embodiments are not limited thereto. For example, “autonomous vehicles” are not limited to cars, but may include any number and type of autonomous machines, such as, robots, autonomous devices, home autonomous devices, etc., and any one or more tasks or operations associated with such autonomous machines may be interchangeably referred to with self-driving.

[0155] The computing device 600 may also include (but is not limited to) large computing systems, such as, server computers, desktop computers, etc., and may also include set-top boxes (e.g., Internet-based cable TV set-top boxes, etc.), global positioning system (GPS)-based devices, etc. The computing device 600 may include mobile computing devices that act as communication devices, such as cellular phones including smart phones, personal digital assistants (PDAs), tablet computers, laptop computers, e-readers, smart TVs, TV platforms, wearable devices (e.g., glasses, watches, bracelets, smart cards, jewelry, clothing articles, etc.), media players, etc. For example, in one embodiment, the computing device 600 may include a mobile computing device employing a managed integrated circuit (“IC”) such as a system on a chip (“SoC” or “SOC”) computer platform that integrates various hardware and / or software components of the computing device 600 on a single chip.

[0156] As shown, in one embodiment, the computing device 600 may include any number and type of hardware and / or software components, such as (but not limited to), a graphics processing unit (“GPU” or simply “graphics processor”) 614, a graphics driver (also referred to as “GPU driver”, “graphics driver logic”, “driver logic”, user mode driver (UMD), UMD, user mode driver framework (UMDF), UMDF or simply “driver”) 616, a central processing unit (“CPU” or simply “application processor”) 612, a memory 608, a network device, a driver, etc., and input / output (I / O) sources 604, such as, a touch screen, a touch panel, a touchpad, a virtual or conventional keyboard, a virtual or conventional mouse, ports, connectors, etc. The computing device 600 may include an operating system (OS) 606 that acts as an interface between the hardware and / or physical resources of the computing device 600 and the user. It is contemplated that the graphics processor 614 and the application processor 612 may be Figure 1 one or more of the processors 102.

[0157] It should be understood that for some implementations, systems equipped with fewer or more components than the examples described above may be preferred. Thus, depending on numerous factors (such as, price constraints, performance requirements, technological improvements, or other circumstances), the configuration of the computing device 600 may vary from implementation to implementation.

[0158] An embodiment may be implemented as any one or combination of the following: one or more microchips or integrated circuits interconnected using a motherboard, hardwired logic, software stored in a memory device and executed by a microprocessor, firmware, an application specific integrated circuit (ASIC), and / or a field programmable gate array (FPGA). By way of example, the terms "logic", "module", "component", "engine", and "mechanism" may include software or hardware and / or a combination of software and hardware.

[0159] In one embodiment, the coordination / utilization mechanism 610 may be hosted or facilitated by the operating system 606 of the computing device 600. In another embodiment, the coordination / utilization mechanism 610 may be hosted by or be part of the graphics processing unit ("GPU" or simply "graphics processor") 614 or the firmware of the graphics processor 614. For example, the coordination / utilization mechanism 610 may be embedded in the processing hardware of the graphics processor 614 or be implemented as part of the processing hardware. Similarly, in yet another embodiment, the coordination / utilization mechanism 610 may be hosted by or be part of the central processing unit ("CPU" or simply "application processor") 612. For example, the coordination / utilization mechanism 610 may be embedded in the processing hardware of the application processor 612 or be implemented as part of the processing hardware. In yet another embodiment, the coordination / utilization mechanism 610 may be hosted by or be part of any number and type of components of the computing device 600, such as, a part of the coordination / utilization mechanism 610 may be hosted by or be part of the operating system 606, another part may be hosted by or be part of the graphics processor 614, another part may be hosted by or be part of the application processor 612, and one or more parts of the coordination / utilization mechanism 610 may be hosted by or be part of the operating system 606 and / or any number and type of devices of the computing device 600. It is contemplated that one or more parts or components of the coordination / utilization mechanism 610 may be used as hardware, software, and / or firmware.

[0160] It is contemplated that the embodiments are not limited to any specific implementation or hosting of the coordination / utilization mechanism 610, and the coordination / utilization mechanism 610 and one or more of its components may be implemented as hardware, software, firmware, or any combination thereof.

[0161] The computing device 600 may also host one or more network interfaces to provide access to a network, such as a LAN, a wide area network (WAN), a metropolitan area network (MAN), a personal area network (PAN), Bluetooth, a cloud network, a mobile network (e.g., 3rd generation (3G), 4th generation (4G), etc.), an intranet, the Internet, etc. The one or more network interfaces may include, for example, a wireless network interface having an antenna, and the wireless network interface may represent one or more antennas. The one or more network interfaces may also include, for example, a wired network interface that communicates with a remote device via a network cable, and the network cable may be, for example, an Ethernet cable, a coaxial cable, an optical fiber cable, a serial cable, or a parallel cable.

[0162] Embodiments may be provided, for example, as a computer program product that may include one or more machine-readable media having machine-executable instructions stored thereon, and when the machine-executable instructions are executed by one or more machines (such as a computer, a network of computers, or other electronic devices), the machine-executable instructions may cause the one or more machines to perform operations in accordance with the embodiments described herein. Machine-readable media may include, but are not limited to: floppy disks, optical disks, CD-ROMs (compact disk read-only memories), and magneto-optical disks, ROMs, RAMs, EPROMs (erasable programmable read-only memories), EEPROMs (electrically erasable programmable read-only memories), magnetic or optical cards, flash memory, or other types of media / machine-readable media suitable for storing machine-executable instructions.

[0163] In addition, embodiments may be downloaded as a computer program product, where the program may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) via a communication link (e.g., a modem and / or a network connection) by means of one or more data signals embodied in and / or modulated by a carrier wave or other propagation medium.

[0164] Throughout this document, the term "user" may be interchangeably referred to as "viewer", "observer", "person", "individual", "end user", etc. It should be noted that throughout this document, terms such as "graphics domain" may be interchangeably referred to as "graphics processing unit", "graphics processor", or simply "GPU", and similarly, "CPU domain" or "host domain" may be interchangeably referred to as "computer processing unit", "application processor", or simply "CPU".

[0165] It should be noted that throughout this document, terms such as "node", "compute node", "server", "server device", "cloud computer", "cloud server", "cloud server computer", "machine", "host", "device", "compute device", "computer", "computer system", etc. are used interchangeably. It should be further noted that throughout this document, terms such as "application", "software application", "program", "software program", "package", "software package", etc. are used interchangeably. Additionally, throughout this document, terms such as "job", "input", "request", "message", etc. are used interchangeably.

[0166] Figure 7 shows a Figure 6 coordination / utilization mechanism 610 according to one embodiment. For the sake of brevity, many of the details already discussed with reference to Figures 1 to 6 are not repeated or discussed hereafter. In one embodiment, the coordination / utilization mechanism 610 may include any number and type of components, such as (but not limited to): detection / monitoring logic 701; pre-analysis training logic 703; inference coordination logic 705; and communication / compatibility logic 707; early fusion logic 709; neural network scheduling logic 711; and processing utilization logic 713.

[0167] For example, in terms of precision capabilities, current graphics processing hardware is more powerful than what is generally required for inference. Embodiments provide a new technique for using the detection / monitoring logic 701 to detect and monitor a pre-analyzed training dataset and then trigger the pre-analysis training logic 703 to determine a range <X, Y> and configure the graphics hardware to be within this value range.

[0168] Embodiments provide a new technique for increasing the ability to configure processing hardware such as the graphics processor 614, application processor 612, etc. to adapt to a dataset to improve the energy efficiency of inference computations. For example, the inference / prediction data precision can be determined by first detecting and monitoring the dataset as facilitated by the detection / monitoring logic 701 and simultaneously or subsequently analyzing the precision associated with such a dataset, which may allow for maintaining energy efficiency while adapting the hardware built for superset capabilities when the dataset is used and applied.

[0169] In some embodiments, the inference hardware (such as the application processor 612 and / or the graphics processor 614) can be designed a priori for maximum capabilities (such as precision, etc.). For example, at runtime, a subset of the capabilities supported by the corresponding processor hardware may require precision capabilities. In one embodiment, the information observed and obtained from the training dataset can be used to configure the hardware, such as the hardware of the application processor 612 and / or the graphics processor 614. In one embodiment, using superset hardware results in sub-optimal energy efficiency because the software application discards or ignores the additional capabilities.

[0170] As shown in reference Figure 8A the inference hardware (such as the hardware of the application processor 612 and / or the graphics processor 614) can be designed to cover any expected data size and precision. To improve efficiency during inference, those components or parts of the hardware that are not required by the dataset can be turned off to save power, energy, etc., but in such applications, of more interest is maximizing the throughput of the hardware. Additionally, to increase the number of operations performed per second, those hardware blocks required for various operations (such as addition, multiplication, accumulation, etc.) can be reconfigured to be facilitated by the pre-analysis training logic 703, such as the information to be configured can be generated based on the dataset during training and subsequently continue to be transmitted to the hardware configuration controller at runtime, as facilitated by the pre-analysis training logic 703.

[0171] Embodiments provide a new technique for improving graphics processor utilization via multiple contexts during inference. For example, by using the processing utilization logic 713, support for running multiple contexts is increased in the graphics processor 614, where each context (such as an application process) can be used to solve the inference of a neural network. These contexts can have separate address spaces that can be executed by relevant hardware such as the graphics processor 614.

[0172] In one embodiment, as facilitated by the processing utilization logic 713, the hardware-based microcontroller (e.g., the context scheduler) can be detected / monitored by the logic 701 to monitor how many processing devices (such as the graphics processor 614) are being utilized by the current context, such as determining whether there are more inference problems to be solved. Generally, inference problems are simpler and may not fully utilize the graphics processor 614, so in this and other such cases, the graphics processor 614 is not under-utilized. This is illustrated and further described with reference to Figure 8B and further described.

[0173] The embodiments further provide a new technique for facilitating the coordination of inference outputs with sensors (e.g., cameras, microphones, other sensors, etc.). For example, conventional techniques do not provide coordination between inference outputs and the sensors providing the inputs. The embodiments provide a new technique capable of finding sensors to perform tasks (e.g., applying filters, activating devices, adjusting cameras, etc.), thereby allowing for improved accuracy of inference outputs. For example, when the inference confidence drops below a threshold, a filter can be applied to the camera to attempt to increase the inference confidence by capturing or focusing on certain objects or scenes while ignoring others, as facilitated by the inference coordination logic 705.

[0174] This new technique further allows Figure 6 system-level coordination between the sensors of the I / O source 604 and deep learning algorithms and techniques, which can make the sensors at the track center of a centralized supercomputer in an autonomous vehicle such as the autonomous machine 600 meaningful. As the system moves towards centralized sensor processing (rather than the sensors themselves), the coordination between the sensors and the various filters they can apply is based on the knowledge present in the central brain of the computer, which highlights the difference between detected and undetected objects. This is further illustrated with reference to Figure 8C further description.

[0175] The embodiments further provide a new technique for providing ensemble-based object detection. For example, it is possible to make actual decisions within the model, as opposed to waiting for the next output to decide outside the model, such as when dealing with different types of sensors having different time series data rates in autonomous driving.

[0176] In one embodiment, early fusion logic 709 can be used to facilitate early communication between a camera model and another model based on images captured by one or more cameras, such as a light detection and ranging (“LiDAR”, “LIDAR” or simply “radar”) model. This early communication can include exchanging early cues that lead to early path planning, decision making, etc. through a combined fusion object identification (ID) module, as facilitated by the early fusion logic 703. In one embodiment, this early communication enables early fusion to be achieved by sharing cues across models to reduce the typical separate fusions that occur after each model is completed individually. This new technique can be combined with or implemented at the early fusion process and is performed to replace low-level fusion. This is illustrated with reference to Figure 8D and further described.

[0177] The embodiment further provides a new technique for scheduling a neural network (NN), wherein such scheduling may include fault-tolerant scheduling of the NN for time-criticality and power efficiency, as facilitated by the NN scheduling logic 710. Further, at deployment, multiple applications may coexist in the graphics processor 614 for inference, wherein a percentage priority for each process is defined, such that the graphics processor 614 may schedule processes based on a percentage of the total available threads, as facilitated by the NN scheduling logic 710.

[0178] In one embodiment, the above percentages may be dynamically adjusted by the user or other profile result primitives such that the user updates the percentages, wherein the user defines a lower limit and an expected percentage. Further, a microcontroller with a real-time operating system (RTOS) that manages sensor inputs may be used to wake up and perform periodic training with training priorities based on time-criticality. It is envisioned that for an autonomous vehicle, such as the autonomous machine 600, it may be necessary to centralize a supercomputer, such as for real-time safety and security purposes, capable of virtualizing workloads and then prioritizing them.

[0179] As will be described and further elaborated with reference to Figure 9A and Figure 9B At deployment, multiple applications may coexist in the graphics processor 614, wherein a percentage priority may be defined for each process. For example, the graphics processor 614 may be facilitated by the NN scheduling logic 711 to schedule processes based on a percentage of the total available threads and other resources. This percentage may be dynamically adjusted by the user or other profile results, wherein primitives are provided for the user to update the percentage. For example, the user may define a lower limit and an expected percentage, wherein the user may require this feature to tune the graphics processor utilization based on current applications and hardware capabilities.

[0180] The following table shows how a GPU, such as the graphics processor 614, may be used to store relevant information in hardware or memory. For example, there may be primitives for the user to select and write the desired lower limit percentage for a process identified by a proportional integral derivative (PID), while there are also primitives for the user to read the percentage currently allocated by the system and the user's desired lower limit percentage. Any system-allocated percentage may be managed by the GPU hardware or through a privileged management process.

[0181]

[0182] As the use of deep learning in safety-critical applications has grown rapidly, it is also possible to consider the "safety-critical" aspects of these uses to ensure that inference processing occurs within a deterministic and guaranteed amount of time, such as a Fault Tolerant Time Interval (FTTI). This needs to be done before the failure to compute the result of any inference operation causes the real-time safety-critical control loop application to fail and may subsequently cause harm or injury to people.

[0183] The reason for this somewhat troublesome consideration is that the computing elements that perform inference operations (such as the graphics processor 614) are generally responsible for performing other tasks, such as other inference operations that are not safety-critical. For example, in an industrial robot, one trained model can be used for human detection to avoid the robot hitting a person, while another trained model running on the same computing element at the same time can be used to apply personalized aspects to the robot's behavior.

[0184] Therefore, it is important that for these "mixed-criticality" applications, the computing device 600 can be aware of the "safety-criticality" of the specific inference model (e.g., ASIL-D vs. ASIL-B or SIL-4 vs. SIL-1) when scheduling and allocating computing resources, including any ability to interrupt a lower-criticality model with a higher-criticality model, as facilitated by the NN scheduling logic 711. This is illustrated and further described with reference to Figure 9C and further described.

[0185] In addition, the communication / compatibility logic 707 can be used to facilitate the required communication and compatibility between any number of devices of the computing device 600 and the various components of the coordination / utilization mechanism 610.

[0186] The communication / compatibility logic 707 can be used to facilitate dynamic communication and compatibility between the computing device 600 and any number and type of the following devices: other computing devices (such as mobile computing devices, desktop computers, server computing devices, etc.); processing devices or components (such as CPUs, GPUs, etc.); capture / sensing / detection devices (such as capture / sensing components, including cameras, depth-sensing cameras, camera sensors, red-green-blue (“RGB” or “rgb”) sensors, microphones, etc.); display devices (such as output components, including display screens, display areas, display projectors, etc.); user / context awareness components and / or identification / verification sensors / devices (such as biosensors / detectors, scanners, etc.); (multiple) databases 730, such as memories or storage devices, databases and / or data sources (such as data storage devices, hard disk drives, solid state drives, hard disks, memory cards or devices, storage circuits, etc.); (multiple) communication media 725, such as one or more communication channels or networks (e.g., cloud networks, the Internet, intranets, cellular networks, proximity networks, such as Bluetooth, Bluetooth Low Energy (BLE), Smart Bluetooth, Wi-Fi Proximity, Radio Frequency Identification (RFID), Near Field Communication (NFC), Body Area Network (BAN), etc.); wireless or wired communication and related protocols (e.g., WiMAX, Ethernet, etc.); connectivity and location management technologies; software applications / websites (e.g., social and / or business social websites, etc., business applications, games, and other entertainment applications, etc.); and programming languages, etc., while ensuring compatibility with changing technologies, parameters, protocols, standards, etc.

[0187] Furthermore, any use of specific brands, words, terms, phrases, names, and / or acronyms should not be read as limiting the embodiments to software or devices with such labels in literature outside of the product or this document, such as “detect,” “observe,” “decide,” “normal path,” “detour,” “computing block,” “bypass,” “frequently used data value,” “FDV,” “finite state machine,” “training set,” “agent,” “machine,” “vehicle,” “robot,” “drive,” “CNN,” “DNN,” “NN,” “execution unit,” “EU,” “shared local memory,” “SLM,” “graphics stream,” “cache,” “graphics cache,” “GPU,” “graphics processor,” “GPU domain,” “GPGPU,” “CPU,” “application processor,” “CPU domain,” “graphics driver,” “workload,” “application,” “graphics pipeline,” “pipelining process,” “API,” “3D API,” "Hardware", "software", "agent", "graphics driver", "kernel mode graphics driver", "user mode driver", "user mode driver framework", "buffer", "graphics buffer", "task", "process", "operation", "software application", "game", etc.

[0188] It is contemplated that any number and type of components may be added to and / or removed from the coordination / utilization mechanism 610 to facilitate various embodiments including adding, removing, and / or strengthening certain features. For simplicity, clarity, and ease of understanding of the coordination / utilization mechanism 610, many standard and / or known components (such as standard and / or known components of a computing device) are not shown or discussed herein. It is contemplated that the embodiments described herein are not limited to any particular technology, topology, system, architecture, and / or standard, and are dynamic enough to adopt and adapt to any future changes.

[0189] Figure 8A A transaction framework 800 at the application processor 612 and / or graphics processor 614 for facilitating pre-analysis training is shown according to one embodiment. For the sake of brevity, many of the details previously discussed may not be discussed or repeated hereinafter. Figures 1 to 7 Any process associated with the framework 800 may be executed by processing logic, which may include hardware (e.g., circuitry, dedicated logic, programmable logic, etc.), software (such as instructions running on a processing device), or a combination thereof, as facilitated by the coordination / utilization mechanism 610 of Figure 6 For the sake of brevity and clarity of representation, the processes associated with the framework 800 may be shown or enumerated in a linear order; however, it is contemplated that any number of processes may be executed in parallel, asynchronously, or in a different order. In addition, the embodiments are not limited to any specific architectural placement, framework, setting, or structure of the processes and / or components, such as the framework 800.

[0190] As shown, in one embodiment, the inference hardware (such as the hardware of the application processor 612 and / or graphics processor 614) may be developed in a specific manner such that it is capable of covering all expected data sizes and precisions. For example, to improve efficiency during inference, certain portions of the hardware that are not required by the dataset may be turned off to save power, energy, etc. However, in some applications, it is considered more important to maximize the throughput of the hardware.

[0191] In the illustrated embodiment, the framework 800 includes training data 801, a learning block 803, inference data 805, and a configurable hardware model 807, wherein the illustrated training data 801 is continuously transmitted to one or more of the learning block 803 and the configurable hardware model 807, such as by transmitting configuration information 809 from the training data 801 to the configurable hardware model 807. Furthermore, in an embodiment, receiving input from the training data 801, the learning block 803, and the inference data 805, one or more configurable hardware models 807, results in inferences / predictions 811, as shown.

[0192] For example, to increase the number of operations performed per second, those processing hardware blocks required for addition, multiplication, accumulation, etc. may be reconfigured using configuration information 809 from training data 801 to be used as part of configurable hardware model 807. Such configuration information 809 may be generated at training time based on one or more data sets and transmitted at runtime to a hardware configuration controller at application processor 612 and / or graphics processor 614, such as by Figure 7 The pre-analysis training logic 703 facilitates.

[0193] Figure 8B A graphics processor 614 for improving processing utilization according to one embodiment is shown. For the sake of brevity, the previously referenced Figures 1 to 8A Any process associated with graphics processor 614 may be performed by processing logic, which may include hardware (e.g., circuitry, dedicated logic, programmable logic, etc.), software (e.g., instructions executed on a processing device), or a combination thereof, such as by Figure 6 The coordination / utilization mechanism 610 is facilitated by. For simplicity and clarity of presentation, the processes associated with the graphics processor 614 may be shown or listed in a linear order; however, it is contemplated that any number of processes may be executed in parallel, asynchronously, or in a different order. Furthermore, embodiments are not limited to any specific architectural placement, framework, arrangement, or structure of processes and / or components, such as the illustrated architectural placement within the graphics processor 614.

[0194] In one embodiment, as shown, execution unit (EU) blocks 831A, 831B, 831C, and 831D are running in context-0, while EU blocks 833A, 833B, 833C, 833D, 833E, and 833F are running in context-1. As shown, graphics processor 614 is shown as hosting stream processor (SMM0) 821 and SMM1 823, which further include barrier 835A, L1 cache 837A, shared local memory (SLM) 839A and barrier 835B, L2 cache 837B, SLM 839B, respectively.

[0195] As shown, the context scheduler 820 performs monitoring of processor utilization through the GPU using the monitoring block 825, such as monitoring the utilization of the graphics processor 614, as facilitated by Figure 7 the detection / monitoring logic 701. As further shown, context-0 and context-1, represented by EU 831A through 831D and EU 833A through 833F, respectively, have separate address spaces, where in one embodiment, the microcontroller context scheduler 820 of the graphics processor 614 monitors the extent to which the graphics processor 614 is utilized. If the utilization rate is considered low, then the context scheduler 820 can dispatch more contexts, thereby allowing additional inference problems to be resolved.

[0196] Figure 8C A transaction sequence 850 for improving the coordination of inference output with sensors is shown according to one embodiment. For the sake of brevity, many of the details previously discussed may not be discussed or repeated hereinafter Figures 1 to 8B Any process associated with the transaction sequence 850 can be executed by processing logic, which can include hardware (e.g., circuitry, dedicated logic, programmable logic, etc.), software (such as instructions running on a processing device), or a combination thereof, as facilitated by Figure 6 the coordination / utilization mechanism 610. For the sake of brevity and clarity of representation, the processes associated with the transaction sequence 850 can be shown or enumerated in a linear order; however, it is contemplated that any number of processes can be executed in parallel, asynchronously, or in a different order. Additionally, the embodiments are not limited to any specific architectural placement, framework, setting, or structure of the processes and / or components, such as the architectural placement shown within the transaction sequence 850.

[0197] The transaction sequence 850 begins with Figure 6 the sensor 851 (e.g., an intelligent camera) of the I / O source 604, where the sensor 851 can include any number and type of sensors, such as an intelligent camera with an integrated image, a signal processor, where, for example, an Internet service provider (ISP) can be external to the camera. As shown, the image is captured by the sensor / camera 851, and the initially captured image is then transmitted to the model 853, which can (such as at 13%) indicate that the probability of the node inference result is much lower than normal (or below a certain threshold).

[0198] At 855, in one embodiment, before any inference operations are completed, the sensor / camera 851 and / or the ISP are requested to apply a filter to the original image, such that the inference result can be improved, as facilitated by Figure 7The inference coordination logic 705 promotes. For example, filters can be used to reduce any redundant objects in the scene, such as trees, people, stores, animals, etc., which can lead to improved result quality. In one embodiment, Figure 7 the inference coordination logic 705 promotes the sensor / camera 851 to apply the filter to the images and / or videos it captures, such that the filter is used to filter out the redundant traffic in the images and / or videos, subsequently resulting in an improved or enhanced model 857 based on the improved results.

[0199] Figure 8D Illustrates a transaction sequence 870 for improving the coordination of inference output with sensors. For the sake of brevity, many of the details previously discussed may not be discussed or repeated hereafter Figures 1 to 8C discussed. Any process associated with the transaction sequence 850 can be executed by processing logic, which can include hardware (e.g., circuitry, dedicated logic, programmable logic, etc.), software (such as instructions running on a processing device), or a combination thereof, as facilitated by Figure 6 the coordination / utilization mechanism 610. For the sake of simplicity and clarity of representation, the processes associated with the transaction sequence 870 can be shown or enumerated in a linear order; however, it is contemplated that any number of processes can be executed in parallel, asynchronously, or in a different order. Additionally, embodiments are not limited to any specific architectural placement, framework, setting, or structure of the processes and / or components, such as the architectural placement within the illustrated transaction sequence 870.

[0200] The transaction sequence 870 begins with a sensor (e.g., an intelligent camera) 851 that captures images and / or videos of a scene, where these images / videos, etc. are used to create a model, such as a camera model 871. As shown here, using Figure 7 the early fusion logic 709, early communication between the camera model 871 and another model 877 (such as a Lidar model) is facilitated through and using the combined fusion object ID module 873. In one embodiment, the model 877 can be extracted or obtained from a storage device 879, and the model can be Figure 7 a part of one or more in the database 730. As further shown, in one embodiment, this communication can include the correspondence of early cues between the two models 871, 877, where this communication is collected, stored, or transmitted by the combined fusion object ID module 873, such that it can subsequently be used for path planning, decision making, and other similar planning and predictions, as facilitated by Figure 7 the early fusion logic 709.

[0201] Figure 9A 、 Figure 9BShows transaction sequences 900, 930 illustrating a usage model according to an embodiment. For simplicity, many of the details previously discussed may not be discussed or repeated hereinafter Figures 1 to 8D among the details discussed. As shown in transaction sequences 900, 930, there are two basic usage models, where as Figure 9A shown, one is how the GPU hardware or privileged management process can update the system-allocated percentage and adjust each process to comply with the allocation.

[0202] For example, as shown in transaction sequence 900, a PID controller 909 is employed to control and adjust the system-allocated percentage 911 of each process to achieve a high level of GPU utilization. In one embodiment, this PID controller 909 can be hosted by or embedded in the graphics processor 614. As further shown, the user application requirements 901 can act as upper and lower bounds to constrain the controller output, thus keeping the controller output within the limit range by transmitting the upper and lower bounds to the PID controller 909.

[0203] In addition, as shown, data from the current system allocation 903, the immediate demands 905 from the scheduler, and the current control target 907 are also transmitted to the PID controller 909 to allow for better control and management, as facilitated by the NN scheduling logic 711. It is envisioned that the PID controller 909 can have any range of complexity available for percentage allocation, and a proportional-integral-derivative controller can be a basic one.

[0204] Now referring to Figure 9B transaction sequence 930, which shows how user applications update their desired lower percentage according to the current system requirements. For example, as shown, similar to Figure 9A transaction sequence 900, a PID controller 909 is employed, which is capable of receiving relevant information such as the user application process PID requirements 931, the current system allocation 933, the immediate demands 935 from the scheduler, and the current control target 937, in order to subsequently process this information individually and / or jointly to provide better control and adjustment of the next user application requirement 941.

[0205] Figure 9C Shows a chart 950 demonstrating prioritization options according to an embodiment. For simplicity, many of the details previously discussed may not be discussed or repeated hereinafter Figures 1 to 9B among the details discussed. In the illustrated embodiment of chart 950, as shown by Figure 7The NN scheduling logic 711 promotes prioritization that can be used to allocate more execution units to one NN (compared to another NN), which can still allow the non-safety-related network 953 to operate as long as the safety-critical networks 951, 953 have the resources they need. These resources can include or refer to storage, cache, scratchpad, a percentage of some computing elements, etc. This new technology can be implemented in software, hardware, or any combination thereof.

[0206] For example, the non-safety-related NN2 953 is shown as being interrupted because the safety-critical NN3 955 is triggered to run due to some external event or time trigger, where as shown, NN2 953 can then resume after the event or timing at NN3 955 ends.

[0207] Machine Learning Overview

[0208] A machine learning algorithm is an algorithm that can learn based on a set of data. Embodiments of machine learning algorithms can be designed to model high-level abstractions within a dataset. For example, an image recognition algorithm can be used to determine which of several categories a given input belongs to; a regression algorithm can output a numerical value given an input; and a pattern recognition algorithm can be used to generate translated text or perform text-to-speech and / or speech recognition.

[0209] One example type of machine learning algorithm is a neural network. There are many types of neural networks; a simple type of neural network is a feedforward network. A feedforward network can be implemented as an acyclic graph where nodes are arranged in layers. Generally, a feedforward network topology includes an input layer and an output layer, separated by at least one hidden layer. The hidden layer transforms the input received by the input layer into a representation useful for generating an output in the output layer. Network nodes are fully connected via edges to nodes in adjacent layers, but there are no edges between nodes within each layer. Data received at the nodes of the input layer of the feedforward network is propagated (i.e., "fed forward") via an activation function to the nodes of the output layer, which calculates the state of the nodes in each successive layer of the network based on coefficients ("weights"), each of which is associated with one of the edges connecting these layers. Depending on the specific model represented by the algorithm being executed, the output from a neural network algorithm can take various forms.

[0210] Before a machine learning algorithm can be used to model a specific problem, a training data set is used to train the algorithm. Training a neural network involves: selecting a network topology; using a set of training data that represents the problem being modeled by the network; and adjusting the weights until the network model exhibits a minimum error for all instances of the training data set. For example, during the supervised learning training process for a neural network, the output produced by the network in response to an input representing an instance in the training data set is compared with the "correct" labeled output for that instance; an error signal representing the difference between the output and the labeled output is calculated; and the weights associated with the connections are adjusted to minimize the error as the error signal is propagated backward through the layers of the network. When the error for each output generated from an instance of the training data set is minimized, the network is considered to be "trained".

[0211] The accuracy of machine learning algorithms is greatly affected by the quality of the data sets used to train the algorithms. The training process can be computationally intensive and may require a large amount of time on a conventional general-purpose processor. Therefore, parallel processing hardware is used to train many types of machine learning algorithms. This is particularly useful for optimizing the training of neural networks because the computations performed when adjusting the coefficients in a neural network are naturally suited to parallel implementation. Specifically, many machine learning algorithms and software applications have been adapted to use parallel processing hardware within general-purpose graphics processing devices.

[0212] Figure 10 is a generalized diagram of a machine learning software stack 1000. A machine learning application 1002 can be configured to train a neural network using a training data set or to implement machine intelligence using a trained deep neural network. The machine learning application 1002 can include training and inference capabilities for neural networks and / or specialized software, which can be used to train a neural network before deployment. The machine learning application 1002 can implement any type of machine intelligence, including but not limited to: image recognition, mapping and localization, autonomous navigation, speech synthesis, medical imaging, or language translation.

[0213] Hardware acceleration for a machine learning application 1002 can be implemented via a machine learning framework 1004. The machine learning framework 1004 can provide a library of machine learning primitives. Machine learning primitives are the basic operations that machine learning algorithms typically perform. In the absence of the machine learning framework 1004, developers of machine learning algorithms would need to create and optimize the main computational logic associated with the machine learning algorithms and then re-optimize the computational logic when a new parallel processor is developed. In contrast, the machine learning application can be configured to perform the necessary computations using the primitives provided by the machine learning framework 1004. Exemplary primitives include tensor convolution, activation functions, and pooling, which are computational operations performed when training a convolutional neural network (CNN). The machine learning framework 1004 can also provide primitives for implementing basic linear algebra subprograms performed by many machine learning algorithms, such as matrix and vector operations.

[0214] The machine learning framework 1004 can process input data received from the machine learning application 1002 and generate appropriate inputs to a compute framework 1006. The compute framework 1006 can abstract the underlying instructions provided to a GPGPU driver 1008 so that the machine learning framework 1004 can utilize hardware acceleration via GPGPU hardware 1010 without the machine learning framework 1004 having to be very familiar with the architecture of the GPGPU hardware 1010. Additionally, the compute framework 1006 can implement hardware acceleration for the machine learning framework 1004 across multiple types and generations of GPGPU hardware 1010.

[0215] GPGPU Machine Learning Acceleration

[0216] Figure 11 Show a highly parallel general-purpose graphics processing unit 1100 according to an embodiment. In one embodiment, a general-purpose processing unit (GPGPU) 1100 can be configured to be particularly efficient in processing this type of computational workload associated with training deep neural networks. Additionally, the GPGPU 1100 can be directly linked to other instances of GPGPUs to create a multi-GPU cluster, thereby improving the training speed of particularly deep neural networks.

[0217] The GPGPU 1100 includes a host interface 1102 for implementing a connection with a host processor. In one embodiment, the host interface 1102 is a PCI Express interface. However, the host interface can also be a vendor-specific communication interface or communication fabric. The GPGPU 1100 receives commands from the host processor and uses a global scheduler 1104 to distribute execution threads associated with those commands to a set of compute clusters 1106A through 1106H. The compute clusters 1106A through 1106H share a cache memory 1108. The cache memory 1108 can act as a cache memory in the cache memory within the compute clusters 1106A through 1106H.

[0218] The GPGPU 1100 includes memories 1114A through 1114B that are coupled to the compute clusters 1106A through H via a set of memory controllers 1112A through 1112B. In various embodiments, the memories 1114A through 1114B can include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory (such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory). In one embodiment, the memory cells 224A through 224N can also include 3D stacked memory, including but not limited to high bandwidth memory (HBM).

[0219] In one embodiment, each compute cluster GPLAB06A-H includes a set of graphics multiprocessors, such as Figure 4A the graphics multiprocessor 400. The graphics multiprocessors of the compute clusters include various types of integer and floating-point logic units that can perform computational operations at a range of precisions, including precisions suitable for machine learning computations. For example and in one embodiment, at least one subset of the floating-point units of each of the compute clusters 1106A through H can be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of the floating-point units can be configured to perform 64-bit floating-point operations.

[0220] Multiple instances of GPGPU 1100 can be configured to operate as a compute cluster. The communication mechanisms used by the compute cluster for synchronization and data exchange vary across embodiments. In one embodiment, multiple instances of GPGPU 1100 communicate via host interface 1102. In one embodiment, GPGPU 1100 includes an I / O hub 1108 that couples GPGPU 1100 to GPU link 1110, which enables a direct connection to other instances of the GPGPU. In one embodiment, GPU link 1110 is coupled to a dedicated GPU-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 1100. In one embodiment, GPU link 1110 is coupled to a high-speed interconnect for transferring and receiving data to and from other GPGPUs or parallel processors. In one embodiment, multiple instances of GPGPU 1100 are located in separate data processing systems and communicate via a network device that can be accessed via host interface 1102. In one embodiment, in addition to or as an alternative to host interface 1102, GPU link 1110 can also be configured to enable connection to a host processor.

[0221] While the illustrated configuration of GPGPU 1100 can be configured to train a neural network, one embodiment provides an alternative configuration of GPGPU 1100 that can be configured for deployment within a high-performance or low-power inference platform. In the inference configuration, GPGPU 1100 includes fewer compute clusters 1106A through H than in the training configuration. Additionally, the memory technologies associated with memories 1114A through 1114B can differ between the inference and training configurations. In one embodiment, the inference configuration of GPGPU 1100 can support inference-specific instructions. For example, the inference configuration can provide support for one or more 8-bit integer dot product instructions that are typically used during inference operations for deployed neural networks.

[0222] Figure 12 FIG. 1200 shows a multi-GPU computing system 1200 according to an embodiment. The multi-GPU computing system 1200 can include a processor 1202 that is coupled to multiple GPGPUs 1206A through D via a host interface switch 1204. In one embodiment, host interface switch 1204 is a PCI Express switch device that couples processor 1202 to a PCI Express bus through which processor 1202 can communicate with the set of GPGPUs 1206A through D. Each of the multiple GPGPUs 1206A through 1206D can be Figure 11An instance of the GPGPU 1100. The GPGPUs 1206A to D can be interconnected via a set of high-speed point-to-point GPU-GPU links 1216. The high-speed GPU-GPU links can be connected to each of the GPGPUs 1206A to 1206D via dedicated GPU links (e.g., such as the GPU link 1110 in Figure 11 ). The P2P GPU links 1216 enable direct communication between each of the GPGPUs 1206A to D without communicating through the host interface bus (the processor 1202 is connected to the host interface bus). In the case of GPU-GPU traffic for the P2P GPU links, the host interface bus is still available for system memory access or communication with other instances of the multi-GPU computing system 1200 (e.g., via one or more network devices). Although in the illustrated embodiment the GPGPUs 1206A to D are connected to the processor 1202 via the host interface switch 1204, in one embodiment, the processor 1202 includes direct support for the P2P GPU links 1216 and can be directly connected to the GPGPUs 1206A to 1206D.

[0223] Machine Learning Neural Network Implementation

[0224] The computing architectures provided by the embodiments described herein can be configured to perform these types of parallel processing that are particularly suitable for training and deploying neural networks for machine learning. A neural network can generally be generalized as a network of functions with graphical relationships. As is well known in the art, there are various types of neural network implementations used in machine learning. An exemplary type of neural network is the feedforward network as previously described.

[0225] The second exemplary type of neural network is a Convolutional Neural Network (CNN). A CNN is a specialized feedforward neural network for processing data with a known, grid-like topology (such as, image data). Thus, CNNs are commonly used in computer vision and image recognition applications, but they can also be used for other types of pattern recognition, such as speech and language processing. The nodes in the input layer of a CNN are organized into a set of "filters" (feature detectors inspired by the receptive fields found in the retina), and the output of each set of filters is propagated to the nodes in successive layers of the network. The computations used for a CNN include applying the convolution mathematical operation to each filter to produce the output of the filter. Convolution is a specialized mathematical operation performed by two functions to produce a third function, which is a modified version of one of the two original functions. In convolutional network terminology, the first function with respect to convolution can be referred to as the input, while the second function can be referred to as the convolution kernel. The output can be referred to as the feature map. For example, the input to a convolutional layer can be a multi-dimensional data array that defines the various color components of an input image. The convolution kernel can be a multi-dimensional parameter array, where the parameters are adapted through the training process for the neural network.

[0226] A Recurrent Neural Network (RNN) is a class of feedforward neural network that includes feedback connections between layers. An RNN enables the modeling of sequential data by sharing parameter data across different parts of the neural network. The architecture of an RNN includes loops. These loops represent the influence of the current value of a variable on its own value at a future time, as at least a portion of the output data from the RNN is used as feedback for processing subsequent inputs in the sequence. This feature makes RNNs particularly useful for language processing due to the variable nature in which language data can be composed.

[0227] The figures described below present exemplary feedforward, CNN, and RNN networks, and describe general processes for training and deploying each of those types of networks, respectively. It will be understood that these descriptions are exemplary and non-limiting with respect to any particular embodiments described herein, and generally the concepts shown can be applied to deep neural networks and machine learning techniques in general.

[0228] The exemplary neural networks described above can be used to perform deep learning. Deep learning is machine learning using deep neural networks. In contrast to shallow neural networks that include only a single hidden layer, the deep neural networks used in deep learning are artificial neural networks composed of multiple hidden layers. Deeper neural networks are generally more computationally intensive to train. However, the additional hidden layers of the network enable multi-step pattern recognition, which results in reduced output error relative to shallow machine learning techniques.

[0229] Deep neural networks used in deep learning typically include a front-end network for performing feature recognition coupled to a back-end network representing a mathematical model that can perform operations (e.g., object classification, speech recognition, etc.) based on the feature representation provided to the model. Deep learning enables machine learning to be performed without performing manual feature engineering for the model. Instead, a deep neural network can learn features based on the statistical structure or correlations within the input data. The learned features can be provided to the mathematical model, which can map the detected features to an output. The mathematical model used by the network is typically specific to the particular task to be performed, and different models will be used to perform different tasks.

[0230] Once the neural network is structured, a learning model can be applied to the network to train the network to perform a specific task. The learning model describes how to adjust the weights within the model to reduce the output error of the network. Backpropagation of error is a commonly used method for training neural networks. An input vector is presented to the network for processing. A loss function is used to compare the output of the network with the desired output, and an error value is calculated for each neuron in the output layer. These error values are then propagated backward until each neuron has an associated error value that roughly represents its contribution to the original output. The network can then learn from those errors using an algorithm (such as the stochastic gradient descent algorithm) to update the weights of the neural network.

[0231] Figure 13A To B show exemplary convolutional neural networks. Figure 13A Show the individual layers within the CNN. As Figure 13A shown, an exemplary CNN for modeling image processing can receive an input 1302 that describes the red, green, and blue (RGB) components of an input image. The input 1302 can be processed by a plurality of convolutional layers (e.g., convolutional layer 1304, convolutional layer 1306). Optionally, the output from the plurality of convolutional layers can be processed by a set of fully connected layers 1308. Neurons in the fully connected layers have full connections to all the activation functions in the previous layer, as previously described for feedforward networks. The output from the fully connected layers 1308 can be used to generate an output result from the network. Matrix multiplication can be used instead of convolution to calculate the activation functions within the fully connected layers 1308. Not all CNN implementations use the fully connected layer DPLA08. For example, in some implementations, the convolutional layer 1306 can generate the output of the CNN.

[0232] The convolutional layer is sparsely connected, which is different from the traditional neural network configuration found in the fully connected layer 1308. Traditional neural network layers are fully connected such that each output unit interacts with each input unit. However, the convolutional layer is sparsely connected because the output of the convolution of the receptive field (rather than the corresponding state values of each node in the receptive field) is input to the nodes of the subsequent layer, as shown. The kernel associated with the convolutional layer performs the convolution operation and the output of the convolution operation is sent to the next layer. The dimensionality reduction performed within the convolutional layer is one aspect that enables the CNN to scale to handle large images.

[0233] Figure 13B Exemplary computational stages within the convolutional layer of the CNN are shown. The input 1312 to the convolutional layer of the CNN can be processed in three stages of the convolutional layer 1314. These three stages can include a convolution stage 1316, a detector stage 1318, and a pooling stage 1320. Then, the convolutional layer 1314 can output the data to a successive convolutional layer. The last convolutional layer of the network can generate output feature map data or provide an input to the fully connected layer, for example to generate classification values for the input to the CNN.

[0234] A number of convolutions are performed in parallel in the convolution stage 1316 to produce a set of linear activation functions. The convolution stage 1316 can include an affine transformation, which is any transformation that can be specified as a linear transformation plus a translation. Affine transformations include rotation, translation, scaling, and combinations of these transformations. The convolution stage computes the output of a function connected to a specific region in the input (e.g., a neuron), which can be determined as the local region associated with the neuron. The neuron computes the dot product between the weights of the neuron and the region in the local input to which the neuron is connected. The output from the convolution stage 1316 defines a set of linear activation functions to be processed by successive stages of the convolutional layer 1314.

[0235] The linear activation functions can be processed by the detector stage 1318. In the detector stage 1318, each linear activation function is processed by a non-linear activation function. The non-linear activation function increases the non-linear nature of the overall network without affecting the receptive field of the convolutional layer. Several types of non-linear activation functions can be used. One specific type is the rectified linear unit (ReLU), which uses an activation function defined as f(x) = max(0, x), such that the activation function is thresholded to zero.

[0236] The pooling stage 1320 uses a pooling function that replaces the output of the convolutional layer 1306 with a summary statistic of nearby outputs. The pooling function can be used to introduce translation invariance into the neural network so that a slight translation to the input does not change the pooled output. The invariance of local translation can be useful when the feature existence of the input data is more important than the precise location of the feature. Various types of pooling functions can be used during the pooling stage 1320, including maximum pooling, average pooling, and L2 norm pooling. In addition, some CNN implementations do not include a pooling stage. Instead, such an implementation substitutes an additional convolution stage, which has an increased stride relative to the previous convolution stage.

[0237] The output from the convolutional layer 1314 may then be processed by the next layer 1322. The next layer 1322 may be an additional convolutional layer or one of the fully connected layers 1308. For example, Figure 13A The first convolutional layer 1304 can output to the second convolutional layer 1306, and the second convolutional layer can output to the first layer in the fully connected layer 1308.

[0238] Figure 14 An exemplary recurrent neural network 1400 is shown. In a recurrent neural network (RNN), the previous state of the network affects the output of the current state of the network. RNNs can be established in a variety of ways using a variety of functions. The use of RNNs generally revolves around the use of mathematical models to predict the future based on previous input sequences. For example, RNNs can be used to perform statistical language modeling to predict upcoming words given a previous word sequence. The RNN 1400 shown can be described as having the following: an input layer 1402, which receives an input vector; a hidden layer 1404, for implementing a recursive function; a feedback mechanism 1405, for implementing a 'memory' of previous states; and an output layer 1406, for outputting a result. RNN 1400 operates based on time steps. The state of the RNN at a given time step is affected based on the previous time step via the feedback mechanism 1405. For a given time step, the state of the hidden layer 1404 is defined by the previous state and the input at the current time step. The initial input (x1) at the first time step can be processed by the hidden layer 1404. The second input (x2) can be processed by the hidden layer 1404 using the state information determined during the processing of the initial input (x1). The given state can be calculated as f(Ux t +Ws t-1 ), where U and W are parameter matrices. Function f is typically nonlinear, such as a variant of the hyperbolic tangent function (Tanh) or a modified function f(x)=max(0,x). However, the specific mathematical function used in hidden layer 1404 may vary depending on the specific implementation details of RNN 1400.

[0239] In addition to the basic CNN and RNN networks described, variations of those networks can also be implemented. An example RNN variant is the long short-term memory (LSTM) RNN. The LSTM RNN is capable of learning long-term dependencies that may be necessary for processing longer language sequences. A variant of the CNN is the convolutional deep belief network, which has a structure similar to the CNN and is trained in a manner similar to the deep belief network. A deep belief network (DBN) is a generative neural network consisting of multiple layers of stochastic (random) variables. The DBN can be trained layer by layer using greedy unsupervised learning. Then, the learned weights of the DBN can be used to provide a pre-trained neural network by determining a set of optimal initial weights for the neural network.

[0240] Figure 15 Illustrates the training and deployment of a deep neural network. Once a given network has been structured for a task, the training dataset 1502 is used to train the neural network. Various training frameworks 1504 have been developed to enable hardware acceleration of the training process. For example, Figure 10 the machine learning framework 1004 can be configured as the training framework 1004. The training framework 1004 can be hooked up to the untrained neural network 1506 and enable the use of the parallel processing resources described herein to train the untrained neural network to generate a trained neural network 1508.

[0241] To initiate the training process, the initial weights can be selected randomly or by pre-training using a deep belief network. Then, the training loop is performed in a supervised or unsupervised manner.

[0242] Supervised learning is a learning method in which training is performed as an arbitration operation, such as when the training dataset 1502 includes inputs (paired with their expected outputs), or when the training dataset includes inputs with known outputs and the outputs of the neural network are manually graded. The network processes the inputs and compares the resulting outputs with a set of expected or desired outputs. Then, the error is backpropagated through the system. The training framework 1504 can be adjusted to adjust the weights that control the untrained neural network 1506. The training framework 1504 can provide tools for monitoring the extent to which the untrained neural network 1506 converges to a model suitable for generating correct answers based on the known input data. The training process occurs repeatedly as the weights of the network are adjusted to improve the output generated by the neural network. The training process can continue until the neural network reaches a statistically desired accuracy associated with the trained neural network 1508. Then, the trained neural network 1508 can be deployed to perform any number of machine learning operations.

[0243] Unsupervised learning is a learning method in which the network attempts to train itself using unlabeled data. Thus, for unsupervised learning, the training data set 1502 will include input data without any associated output data. The untrained neural network 1506 can learn groupings within the unlabeled input and can determine how individual inputs relate to the overall data set. Unsupervised training can be used to generate self-organizing maps, which are a type of trained neural network 1507 that can perform operations useful in data dimensionality reduction. Unsupervised training can also be used to perform anomaly detection, which allows identification of data points in the input data set that deviate from the normal pattern of the data.

[0244] Variations of supervised and unsupervised training can also be employed. Semi-supervised learning is a technique in which the training data set 1502 includes a mixture of labeled and unlabeled data of the same distribution. Incremental learning is a variant of supervised learning in which input data is continuously used for further training of the model. Incremental learning enables the trained neural network 1508 to adapt to new data 1512 without forgetting the knowledge embedded in the network during initial training.

[0245] Whether supervised or unsupervised, the training process for particularly deep neural networks can be computationally too intensive for a single computing node. A distributed network of computing nodes can be used instead of a single computing node to speed up the training process.

[0246] Figure 16 is a block diagram showing distributed learning. Distributed learning is the training of a model that uses multiple distributed computing nodes to perform supervised or unsupervised training of a neural network. The distributed computing nodes can each include one or more host processors and one or more of the general processing nodes, such as the highly parallel general-purpose graphics processing unit 1100 in FIG. 1100. As shown, distributed learning can perform model parallelism 1602, data parallelization 1604, or a combination of model and data parallelization 1604.

[0247] In model parallelism 1602, different computing nodes in a distributed system can perform training computations for different parts of a single network. For example, each layer of a neural network can be trained by different processing nodes of the distributed system. Benefits of model parallelism include the ability to scale to particularly large models. Splitting the computations associated with different layers of the neural network enables the training of ultra-large neural networks where the weights of all layers will not fit into the memory of a single computing node. In some instances, model parallelism can be particularly useful in performing unsupervised training of large neural networks.

[0248] In data parallelization 1604, different nodes of a distributed network have a complete instance of the model, and each node receives a different portion of the data. The results from the different nodes are then combined. While different methods for data parallelization are possible, data parallel training methods all require a technique for combining the results and synchronizing the model parameters between each node. Exemplary methods for combining data include parameter averaging and update-based data parallelization. Parameter averaging trains each node on a subset of the training data and sets the global parameters (e.g., weights, biases) to the average of the parameters from each node. Parameter averaging uses a central parameter server that holds the parameter data. Update-based data parallelization is similar to parameter averaging, except that instead of passing the parameters from the nodes to the parameter server, the updates to the model are passed. Additionally, update-based data parallelization can be performed in a decentralized manner, where the updates are compressed and passed between nodes.

[0249] For example, combined model and data parallelization 1606 can be implemented in a distributed system in which each computing node includes multiple GPUs. Each node can have a complete instance of the model, where individual GPUs within each node are used to train different parts of the model.

[0250] Distributed training has increased overhead relative to training on a single machine. However, the parallel processors and GPGPUs described herein can each implement techniques for reducing the overhead of distributed training, including techniques for implementing high-bandwidth GPU-GPU data transfer and accelerated remote data synchronization.

[0251] Exemplary Machine Learning Applications

[0252] Machine learning can be applied to solve a number of technical problems, including but not limited to computer vision, autonomous driving and navigation, speech recognition, and language processing. Computer vision has traditionally been one of the most active research areas for machine learning applications. The applications of computer vision range from replicating human visual capabilities (e.g., recognizing faces) to creating new classes of visual capabilities. For example, a computer vision application can be configured to recognize sound waves from vibrations induced in an object visible in a video. Machine learning accelerated by parallel processors enables the use of training datasets that are significantly larger than previously feasible for training computer vision applications, and enables the deployment of inference systems using low-power parallel processors.

[0253] Machine learning accelerated by parallel processors has autonomous driving applications, including lane and road sign recognition, obstacle avoidance, navigation, and driving control. The accelerated machine learning techniques can be used to train driving models based on data sets that define appropriate responses to specific training inputs. The parallel processors described herein can enable the rapid training of increasingly complex neural networks for autonomous driving solutions and enable the deployment of low-power inference processors in mobile platforms suitable for integration into autonomous vehicles.

[0254] Parallel processor-accelerated deep neural networks have enabled machine learning methods for automatic speech recognition (ASR). ASR includes creating a function that computes the most likely language sequence given an input acoustic sequence. Accelerated machine learning using deep neural networks has enabled replacing the previously used hidden Markov models (HMMs) and Gaussian mixture models (GMMs) for ASR.

[0255] Parallel processor-accelerated machine learning can also be used to accelerate natural language processing. Automated learning programs can use statistical inference algorithms to produce models that are robust to errors or unfamiliar inputs. Exemplary natural language processor applications include automatic machine translation between human languages.

[0256] The parallel processing platforms for machine learning can be divided into a training platform and a deployment platform. The training platform is typically highly parallel and includes optimizations for accelerating multi-GPU single-node training and multi-node multi-GPU training. Exemplary parallel processors suitable for training include the highly parallel general-purpose graphics processing unit 1100 of FIG. 1100 and the multi-GPU computing system 1200 of FIG. 1200. In contrast, the deployed machine learning platforms typically include low-power parallel processors suitable for use in products such as cameras, autonomous robots, and autonomous vehicles.

[0257] Figure 17 An exemplary inference system-on-chip (SOC) 1700 suitable for performing inference using a trained model is shown. The SOC 1700 can integrate multiple processing components, including a media processor 1702, a vision processor 1704, a GPGPU 1706, and a multi-core processor 1708. The SOC 1700 can additionally include on-chip memory 1705, which can implement a shared on-chip data pool accessible by each of the processing components. The processing components can be optimized for low-power operation to enable deployment to a variety of machine learning platforms, including autonomous vehicles and autonomous robots. For example, one implementation of the SOC 1700 can be used as part of the main control system for an autonomous vehicle. In the case where the SOC 1700 is configured for use in an autonomous vehicle, the SOC is designed and configured to comply with relevant functional safety standards for deployment jurisdiction.

[0258] During operation, the media processor 1702 and the vision processor 1704 can work in concert to accelerate computer vision operations. The media processor 1702 can enable low-latency decoding of multiple high-resolution (e.g., 4K, 8K) video streams. The decoded video streams can be written to a buffer in the on-chip memory 1705. Then, the vision processor 1704 can parse the decoded video and perform preliminary processing operations on the frames of the decoded video to prepare the frames for processing using a trained image recognition model. For example, the vision processor 1704 can accelerate the convolutional operations for a CNN (for performing image recognition on high-resolution video data), and the backend model computations are performed by the GPGPU 1706.

[0259] The multi-core processor 1708 can include control logic for facilitating the ordering and synchronization of data transfers and shared memory operations performed by the media processor 1702 and the vision processor 1704. The multi-core processor 1708 can also act as an application processor for executing software applications that can use the inference computing capabilities of the GPGPU 1706. For example, at least a portion of the navigation and driving logic can be implemented in software executed on the multi-core processor 1708. Such software can directly issue the computational workload to the GPGPU 1706, or can issue the computational workload to the multi-core processor 1708, which can offload at least a portion of those operations to the GPGPU 1706.

[0260] The GPGPU 1706 can include compute clusters, such as a low-power configuration of the compute clusters 1106A through 1106H within the highly parallel general-purpose graphics processing unit 1100. The compute clusters within the GPGPU 1706 can support instructions that are explicitly optimized for performing inference computations on trained neural networks. For example, the GPGPU 1706 can support instructions for performing low-precision computations (such as 8-bit and 4-bit integer vector operations).

[0261] System Overview II

[0262] Figure 18 is a block diagram of a processing system 1800 according to an embodiment. In various embodiments, the system 1800 includes one or more processors 1802 and one or more graphics processors 1808, and can be a single-processor desktop system, a multi-processor workstation system, or a server system with a large number of processors 1802 or processor cores 1807. In one embodiment, the system 1800 is a processing platform incorporated within a system-on-chip (SoC) integrated circuit for use in a mobile device, a handheld device, or an embedded device.

[0263] Embodiments of system 1800 may include or incorporate a server-based gaming platform, a game console, including a game and media console, a mobile game console, a handheld game console, or an online game console. In some embodiments, system 1800 is a mobile phone, a smartphone, a tablet computing device, or a mobile Internet device. Data processing system 1800 may also include a wearable device (such as a smartwatch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device), coupled to, or integrated in, the wearable device. In some embodiments, data processing system 1800 is a television or set-top box device having one or more processors 1802 and a graphical interface generated by one or more graphics processors 1808.

[0264] In some embodiments, each of the one or more processors 1802 includes one or more processor cores 1807 for processing instructions that, when executed, perform the operations of system and user software. In some embodiments, each of the one or more processor cores 1807 is configured to process a particular instruction set 1809. In some embodiments, the instruction set 1809 may facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction words (VLIW). The multiple processor cores 1807 may each process a different instruction set 1809, which may include instructions for facilitating the emulation of other instruction sets. The processor cores 1807 may also include other processing devices, such as a digital signal processor (DSP).

[0265] In some embodiments, processor 1802 includes a cache memory 1804. Depending on the architecture, processor 1802 may have a single internal cache or multiple levels of internal caches. In some embodiments, the cache memory is shared among the components of processor 1802. In some embodiments, processor 1802 also uses an external cache (e.g., a level 3 (L3) cache or a last-level cache (LLC)) (not shown), and known cache coherence techniques may be used to share the external cache among the processor cores 1807. Additionally, a register file 1806 is included in processor 1802, and the processor may include different types of registers for storing different types of data (e.g., integer registers, floating-point registers, status registers, and instruction pointer registers). Some registers may be general-purpose registers, while other registers may be specific to the design of processor 1802.

[0266] In some embodiments, the processor 1802 is coupled to a processor bus 1810, which is used to transfer communication signals, such as address, data, or control signals, between the processor 1802 and other components within the system 1800. In one embodiment, the system 1800 uses an exemplary 'hub' system architecture, including a memory controller hub 1816 and an input / output (I / O) controller hub 1830. The memory controller hub 1816 facilitates communication between the memory device and other components of the system 1800, while the I / O controller hub (ICH) 1830 provides a connection to I / O devices via a local I / O bus. In one embodiment, the logic of the memory controller hub 1816 is integrated within the processor.

[0267] The memory device 1820 can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or some other memory device with suitable performance for use as a processing memory. In one embodiment, the memory device 1820 can operate as the system memory of the system 1800 to store data 1822 and instructions 1821 for use when one or more processors 1802 execute an application or process. The memory controller hub 1816 is also coupled to an optional external graphics processor 1812, which can communicate with one or more graphics processors 1808 in the processor 1802 to perform graphics and media operations.

[0268] In some embodiments, the ICH 1830 enables peripheral components to be connected to the memory device 1820 and the processor 1802 via a high-speed I / O bus. The I / O peripherals include, but are not limited to: an audio controller 1846, a firmware interface 1828, a wireless transceiver 1826 (e.g., Wi-Fi, Bluetooth), a data storage device 1824 (e.g., a hard disk drive, a flash memory, etc.), and a legacy I / O controller 1840 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system. One or more universal serial bus (USB) controllers 1842 connect multiple input devices, such as a keyboard and a mouse 1844 combination. The network controller 1834 can also be coupled to the ICH 1830. In some embodiments, a high-performance network controller (not shown) is coupled to the processor bus 1810. It should be understood that the system 1800 shown is exemplary and not restrictive, as other types of data processing systems configured in different ways can also be used. For example, the I / O controller hub 1830 can be integrated within one or more processors 1802, or the memory controller hub 1816 and the I / O controller hub 1830 can be integrated within a discrete external graphics processor (such as the external graphics processor 1812).

[0269] Figure 19 is a block diagram of an embodiment of a processor 1900 having one or more processor cores 1902A through 1902N, an integrated memory controller 1914, and an integrated graphics processor 1908. Figure 19 Those elements of having the same reference numbers (or names) as elements in any other figure herein may operate or function in any manner similar to the manner described elsewhere herein, but are not limited thereto. Processor 1900 may include additional cores up to and including additional core 1902N represented by the dashed box. Processor cores 1902A through 1902N each include one or more internal cache units 1904A through 1904N. In some embodiments, each processor core may also access one or more shared cache units 1906.

[0270] Internal cache units 1904A through 1904N and shared cache unit 1906 represent the cache memory hierarchy internal to processor 1900. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, where the highest level of cache is classified as the LLC before external memory. In some embodiments, cache coherence logic maintains coherence between cache units 1906 and 1904A through 1904N.

[0271] In some embodiments, processor 1900 may also include a set of one or more bus controller units 1916 and a system agent core 1910. One or more bus controller units 1916 manage a set of peripheral buses, such as one or more peripheral component interconnect buses (e.g., PCI, PCI Express). System agent core 1910 provides management functions for the various processor components. In some embodiments, system agent core 1910 includes one or more integrated memory controllers 1914 for managing access to various external memory devices (not shown).

[0272] In some embodiments, one or more of processor cores 1902A through 1902N include support for simultaneous multithreading. In such embodiments, system agent core 1910 includes components for coordinating and operating cores 1902A through 1902N during multithreaded processing. Additionally, system agent core 1910 may also include a power control unit (PCU) that includes logic and components for regulating the power states of processor cores 1902A through 1902N and graphics processor 1908.

[0273] In some embodiments, additionally, the processor 1900 further includes a graphics processor 1908 for performing graphics processing operations. In some embodiments, the graphics processor 1908 is coupled to the shared cache unit 1906 set and the system agent core 1910, and the system agent core includes one or more integrated memory controllers 1914. In some embodiments, the display controller 1911 is coupled to the graphics processor 1908 to drive the graphics processor output to one or more coupled displays. In some embodiments, the display controller 1911 can be a separate module coupled to the graphics processor via at least one interconnect, or can be integrated within the graphics processor 1908 or the system agent core 1910.

[0274] In some embodiments, the ring-based interconnect unit 1912 is used to couple the internal components of the processor 1900. However, alternative interconnect units can be used, such as point-to-point interconnects, switched interconnects, or other techniques, including those well known in the art. In some embodiments, the graphics processor 1908 is coupled to the ring interconnect 1912 via the I / O link 1913.

[0275] The exemplary I / O link 1913 represents at least one of multiple varieties of multiple I / O interconnects, including package I / O interconnects that facilitate communication between various processor components and the high-performance embedded memory module 1918 (such as an eDRAM module). In some embodiments, each of the processor cores 1902A to 1902N and the graphics processor 1908 uses the embedded memory module 1918 as a shared last-level cache.

[0276] In some embodiments, the processor cores 1902A to 1902N are homogeneous cores that execute the same instruction set architecture. In another embodiment, the processor cores 1902A to 1902N are heterogeneous in terms of the instruction set architecture (ISA), where one or more of the processor cores 1902A to 1902N execute a first instruction set, while at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, the processor cores 1902A to 1902N are homogeneous in terms of microarchitecture, where one or more cores with relatively high power consumption are coupled to one or more power-efficient cores. Additionally, the processor 1900 can be implemented on one or more chips or as a SoC integrated circuit having the illustrated components among other components.

[0277] Figure 20is a block diagram of a graphics processor 2000, which can be a discrete graphics processing unit or a graphics processor integrated with multiple processing cores. In some embodiments, the graphics processor communicates with memory via a mapped I / O interface to registers on the graphics processor and using commands placed in the processor memory. In some embodiments, the graphics processor 2000 includes a memory interface 2014 for accessing memory. The memory interface 2014 can be an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory.

[0278] In some embodiments, the graphics processor 2000 further includes a display controller 2002 for driving display output data to a display device 2020. The display controller 2002 includes hardware for one or more overlapping planes of the display and components for multi-layer video or user interface elements. In some embodiments, the graphics processor 2000 includes a video codec engine 2006 for encoding, decoding, or transcode media between one or more media coding formats, including but not limited to: Moving Picture Experts Group (MPEG) (such as MPEG-2), Advanced Video Coding (AVC) formats (such as H.264 / MPEG-4 AVC), and Society of Motion Picture and Television Engineers (SMPTE) 421M / VC-1, and Joint Photographic Experts Group (JPEG) formats (such as JPEG and Motion JPEG (MJPEG) formats).

[0279] In some embodiments, the graphics processor 2000 includes a block image transfer (BLIT) engine 2004 for performing two-dimensional (2D) rasterizer operations, including for example bit boundary block transfer. However, in one embodiment, 2D graphics operations are performed using one or more components of the Graphics Processing Engine (GPE) 2010. In some embodiments, the Graphics Processing Engine 2010 is a computing engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0280] In some embodiments, the GPE 2010 includes a 3D pipeline 2012 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions for 3D primitive shapes (e.g., rectangles, triangles, etc.). The 3D pipeline 2012 includes programmable and fixed function elements that perform various tasks within the elements of the 3D / media subsystem 2015 and / or the generated execution threads. Although the 3D pipeline 2012 can be used to perform media operations, embodiments of the GPE 2010 also include a media pipeline 2016 specifically for performing media operations, such as video post-processing and image enhancement.

[0281] In some embodiments, media pipeline 2016 includes fixed function or programmable logic units to perform one or more specialized media operations, such as video decode acceleration, video deinterlacing, and video encode acceleration, in place of, or on behalf of, video codec engine 2006. In some embodiments, additionally, media pipeline 2016 also includes a thread generation unit to generate threads for execution on 3D / media subsystem 2015. The generated threads perform computations for media operations on one or more graphics execution units included in 3D / media subsystem 2015.

[0282] In some embodiments, 3D / media subsystem 2015 includes logic for executing threads generated by 3D pipeline 2012 and media pipeline 2016. In one embodiment, the pipeline sends thread execution requests to 3D / media subsystem 2015, which includes thread dispatch logic for arbitrating and dispatching the requests to available thread execution resources. Execution resources include an array of graphics execution units for processing 3D and media threads. In some embodiments, 3D / media subsystem 2015 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory (including registers and addressable memory) for sharing data between threads and for storing output data.

[0283] 3D / Media Processing

[0284] Figure 21 is a block diagram of graphics processing engine 2110 of a graphics processor according to some embodiments. In one embodiment, graphics processing engine (GPE) 2110 is Figure 20 a version of GPE 2010 as shown. Figure 21 Those elements having the same reference numbers (or names) as elements in any other figure herein may operate or function in any manner similar to the ways described elsewhere herein, but are not limited to these. For example, 3D pipeline 2012 and media pipeline 2016 are shown. Media pipeline 2016 is optional in some embodiments of GPE 2110 and may not be explicitly included within GPE 2110. For example and in at least one embodiment, a separate media and / or image processor is coupled to GPE 2110. Figure 20 3D pipeline 2012 and media pipeline 2016. Media pipeline 2016 is optional in some embodiments of GPE 2110 and may not be explicitly included within GPE 2110. For example and in at least one embodiment, a separate media and / or image processor is coupled to GPE 2110.

[0285] In some embodiments, GPE 2110 is coupled to or includes a command stream converter 2103 that provides a command stream to 3D pipeline 2012 and / or media pipeline 2016. In some embodiments, command stream converter 2103 is coupled to a memory, which may be a system memory, or one or more of an internal cache memory and a shared cache memory. In some embodiments, command stream converter 2103 receives commands from the memory and sends these commands to 3D pipeline 2012 and / or media pipeline 2016. The commands are instructions fetched from a ring buffer storing commands for 3D pipeline 2012 and media pipeline 2016. In one embodiment, additionally, the ring buffer may further include a batch command buffer storing multiple batches of multiple commands. Commands for 3D pipeline 2012 may also include references to data stored in the memory, such as but not limited to vertex and geometry data for 3D pipeline 2012 and / or image data and memory objects for media pipeline 2016. 3D pipeline 2012 and media pipeline 2016 process the commands by performing operations via logic within their respective pipelines or by dispatching one or more execution threads to execution unit array 2114.

[0286] In various embodiments, 3D pipeline 2012 may execute one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to graphics core array 2114. Graphics core array 2114 provides a unified execution resource block. The multi-purpose execution logic (e.g., execution units) within graphics core array 2114 includes support for various 3D API shader languages and may execute multiple simultaneously executing threads associated with multiple shaders.

[0287] In some embodiments, graphics core array 2114 also includes execution logic for performing media functions such as video and / or image processing. In one embodiment, in addition to graphics processing operations, the execution units further include general-purpose logic programmable to perform parallel general-purpose computing operations. The general-purpose logic may execute processing operations in parallel with or in combination with the general-purpose logic within (a) processor core(s) 1807 or Figure 18 cores 1902A to 1902N within Figure 19 ..

[0288] Output data generated by threads executing on the graphics core array 2114 can output data to memory in a unified return buffer (URB) 2118. The URB 2118 can store data for multiple threads. In some embodiments, the URB 2118 can be used to send data between different threads executing on the graphics core array 2114. In some embodiments, the URB 2118 can additionally be used for synchronization between threads on the graphics core array and fixed function logic within the shared function logic 2120.

[0289] In some embodiments, the graphics core array 2114 is scalable such that the array includes a variable number of graphics cores, each having a variable number of execution units based on the target power and performance levels of the GPE 2110. In one embodiment, the execution resources are dynamically scalable such that execution resources can be enabled or disabled as needed.

[0290] The graphics core array 2114 is coupled to shared function logic 2120, which includes multiple resources shared among the graphics cores in the graphics core array. The shared functions within the shared function logic 2120 are hardware logic units that provide dedicated complementary functions to the graphics core array 2114. In various embodiments, the shared function logic 2120 includes, but is not limited to, sampler 2121, math 2122, and inter-thread communication (ITC) 2123 logic. Additionally, some embodiments implement one or more caches 2125 within the shared function logic 2120. The shared function is implemented when the demand for a given dedicated function is not sufficient to be included within the graphics core array 2114. Instead, a single instance of the dedicated function is implemented as an independent entity within the shared function logic 2120 and shared among the execution resources within the graphics core array 2114. The exact set of functions shared among and included within the graphics core array 2114 varies between embodiments.

[0291] Figure 22 is a block diagram of another embodiment of the graphics processor 2200. Figure 22 Those elements having the same reference numbers (or names) as elements in any other figure herein can operate or function in any manner similar to the ways described elsewhere herein, but are not limited to these.

[0292] In some embodiments, the graphics processor 2200 includes a ring interconnect 2202, a pipeline front end 2204, a media engine 2237, and graphics cores 2280A through 2280N. In some embodiments, the ring interconnect 2202 couples the graphics processor to other processing units, including other graphics processors or one or more general processor cores. In some embodiments, the graphics processor is one of multiple processors integrated within a multi-core processing system.

[0293] In some embodiments, the graphics processor 2200 receives multiple batches of commands via the ring interconnect 2202. The incoming commands are interpreted by the command stream converter 2203 in the pipeline front end 2204. In some embodiments, the graphics processor 2200 includes scalable execution logic for performing 3D geometry processing and media processing via the (multiple) graphics cores 2280A to 2280N. For 3D geometry processing commands, the command stream converter 2203 supplies the commands to the geometry pipeline 2236. For at least some media processing commands, the command stream converter 2203 supplies the commands to the video front end 2234, which is coupled to the media engine 2237. In some embodiments, the media engine 2237 includes a Video Quality Engine (VQE) 2230 for video and image post-processing and a Multi-Format Encoding / Decoding (MFX) 2233 engine for providing hardware-accelerated encoding and decoding of media data. In some embodiments, the geometry pipeline 2236 and the media engine 2237 each generate execution threads for the thread execution resources provided by at least one graphics core 2280A.

[0294] In some embodiments, the graphics processor 2200 includes scalable thread execution resource characterization module cores 2280A to 2280N (sometimes referred to as core shards), each of which has multiple sub-cores 2250A to 2250N, 2260A to 2260N (sometimes referred to as core sub-shards). In some embodiments, the graphics processor 2200 can have any number of graphics cores 2280A to 2280N. In some embodiments, the graphics processor 2200 includes a graphics core 2280A that has at least a first sub-core 2250A and a second sub-core 2260A. In other embodiments, the graphics processor is a low-power processor with a single sub-core (e.g., 2250A). In some embodiments, the graphics processor 2200 includes multiple graphics cores 2280A to 2280N, each of which includes a set of first sub-cores 2250A to 2250N and a set of second sub-cores 2260A to 2260N. Each sub-core in the set of first sub-cores 2250A to 2250N includes at least a first set of execution units 2252A to 2252N and media / texture samplers 2254A to 2254N. Each sub-core in the set of second sub-cores 2260A to 2260N includes at least a second set of execution units 2262A to 2262N and samplers 2264A to 2264N. In some embodiments, each sub-core 2250A to 2250N, 2260A to 2260N shares a set of shared resources 2270A to 2270N. In some embodiments, the shared resources include shared cache memory and pixel operation logic. Other shared resources may also be included in various embodiments of the graphics processor.

[0295] Execution Logic

[0296] Figure 23 shows thread execution logic 2300, which includes an array of processing elements employed in some embodiments of the GPE. Figure 23 Those elements having the same reference numbers (or names) as elements in any other figure herein may operate or function in any manner similar to the ways described elsewhere herein, but are not limited to these.

[0297] In some embodiments, thread execution logic 2300 includes a pixel shader 2302, a thread dispatcher 2304, an instruction cache 2306, an extensible array of execution units including a plurality of execution units 2308A through 2308N, a sampler 2310, a data cache 2312, and a data port 2314. In one embodiment, the included components are interconnected via an interconnect structure that links to each of the components. In some embodiments, thread execution logic 2300 includes one or more connections to memory (such as system memory or cache memory) via instruction cache 2306, data port 2314, sampler 2310, and one or more of execution unit arrays 2308A through 2308N. In some embodiments, each execution unit (e.g., 2308A) is an individual vector processor capable of executing multiple synchronous threads and processing multiple data elements in parallel for each thread. In some embodiments, execution unit arrays 2308A through 2308N include any number of individual execution units.

[0298] In some embodiments, execution unit arrays 2308A through 2308N are primarily used to execute "shader" programs. In some embodiments, the execution units in arrays 2308A through 2308N execute an instruction set (which includes native support for many standard 3D graphics shader instructions), enabling shader programs from graphics libraries (such as Direct3D and OpenGL) to be executed with minimal translation. The execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general-purpose processing (e.g., compute and media shaders).

[0299] Each execution unit in execution unit arrays 2308A through 2308N operates on an array of data elements. The number of data elements is the "execution size", or the number of lanes for an instruction. An execution lane is the logical execution unit for data element access, masking, and flow control within an instruction. The number of lanes can be independent of the number of physical arithmetic logic units (ALUs) or floating-point units (FPUs) for a particular graphics processor. In some embodiments, execution units 2308A through 2308N support integer and floating-point data types.

[0300] The execution unit instruction set includes single instruction multiple data (SIMD) or single instruction multiple thread (SIMT) instructions. Individual data elements can be stored in registers as a packed data type, and the execution unit will process each element based on the data size of the element. For example, when operating on a 256-bit wide vector, the 256-bit vector is stored in a register, and the execution unit operates on the vector as four individual 64-bit compressed data elements (quad-word (QW) sized data elements), eight individual 32-bit compressed data elements (double-word (DW) sized data elements), sixteen individual 16-bit compressed data elements (word (W) sized data elements), or thirty-two individual 8-bit data elements (byte (B) sized data elements). However, different vector widths and register sizes are possible.

[0301] One or more internal instruction caches (e.g., 2306) are included in the thread execution logic 2300 to cache thread instructions for the execution units. In some embodiments, one or more data caches (e.g., 2312) are included to cache thread data during thread execution. In some embodiments, a sampler 2310 is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, sampler 2310 includes specialized texture or media sampling functionality to process texture or media data during sampling before providing the sampled data to the execution units.

[0302] During execution, the graphics and media pipeline sends thread initiation requests to the thread execution logic 2300 via the thread generation and dispatch logic. In some embodiments, the thread execution logic 2300 includes a local thread dispatcher 2304 that arbitrates thread initiation requests from the graphics pipeline and the media pipeline and instantiates the requested threads on one or more of the execution units 2308A through 2308N. For example, a geometry pipeline (e.g., Figure 22 2236) dispatches vertex processing, tessellation, or geometry processing threads to the thread execution logic 2300 ( Figure 23)。In some embodiments, the thread dispatcher 2304 may also handle runtime thread generation requests from executing shader programs.

[0303] Once a set of geometric objects has been processed and rasterized into pixel data, the pixel shader 2302 is called to further compute output information and cause the results to be written to an output surface (e.g., a color buffer, a depth buffer, a stencil buffer, etc.). In some embodiments, the pixel shader 2302 computes the values of vertex attributes that are interpolated across the rasterized objects. In some embodiments, the pixel shader 2302 then executes a pixel shader program supplied by an application programming interface (API). To execute the pixel shader program, the pixel shader 2302 dispatches threads to execution units (e.g., 2308A) via the thread dispatcher 2304. In some embodiments, the pixel shader 2302 uses texture sampling logic in the sampler 2310 to access texture data in a texture map stored in memory. Arithmetic operations on the texture data and the input geometric data compute the pixel color data for each geometric fragment, or discard one or more pixels without further processing.

[0304] In some embodiments, the data port 2314 provides a memory access mechanism for the thread execution logic 2300 to output processed data to memory for processing on the graphics processor output pipeline. In some embodiments, the data port 2314 includes or is coupled to one or more cache memories (e.g., the data cache 2312) to cache data via the data port for memory access.

[0305] Figure 24 is a block diagram showing a graphics processor instruction format 2400 according to some embodiments. In one or more embodiments, the graphics processor execution units support an instruction set with multiple formats. The solid boxes show components typically included in the execution unit instructions, while the dashed boxes include optional components or components only included in a subset of the instructions. In some embodiments, the described and shown instruction format 2400 is a macro-instruction, as they are the instructions supplied to the execution unit, as opposed to micro-operations generated from instruction decoding (once the instruction has been processed).

[0306] In some embodiments, the graphics processor execution units natively support instructions in a 128-bit instruction format 2410. A 64-bit compact instruction format 2430 can be used for some instructions based on the selected instruction, multiple instruction options, and the number of operands. The native 128-bit instruction format 710 provides access to all instruction options, while some options and operations are restricted in the 64-bit format 2430. The native instructions available in the 64-bit instruction format 2430 vary according to the embodiment. In some embodiments, a set of index values in an index field 2413 is used to partially compress the instruction. The execution unit hardware refers to a set of compression tables based on the index values and uses the compression table output to reconstruct the native instruction in the 128-bit instruction format 2410.

[0307] For each format, an instruction opcode 2412 defines the operation to be performed by the execution unit. The execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an add instruction, the execution unit performs a synchronous add operation across each color channel, which represents a texture element or a picture element. By default, the execution unit executes each instruction across all data channels of the operand. In some embodiments, an instruction control field 2414 enables control of certain execution options, such as channel selection (e.g., predication) and data channel ordering (e.g., mixing). For 128-bit instructions 2410, an execution size field 2416 limits the number of data channels that will be executed in parallel. In some embodiments, the execution size field 2416 is not available for the 64-bit compact instruction format 2430.

[0308] Some execution unit instructions have up to three operands, including two source operands (src0 2420, src1 2422) and one destination 2418. In some embodiments, the execution unit supports dual-destination instructions, where one of these destinations is implicit. Data operation instructions can have a third source operand (e.g., SRC2 2424), where the instruction opcode 2412 determines the number of source operands. The last source operand of the instruction can be an immediate (e.g., hard-coded) value passed with the instruction.

[0309] In some embodiments, the 128-bit instruction format 2410 includes access / address mode information 2426, which, for example, defines whether to use a direct register addressing mode or an indirect register addressing mode. When using the direct register addressing mode, the register addresses of one or more operands are provided directly by bits in the instruction 2410.

[0310] In some embodiments, the 128-bit instruction format 2410 includes an access / address mode field 2426 that specifies the address mode and / or access mode of the instruction. In one embodiment, the access mode is used to define the data access alignment for the instruction. Some embodiments support access modes including a 16-byte aligned access mode and a 1-byte aligned access mode, where the byte alignment of the access mode determines the access alignment of the instruction operands. For example, when in a first mode, instruction 2410 may use byte-aligned addressing for source and destination operands, and when in a second mode, instruction 2410 may use 16-byte aligned addressing for all source and destination operands.

[0311] In one embodiment, the address mode portion of the access / address mode field 2426 determines whether the instruction uses direct addressing or indirect addressing. When using the direct register addressing mode, the bits in instruction 2410 directly provide the register addresses of one or more operands. When using the indirect register addressing mode, the register addresses of one or more operands can be calculated based on the address register value and the address immediate field in the instruction.

[0312] In some embodiments, the instructions are grouped based on the opcode 2412 bit field to simplify opcode decoding 2440. For an 8-bit opcode, bits 4, 5, and 6 allow the execution unit to determine the type of the opcode. The exact opcode grouping shown is merely exemplary. In some embodiments, the move and logic opcode group 2442 includes data move and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, the move and logic group 2442 shares the five most significant bits (MSB), where the move (mov) instruction takes the form 0000xxxxb and the logic instruction takes the form 0001xxxxb. The flow control instruction group 2444 (e.g., call, jmp) includes instructions that take the form 0010xxxxb (e.g., 0x20). The miscellaneous instruction group 2446 includes a mix of instructions, including synchronization instructions (e.g., wait, send) that take the form 0011xxxxb (e.g., 0x30). The parallel math instruction group 2448 includes per-component arithmetic instructions (e.g., add, mul) that take the form 0100xxxxb (e.g., 0x40). The parallel math group 2448 performs arithmetic operations in parallel across data channels. The vector math group 2450 includes arithmetic instructions (e.g., dp4) that take the form 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic operations on vector operands, such as dot product operations.

[0313] Graphics Pipeline

[0314] Figure 25 It is a block diagram of another embodiment of the graphics processor 2500. Figure 25 Those elements having the same reference numbers (or names) as elements in any other figure herein may operate or function in any manner similar to those described elsewhere herein, but are not limited thereto.

[0315] In some embodiments, the graphics processor 2500 includes a graphics pipeline 2520, a media pipeline 2530, a display engine 2540, thread execution logic 2550, and a render output pipeline 2570. In some embodiments, the graphics processor 2500 is a graphics processor within a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or by commands issued via the ring interconnect 2502 to the graphics processor 2500. In some embodiments, the ring interconnect 2502 couples the graphics processor 2500 to other processing components, such as other graphics processors or general-purpose processors. Commands from the ring interconnect 2502 are interpreted by a command stream converter 2503 that supplies instructions to individual components of the graphics pipeline 2520 or the media pipeline 2530.

[0316] In some embodiments, the command stream converter 2503 directs the operation of a vertex fetcher 2505 that reads vertex data from memory and executes vertex processing commands provided by the command stream converter 2503. In some embodiments, the vertex fetcher 2505 provides vertex data to a vertex shader 2507 that performs coordinate space transformation and lighting operations on each vertex. In some embodiments, the vertex fetcher 2505 and the vertex shader 2507 execute vertex processing instructions by dispatching execution threads to execution units 2552A through 2552B via a thread dispatcher 2531.

[0317] In some embodiments, the execution units 2552A through 2552B are an array of vector processors having an instruction set for performing graphics and media operations. In some embodiments, the execution units 2552A through 2552B have attached L1 caches 2551 that are dedicated to each array or shared between the arrays. The cache can be configured as a data cache, an instruction cache, or a single cache that is partitioned to contain data and instructions in different partitions.

[0318] In some embodiments, the graphics pipeline 2520 includes a tessellation component for performing hardware-accelerated tessellation of 3D objects. In some embodiments, the programmable hull shader 811 configures the tessellation operation. The programmable domain shader 817 provides backend evaluation of the tessellation output. The tessellator 2513 operates in the direction of the hull shader 2511 and includes dedicated logic for generating a set of detailed geometric objects based on a coarse geometric model that is provided as input to the graphics pipeline 2520. In some embodiments, if tessellation is not used, the tessellation components 2511, 2513, 2517 can be bypassed.

[0319] In some embodiments, the complete geometric object can be processed by the geometry shader 2519 via one or more threads dispatched to the execution units 2552A to 2552B, or can proceed directly to the clipper 2529. In some embodiments, the geometry shader operates on the entire geometric object (rather than vertices or vertex patches as in previous stages of the graphics pipeline). If tessellation is disabled, the geometry shader 2519 receives input from the vertex shader 2507. In some embodiments, the geometry shader 2519 can be programmed by a geometry shader program to perform geometric tessellation when the tessellation unit is disabled.

[0320] Before rasterization, the clipper 2529 processes the vertex data. The clipper 2529 can be a fixed-function clipper or a programmable clipper with clipping and geometry shader functionality. In some embodiments, the rasterizer and depth test component 2573 in the render output pipeline 2570 dispatches pixel shaders to convert the geometric object into its per-pixel representation. In some embodiments, the pixel shader logic is included in the thread execution logic 2550. In some embodiments, the application can bypass rasterization and access the un-rasterized vertex data via the egress unit 2523.

[0321] The graphics processor 2500 has an interconnect bus, an interconnect fabric, or some other interconnect mechanism that allows data and messages to be passed among the major components of the graphics processor. In some embodiments, the execution units 2552A to 2552B and the associated cache(s) 2551, texture and media sampler 2554, and texture / sampler cache 2558 are interconnected via a data port 2556 to perform memory accesses and communicate with the render output pipeline components of the processor. In some embodiments, the sampler 2554, caches 2551, 2558, and execution units 2552A to 2552B each have separate memory access paths.

[0322] In some embodiments, the rendering output pipeline 2570 includes a rasterizer and depth test component 2573 that converts vertex-based objects into associated pixel-based representations. In some embodiments, the rendering output pipeline 2570 includes a windower / masker unit for performing fixed function triangle and line rasterization. Associated rendering cache 2578 and depth cache 2579 are also available in some embodiments. Pixel operation component 2577 performs pixel-based operations on the data, however in some instances, pixel operations associated with 2D operations (e.g., bitblt with blending) are performed by 2D engine 2541, or at display time by display controller 2543 using overlapping display planes instead. In some embodiments, shared L3 cache 2575 is available to all graphics components, allowing data to be shared without using the main system memory.

[0323] In some embodiments, the graphics processor media pipeline 2530 includes a media engine 2537 and a video front end 2534. In some embodiments, the video front end 2534 receives pipeline commands from command stream converter 2503. In some embodiments, the media pipeline 2530 includes a separate command stream converter. In some embodiments, the video front end 2534 processes media commands before sending the commands to media engine 2537. In some embodiments, media engine 2537 includes a thread generation function for generating threads for dispatch to thread execution logic 2550 via thread dispatcher 2531.

[0324] In some embodiments, the graphics processor 2500 includes a display engine 2540. In some embodiments, the display engine 2540 is external to the processor 2500 and is coupled to the graphics processor via a ring interconnect 2502, or some other interconnect bus or mechanism. In some embodiments, the display engine 2540 includes a 2D engine 2541 and a display controller 2543. In some embodiments, the display engine 2540 contains dedicated logic capable of operating independently of the 3D pipeline. In some embodiments, the display controller 2543 is coupled to a display device (not shown), which may be a system integrated display device (such as in a laptop computer), or an external display device attached via a display device connector.

[0325] In some embodiments, the graphics pipeline 2520 and the media pipeline 2530 may be configured to perform operations based on multiple graphics and media programming interfaces and are not dedicated to any one application programming interface (API). In some embodiments, the driver software of the graphics processor converts API dispatches dedicated to a particular graphics or media library into commands that can be processed by the graphics processor. In some embodiments, support is provided for the Open Graphics Library (OpenGL) and Open Computing Language (OpenCL) from the Khronos Group, the Direct3D library from Microsoft Corporation, or support may be provided for both OpenGL and D3D. Support may also be provided for the Open Source Computer Vision Library (OpenCV). Future APIs with compatible 3D pipelines will also be supported if a mapping from the future API's pipeline to the graphics processor's pipeline can be made.

[0326] Graphics Pipeline Programming

[0327] Figure 26A is a block diagram showing a graphics processor command format 2600 according to some embodiments. Figure 26B is a block diagram showing a graphics processor command sequence 2610 according to an embodiment. Figure 26A The solid boxes in show components that are typically included in a graphics command, while the dashed boxes include components that are optional or are only included in a subset of the graphics commands. Figure 26A An exemplary graphics processor command format 2600 includes a target client 2602 for identifying the command, a command operation code (opcode) 2604, and a data field 2606 for the relevant data of the command. Some commands also include a sub-opcode 2605 and a command size 2608.

[0328] In some embodiments, the client 2602 defines the client unit of the graphics device that processes the command data. In some embodiments, the graphics processor command parser examines the client field of each command to adjust the further processing of the command and route the command data to the appropriate client unit. In some embodiments, the graphics processor client units include a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline for processing commands. Once the command is received by the client unit, the client unit reads the opcode 2604 and the sub-opcode 2605 (if present) to determine the operation to be performed. The client unit uses the information within the data field 2606 to execute the command. For some commands, an explicit command size 2608 is expected to define the size of the command. In some embodiments, the command parser automatically determines the size of at least some of the commands based on the command opcode. In some embodiments, the commands are aligned by a multiple of the double-word length.

[0329] Figure 26B The flow diagram in shows an exemplary graphics processor command sequence 2610. In some embodiments, software or firmware of a data processing system characterized by an embodiment of a graphics processor uses a version of the shown command sequence to initiate, execute, and terminate a set of graphics operations. A sample command sequence is shown and described for illustrative purposes only, and embodiments are not limited to these particular commands or this command sequence. Also, the commands may be issued as a batch of commands in a command sequence such that the graphics processor will process the command sequence in at least a partially simultaneous manner.

[0330] In some embodiments, the graphics processor command sequence 2610 may begin with a pipeline dump clear command 2612 to cause any active graphics pipeline to complete the current outstanding commands for that pipeline. In some embodiments, the 3D pipeline 2622 and the media pipeline 2624 do not operate simultaneously. The pipeline dump clear is executed to cause the active graphics pipeline to complete any outstanding commands. In response to the pipeline dump clear, the command parser for the graphics processor will stop command processing until the active rendering engine has completed the outstanding operations and invalidated the associated read cache. Optionally, any data marked 'dirty' in the render cache may be dumped to memory. In some embodiments, the pipeline dump clear command 2612 may be used for pipeline synchronization or before putting the graphics processor into a low power state.

[0331] In some embodiments, a pipeline select command 2613 is used when the command sequence requires the graphics processor to explicitly switch between pipelines. In some embodiments, the pipeline select command 2613 is only required once in the execution context before issuing pipeline commands, unless the context is to issue commands for two pipelines. In some embodiments, the pipeline dump clear command 2612 is exactly required before the pipeline switch via the pipeline select command 2613.

[0332] In some embodiments, the pipeline control command 2614 configures the graphics pipeline for operation and programs the 3D pipeline 2622 and the media pipeline 2624. In some embodiments, the pipeline control command 2614 configures the pipeline state of the active pipeline. In one embodiment, the pipeline control command 2614 is used for pipeline synchronization and for clearing data from one or more cache memories within the active pipeline before processing a batch of commands.

[0333] In some embodiments, command 2616 for returning buffer status is used to configure a set of return buffers for corresponding pipelines to write data. Some pipeline operations require allocating, selecting, or configuring one or more return buffers, and during processing, the operations write intermediate data into the one or more return buffers. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform cross-thread communication. In some embodiments, configuring return buffer status 2616 includes selecting the size and number of return buffers for a set of pipeline operations.

[0334] The remaining commands in the command sequence differ based on the active pipelines being used. Based on pipeline determination 2620, the command sequence is customized for a 3D pipeline 2622 starting with a 3D pipeline state 2630, or a media pipeline 2624 starting at a media pipeline state 2640.

[0335] Commands for 3D pipeline state 2630 include 3D state setting commands for vertex buffer status, vertex element status, constant color status, depth buffer status, and other status variables to be configured before processing 3D primitive commands. The values of these commands are determined at least in part based on the particular 3D API in use. In some embodiments, 3D pipeline state 2630 commands can also selectively disable or bypass specific pipeline elements if those elements will not be used.

[0336] In some embodiments, 3D primitive 2632 commands are used to submit 3D primitives to be processed by the 3D pipeline. The commands and associated parameters passed to the graphics processor via 3D primitive 2632 commands are forwarded to the vertex fetch function in the graphics pipeline. The vertex fetch function uses 3D primitive 2632 command data to generate multiple vertex data structures. The vertex data structures are stored in one or more return buffers. In some embodiments, 3D primitive 2632 commands are used to perform vertex operations on 3D primitives via a vertex shader. To process the vertex shader, 3D pipeline 2622 dispatches shader execution threads to the graphics processor execution units.

[0337] In some embodiments, the 3D pipeline 2622 is triggered via the execution of a 2634 command or an event. In some embodiments, a register write triggers command execution. In some embodiments, execution is triggered via a 'go' or 'kick' command in a command sequence. In one embodiment, a pipeline synchronization command is used to trigger command execution in order to clear the command sequence via a graphics pipeline dump. The 3D pipeline performs geometric processing on 3D primitives. Once the operation is complete, the resulting geometric objects are rasterized, and the pixel engine colors the resulting pixels. For these operations, additional commands for controlling pixel coloring and pixel backend operations may also be included.

[0338] In some embodiments, when performing media operations, the graphics processor command sequence 2610 follows the media pipeline 2624 path. Generally, the specific uses and ways of programming the media pipeline 2624 depend on the media or computing operations to be performed. During media decoding, specific media decoding operations can be offloaded to the media pipeline. In some embodiments, the media pipeline can also be bypassed, and the resources provided by one or more general-purpose processing cores can be used to perform media decoding wholly or in part. In one embodiment, the media pipeline also includes elements for general-purpose graphics processing unit (GPGPU) operations, where the graphics processor is used to perform SIMD vector operations using a compute shader program that is not explicitly related to rendering graphics primitives.

[0339] In some embodiments, the media pipeline 2624 is configured in a manner similar to the 3D pipeline 2622. A set of commands for configuring the media pipeline state 2640 is dispatched or placed into the command queue, before the media object command 2642. In some embodiments, the commands 2640 for the media pipeline state include data for configuring the media pipeline elements that will be used to process media objects. This includes data for configuring video decoding and video encoding logic within the media pipeline, such as encoding or decoding formats. In some embodiments, the commands 2640 for the media pipeline state also support using one or more pointers for "indirect" state elements that contain a batch of state settings.

[0340] In some embodiments, the media object command 2642 supplies a pointer to a media object for processing by a media pipeline. The media object includes a memory buffer that contains video data to be processed. In some embodiments, all media pipeline states must be valid before issuing the media object command 2642. Once the pipeline states are configured and the media object command 2642 is queued, the media pipeline 2624 is triggered via an execute 2644 command or an equivalent execution event (e.g., a register write). The output from the media pipeline 2624 can then be post-processed by operations provided by the 3D pipeline 2622 or the media pipeline 2624. In some embodiments, GPGPU operations are configured and executed in a manner similar to media operations.

[0341] Graphics Software Architecture

[0342] Figure 27 An exemplary graphics software architecture of a data processing system 2700 is shown in accordance with some embodiments. In some embodiments, the software architecture includes a 3D graphics application 2710, an operating system 2720, and at least one processor 2730. In some embodiments, the processor 2730 includes a graphics processor 2732 and one or more general-purpose processor cores 2734. The graphics application 2710 and the operating system 2720 each execute in the system memory 2750 of the data processing system.

[0343] In some embodiments, the 3D graphics application 2710 includes one or more shader programs that include shader instructions 2712. The shader language instructions can be in a high-level shader language such as High-Level Shader Language (HLSL) or OpenGL Shading Language (GLSL). The application also includes executable instructions 2714 that are in a machine language suitable for execution by the general-purpose processor cores 2734. The application also includes a graphics object 2716 defined by vertex data.

[0344] In some embodiments, the operating system 2720 is from Microsoft Corporation An operating system, a proprietary UNIX-like operating system, or an open-source UNIX-like operating system using a Linux kernel variant. The operating system 2720 can support a graphics API 2722, such as a Direct3D API, an OpenGL API. When the Direct3D API is in use, the operating system 2720 uses a front-end shader compiler 2724 to compile any shader instructions 2712 in HLSL into a lower-level shader language. The compilation can be just-in-time (JIT) compilation, or the application can perform shader pre-compilation. In some embodiments, during the compilation of the 3D graphics application 2710, high-level shaders are compiled into low-level shaders..

[0345] In some embodiments, the user-mode graphics driver 2726 includes a back-end shader compiler 2727 that is used to convert the shader instructions 2712 into a hardware-specific representation. When the OpenGL API is in use, the shader instructions 2712 in the GLSL high-level language are passed to the user-mode graphics driver 2726 for compilation. In some embodiments, the user-mode graphics driver 2726 uses the operating system kernel-mode function 2728 to communicate with the kernel-mode graphics driver 2729. In some embodiments, the kernel-mode graphics driver 2729 communicates with the graphics processor 2732 to dispatch commands and instructions.

[0346] IP Core Implementation

[0347] One or more aspects of at least one embodiment can be implemented by representative code stored on a machine-readable medium that represents and / or defines logic within an integrated circuit such as a processor. For example, the machine-readable medium can include instructions that represent the various logics within the processor. When read by a machine, the instructions can cause the machine to fabricate logic for performing the techniques described herein. Such representations (referred to as "IP cores") are reusable units of the logic of an integrated circuit that can be stored as a hardware model that describes the structure of the integrated circuit on a tangible, machine-readable medium. The hardware model can be supplied to various consumers or manufacturing facilities that load the hardware model on a manufacturing machine for fabricating the integrated circuit. The integrated circuit can be fabricated such that the circuit performs the operations described in association with any of the embodiments herein.

[0348] Figure 28is a block diagram showing an IP core development system 2800 that can be used to fabricate integrated circuits to perform operations according to an embodiment. The IP core development system 2800 can be used to generate modular, reusable designs that can be incorporated into larger designs or used to build an entire integrated circuit (e.g., a SOC integrated circuit). A design facility 2830 can generate a software simulation 2810 of the IP core design using a high-level programming language (e.g., C / C++). The software simulation 2810 can be used to design, test, and verify the behavior of the IP core using a simulation model 2812. The simulation model 2812 can include functional, behavioral, and / or timing simulations. A register transfer level (RTL) design 2815 can then be created or synthesized by the simulation model 2812. The RTL design 2815 is an abstraction of the behavior of an integrated circuit that models the flow of digital signals between hardware registers (including the associated logic performed using the modeled digital signals). In addition to the RTL design 2815, lower-level designs at the logic level or transistor level can also be created, designed, or synthesized. Thus, the specific details of the initial design and simulation can vary.

[0349] The RTL design 2815 or an equivalent can be further synthesized by the design facility into a hardware model 2820, which can be in a hardware description language (HDL) or some other representation of physical design data. The HDL can be further simulated or tested to verify the IP core design. A non-volatile memory 2840 (e.g., a hard disk, flash memory, or any non-volatile storage medium) can be used to store the IP core design for delivery to a third-party manufacturing facility 2865. Alternatively, the IP core design can be transmitted (e.g., via the Internet) over a wired connection 2850 or a wireless connection 2860. The manufacturing facility 2865 can then fabricate an integrated circuit that is at least partially based on the IP core design. The fabricated integrated circuit can be configured to perform operations according to at least one embodiment described herein.

[0350] Exemplary System-on-Chip Integrated Circuit

[0351] Figures 29 to 31 Shows exemplary integrated circuits and associated graphics processors that can be fabricated using one or more IP cores according to various embodiments described herein. In addition to those shown, other logic and circuitry can be included, including additional graphics processors / cores, peripheral interface controllers, or general processor cores.

[0352] Figure 29is a block diagram showing an exemplary system-on-chip integrated circuit 2900 that can be fabricated using one or more IP cores according to an embodiment. The exemplary integrated circuit 2900 includes one or more application processors 2905 (e.g., CPUs), at least one graphics processor 2910, and may additionally include an image processor 2915 and / or a video processor 2920, any of which may be a modular IP core from the same or multiple different design facilities. The integrated circuit 2900 includes peripheral or bus logic, including a USB controller 2925, a UART controller 2930, an SPI / SDIO controller 2929, and an 2 S / I 2 C controller 2940. Additionally, the integrated circuit may further include a display device 2945, which is coupled to one or more of a high-definition multimedia interface (HDMI) controller 2950 and a mobile industry processor interface (MIPI) display interface 2955. Storage may be provided by a flash memory subsystem 2960 (including flash memory and a flash memory controller). A memory interface may be provided via a memory controller 2965 to access SDRAM or SRAM memory devices. Additionally, some integrated circuits further include an embedded security engine 2970.

[0353] Figure 30 is a block diagram showing an exemplary graphics processor 3010 of a system-on-chip integrated circuit that can be fabricated using one or more IP cores according to an embodiment. The graphics processor 3010 may be Figure 29 a variant of the graphics processor 2910. The graphics processor 3010 includes a vertex processor 3005 and one or more fragment processors 3015A through 3015N (e.g., 3015A, 3015B, 3015C, 3015D, up to 3015N-1 and 3015N). The graphics processor 3010 may execute different shader programs via separate logic such that the vertex processor 3005 is optimized to perform operations of a vertex shader program, while the one or more fragment processors 3015A through 3015N perform fragment (e.g., pixel) shading operations for a fragment or pixel shader program. The vertex processor 3005 executes the vertex processing stage of a 3D graphics pipeline and generates primitives and vertex data. The (multiple) fragment processors 3015A through 3015N use the primitives and vertex data generated by the vertex processor 3005 to produce a frame buffer that is displayed on a display device. In one embodiment, the (multiple) fragment processors 3015A through 3015N are optimized to execute fragment shader programs provided in the OpenGL API, which may be used to perform operations similar to those of pixel shader programs provided in the Direct 3D API.

[0354] Additionally, the graphics processor 3010 further includes one or more memory management units (MMUs) 3020A to 3020B, one or more caches 3025A to 3025B, and (multiple) circuit interconnections 3030A to 3030B. One or more MMUs 3020A to 3020B provide virtual-to-physical address mapping for the graphics processor 3010 for the vertex processor 3005 and / or one or more fragment processors 3015A to 3015N. In addition to vertex or image / texture data stored in one or more caches 3025A to 3025B, the virtual-to-physical address mapping may also reference vertex or image / texture data stored in memory. In one embodiment, one or more MMUs 3025A to 3025B may be synchronized with one or more MMUs included in other MMUs within the system, including one or more MMUs associated with Figure 29 one or more application processors 2905, image processors 2915, and / or video processors 2920 of, such that each of the processors 2905 to 2920 can participate in a shared or unified virtual memory system. According to an embodiment, one or more circuit interconnections 3030A to 3030B enable the graphics processor 3010 to interact with other IP cores within the SoC via the internal bus of the SoC or via a direct connection.

[0355] Figure 31 is a block diagram showing an additional exemplary graphics processor 3110 of a system-on-chip integrated circuit that can be fabricated using one or more IP cores according to an embodiment. The graphics processor 3110 may be Figure 29 a variant of the graphics processor 2910. The graphics processor 3110 includes Figure 30 one or more MMUs 3020A to 03020B, caches 03025A to 03025B, and circuit interconnections 3030A to 3030B of the integrated circuit 3000.

[0356] The graphics processing unit 3110 includes one or more shader cores 3115A through 3115N (e.g., 3115A, 3115B, 3115C, 3115D, 3115E, 3115F through 3015N-1, and 3015N), which provide a unified shader core architecture where a single core or type or core can execute all types of programmable shader code (including shader program code) to implement vertex shaders, fragment shaders, and / or compute shaders. The exact number of shader cores present can vary in embodiments and implementations. Additionally, the graphics processing unit 3110 includes an inter-core task manager 3105 that acts as a thread dispatcher to dispatch execution threads to one or more shader cores 3115A through 3115N. The graphics processing unit 3110 further includes a tiling unit 3118 to accelerate tiling operations for tile-based rendering, where the rendering operations for a scene are subdivided in image space. Tile-based rendering can be used to exploit local spatial coherence within a scene or optimize the use of internal caches.

[0357] References to "one embodiment", "an embodiment", "example embodiment", "various embodiments", etc. indicate that the (s) embodiment(s) so described may include a particular feature, structure, or characteristic, but not every embodiment necessarily includes that particular feature, structure, or characteristic. Moreover, some embodiments may have some, all, or none of the features described for other embodiments.

[0358] In the foregoing specification, embodiments have been described with reference to specific exemplary embodiments. However, it will be apparent that various modifications and changes can be made thereto without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

[0359] In the following specification and claims, the term "coupled" and its derivatives may be used. "Coupled" is used to indicate that two or more elements cooperate or interact with each other, but there may or may not be an intervening physical or electrical component between them.

[0360] As used in the claims, unless otherwise specified, the use of the ordinal adjectives "first", "second", "third", etc. to describe common elements merely indicates that different instances of like elements are being referred to and is not intended to imply that the elements so described must be in a given order (whether in time, space, rank, or any other manner).

[0361] The following clauses and / or examples relate to further embodiments or examples. Details in the examples can be used anywhere in one or more embodiments. The various features of different embodiments or examples can be combined in various ways with some of the features included and other features excluded to suit various different applications. The examples can include a subject matter such as, a method; an apparatus for performing actions of the method; at least one machine-readable medium including instructions which, when executed by a machine, cause the machine to perform actions of the method or the apparatus; or a device or system for facilitating hybrid communication according to the embodiments and examples described herein.

[0362] Some embodiments relate to Example 1, which includes an apparatus for facilitating inference coordination and processing utilization of machine learning at an autonomous machine, the apparatus including: detection / monitoring logic, facilitated by or at least partially incorporated into a processor, the detection / monitoring logic for detecting, during training, information related to one or more tasks to be performed based on a training data set associated with the processor including a graphics processor; and pre-analysis training logic, facilitated by or at least partially incorporated into the processor, the pre-analysis training logic for analyzing the information to determine one or more portions of the hardware associated with the processor that can support the one or more tasks, wherein the pre-analysis training logic further configures the hardware to pre-select the one or more portions to perform the one or more tasks while other portions of the hardware remain available for other tasks.

[0363] Example 2 includes the subject matter as described in Example 1, further including: inference coordination logic, facilitated by or at least partially incorporated into the processor, the inference coordination logic for establishing coordination between one or more sensors and an inference output associated with an inference operation related to the training data set, wherein establishing the coordination includes facilitating the one or more sensors to apply one or more filters to one or more images to change the inference output to match a normal threshold before completion of the inference operation, wherein the one or more sensors include one or more cameras for capturing the one or more images of a scene.

[0364] Example 3 includes the subject matter as described in Examples 1 to 2, further including: early fusion logic, facilitated by or at least partially incorporated into the processor, the early fusion logic for facilitating the transmission of cues between a camera model obtained from the one or more cameras and an existing model obtained from one or more databases, wherein the cues include early cues for enabling early fusion to facilitate prediction, path planning, and decision making.

[0365] Example 4 includes the subject matter as described in Examples 1 to 3, further including: neural network scheduling logic, which is facilitated by or at least partially incorporated into the processor, the neural network scheduling logic being configured to prioritize the scheduling of a plurality of neural networks, the plurality of neural networks including safety-critical neural networks and non-safety-critical neural networks, wherein prioritizing the scheduling includes interrupting one or more of the non-safety-critical neural networks to allow one or more of the safety-critical neural networks to continue to execute their tasks without interruption.

[0366] Example 5 includes the subject matter as described in Examples 1 to 4, wherein prioritizing the scheduling includes, for one or more of the plurality of neural networks, reallocating one or more execution units from one neural network to another neural network or adjusting one or more of the memory, cache, scratchpad, and computing elements.

[0367] Example 6 includes the subject matter as described in Examples 1 to 5, further including: processing utilization logic, which is facilitated by or at least partially incorporated into the processor, the processing utilization logic being configured to facilitate the hardware units of the graphics processor to monitor the utilization of the hardware through an existing context, wherein the processing utilization logic is further configured to facilitate the context scheduler of the graphics processor to adjust the allocation of the hardware to the existing context or a new context based on the utilization.

[0368] Example 7 includes the subject matter as described in Examples 1 to 6, wherein the graphics processor coexists with an application processor on a common semiconductor package.

[0369] Some embodiments relate to Example 8, which includes a method for facilitating inference coordination and processing utilization of machine learning at an autonomous machine, the method including: at training, detecting information related to one or more tasks to be executed based on a training data set related to a processor including a graphics processor; analyzing the information to determine one or more parts of the hardware related to the processor that can support the one or more tasks; and configuring the hardware to pre-select the one or more parts to execute the one or more tasks, while other parts of the hardware remain available for other tasks.

[0370] Example 9 includes the subject matter as described in Example 8, further including: establishing coordination between one or more sensors and an inference output, the inference output being associated with an inference operation related to the training data set, wherein establishing the coordination includes facilitating the one or more sensors to apply one or more filters to one or more images to change the inference output to match a normal threshold before completing the inference operation, wherein the one or more sensors include one or more cameras for capturing the one or more images of the scene.

[0371] Example 10 includes the subject matter as described in Examples 8 to 9, further including: facilitating the transmission of a hint between a camera model obtained from the one or more cameras and an existing model obtained from one or more databases, wherein the hint includes an early hint for implementing early fusion to facilitate prediction, path planning, and decision making.

[0372] Example 11 includes the subject matter as described in Examples 8 to 10, further including: prioritizing the scheduling of multiple neural networks, the multiple neural networks including safety-critical neural networks and non-safety-critical neural networks, wherein prioritizing the scheduling includes interrupting one or more of the non-safety-critical neural networks to allow one or more of the safety-critical neural networks to continue to execute their tasks without interruption.

[0373] Example 12 includes the subject matter as described in Examples 8 to 11, wherein prioritizing the scheduling includes, for one or more of the multiple neural networks, reallocating one or more execution units from one neural network to another neural network or adjusting one or more of memory, cache, scratchpad, and computing elements.

[0374] Example 13 includes the subject matter as described in Examples 8 to 12, further including: facilitating the hardware units of the graphics processor to monitor the utilization of the hardware through an existing context; and facilitating the context scheduler of the graphics processor to adjust the allocation of the hardware to the existing context or a new context based on the utilization.

[0375] Example 14 includes the subject matter as described in Examples 8 to 13, wherein the graphics processor coexists with an application processor on a common semiconductor package.

[0376] Some embodiments relate to Example 15, which includes a graphics processing system that includes a computing device having a memory coupled to a processor, the processor for: at training, detecting information related to one or more tasks to be performed based on a training data set related to a processor that includes a graphics processor; analyzing the information to determine one or more portions of the hardware related to the processor that can support the one or more tasks; and configuring the hardware to pre-select the one or more portions to perform the one or more tasks, while other portions of the hardware remain available for other tasks.

[0377] Example 16 includes the subject matter as described in Example 15, wherein the operations further include: establishing coordination between one or more sensors and an inference output associated with an inference operation related to the training data set, wherein establishing the coordination includes facilitating the one or more sensors applying one or more filters to one or more images to alter the inference output to match a normality threshold before completion of the inference operation, wherein the one or more sensors include one or more cameras for capturing the one or more images of the scene.

[0378] Example 17 includes the subject matter as described in Examples 15 - 16, wherein the operations further include: facilitating the transmission of cues between a camera model obtained from the one or more cameras and an existing model obtained from one or more databases, wherein the cues include early cues for enabling early fusion to facilitate prediction, path planning, and decision making.

[0379] Example 18 includes the subject matter as described in Examples 15 - 17, wherein the operations further include: prioritizing the scheduling of multiple neural networks, the multiple neural networks including safety - critical neural networks and non - safety - critical neural networks, wherein prioritizing the scheduling includes interrupting one or more of the non - safety - critical neural networks to allow one or more of the safety - critical neural networks to continue to perform their tasks without interruption.

[0380] Example 19 includes the subject matter as described in Examples 15 - 18, wherein prioritizing the scheduling includes, for one or more of the multiple neural networks, re - allocating one or more execution units from one neural network to another neural network or adjusting one or more of a memory, cache, scratchpad, and computing elements.

[0381] Example 20 includes the subject matter as described in Examples 15 to 19, wherein the processor is further configured to: facilitate monitoring of the utilization of the hardware by the hardware units of the graphics processor through an existing context; and facilitate adjustment by the context scheduler of the graphics processor of the allocation of the hardware to the existing context or a new context based on the utilization.

[0382] Example 21 includes the subject matter as described in Examples 15 to 20, wherein the graphics processor coexists with an application processor on a common semiconductor package.

[0383] Example 22 includes at least one non-transitory or tangible machine-readable medium including a plurality of instructions that, when executed on a computing device, implement or perform the method as described in any one of the claims or Examples 8 to 14.

[0384] Example 23 includes at least one machine-readable medium including a plurality of instructions that, when executed on a computing device, implement or perform the method as described in any one of the claims or Examples 8 to 14.

[0385] Example 24 includes a system including means for implementing or performing the method as described in any one of the claims or Examples 8 to 14.

[0386] Example 25 includes an apparatus including means for performing the method as described in any one of the claims or Examples 8 to 14.

[0387] Example 26 includes a computing device arranged to implement or perform the method as described in any one of the claims or Examples 8 to 14.

[0388] Example 27 includes a communication device arranged to implement or perform the method as described in any one of the claims or Examples 8 to 14.

[0389] Example 28 includes at least one machine-readable medium including a plurality of instructions that, when executed on a computing device, implement or perform the method as described in any of the preceding claims or realize the apparatus as described in any of the preceding claims.

[0390] Example 29 includes at least one non-transitory or tangible machine-readable medium including a plurality of instructions that, when executed on a computing device, implement or perform the method as described in any of the preceding claims or realize the apparatus as described in any of the preceding claims.

[0391] Example 30 includes a system that includes mechanisms arranged to implement or perform the method as claimed in any of the preceding claims or to realize the apparatus as claimed in any of the preceding claims.

[0392] Example 31 includes an apparatus that includes means for performing the method as claimed in any of the preceding claims.

[0393] Example 32 includes a computing device arranged to implement or perform the method as claimed in any of the preceding claims or to realize the apparatus as claimed in any of the preceding claims.

[0394] Example 33 includes a communication device arranged to implement or perform the method as claimed in any of the preceding claims or to realize the apparatus as claimed in any of the preceding claims.

[0395] The accompanying drawings and the foregoing description give examples of embodiments. Those skilled in the art will understand that one or more of the described elements may be well combined into a single functional element. Alternatively, some elements may be divided into multiple functional elements. Elements from one embodiment may be added to another embodiment. For example, the order of the processes described herein may be changed and is not limited to the manner described herein. In addition, the actions of any flowchart need not be performed in the order shown; nor is it necessary to perform all actions. And those actions that do not depend on other actions may be performed in parallel with other actions. The scope of the embodiments is in no way limited to these specific examples. Many variations such as differences in the structure, dimensions, and use of materials are possible, whether or not explicitly given in the specification. The scope of the embodiments is at least as wide as the scope given by the appended claims.

Claims

1. An apparatus for facilitating inference coordination and processing utilization of machine learning at an autonomous machine, the apparatus comprising: One or more processors, including a graphics processor, the one or more processors configured to: At training, detect information related to one or more tasks to be performed based on a training data set related to the one or more processors; Analyze the information to determine one or more portions of the hardware related to the processors that can support the one or more tasks, and configure the hardware to pre-select the one or more portions to perform the one or more tasks, while other portions of the hardware remain available for other tasks; And Prioritize scheduling of a plurality of neural networks, the plurality of neural networks including safety-critical neural networks and non-safety-critical neural networks, wherein prioritizing scheduling includes interrupting one or more of the non-safety-critical neural networks to allow one or more of the safety-critical neural networks to continue to perform their tasks without interruption.

2. The device according to claim 1, wherein The one or more processors are further configured to establish coordination between one or more sensors and an inference output associated with an inference operation related to the training data set, wherein establishing coordination includes facilitating the one or more sensors applying one or more filters to one or more images to alter the inference output to match a normal threshold before completion of the inference operation, wherein the one or more sensors include one or more cameras for capturing the one or more images of a scene.

3. The device according to claim 1, wherein, The one or more processors are further configured to facilitate transmission of cues between a camera model obtained from the one or more cameras and an existing model obtained from one or more databases, wherein the cues include early cues for enabling early fusion to facilitate prediction, path planning, and decision making.

4. The device according to claim 1, wherein, Prioritizing scheduling includes, for one or more of the plurality of neural networks, reallocating one or more execution units from one neural network to another neural network, or adjusting one or more of memory, cache, scratchpad, and computing elements.

5. The device according to claim 1, wherein, The one or more processors are further configured to facilitate monitoring of utilization of the hardware by hardware units of the graphics processor through an existing context, and facilitate adjustment by a context scheduler of the graphics processor of the allocation of the hardware to the existing context or a new context based on the utilization.

6. The device according to claim 1, wherein The graphics processor coexists with an application processor of the one or more processors on a common semiconductor package.

7. A method for facilitating inference coordination and processing utilization of machine learning at an autonomous machine, the method comprising: At training, detect information related to one or more tasks to be performed based on a training data set related to one or more processors including a graphics processor; Analyze the information to determine one or more portions of the hardware related to the one or more processors that can support the one or more tasks; Configure the hardware to pre-select the one or more parts to perform the one or more tasks, while the other parts of the hardware remain available for other tasks; and Prioritize the scheduling of a plurality of neural networks, the plurality of neural networks including safety-critical neural networks and non-safety-critical neural networks, wherein prioritizing the scheduling includes interrupting one or more of the non-safety-critical neural networks to allow one or more of the safety-critical neural networks to continue to perform their tasks without interruption.

8. The method according to claim 7, further comprising establishing a coordination between one or more sensors and an inferred output, the inferred output being associated with an inference operation related to the training data set, wherein, Establish coordination including facilitating the one or more sensors to apply one or more filters to one or more images to change the inference output to match a normal threshold before completing the inference operation, wherein the one or more sensors include one or more cameras for capturing the one or more images of the scene.

9. The method of claim 7, further comprising facilitating the transmission of cues between a camera model obtained from the one or more cameras and an existing model obtained from one or more databases, wherein, The hint includes an early hint for implementing early fusion to facilitate prediction, path planning, and decision-making.

10. The method according to claim 7, wherein, Prioritizing the scheduling includes, for one or more of the plurality of neural networks, reallocating one or more execution units from one neural network to another neural network or adjusting one or more of memory, cache, scratchpad, and computing elements.

11. The method according to claim 7, further comprising: Facilitate the hardware units of the graphics processor to monitor the utilization of the hardware through an existing context; and Facilitate the context scheduler of the graphics processor to adjust the allocation of the hardware to the existing context or a new context based on the utilization.

12. The method according to claim 7, wherein, The graphics processor coexists with an application processor of the one or more processors on a common semiconductor package.

13. At least one machine-readable medium, comprising a plurality of instructions that, when executed on a computing device, implement or perform the method claimed in any one of claims 7 to 12.

14. A system, comprising means for implementing or performing the method claimed in any one of claims 7 to 12.

15. An apparatus, comprising means for performing the method claimed in any one of claims 7 to 12.

16. A computing device, arranged to implement or perform the method claimed in any one of claims 7 to 12.

17. A communication device, arranged to implement or perform the method claimed in any one of claims 7 to 12.

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