System, device, and method for adaptive sub - sharding

Abstract

The present application discloses an adaptive sub - tessellation system, device, and method. The system, device, and method can provide a way to subdivide a tessellation generated in a graphics processing pipeline into sub - tessellations and generate sub - tessellation surface tessellations of the sub - tessellations. More specifically, the system, device, and method can provide a way to diverge the size of surface tessellations within the interior region of a tessellation or sub - tessellation to a configurable size based on the position of each of the surface tessellations. The system, device, and method can determine the number of tessellation factors to be used based on one or more of the following: the granularity level of one or more domains of the scene to be digitally rendered, the available computing power, or the power consumption for computing the number of tessellation factors.

Description

Technical Field

[0001] Embodiments generally relate to data processing. More specifically, embodiments relate to the use of adaptive subpatches during data processing in a graphics processor. Background Art

[0002] Current parallel graphics data processing involves developing systems and methods for performing specific operations such as linear interpolation, tessellation, rasterization, texture mapping, depth testing, etc. Traditionally, graphics processors have used fixed-function computing units to process graphics data. However, recently, parts of the graphics processor have been made programmable, enabling these processors to support a wider range of operations regarding the processing of vertex and fragment data.

[0003] To further improve performance, graphics processors typically implement processing techniques such as pipelining operations, which attempt to process as much graphics data as possible in parallel across different parts of the graphics pipeline. A parallel graphics processor with a single instruction multiple thread (SIMT) architecture can be designed to maximize the amount of parallel processing in the graphics pipeline. In the SIMT architecture, groups of parallel threads attempt to synchronously execute program instructions as often as possible to improve processing efficiency. These solutions rely on host processor synchronization, which can limit performance such as the possible amount of parallel processing. Brief Description of the Drawings

[0004] Various advantages of the embodiments will become apparent to those skilled in the art by reading the following description and the appended claims and by referring to the following drawings, in which:

[0005] Figure 1 is a block diagram showing a computer system configured to implement one or more aspects of the embodiments described herein;

[0006] Figures 2A to 2D shows a parallel processor component according to an embodiment;

[0007] Figures 3A to 3B is a block diagram of a graphics multiprocessor according to an embodiment;

[0008] Figures 4A to 4F shows an exemplary architecture in which multiple GPUs are communicatively coupled to multiple multi-core processors;

[0009] Figure 5 shows a graphics processing pipeline according to an embodiment;

[0010] Figure 6 is a block diagram showing a computer system configured to generate subpatches for tessellation according to an embodiment;

[0011] Figure 7AConceptual diagram of an example of a tessellation factor for a quadrilateral patch according to an embodiment;

[0012] Figure 7B Conceptual diagram of an example of tessellation of adjacent patches according to an embodiment;

[0013] Figure 8 Flowchart of an example of a method for generating sub - patches according to an embodiment;

[0014] Figure 9A and Figure 9B Conceptual diagram of an example of tessellation sizes with and without perspective distortion according to an embodiment;

[0015] Figure 10 Conceptual diagram of a quadrilateral patch subdivided into sub - patches according to an embodiment;

[0016] Figure 11 Diagram of an example of a head - mounted display (HMD) system according to an embodiment;

[0017] Figure 12 Is included according to an embodiment in Figure 11 Block diagram of an example of functional components in an HMD system;

[0018] Figure 13 Block diagram of an example of a general - purpose processing cluster included in a parallel processing unit according to an embodiment;

[0019] Figure 14 Conceptual diagram of an example of a graphics processing pipeline that can be implemented within a parallel processing unit according to an embodiment;

[0020] Figure 15 Block diagram of an example of a streaming multi - processor according to an embodiment;

[0021] Figures 16 to 18 Block diagram of an example of an overview of a data processing system according to an embodiment;

[0022] Figure 19 Block diagram of an example of a graphics processing engine according to an embodiment;

[0023] Figures 20 to 22 Block diagram of an example of an execution unit according to an embodiment;

[0024] Figure 23 Block diagram of an example of a graphics pipeline according to an embodiment;

[0025] Figures 24A to 24B Block diagram of an example of a graphics pipeline according to an embodiment;

[0026] Figure 25 Block diagram of an example of a graphics software architecture according to an embodiment;

[0027] Figure 26 is a block diagram of an example of an intellectual property (IP) core development system according to an embodiment; and

[0028] Figure 27 is a block diagram of an example of a system-on-chip integrated circuit according to an embodiment. DETAILED DESCRIPTION

[0029] In the following description, numerous specific details are set forth to provide a more thorough understanding of the present disclosure. However, it will be apparent to one of ordinary skill in the art that the invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described so as not to obscure the invention.

[0030] System Overview

[0031] Figure 1 is a block diagram showing a computing system 100 configured to implement one or more aspects of the embodiments described herein. The computing system 100 includes a processing subsystem 101 having one or more processors 102 and a system memory 104, the processors communicating with the system memory via an interconnect path that may include a memory hub 105. The memory hub 105 may be a separate component within a chipset component or may be integrated within one or more of the processors 102. The memory hub 105 is coupled to an I / O subsystem 111 via a communication link 106. The I / O subsystem 111 includes an I / O hub 107 that may enable the computing system 100 to receive input from one or more input devices 108. Additionally, the I / O hub 107 may enable a display controller to provide output to one or more display devices 110A, the display controller being included within one or more of the processors 102. In one embodiment, one or more of the display devices 110A coupled to the I / O hub 107 may include a local, internal, or embedded display device.

[0032] In one embodiment, the processing subsystem 101 includes one or more parallel processors 112 that are coupled to the memory hub 105 via a bus or other communication link 113. The communication link 113 can be one of any number of standard-based communication link technologies or protocols (such as, but not limited to, the PCI Express bus), or can be a vendor-specific communication interface or communication fabric. In one embodiment, one or more parallel processors 112 form a computationally concentrated parallel or vector processing system that includes a large number of processing cores and / or processing clusters (such as, an integrated many-core (MIC) processor). In one embodiment, one or more parallel processors 112 form a graphics processing subsystem that can output pixels to one of one or more display devices 110A coupled via the I / O hub 107. One or more parallel processors 112 can also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 110B.

[0033] Within the I / O subsystem 111, the system storage unit 114 can be connected to the I / O hub 107 to provide a storage mechanism for the computing system 100. The I / O switch 116 can be used to provide an interface mechanism to enable connections between the I / O hub 107 and other components (such as, a network adapter 118 and / or a wireless network adapter 119 that can be integrated into the platform, and various other devices that can be added via one or more plug-in devices 120). The network adapter 118 can be an Ethernet adapter or another wired network adapter. The wireless network adapter 119 can include one or more of the following: Wi-Fi, Bluetooth, near field communication (NFC), or other network devices that include one or more radio devices.

[0034] The computing system 100 can include other components not explicitly shown, including USB or other port connectors, optical storage drives, video capture devices, etc., which can also be connected to the I / O hub 107. The communication paths interconnecting the various components within Figure 1 can be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect)-based protocol (e.g., the PCI Express bus) or any other bus or point-to-point communication interface and / or protocol (such as, the NV-Link high-speed interconnect, or an interconnect protocol known in the art).

[0035] In one embodiment, one or more parallel processors 112 include circuitry optimized for graphics and video processing (including, e.g., video output circuitry) and constitute a graphics processing unit (GPU). In another embodiment, one or more parallel processors 112 include circuitry optimized for general-purpose processing while maintaining the underlying computing architecture described in more detail herein. In yet another embodiment, components of the computing system 100 may be integrated with one or more other system elements on a single integrated circuit. For example, one or more parallel processors 112, the memory hub 105, the processor 102, and the I / O hub 107 may be integrated into a system-on-chip (SoC) integrated circuit. Alternatively, components of the computing system 100 may be integrated into a single package to form a system-in-package (SIP) configuration. In one embodiment, at least a portion of the components of the computing system 100 may be integrated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules into a modular computing system.

[0036] It will be recognized that the computing system 100 shown herein is illustrative, and various variations and modifications are possible. The connection topology may be modified as needed, including the number and arrangement of bridges, the number of processors 102, and the number of parallel processors 112. For example, in some embodiments, the system memory 104 is connected directly to the processors 102 rather than through a bridge, while other devices communicate with the system memory 104 via the memory hub 105 and the processors 102. In other alternative topologies, the parallel processors 112 are connected to the I / O hub 107 or directly to one of the one or more processors 102 rather than to the memory hub 105. In other embodiments, the I / O hub 107 and the memory hub 105 may be integrated into a single chip. Some embodiments may include two or more sets of processors 102 attached via multiple sockets, which may be coupled to two or more instances of the parallel processors 112.

[0037] Some of the specific components shown herein are optional and may not be included in all implementations of the computing system 100. For example, any number of plug-in cards or peripherals may be supported, or some components may be eliminated. Additionally, some architectures may use different terms for components similar to those shown Figure 1 herein. For example, in some architectures, the memory hub 105 may be referred to as a north bridge, while the I / O hub 107 may be referred to as a south bridge.

[0038] Figure 2AShows a parallel processor 200 according to an embodiment. Various components of the parallel processor 200 may be implemented using one or more integrated circuit devices, such as programmable processors, application specific integrated circuits (ASICs), or field programmable gate arrays (FPGAs). According to an embodiment, the illustrated parallel processor 200 is Figure 1 a variant of one or more of the parallel processors 112 shown in

[0039] In one embodiment, the parallel processor 200 includes a parallel processing unit 202. The parallel processing unit includes an I / O unit 204 that enables communication with other devices, including other instances of the parallel processing unit 202. The I / O unit 204 may be directly connected to other devices. In one embodiment, the I / O unit 204 is connected to other devices via the use of a hub or switch interface, such as a memory hub 105. The connection between the memory hub 105 and the I / O unit 204 forms a communication link 113. Within the parallel processing unit 202, the I / O unit 204 is connected to a host interface 206 and a memory crossbar 216, where the host interface 206 receives commands related to performing processing operations, and the memory crossbar 216 receives commands related to performing memory operations.

[0040] When the host interface 206 receives command buffers via the I / O unit 204, the host interface 206 may direct the work operations for executing those commands to a front end 208. In one embodiment, the front end 208 is coupled to a scheduler 210 that is configured to distribute commands or other work items to an array of processing clusters 212. In one embodiment, the scheduler 210 ensures that the array of processing clusters 212 is properly configured and in an active state before tasks are distributed to the processing clusters of the array of processing clusters 212. In one embodiment, the scheduler 210 is implemented via firmware logic executed on a microcontroller. The microcontroller-implemented scheduler 210 may be configured to perform complex scheduling and work distribution operations at both coarse-grained and fine-grained levels, enabling fast preemption and context switching of threads executing on the processing array 212. In one embodiment, host software may demonstrate a workload via one of a plurality of image processing doorbells for scheduling on the processing array 212. The workload may then be automatically distributed across the processing array 212 by the scheduler 210 logic within the scheduler microcontroller.

[0041] The processing cluster array 212 can include up to "N" processing clusters (e.g., cluster 214A, cluster 214B, up to cluster 214N). Each of the clusters 214A - 214N of the processing cluster array 212 can execute a large number of concurrent threads. The scheduler 210 can use various scheduling and / or workload distribution algorithms to allocate work to the clusters 214A - 214N of the processing cluster array 212, and the various scheduling and / or workload distribution algorithms can vary depending on the workload generated for each type of program or computation. Scheduling can be handled dynamically by the scheduler 210, or can be assisted in part by compiler logic during the compilation of program logic configured to be executed by the processing cluster array 212. In one embodiment, different clusters 214A - 214N of the processing cluster array 212 can be assigned to process different types of programs, or to perform different types of computations.

[0042] The processing cluster array 212 can be configured to perform various types of parallel processing operations. In one embodiment, the processing cluster array 212 is configured to perform general - purpose parallel computing operations. For example, the processing cluster array 212 can include logic for performing processing tasks, including filtering video and / or audio data, performing modeling operations (including physical operations), and performing data transformations.

[0043] In one embodiment, the processing cluster array 212 is configured to perform parallel graphics processing operations. In embodiments where the parallel processor 200 is configured to perform graphics processing operations, the processing cluster array 212 can include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, and tessellation logic and other vertex processing logic. Additionally, the processing cluster array 212 can be configured to execute shader programs related to graphics processing, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. The parallel processing unit 202 can pass data from the system memory via the I / O unit 204 for processing. During processing, the passed - through data can be stored in on - chip memory (e.g., parallel processor memory 222) during processing and then written back to the system memory.

[0044] In one embodiment, when the parallel processing unit 202 is used to perform graphics processing, the scheduler 210 may be configured to divide the processing workload into tasks of approximately equal size to better enable the distribution of graphics processing operations to the multiple clusters 214A through 214N in the processing cluster array 212. In some embodiments, multiple portions of the processing cluster array 212 may be configured to perform different types of processing. For example, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations to produce a rendered image for display. Intermediate data generated by one or more of the clusters 214A through 214N may be stored in a buffer to allow the transfer of the intermediate data between the clusters 214A through 214N for further processing.

[0045] During operation, the processing cluster array 212 may receive processing tasks to be executed via the scheduler 210, which receives commands defining the processing tasks from the front end 208. For graphics processing operations, the processing tasks may include indices of data to be processed (e.g., surface (patch) data, primitive data, vertex data, and / or pixel data) as well as status parameters and commands defining how the data is to be processed (e.g., what program is to be executed). The scheduler 210 may be configured to obtain the indices corresponding to the tasks or may receive these indices from the front end 208. The front end 208 may be configured to ensure that the processing cluster array 212 is in an effective state before initiating the workload specified by incoming command buffers (e.g., batch buffers, push buffers, etc.).

[0046] Each of one or more instances of the parallel processing unit 202 may be coupled to the parallel processor memory 222. The parallel processor memory 222 may be accessed via a memory crossbar 216 that may receive memory requests from the processing cluster array 212 as well as the I / O unit 204. The memory crossbar 216 may access the parallel processor memory 222 via a memory interface 218. The memory interface 218 may include a plurality of partitioning units (e.g., partitioning unit 220A, partitioning unit 220B, up to partitioning unit 220N), each of which may be coupled to a portion (e.g., a memory unit) of the parallel processor memory 222. In one implementation, the number of partitioning units 220A - 220N is configured to be equal to the number of memory units such that the first partitioning unit 220A has a corresponding first memory unit 224A, the second partitioning unit 220B has a corresponding memory unit 224B, and the Nth partitioning unit 220N has a corresponding Nth memory unit 224N. In other embodiments, the number of partitioning units 220A - 220N may not be equal to the number of memory devices.

[0047] In various embodiments, the memory units 224A through 224N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory (such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory). In one embodiment, the memory units 224A through 224N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). Those skilled in the art will recognize that the specific implementation of the memory units 224A through 224N may vary and may be selected from one of a variety of conventional designs. A render target (such as a frame buffer or a texture map) may be stored across the memory units 224A through 224N, allowing the partitioning units 220A through 220N to write multiple portions of each render target in parallel to efficiently utilize the available bandwidth of the parallel processor memory 222. In some embodiments, a local instance of the parallel processor memory 222 may be excluded in favor of a unified memory design that utilizes system memory in conjunction with local cache memory.

[0048] In one embodiment, any one of clusters 214A - 214N of processing cluster array 212 can process data to be written into any one of memory cells 224A - 224N within parallel processor memory 222. Memory crossbar 216 can be configured to pass the output of each of clusters 214A - 214N to any of partition units 220A - 220N or another one of clusters 214A - 214N that can perform additional processing operations on the output. Each of clusters 214A - 214N can communicate with memory interface 218 through memory crossbar 216 to read from or write to various external memory devices. In one embodiment, memory crossbar 216 has a connection to memory interface 218 to communicate with I / O unit 204 and has a connection to a local instance of parallel processor memory 222, enabling processing units within different processing clusters 214A - 214N to communicate with system memory or other memory not local to the parallel processing unit 202. In one embodiment, memory crossbar 216 can use virtual channels to separate the traffic flow between clusters 214A - 214N and partition units 220A - 220N.

[0049] Although a single instance of parallel processing unit 202 is shown within parallel processor 200, any number of instances of parallel processing unit 202 can be included. For example, multiple instances of parallel processing unit 202 can be provided on a single plug - in card, or multiple plug - in cards can be interconnected. Different instances of parallel processing unit 202 can be configured to interoperate even if these different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example and in one embodiment, some instances of parallel processing unit 202 can include higher - precision floating - point units relative to other instances. Systems including one or more instances of parallel processing unit 202 or parallel processor 200 can be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0050] Figure 2B is a block diagram of partition unit 220 according to an embodiment. In one embodiment, partition unit 220 is Figure 2AAn example of one of the partition units 220A through 220N. As shown, partition unit 220 includes an L2 cache 221, a frame buffer interface 225, and a ROP 226 (raster operation unit). The L2 cache 221 is a read / write cache configured to perform load and store operations received from the memory crossbar 216 and the ROP 226. Read misses and urgent writeback requests are output from the L2 cache 221 to the frame buffer interface 225 for processing. Updates may also be sent to the frame buffer via the frame buffer interface 225 for processing. In one embodiment, the frame buffer interface 225 interfaces with one of the memory cells in the parallel processor memory, such as the memory cells 224A through 224N of FIG. 2 (e.g., within the parallel processor memory 222).

[0051] In a graphics application, the ROP 226 is a processing unit that performs raster operations such as stencil, z-test, blending, etc. The ROP 226 then outputs the processed graphics data stored in the graphics memory. In some embodiments, the ROP 226 includes compression logic for compressing depth or color data written to the memory and decompressing depth or color data read from the memory. The compression logic may be lossless compression logic that utilizes one or more of a variety of compression algorithms. The type of compression performed by the ROP 226 may vary based on the statistical characteristics of the data to be compressed. For example, in one embodiment, delta color compression is performed on the depth and color data on a per-tile basis.

[0052] In some embodiments, the ROP 226 is included within each processing cluster (e.g., clusters 214A through 214N of FIG. 2) rather than within the partition unit 220. In such embodiments, read and write requests for pixel data are transmitted via the memory crossbar 216 rather than pixel fragment data. The processed graphics data may be displayed on a display device (such as Figure 1 one of the one or more display devices 110), routed for further processing by the (one or more) processors 102, or routed for further processing by Figure 2A one of the processing entities within the parallel processor 200.

[0053] Figure 2Cis a block diagram of a processing cluster 214 within a parallel processing unit according to an embodiment. In one embodiment, the processing cluster is an instance of one of the processing clusters 214A through 214N of FIG. 2. The processing cluster 214 may be configured to execute many threads in parallel, where the term "thread" refers to an instance of a particular program executing on a particular set of input data. In some embodiments, single instruction, multiple data (SIMD) instruction issue techniques are used to support parallel execution of a large number of threads without providing multiple independent instruction units. In other embodiments, single instruction, multiple threads (SIMT) techniques are used to support parallel execution of a large number of generally synchronous threads using a common instruction unit configured to issue instructions to a set of processing engines within each of the processing clusters. Unlike SIMD execution regimes where all processing engines typically execute the same instruction, SIMT execution allows different threads to more easily follow divergent execution paths through a given thread program. Those skilled in the art will understand that SIMD processing regimes represent a functional subset of SIMT processing regimes.

[0054] The operation of the processing cluster 214 may be controlled via a pipeline manager 232 that distributes processing tasks to SIMT parallel processors. The pipeline manager 232 receives instructions from the scheduler 210 of FIG. 2 and manages the execution of those instructions via the graphics multiprocessor 234 and / or the texture unit 236. The illustrated graphics multiprocessor 234 is an exemplary instance of a SIMT parallel processor. However, various types of SIMT parallel processors with different architectures may be included within the processing cluster 214. One or more instances of the graphics multiprocessor 234 may be included within the processing cluster 214. The graphics multiprocessor 234 may process data, and a data crossbar 240 may be used to distribute the processed data to one of a number of possible destinations, including other shader units. The pipeline manager 232 may facilitate the distribution of the processed data by specifying the destination of the processed data to be distributed via the data crossbar 240.

[0055] Each graphics multiprocessor 234 within the processing cluster 214 may include an identical set of functional execution logic (e.g., arithmetic logic units, load-store units, etc.). The functional execution logic may be configured in a pipeline manner in which new instructions may be issued before previous instructions are completed. The functional execution logic supports a wide variety of operations, including integer and floating-point arithmetic, comparison operations, boolean operations, bit shifting, and calculation of various algebraic functions. In one embodiment, different operations may be performed using the same functional unit hardware, and any combination of functional units may exist.

[0056] Instructions transmitted to processing cluster 214 constitute threads. A set of threads that execute across a group of parallel processing engines is a thread group. The thread group executes the same program on different input data. Each thread within the thread group can be assigned to a different processing engine within graphics multiprocessor 234. The thread group can include fewer threads than the number of processing engines within graphics multiprocessor 234. When the thread group includes fewer threads than the number of processing engines, one or more of the processing engines can be idle during the period in which the thread group is being processed. The thread group can also include more threads than the number of processing engines within graphics multiprocessor 234. When the thread group includes more threads than the number of processing engines within graphics multiprocessor 234, processing can be executed on consecutive clock cycles. In one embodiment, multiple thread groups can be executed concurrently on graphics multiprocessor 234.

[0057] In one embodiment, graphics multiprocessor 234 includes an internal cache memory to perform load and store operations. In one embodiment, graphics multiprocessor 234 can forgo the internal cache and use the cache memory (e.g., L1 cache 308) within processing cluster 214. Each graphics multiprocessor 234 also has access to an L2 cache within a partition unit (e.g., partition units 220A - 220N of FIG. 2) that is shared among all processing clusters 214 and can be used to transfer data between threads. Graphics multiprocessor 234 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. Any memory external to parallel processing unit 202 can be used as global memory. Multiple embodiments in which processing cluster 214 includes multiple instances of graphics multiprocessor 234 can share common instructions and data, which can be stored in L1 cache 308.

[0058] Each processing cluster 214 can include an MMU 245 (memory management unit) configured to map virtual addresses to physical addresses. In other embodiments, one or more instances of MMU 245 can reside within memory interface 218 of FIG. 2. MMU 245 includes: a set of page table entries (PTEs) for mapping virtual addresses of tiles (more discussion on tiling) to physical addresses; and optionally a cache line index. MMU 245 can include an address translation lookaside buffer (TLB) or cache that can reside within graphics multiprocessor 234 or L1 cache or processing cluster 214. The physical address is processed to distribute surface data access locality, thereby allowing efficient request interleaving among partition units. The cache line index can be used to determine whether a request for a cache line is a hit or a miss.

[0059] In graphics and computing applications, processing cluster 214 may be configured such that each graphics multiprocessor 234 is coupled to a texture unit 236 for performing texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. As needed, texture data is read from an internal texture L1 cache (not shown) or, in some embodiments, from an L1 cache within graphics multiprocessor 234, and the texture data is fetched from an L2 cache, local parallel processor memory, or system memory. Each graphics multiprocessor 234 outputs the processed tasks to data crossbar 240 to provide the processed tasks to another processing cluster 214 for further processing or to store the processed tasks in an L2 cache, local parallel processor memory, or system memory via memory crossbar 216. preROP 242 (e.g., pre-raster operation unit) is configured to receive data from graphics multiprocessor 234 and direct the data to ROP units, which may be co-located with partition units (e.g., partition units 220A - 220N of FIG. 2) as described herein. The preROP 242 unit may perform optimizations for color blending, organize pixel color data, and perform address translation.

[0060] It will be recognized that the core architectures described herein are illustrative and that various variations and modifications are possible. Any number of processing units (e.g., graphics multiprocessor 234, texture unit 236, preROP 242, etc.) may be included within processing cluster 214. Additionally, although only one processing cluster 214 is shown, the parallel processing unit as described herein may include any number of instances of processing cluster 214. In one embodiment, each processing cluster 214 may be configured to operate independently of other processing clusters 214 using separate and distinct processing units, L1 caches, etc.

[0061] Figure 2D A graphics multiprocessor 234 is shown in accordance with one embodiment. In such an embodiment, graphics multiprocessor 234 is coupled to a pipeline manager 232 of processing cluster 214. Graphics multiprocessor 234 has an execution pipeline that includes, but is not limited to: an instruction cache 252, an instruction unit 254, an address mapping unit 256, a register file 258, one or more general-purpose graphics processing unit (GPGPU) cores 262, and one or more load / store units 266. The GPGPU cores 262 and load / store units 266 are coupled to cache memory 272 and shared memory 270 via a memory and cache interconnect 268.

[0062] In one embodiment, the instruction cache 252 receives a stream of instructions to be executed from the pipeline manager 232. These instructions are cached in the instruction cache 252 and dispatched by the instruction unit 254 for execution. The instruction unit 254 may dispatch instructions as thread groups (e.g., warps), where each thread of the thread group is assigned to a different execution unit within the GPGPU core 262. Instructions can access any of the local, shared, or global address spaces by specifying an address within a unified address space. The address mapping unit 256 can be used to translate an address in the unified address space into a distinct memory address that can be accessed by the load / store unit 266.

[0063] The register file 258 provides a set of registers for the functional units of the graphics multiprocessor 324. The register file 258 provides temporary storage for the operands of the data paths connected to the functional units (e.g., GPGPU core 262, load / store unit 266) of the graphics multiprocessor 324. In one embodiment, the register file 258 is partitioned among each of these functional units such that each functional unit is allocated a dedicated portion of the register file 258. In one embodiment, the register file 258 is partitioned among different warps executed by the graphics multiprocessor 324.

[0064] The GPGPU cores 262 may each include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing the instructions of the graphics multiprocessor 324. According to an embodiment, the GPGPU cores 262 may be architecturally similar or may be architecturally different. For example and in one embodiment, a first portion of the GPGPU core 262 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or may implement variable-precision floating-point arithmetic. The graphics multiprocessor 324 may additionally include one or more fixed-function or special-function units to perform specific functions (such as, copy rectangle or pixel blend operations). In one embodiment, one or more of the GPGPU cores may also include fixed or special-function logic.

[0065] In one embodiment, the GPGPU core 262 includes SIMD logic capable of executing a single instruction on multiple sets of data. In one embodiment, the GPGPU core 262 may physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. SIMD instructions for the GPGPU core may be generated at compile time by a shader compiler or may be automatically generated when executing a program written and compiled for a single-program multiple-data (SPMD) or SIMT architecture. Multiple threads of a program configured for the SIMT execution model may be executed via a single SIMD instruction. For example, in one embodiment, eight SIMT threads performing the same or similar operations may be executed in parallel via a single SIMD8 logical unit.

[0066] The memory and cache interconnect 268 is an interconnect network that connects each of the functional units of the graphics multiprocessor 234 to the register file 258 and to the shared memory 270. In one embodiment, the memory and cache interconnect 268 is a crossbar interconnect that allows the load / store unit 266 to perform load and store operations between the shared memory 270 and the register file 258. The register file 258 can operate at the same frequency as the GPGPU core 262, whereby data transfer between the GPGPU core 262 and the register file 258 is very low latency. The shared memory 270 can be used to implement communication between threads executing on the functional units within the graphics multiprocessor 234. The cache memory 272 can be used as, for example, a data cache to cache texture data communicated between the functional units and the texture unit 236. The shared memory 270 can also be used as a program-managed cache. Threads executing on the GPGPU core 262 can also programmatically store data in the shared memory in addition to the automatically cached data stored in the cache memory 272.

[0067] Figures 3A to 3B Additional graphics multiprocessors according to embodiments are shown. The shown graphics multiprocessors 325, 350 are Figure 2C variants of the graphics multiprocessor 234. The shown graphics multiprocessors 325, 350 may be configured as streaming multiprocessors (SMs) capable of executing a large number of execution threads simultaneously.

[0068] Figure 3A A graphics multiprocessor 325 according to an additional embodiment is shown. The graphics multiprocessor 325 relative to Figure 2DThe graphics multiprocessor 234 includes multiple additional instances of execution resource units. For example, the graphics multiprocessor 325 may include multiple instances of instruction units 332A to 332B, register files 334A - 334B, and texture units 344A - 344B. The graphics multiprocessor 325 also includes multiple sets of graphics or compute execution units (e.g., GPGPU cores 336A to 336B, GPGPU cores 337A to 337B, GPGPU cores 338A to 338B) and multiple sets of load / store units 340A to 340B. In one embodiment, the execution resource units have a common instruction cache 330, texture and / or data cache memory 342, and shared memory 346.

[0069] The various components can communicate via the interconnect structure 327. In one embodiment, the interconnect structure 327 includes one or more crossbars to enable communication between the various components of the graphics multiprocessor 325. In one embodiment, the interconnect structure 327 is a separate high - speed network structure layer on which each component of the graphics multiprocessor 325 is stacked. The components of the graphics multiprocessor 325 communicate with remote components via the interconnect structure 327. For example, the GPGPU cores 336A - 336B, 337A - 337B, and 338A - 338B can each communicate with the shared memory 346 via the interconnect structure 327. The interconnect structure 327 can arbitrate communication within the graphics multiprocessor 325 to ensure fair bandwidth allocation between components.

[0070] Figure 3B A graphics multiprocessor 350 according to an additional embodiment is shown. The graphics processor includes multiple sets of execution resources 356A to 356D, where each set of execution resources includes multiple instruction units, register files, GPGPU cores, and load - store units, as Figure 2D and Figure 3A shown. The execution resources 356A to 356D can work in concert with the texture units 360A to 360D for texture operations while sharing the instruction cache 354 and the shared memory 362. In one embodiment, the execution resources 356A to 356D can share the instruction cache 354, the shared memory 362, and multiple instances of texture and / or data cache memories 358A to 358B. The various components can communicate via an interconnect structure 352 similar to Figure 3A the interconnect structure 327.

[0071] Those skilled in the art will understand that Figure 1 、 Figures 2A to 2D and Figures 3A to 3BThe architecture described herein is descriptive and non - limiting with respect to the scope of the present embodiment. Thus, without departing from the scope of the embodiments described herein, the techniques described herein may be implemented on any properly configured processing unit, including but not limited to one or more mobile application processors, one or more desktop computer or server central processing units (CPUs) (including multi - core CPUs), one or more parallel processing units (e.g., the parallel processing unit 202 of FIG. 2), and one or more graphics processors or dedicated processing units.

[0072] In some embodiments, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general - purpose GPU (GPGPU) functions. The GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high - speed interconnect such as PCIe or NVLink). In other embodiments, the GPU may be integrated on the same package or chip as these cores and communicatively coupled to these cores via an internal processor bus / interconnect (i.e., within the package or chip). Regardless of the manner in which the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0073] Techniques for GPU-to-Host Processor Interconnect

[0074] Figure 4A An exemplary architecture is shown where multiple GPUs 410 to 413 are communicatively coupled to multiple multi - core processors 405 to 406 via high - speed links 440 to 443 (e.g., buses, point - to - point interconnects, etc.). In one embodiment, depending on the implementation, the high - speed links 440 to 443 support a communication throughput of 4 GB / s, 30 GB / s, 80 GB / s, or higher. Various interconnect protocols may be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. However, the basic principles of the present invention are not limited to any particular communication protocol or throughput.

[0075] Additionally, in one embodiment, two or more of the GPUs 410 to 413 are interconnected via high - speed links 444 to 445, which may be implemented using the same or different protocols / links as those used for the high - speed links 440 to 443. Similarly, two or more of the multi - core processors 405 to 406 may be connected via a high - speed link 433, which may be a symmetric multi - processor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, Figure 4AAll communication between the various system components shown can be implemented using the same protocol / link (e.g., via a common interconnect structure). However, as mentioned, the basic principles of the present invention are not limited to any particular type of interconnect technology.

[0076] In one embodiment, each of the multi-core processors 405 to 406 is communicatively coupled to the processor memories 401 to 402 via the memory interconnects 430 to 431, respectively, and each of the GPUs 410 to 413 is communicatively coupled to the GPU memories 420 to 423 via the GPU memory interconnects 450 to 453, respectively. The memory interconnects 430 to 431 and 450 to 453 may utilize the same or different memory access technologies. By way of example and without limitation, the processor memories 401 to 402 and the GPU memories 420 to 423 may be volatile memories such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memories such as 3D XPoint or nano random access memory. In one embodiment, a portion of the memory may be volatile memory, and another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0077] As described below, although the various processors 405 to 406 and GPUs 410 to 413 may be physically coupled to specific memories 401 to 402, 420 to 423, respectively, a unified memory architecture can be implemented in which the same virtual system address space (also referred to as the "effective address" space) is distributed among all the individual physical memories. For example, each of the processor memories 401 to 402 may include 64 GB of the system memory address space, and each of the GPU memories 420 to 423 may include 32 GB of the system memory address space (resulting in a total of 256 GB of addressable memory in this example).

[0078] Figure 4B Additional details of the interconnect between the multi-core processor 407 and the graphics acceleration module 446 according to one embodiment are shown. The graphics acceleration module 446 may include one or more GPU chips integrated on a line card that is coupled to the processor 407 via a high-speed link 440. Alternatively, the graphics acceleration module 446 may be integrated on the same package or chip as the processor 407.

[0079] The illustrated processor 407 includes multiple cores 460A through 460D, each core having a translation lookaside buffer 461A through 461D and one or more caches 462A through 462D. These cores may include various other components for executing instructions and processing data, which are not shown to avoid obscuring the basic principles of the present invention (e.g., instruction fetch units, branch prediction units, decoders, execution units, reorder buffers, etc.). The caches 462A through 462D may include level 1 (L1) and level 2 (L2) caches. Additionally, one or more shared caches 426 may be included in the cache hierarchy and shared by multiple sets of cores 460A through 460D. For example, one embodiment of processor 407 includes 24 cores, each having its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one of the L2 and L3 caches is shared by two adjacent cores. Processor 407 and graphics accelerator integration module 446 are connected to system memory 441, which may include processor memories 401 through 402.

[0080] Data and instructions stored in the various caches 462A through 462D, 456, and system memory 441 are kept consistent via inter-core communication over coherence bus 464. For example, each cache may have cache coherence logic / circuit associated therewith to communicate via coherence bus 464 in response to a detected read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented via coherence bus 464 to snoop on cache accesses. Cache snooping / coherence techniques are well understood by those skilled in the art and will not be described in detail herein to avoid obscuring the basic principles of the present invention.

[0081] In one embodiment, proxy circuit 425 communicatively couples graphics acceleration module 446 to coherence bus 464, allowing graphics acceleration module 446 to participate in the cache coherence protocol as a peer of the cores. Specifically, interface 435 provides connectivity to proxy circuit 425 via high-speed link 440 (e.g., PCIe bus, NVLink, etc.), and interface 437 connects graphics acceleration module 446 to link 440.

[0082] In one implementation, the accelerator integrated circuit 436 represents multiple graphics processing engines 431, 432, N of the graphics acceleration module 446 to provide cache management, memory access, context management, and interrupt management services. The graphics processing engines 431, 432, N may each include a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 431, 432, N may include different types of graphics processing engines within the GPU, such as graphics execution units, media processing engines (e.g., video encoder / decoder), samplers, and blit engines. In other words, the graphics acceleration module can be a GPU having multiple graphics processing engines 431 to 432, N, or the graphics processing engines 431 to 432, N can be individual GPUs integrated on a common package, line card, or chip.

[0083] In one embodiment, the accelerator integrated circuit 436 includes a memory management unit (MMU) 439 to perform various memory management functions, such as virtual-to-physical memory translation (also known as effective-to-real memory translation) and a memory access protocol for accessing system memory 441. The MMU 439 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective to physical / real address translations. In one implementation, the cache 438 stores commands and data for efficient access by the graphics processing engines 431 to 432, N. In one embodiment, the data stored in the cache 438 and the graphics memories 433 to 434, N is kept consistent with the core caches 462A to 462D, 456, and the system memory 411. As mentioned, this can be achieved via the proxy circuit 425, which participates in the cache coherence mechanism on behalf of the cache 438 and the memories 433 to 434, N (e.g., sending updates related to modifications / accesses to cache lines on the processor caches 462A to 462D, 456 to the cache 438, and receiving updates from the cache 438).

[0084] A set of registers 445 stores context data for threads executed by the graphics processing engines 431 to 432, N, and the context management circuit 448 manages thread contexts. For example, the context management circuit 448 may perform save and restore operations during context switching to save and restore the contexts of various threads (e.g., where the first thread is saved and the second thread is stored so that the second thread can be executed by the graphics processing engine). For example, during context switching, the context management circuit 448 may store the current register values into a specified area in memory (e.g., identified by a context pointer). Then, it may restore these register values when returning to the context. In one embodiment, the interrupt management circuit 447 receives and processes interrupts received from system devices.

[0085] In one implementation, the MMU 439 converts virtual / valid addresses from the graphics processing engine 431 into real / physical addresses in the system memory 411. One embodiment of the accelerator integrated circuit 436 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 446 and / or other accelerator devices. The graphics accelerator module 446 can be dedicated to a single application executing on the processor 407 or can be shared among multiple applications. In one embodiment, a virtualized graphics execution environment is presented where multiple applications or virtual machines (VMs) share the resources of the graphics processing engines 431 through 432, N. These resources can be further divided into "slices" that are allocated to the VMs and / or applications based on processing requirements and priorities associated with different VMs and / or applications.

[0086] Thus, the accelerator integrated circuit acts as a bridge to the system of the graphics accelerator module 446 and provides address translation and system memory cache services. Additionally, the accelerator integrated circuit 436 can provide virtualization facilities to the host processor to manage the virtualization, interrupts, and memory management of the graphics processing engine.

[0087] Since the hardware resources of the graphics processing engines 431 through 432, N are explicitly mapped to the real address space seen by the host processor 407, any host processor can directly address these resources using valid address values. In one embodiment, one function of the accelerator integrated circuit 436 is to physically isolate the graphics processing engines 431 through 432, N such that they appear to the system as independent units.

[0088] As mentioned, in the illustrated embodiment, one or more graphics memories 433 through 434, M are coupled to each of the graphics processing engines 431 through 432, N, respectively. The graphics memories 433 through 434, M store the instructions and data processed by each of the graphics processing engines 431 through 432, N. The graphics memories 433 through 434, M can be volatile memories such as DRAM (including stacked DRAM), GDDR memories (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memories such as 3D XPoint or nano random access memory (Nano-Ram).

[0089] In one embodiment, to reduce data traffic on link 440, a biasing technique is used to ensure that the data stored in graphics memories 433 - 434, M is the data that will be most frequently used by graphics processing engines 431 - 432, N and preferably not used (at least not frequently) by cores 460A - 460D. Similarly, the biasing mechanism attempts to keep the data required by the cores (and preferably not by graphics processing engines 431 - 432, N) in caches 462A - 462D, 456 of these cores and in system memory 411.

[0090] Figure 4C Another embodiment is shown where accelerator integrated circuit 436 is integrated within processor 407. In this embodiment, graphics processing engines 431 - 432, N communicate directly to accelerator integrated circuit 436 via interface 437 and interface 435 (again, these interfaces can utilize any form of bus or interface protocol) over high - speed link 440. Accelerator integrated circuit 436 can perform the same operations as described with respect to Figure 4B but potentially at a higher throughput considering its very close proximity to coherence bus 462 and caches 462A - 462D, 426.

[0091] One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization). The latter can include a programming model controlled by accelerator integrated circuit 436 and a programming model controlled by graphics acceleration module 446.

[0092] In one embodiment of the dedicated process model, graphics processing engines 431 - 432, N are dedicated to a single application or process under a single operating system. A single application can funnel other application requests to graphics engines 431 - 432, N, thus providing virtualization within a VM / partition.

[0093] In the dedicated process programming model, graphics processing engines 431 - 432, N can be shared by multiple VM / application partitions. The shared model requires the hypervisor to virtualize graphics processing engines 431 - 432, N to allow access by each operating system. For a non - hypervisor single - partition system, graphics processing engines 431 - 432, N are owned by the operating system. In both cases, the operating system can virtualize graphics processing engines 431 - 432, N to provide access to each process or application.

[0094] For a shared programming model, the graphics acceleration module 446 or individual graphics processing engines 431-432, N use a process handle to select process elements. In one embodiment, the process elements are stored in the system memory 411 and can be addressed using the effective address to real address translation techniques described herein. The process handle can be an implementation-specific value provided to the host process when registering its context with the graphics processing engines 431-432, N (i.e., calling system software to add the process element to the process element linked list). The lower 16 bits of the process handle can be the offset of the process element within the process element linked list.

[0095] Figure 4D Exemplary accelerator integration slice 490 is shown. As used herein, "slice" includes a designated portion of the processing resources of the accelerator integrated circuit 436. The application effective address space 482 within the system memory 411 stores process elements 483. In one embodiment, the process elements 483 are stored in response to a GPU call 481 from an application 480 executing on the processor 407. The process elements 483 contain the process state of the corresponding application 480. The work descriptor (WD) 484 contained within the process element 483 can be a single job requested by the application or can contain a pointer to a job queue. In the latter case, the WD 484 is a pointer to the job request queue within the application's address space 482.

[0096] The graphics acceleration module 446 and / or individual graphics processing engines 431-432, N can be shared by all processes or a subset of processes in the system. Embodiments of the present invention include infrastructure for setting the process state and sending the WD 484 to the graphics acceleration module 446 to start a job in a virtualized environment.

[0097] In one implementation, the dedicated process programming model is implementation-specific. In this model, a single process owns the graphics acceleration module 446 or an individual graphics processing engine 431. Since the graphics acceleration module 446 is owned by a single process, when the graphics acceleration module 446 is assigned, the hypervisor initializes the accelerator integrated circuit 436 for the owning partition and the operating system initializes the accelerator integrated circuit 436 for the owning process.

[0098] In operation, the WD fetch unit 491 in the accelerator integrated slice 490 fetches the next WD 484, which includes an indication of work to be completed by one of the graphics processing engines in the graphics acceleration module 446. Data from the WD 484 can be stored in the register 445 and used by the MMU 439, interrupt management circuit 447, and / or context management circuit 446 as shown. For example, one embodiment of the MMU 439 includes a segment / page walk circuit for accessing the segment / page table 486 within the OS virtual address space 485. The interrupt management circuit 447 can process the interrupt event 492 received from the graphics acceleration module 446. When performing a graphics operation, the effective address 493 generated by the graphics processing engines 431 to 432, N is translated to a real address by the MMU 439.

[0099] In one embodiment, a set of identical registers 445 is replicated for each graphics processing engine 431 to 432, N and / or graphics acceleration module 446, and these registers can be initialized by the hypervisor or the operating system. Each of these replicated registers can be included in the accelerator integrated slice 490. Exemplary registers that can be initialized by the hypervisor are shown in Table 1.

[0100] Table 1 - Registers Initialized by the Hypervisor

[0101] 1 Slice Control Register 2 Real Address (RA) Scheduled Process Region Pointer 3 Authority Mask Override Register 4 Interrupt Vector Table Entry Offset 5 Interrupt Vector Table Entry Limit 6 Status Register 7 Logical Partition ID 8 Real Address (RA) Hypervisor Accelerator Utilization Record Pointer 9 Storage Description Register

[0102] Exemplary registers that can be initialized by the operating system are shown in Table 2.

[0103] Table 2 - Registers Initialized by the Operating System

[0104] 1 Process and Thread Identification 2 Effective Address (EA) Context Save / restore Pointer 3 Virtual Address (VA) Accelerator Utilization Record Pointer 4 Virtual Address (VA) Storage Segment Table Pointer 5 Authority Mask 6 Work Descriptor

[0105] In one embodiment, each WD 484 is specific to a particular graphics acceleration module 446 and / or graphics processing engine 431 to 432, N. It contains all the information required for the graphics processing engines 431 to 432, N to complete their work, or it can be a pointer to a memory location where the application has set up a command queue for the work to be done.

[0106] Figure 4E Additional details of one embodiment of the shared model are shown. This embodiment includes a hypervisor real address space 498 in which a process element list 499 is stored. The hypervisor real address space 498 can be accessed via the hypervisor 496, which virtualizes the graphics acceleration module engine for the operating system 495.

[0107] The shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 446. There are two programming models in which the graphics acceleration module 446 is shared by multiple processes and partitions: time slice sharing and graphics directed shared.

[0108] In this model, the hypervisor 496 owns the graphics acceleration module 446 and makes its functionality available to all operating systems 495. To enable the graphics acceleration module 446 to support virtualization by the hypervisor 496, the graphics acceleration module 446 may follow the following requirements: 1) The job requests of the application must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 446 must provide a context save and restore mechanism. 2) The graphics acceleration module 446 is guaranteed to complete the job requests of the application (including any translation faults) within a specified amount of time, or the graphics acceleration module 446 provides the ability to handle preempted jobs. 3) When operating in the directed sharing programming model, fairness of the graphics acceleration module 446 between processes must be guaranteed.

[0109] In one embodiment, for the shared model, the application 480 needs to use the graphics acceleration module 446 type, work descriptor (WD), privilege mask register (AMR) value, and context save / restore area pointer (CSRP) to make an operating system 495 system call. The graphics acceleration module 446 type describes the target acceleration function for the system call. The graphics acceleration module 446 type can be a system-specific value. The WD is formatted specifically for the graphics acceleration module 446 and can be in the form of a graphics acceleration module 446 command, a valid address pointer to a user-defined structure, a valid address pointer to a command queue, or any other data structure used to describe the work to be done by the graphics acceleration module 446. In one embodiment, the AMR value is the AMR state to be used for the current process. The value passed to the operating system is similar to the application that sets the AMR. If the accelerator integrated circuit 436 and the graphics acceleration module 446 implementation do not support the user privilege mask override register (UAMOR), then the operating system can apply the current UAMOR value to the AMR value and then pass the AMR in the hypervisor call. Optionally, the hypervisor 496 can apply the current privilege mask override register (AMOR) value and then place the AMR in the process element 483. In one embodiment, the CSRP is one of the registers 445 that contains the valid address of a region in the application's address space 482 for the graphics acceleration module 446 to save and restore the context state. This pointer is optional if there is no need to save state between jobs or when a job is preempted. The context save / restore area can be pinned system memory.

[0110] When a system call is received, the operating system 495 can verify that the application 480 is registered and has been granted permission to use the graphics acceleration module 446. Then, the operating system 495 uses the information shown in Table 3 to call the hypervisor 496.

[0111] Table 3 - OS to Hypervisor Call Parameters

[0112] 1 Work Descriptor (WD) 2 Authority Mask Register (AMR) Value (Potentially Masked) 3 Effective Address (EA) Context Save / restore Region Pointer (CSRP) 4 Process ID (PID) and Optional Thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual Address of Storage Segment Table Pointer (SSTP) 7 Logical Interrupt Service Number (LISN)

[0113] When a hypervisor call is received, the hypervisor 496 verifies that the operating system 495 is registered and has been granted permission to use the graphics acceleration module 446. Then, the hypervisor 496 places the process element 483 into the linked list of process elements of the corresponding graphics acceleration module 446 type. The process element may include the information shown in Table 4.

[0114] Table 4 - Process Element Information

[0115] 1 Work Descriptor (WD) 2 Authority Mask Register (AMR) Value (Potentially Masked) 3 Effective Address (EA) Context Save / restore Region Pointer (CSRP) 4 Process ID (PID) and Optional Thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual Address of Storage Segment Table Pointer (SSTP) 7 Logical Interrupt Service Number (LISN) 8 Interrupt Vector Table Derived from Hypervisor Call Parameters 9 Status Register (SR) Value 10 Logical Partition ID (LPID) 11 Real Address (RA) Hypervisor Accelerator Utilization Record Pointer 12 Memory Descriptor Register (SDR)

[0116] In one embodiment, the hypervisor initializes the registers 445 of multiple accelerator integrated slices 490.

[0117] As Figure 4F shown, one embodiment of the present invention employs unified memory that can be addressed via a common virtual memory address space for accessing physical processor memories 401 to 402 and GPU memories 420 to 423. In such an implementation, operations executed on the GPUs 410 to 413 utilize the same virtual / effective memory address space to access the processor memories 401 to 402 and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to the processor memory 401, a second portion is allocated to the second processor memory 402, a third portion is allocated to the GPU memory 420, and so on. Thus, the entire virtual / effective memory space (sometimes referred to as the effective address space) is distributed across each of the processor memories 401 to 402 and the GPU memories 420 to 423, allowing any processor or GPU to access any physical memory using the virtual address mapped to that memory.

[0118] In one embodiment, the bias / coherency management circuits 494A to 494E within one or more of the MMUs 439A to 439E ensure cache coherency between the host processor (e.g., 405) and the caches of the GPUs 410 to 413, and implement a bias technique for physical memory indicating where certain types of data should be stored. Although Figure 4FMultiple instances of bias / coherence management circuits 494A - 494E are shown, but the bias / coherence circuits may be implemented within the MMU of one or more host processors 405 and / or within the accelerator integrated circuit 436.

[0119] One embodiment allows GPU attached memories 420 - 423 to be mapped as part of system memory and accessed using shared virtual memory (SVM) techniques, without suffering from the typical performance penalties associated with full system cache coherence. This ability to access GPU attached memories 420 - 423 as system memory without heavy cache coherence overhead provides a beneficial operating environment for GPU offloading. This arrangement allows host processor 405 software to set operands and access computation results without the overhead of traditional I / O DMA data copying. Such traditional copying involves driver calls, interrupts, and memory mapped I / O (MMIO) accesses, all of which are inefficient relative to simple memory access. At the same time, the ability to access GPU attached memories 420 - 423 without cache coherence overhead can be critical to the execution time of offloaded computations. In cases with substantial streaming write memory traffic, for example, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPUs 410 - 413. The efficiency of operand setting, result access, and GPU computation all play a role in determining the effectiveness of GPU offloading.

[0120] In one implementation, the selection between GPU bias and host processor bias is driven by a bias tracker data structure. A bias table may be used, for example, which can be a page - granularity structure (i.e., controlled at the granularity of a memory page) that includes 1 or 2 bits per GPU attached memory page. One or more stolen memory ranges of GPU attached memories 420 - 423 may be employed to implement the bias table, with or without a bias cache in GPUs 410 - 413 (e.g., for caching frequently used / recently used entries of the bias table). Alternatively, the entire bias table may be maintained within the GPU.

[0121] In one implementation, the bias table entries associated with each access to the GPU attached memories 420-423 are accessed before actually accessing the GPU memory, thereby causing the following operations. First, local requests from GPUs 410-413 that look for their pages in the GPU bias (these local requests find their pages in the GPU bias) are directly forwarded to the corresponding GPU memories 420-423. Local requests from the GPUs (these local requests find their pages in the host bias) are forwarded to the processor 405 (e.g., via the high-speed link as discussed above). In one embodiment, requests from the processor 405 that look for the requested page in the host processor bias complete requests similar to normal memory reads. Alternatively, requests for GPU bias pages can be forwarded to GPUs 410-413. Then, if the GPU is not currently using the page, it can transition the page to the host processor bias.

[0122] The bias state of a page can be changed by a software-based mechanism, a hardware-assisted software-based mechanism, or a purely hardware-based mechanism for a limited set of cases.

[0123] One mechanism for changing the bias state employs an API call (e.g., OpenCL), which in turn calls the device driver of the GPU, which in turn sends a message (or queues a command descriptor) to the GPU to direct it to change the bias state and perform a cache flushing operation in the host for some transitions. The cache flushing operation is required for transitions from the host processor 405 bias to the GPU bias, but not for the reverse transition.

[0124] In one embodiment, cache coherence is maintained by temporarily rendering GPU bias pages that cannot be cached by the host processor 405. To access these pages, the processor 405 can request access from the GPU 410, which may or may not immediately grant access depending on the implementation. Therefore, to reduce communication between the processor 405 and the GPU 410, it is advantageous to ensure that the GPU bias pages are those that are needed by the GPU but not by the host processor 405 (and vice versa).

[0125] Graphics Processing Pipeline

[0126] Figure 5 Displays a graphics processing pipeline 500 according to an embodiment. In one embodiment, a graphics processor may implement the displayed graphics processing pipeline 500. The graphics processor may be included within a parallel processing subsystem as described herein, such as the parallel processor 200 of FIG. 2, which in one embodiment isFigure 1 Variants of the (multiple) parallel processors 112. Various parallel processing systems may implement the graphics processing pipeline 500 via one or more instances of a parallel processing unit (e.g., the parallel processing unit 202 of FIG. 2) as described herein. For example, a shader unit (e.g., the graphics multiprocessor 234 of FIG. 3) may be configured to perform the functions of one or more of the vertex processing unit 504, the tessellation control processing unit 508, the tessellation evaluation processing unit 512, the geometry processing unit 516, and the fragment / pixel processing unit 524. The functions of the data assembler 502, the primitive assembler 506, 514, 518, the tessellation unit 510, the rasterizer 522, and the raster operation unit 526 may also be performed by other processing engines and corresponding partitioning units (e.g., the partitioning units 220A to 220N of FIG. 2) within a processing cluster (e.g., the processing cluster 214 of FIG. 3). The graphics processing pipeline 500 may also be implemented using dedicated processing units for one or more functions. In one embodiment, one or more portions of the graphics processing pipeline 500 may be performed by parallel processing logic within a general-purpose processor (e.g., a CPU). In one embodiment, one or more portions of the graphics processing pipeline 500 may access on-chip memory (e.g., the parallel processor memory 222 as in FIG. 2) via a memory interface 528, which may be an instance of the memory interface 218 of FIG. 2.

[0127] In one embodiment, the data assembler 502 is a processing unit that collects vertex data of surfaces and primitives. The data assembler 502 then outputs the vertex data including vertex attributes to the vertex processing unit 504. The vertex processing unit 504 is a programmable execution unit that executes a vertex shader program to illuminate and transform the vertex data as specified by the vertex shader program. The vertex processing unit 504 reads data stored in a cache, local, or system memory for use in processing the vertex data, and the vertex processing unit 504 may be programmed to transform the vertex data from an object-based coordinate representation to a world space coordinate space or a normalized device coordinate space.

[0128] A first instance of the primitive assembler 506 receives vertex attributes from the vertex processing unit 504. The primitive assembler 506 reads the stored vertex attributes as needed and constructs graphics primitives for processing by the tessellation control processing unit 508. The graphics primitives include triangles, line segments, points, patches, etc. supported by various graphics processing application programming interfaces (APIs).

[0129] The tessellation control processing unit 508 treats the input vertices as control points for geometric patches. The control points are transformed from an input representation of the patch (e.g., the basis of the patch) to a representation suitable for use by the tessellation evaluation processing unit 512 in surface evaluation. The tessellation control processing unit 508 may also compute the tessellation factors for the edges of the geometric patch. The tessellation factors are applied to individual edges and quantify the view-dependent level of detail associated with that edge. The tessellation unit 510 is configured to receive the tessellation factors for the edges of the patch and to tessellate the patch surface into a plurality of geometric primitives such as line, triangle, or quadrilateral primitives, which are transmitted to the tessellation evaluation processing unit 512. The tessellation evaluation processing unit 512 operates on the parameterized coordinates of the subdivided patch to generate a surface representation and vertex attributes for each vertex associated with the geometric primitives.

[0130] A second instance of the primitive assembler 514 receives the vertex attributes from the tessellation evaluation processing unit 512, reads the stored vertex attributes as needed, and constructs graphics primitives for processing by the geometry processing unit 516. The geometry processing unit 516 is a programmable execution unit that executes a geometry shader program to transform the graphics primitives received from the primitive assembler 514 as specified by the geometry shader program. In one embodiment, the geometry processing unit 516 is programmed to subdivide the graphics primitives into one or more new graphics primitives and to compute the parameters for rasterizing the new graphics primitives.

[0131] In some embodiments, the geometry processing unit 516 may add or delete elements in the geometry stream. The geometry processing unit 516 outputs the parameters and vertices specifying the new graphics primitives to the primitive assembler 518. The primitive assembler 518 receives the parameters and vertices from the geometry processing unit 516 and constructs graphics primitives for processing by the viewport scale, cull, and clip unit 520. The geometry processing unit 516 reads data stored in the parallel processor memory or system memory for use in processing geometric data. The viewport scale, cull, and clip unit 520 performs clipping, culling, and viewport scaling and outputs the processed graphics primitives to the rasterizer 522.

[0132] The rasterizer 522 may perform depth culling and other depth-based optimizations. The rasterizer 522 also performs scan conversion of new graphics primitives to generate fragments and outputs those fragments and associated coverage data to the fragment / pixel processing unit 524. The fragment / pixel processing unit 524 is a programmable execution unit configured to execute a fragment shader program or a pixel shader program. The fragment / pixel processing unit 524 transforms the fragments or pixels received from the rasterizer 522 as specified by the fragment or pixel shader program. For example, the fragment / pixel processing unit 524 may be programmed to perform operations, including but not limited to texture mapping, shading, blending, texture correction, and perspective correction, that produce shaded fragments or pixels output to the raster operations unit 526. The fragment / pixel processing unit 524 may read data stored in the parallel processor memory or system memory for use in processing fragment data. The fragment or pixel shader program may be configured to shade at samples, pixels, tiles, or other granularities depending on the sampling rate configured for the processing unit.

[0133] The raster operations unit 526 is a processing unit that performs raster operations including but not limited to stencil printing, z-testing, blending, etc., and outputs pixel data as processed graphics data to be stored in the graphics memory (e.g., the parallel processor memory 222 and / or Figure 1 the system memory 104 in FIG. 2), displayed on one or more display devices 110, or further processed by one of the one or more processors 102 or (multiple) parallel processors 112. In some embodiments, the raster operations unit 526 is configured to compress z or color data written to memory and decompress z or color data read from memory.

[0134] Adaptive Sub-Sharding

[0135] Figure 6 is a block diagram showing a computer system 600 configured to generate subpatches for tessellation. The system 600 may include: a power supply 602 for powering the system 600; a graphics pipeline device 604; a hardware fixed-function tessellator unit 606; and a display subsystem 608 communicatively coupled to the graphics pipeline device 604.

[0136] The graphics pipeline device 604 may include a hull shader unit 610, such as in Figure 5As described at the tessellation control processing unit 508. The graphics pipeline device 604 can send geometric data to the hull shader unit 610. The hull shader unit 610 can determine whether the geometric data generated in the graphics pipeline includes one or more patches, and send the one or more patches to the hull shader core 612. A patch can be a compact definition of a complex geometric object. Each sub-patch can include a sub-patch tessellation factor. In one implementation, the hull shader core 612 determines not to generate one or more sub-patches.

[0137] The hull shader core 612 can determine to generate sub-patches and sub-patch tessellation factors for the tessellated surface associated with the one or more patches, and specify how to break down the patch into a certain number of sub-patches with individual tessellation factors. The sub-patch tessellation factor can have a value between 1 and 64, and the value can determine the number of outer edges and / or the number of segments for each outer edge to be used for generating the sub-patch tessellation.

[0138] As shown in system 600, the generated adaptive sub-patches can specify individual tessellation factors for the sub-patches to control the triangle size processed by the fixed-function tessellator, where adjacent segments of the outer edges between sub-patches have the same tessellation factor. For example, for a perspective view, smaller segments can be used to finely tessellate the tessellation factor of the sub-patches to be rendered in the foreground (e.g., by the hull shader core 612), while larger segments can be used to coarsely tessellate the sub-patches to be rendered in the background.

[0139] The hull shader kernel 612 can adaptively determine the tessellation granularity by defining one or more of the subpatches or the tessellation factors for each subpatch. The subpatches or the tessellation factors can be defined based on scene elements, such as the perspective angle or degree from a fixed or relative position, the priority of one or more regions of the scene, and interesting objects identified by configurable object identifiers provided, for example, by an application (e.g., an application developer). The hull shader kernel 612 can use the adaptive tessellation granularity to render one or more textures of the surfaces of objects in the scene. The hull shader kernel 612 can responsively maintain a target triangle size (e.g., fragment size) based on one or more granularity factors. The granularity factors can include the system rendering processing capabilities, the size of the tessellation (e.g., fragments) for processing the minimum or most efficient number of patches and / or subpatches, and / or a rendering quality threshold. Conventional hull shaders can limit the determination of patches based on the outer edges of the patches. In contrast, the hull shader kernel 612 can responsively define adaptive subpatches with individual tessellation factors based on performance and / or scene perspective. The hull shader kernel 612 can forward the adaptive subpatches with individual tessellation factors to the hardware fixed-function tessellator 606 having a list identifying each subpatch.

[0140] Although the edges of a patch or subpatch can be defined by multiple fragments, for traditional uniform tessellation, the inner edges can define the size of the tessellation (e.g., the tessellation granularity) using two tessellation factors (e.g., the minimum tessellation factor and the maximum tessellation factor for each dimension). When rendering a scene with perspective (e.g., a 3D scene or image to be rendered), the adaptive subpatches can provide geometric compression to process geometric data (e.g., for 3D rendering). The adaptive subpatches with different tessellation factors for different parts of the patch can include independent tessellation factors, where adjacent fragments of the outer edge have the same tessellation factors (e.g., the minimum tessellation factor value and the maximum tessellation factor for each dimension value).

[0141] Compared with traditional three-dimensional (3D) application programming interfaces (APIs), the hardware fixed-function tessellator unit 606 can generate subpatch tessellations of the subpatches based on the subpatch tessellation factors and generate subpatch specifications based on the subpatch tessellations. Traditional 3D APIs can implement patch tessellations for tessellating triangle domains and / or quadrilateral domains based on a single set of calculated tessellation factors (e.g., outer edge tessellation factors and inner tessellation factors).

[0142] System 600 may include a domain shader unit 614 that uses displacement mapping to convert a subpatch specification into a digital rendered scene using vertex data computed by the domain shader unit 614 for tessellated patches and / or subpatches. The domain shader unit 614 may receive vertices (e.g., parametric domain coordinates) from a fixed function tessellator and convert the coordinates (e.g., using displacement mapping or a mapping operation) into a perspective scene, and a display subsystem may visually render one or more scenes associated with subpatch tessellation and subpatch specification. The vertex data may then be used by one or more of the downstream pipeline units (514 - 526) to render the tessellated geometry.

[0143] Figure 7A FIG. is a conceptual diagram of an example of a tessellation factor of a quad domain patch 700 according to an embodiment. A patch or subpatch may belong to one of a variety of domain types including quadrilateral or triangular domain type patches or subpatches. For example, a quad domain patch or a quad domain subpatch may have four "outer" tessellation factors 702, 704, 706, 708 associated with the four outer edges of the quad domain patch or quad domain subpatch. A hull shader kernel (e.g., as described with respect to the hull shader kernel 612 at Figure 6 may generate values of subpatch parameters that identify subpatch attributes in each dimension of an N - dimensional patch or subpatch. One or more of the subpatch parameters may include one or more values that identify a start subpatch boundary and an end subpatch boundary of a subpatch position within the patch. The subpatch parameters may identify and / or the subpatch attributes may include domain parametric coordinates that identify a position along an edge of the patch, as may be defined by a parametric value between zero and one. For example, subpatch parameters (e.g., parametric factors - where each dimension in an N - dimensional patch has a value from 0 to 1, such as a two - dimensional quadrilateral patch having 0, 0 to 1, 1). The tessellation factors 702, 704, 706, 708 may be set (e.g., computed), and the subpatch positions along the edges may be defined by start boundary pairs and end boundary pairs for each subpatch, e.g., (0, 0), (1, 0) at 710, 712, (1, 0), (1, 1) at 712, 714, (1, 1), (0, 1) at 714, 716, and (0, 1), (0, 0) at 716, 710.

[0144] For an N-dimensional (e.g., N = 3, 3D) patch or sub-patch, the number of "outer" tessellation factors can be equal to N squared. For example, 2D can use four "outer" tessellation factors, and 3D can use eight "outer" tessellation factors, e.g., one tessellation factor per outer edge (e.g., a segment of the outer edge). In other implementations, the number of tessellation factors used can be adjusted based on one or more of scene perspective, the level of granularity of one or more domains of the scene to be digitally rendered, available computing power, computing performance, or power consumption for computing the number of tessellation factors.

[0145] For a 2D quad patch or 2D quad sub-patch, two "inner" tessellation factors 718, 720 can be associated with the "inner region" 722 of the patch or sub-patch. The inner tessellation factors can determine how to divide the inner region in M dimensions, e.g., where M = 2, two directions. The inner tessellation factors can include most of the triangles in the tessellated patch or sub-patch (e.g., if not all triangles). A quad or triangle patch or quad or triangle sub-patch can include transition regions 724, 726, 728, 730 between the corresponding outer edges (e.g., or segments of the edges) of the patch or sub-patch and the "inner region" 722.

[0146] Figure 7B is a conceptual diagram of an example of the tessellation of adjacent patches 750 according to an embodiment. The hull shader kernel can generate sub-patches for the tessellated surfaces 752, 754, 756, 758, 760 associated with the patch. The patch and sub-patches can identify one or more domains. The domains can be subdivided into triangular or quadrilateral domains. The hull shader kernel can adaptively generate tessellation factors (TFs) to specify the level of tessellation of the sub-patches of the patch, including quad sub-patches 752, 754, 756 and / or triangular sub-patches 758, 760. Each sub-patch can include sub-patch tessellation factors. Each tessellation factor can specify the number of segments 762, 764, 766, 768, 770 into which the hardware fixed-function tessellator can divide the edges of the patch or sub-patch. For example, quad sub-patches 752 and 756 share an edge that is divided into segments such as 762, 764, etc., quad sub-patches 754 and 756 share an edge that is divided into segments such as 770, etc., and quad sub-patch 766 and triangular sub-patches 768, 760 share an edge that is divided into segments such as 766, 768, etc.

[0147] To eliminate gaps (e.g., cracks) between adjacent edges of adjacent patches and / or sub-patches, the outer edge tessellation factor can be specified to be the same for a given shared edge (e.g., or a segment of an edge). Given an inner edge, the tessellation factor can be different from the corresponding outer edge tessellation factor, and a "transition" region can be used to connect the inner or outer edge to one or more irregular triangle strips.

[0148] The hardware-fixed functional tessellator can generate the sub-patch tessellation of the sub-patch based on the sub-patch tessellation factor and generate a sub-patch specification based on the sub-patch tessellation. The sub-patch tessellation can define a plurality of triangles that define the geometry of an object or surface for digital rendering in a scene. The hull shader kernel can adaptively and in real time compute the sub-patch tessellation factor based on performance considerations or a patch mesh that defines a geometric object. The sub-patch specification can include control points. The domain shader can use displacement mapping to transform the sub-patch specification and / or the control points into a digital rendering scene.

[0149] Now turning to Figure 8 , an example of a method 800 for generating sub-patches according to an embodiment is shown. The method 800 can be implemented as a module or related component in a set of logical instructions stored in a non-transitory machine or computer-readable storage medium such as random access memory (RAM), read-only memory (ROM), programmable ROM (PROM), firmware, flash memory, etc., in configurable logic such as, for example, a programmable logic array (PLA), a field-programmable gate array (FPGA), a complex programmable logic device (CPLD), or in fixed-function hardware logic using circuit technologies such as, for example, application-specific integrated circuit (ASIC), complementary metal-oxide semiconductor (CMOS), or transistor-transistor logic (TTL) technology or any combination thereof.

[0150] For example, the computer program code for performing the operations shown in method 800 can be written in any combination of one or more programming languages, including object-oriented programming languages such as JAVA, SMALLTALK, C++, etc., and conventional procedural programming languages such as the "C" programming language or similar programming languages. Additionally, the logical instructions can include assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, status-setting data, configuration data for an integrated circuit system, status information for personalizing an electronic circuit system, and / or other structural components native to the hardware (e.g., host processor, central processing unit / CPU, microcontroller, etc.).

[0151] The shown processing block 802 provides: generating sub - patches for tessellation for a subdivision surface associated with a patch. Each sub - patch may include a sub - patch tessellation factor. The tessellation factor may specify the number of segments into which one or more of the outer edges or the inner edges are to be divided. The sub - patch tessellation factor may identify the granularity of the tessellation of the sub - patch.

[0152] The outer - edge tessellation factors of adjacent sub - patches may use equal tessellation factors with each other to eliminate the gaps between the adjacent sub - patches. The shown processing block 804 provides: determining the granularity of the sub - patch tessellation based on the perspective projection of one or more of the patch or the sub - patches; and determining a transition region for connecting adjacent outer edges or inner edges to an irregular triangle strip. The patch and the sub - patches may identify one or more domains. Determining the granularity of the sub - patch tessellation provides: subdividing the one or more domains into triangular domains or quadrilateral domains. The patch and the sub - patches include outer edges and inner edges.

[0153] Block 806 provides: determining whether one of the patch or the sub - patches exhibits perspective distortion based on perspective projection. When one of the patch or the sub - patches exhibits perspective distortion based on perspective projection, the shown processing block 808 provides: diverging the size of the tessellation in the internal region of the one of the patch or the sub - patches based on the position of each of the tessellations within the patch or the sub - patch. One or more of the sub - patch parameters include one or more values identifying a starting sub - patch boundary and an ending sub - patch boundary. The patch and the sub - patches include one or more of a quadrilateral patch type or a triangular patch type.

[0154] The shown processing block 810 provides: generating a sub - patch tessellation of the sub - patch based on the sub - patch tessellation factor. Generating the sub - patch tessellation of the sub - patch based on the sub - patch tessellation factor provides geometric compression, while traditional fixed - function tessellation may limit the amount of data used to provide geometric compression.

[0155] Block 812 provides: generating values of sub - patch parameters and sub - patch specifications that identify sub - patch attributes in each dimension of an N - dimensional sub - patch based on the sub - patch tessellation. The sub - patch specification may include control points. A domain shader may use a displacement map to transform the sub - patch specification in order to generate a digital rendering scene.

[0156] Figure 9A and Figure 9B is a conceptual diagram of examples of tessellation sizes without perspective distortion 900 and with perspective distortion 950 according to an embodiment. Figure 9AShows a tessellation 902, which can be of a uniform size that does not have perspective distortion of the tessellation that might otherwise result in over- or under-tessellation.

[0157] However, as Figure 9B shown, under-tessellation 952 (e.g., occurring in the foreground of the surface) and / or over-tessellation 954 (e.g., occurring in one or more directions away from the foreground of the surface) can occur, for example, when patches and / or sub-patches are mapped to a larger screen area and / or undergo significant perspective distortion. Due to perspective projection, the size of triangles within the interior region can diverge from the target size based on the position of the tessellation (e.g., foreground or other position).

[0158] When a patch or sub-patch exhibits perspective distortion based on perspective projection, the hull shader kernel (e.g., as described with respect to Figure 6 the hull shader kernel 612 at ) can diverge the tessellation size to a configurable size within the interior region of the patch or sub-patch based on the position of each of the tessellations. The hull shader kernel may and / or may not allow an application (e.g., a developer using an API) to subdivide a triangle domain and / or a quadrilateral domain into sub-patches with separate tessellation factors. The hull shader kernel can output a variable list of sub-patch specifications for a given input patch, and a fixed-function tessellator can tessellate the variable list of sub-patch specifications into triangles (e.g., vertex data) in response to limiting and / or eliminating under-tessellation and / or over-tessellation.

[0159] Figure 10 Is a conceptual diagram of an example of a quadrilateral patch 1000 that is subdivided into sub-patches according to an embodiment. The hull shader kernel (e.g., as described with respect to Figure 6 the hull shader kernel 612 at ) can generate sub-patches and sub-patch tessellation factors for a subdivided surface associated with the patch. A hardware fixed-function tessellator can generate sub-patch tessellations of the sub-patches based on the sub-patch tessellation factors and generate sub-patch specifications based on the sub-patch tessellations.

[0160] The hull shader kernel can generate a very fine tessellation granularity in a sub-patch (e.g., the upper-right sub-patch), while generating a much coarser subdivision granularity in another sub-patch (e.g., the lower-left sub-patch). The remaining sub-patches can have an intermediate granularity, e.g., transitioning between sub-patches.

[0161] To specify the subdivision of a patch into sub-patches, a hull shader kernel may compute and output: one or more of outer edge tessellation factors to allow sharing of edges with adjacent patches without gaps (e.g., cracks); and a variable-length list of sub-patch parameters that specify sub-patch attributes in one or more of N directions of an N-dimensional domain. Each sub-patch parameter (e.g., sub-patch attribute) may include: values that specify a start sub-patch boundary and / or an end sub-patch boundary 1002, 1004, 1006 in one of the N directions of the N-dimensional domain; and a list of sub-patch parameters that specify a start sub-patch boundary and / or an end sub-patch boundary 1008, 1010, 1012 in another direction of the N-dimensional domain. The sub-patch specification may include control points. Traditionally, control points may be associated with an entire patch and / or shared across sub-patches.

[0162] The system (e.g., as described with respect to system 600 at Figure 6 ) may include a domain shader for converting the sub-patch specification into a digital rendered scene using displacement mapping. The hull shader kernel may generate values of sub-patch parameters that identify sub-patch attributes in each dimension of the N-dimensional sub-patch. One or more of the sub-patch parameters may include one or more values that identify a start sub-patch boundary and an end sub-patch boundary. The patch and the sub-patch may include one or more of quadrilateral patch types or triangle patch types. The patch and sub-patch may identify one or more domains. The hull shader kernel may subdivide the one or more domains into triangular domains or quadrilateral domains. The patch and the sub-patch may include outer edges and inner edges. The tessellation factor specifies the number of segments into which the outer edge or the inner edge of the sub-patch is to be divided.

[0163] The outer edge tessellation factors of adjacent sub-patches may use equal tessellation factors with each other to eliminate gaps (e.g., cracks) between the adjacent sub-patches. The hull shader kernel may determine a transition zone for connecting adjacent outer edges or inner edges to an irregular triangle strip. Compared with traditional systems, an adaptive sub-patch system may use adaptive tessellation granularity and / or a target triangle size (e.g., segment size) for each sub-patch based on one or more granularity factors to generate sub-patches for tessellation of one or more domains of a scene to be digitally rendered, the tessellation including textures of surfaces of objects in the scene.

[0164] Head-Mounted Display System Overview

[0165] Figure 11Shown is a head-mounted display (HMD) system 1100 worn by a user when experiencing an immersive environment, such as for example a virtual reality (VR) environment, an augmented reality (AR) environment, a multi-player three-dimensional (3D) game, etc. In the example shown, one or more straps 1120 hold the frame 1102 of the HMD system 1100 in front of the user's eyes. Accordingly, the left-eye display 1104 is positioned to be viewed by the user's left eye and the right-eye display 1106 is positioned to be viewed by the user's right eye. In some examples, such as for example a smart phone worn by the user, the left-eye display 1104 and the right-eye display 1106 may alternatively be integrated into a single display. In the case of AR, the displays 1104, 1106 may be see-through displays that allow the user to view the physical environment while other rendered content (e.g., virtual characters, informational annotations, heads-up display / HUD) is presented over a live feed of the physical environment.

[0166] In one example, the frame 1102 includes a lower-left looking camera 1108 to capture an image (e.g., a left hand gesture) from a region generally located in front of the user and below the left eye. Additionally, a lower-right looking camera 1110 may capture an image (e.g., a right hand gesture) from a region generally located in front of the user and below the right eye. The frame 1102 shown also includes a left-front looking camera 1112 and a right-front looking camera 1114 to capture images in front of the user's left and right eyes, respectively. The frame 1102 may also include a left-side looking camera 1116 to capture an image from a region to the left of the user and a right-side looking camera 1118 to capture an image from a region to the right of the user.

[0167] Images captured by the cameras 1108, 1110, 1112, 1114, 1116, 1118, which may have overlapping fields of view, may be used to detect gestures made by the user and to analyze the external environment and / or reproduce the external environment on the displays 1104, 1106. In one example, the detected gestures are used by a (e.g., internal and / or external) graphics processing architecture to render and / or control the virtual representation of the user in a 3D game. In fact, the overlapping fields of view may enable the capture of gestures made by other individuals (e.g., in a multi-player game), where the gestures of the other individuals may also be used to render / control the immersive experience. The overlapping fields of view may also enable the HMD system 1100 to automatically detect obstructions or other impairments near the user. Such methods are particularly advantageous in advanced driver assistance system (ADAS) applications.

[0168] In one example, the left-look camera 1108 and the right-look camera 1110, which provide overlapping fields of view, provide a stereoscopic view with increased resolution. The increased resolution can in turn enable very similar user movements to be distinguished from one another (e.g., with sub-millimeter accuracy). The result can be enhanced performance of the HMD system 1100 with respect to reliability. In fact, the demonstrated solution is useful in a variety of applications, such as, for example, coloring information in an AR setting, exchanging virtual tools / devices among multiple users in a multi-user environment, rendering virtual items (e.g., weapons, swords, people), etc. The postures of other objects, limbs, and / or body parts can also be detected and used to render / control the virtual environment. For example, signals from myelography, electroencephalogram, eye tracking, breathing or panting, hand movements, etc., can be tracked in real time, whether from the wearer or from other individuals in a shared environment. Images captured by the cameras 1108, 1110, 1112, 1114, 1116, 1118 can also be used as context inputs. For example, it may be determined that the user is indicating a specific word to be edited or a specific key to be pressed in a word processing application, a specific weapon to be deployed or a direction of travel in a game, etc.

[0169] In addition, images captured by the cameras 1108, 1110, 1112, 1114, 1116, 1118 can be used to implement shared communication or networked interaction in device operation, medical training, and / or remote / teloperational guidance applications. A task-specific posture library or neural network machine learning can enable tool identification and feedback on the task. For example, virtual tools that are converted into remote, real actions can be enabled. In yet another example, the HMD system 1100 converts the manipulation of a virtual drill within a virtual scene into the remote operation of a drill on a robotic device deployed for searching a collapsed building. Moreover, the HMD system 1100 can be programmable to the extent of including, for example, a protocol that enables the user to add new postures to a list of identifiable postures associated with the user's actions.

[0170] Additionally, the various cameras in the HMD 1100 can be configured to detect spectral frequencies outside the visible wavelengths of the spectrum. The multi-spectral imaging capabilities of the input cameras allow for the tracking of the position of the user and / or objects by eliminating non-essential image features (e.g., background noise). For example, in an augmented reality (AR) application such as surgery, instruments and devices are tracked by their infrared reflectivity without the need for additional tracking aids. Moreover, the HMD 1100 can be employed in low visibility situations, where the "live feeds" from the various cameras can be enhanced or augmented through computer analysis and presented to the user as visual or audio cues.

[0171] The HMD system 1100 can also forego performing any type of data communication with a remote computing system or that requires a power cord (e.g., standalone operation mode). In this regard, the HMD system 1100 can be a “cordless” device having a power unit that enables the HMD system 1100 to operate independently of an external power system. Accordingly, a user can play full-featured games without being tethered to another device (e.g., a game console) or a power source. In a word processing example, the HMD system 1100 presents a virtual keyboard and / or a virtual mouse on displays 1104 and 1106 to provide a virtual desktop or word processing scenario. Thus, the pose identification data captured by one or more of the cameras represents user typing activity on the virtual keyboard or movement of the virtual mouse. Advantages include, but are not limited to: portability and the privacy of the virtual desktop in isolating nearby individuals. The underlying graphics processing architecture can support compression and / or decompression of video and audio signals. Also, providing separate images to the user's left and right eyes can assist in the rendering, generation, and / or perception of 3D scenes. The relative positions of the left-eye display 1104 and the right-eye display 1106 can also be adjustable to match variations in the interocular distance between different users.

[0172] Figure 11 The number of cameras shown is only for illustrative purposes. In fact, depending on the environment, the HMD system 1100 can include fewer than six or more than six cameras.

[0173] Functional Components of the HMD System

[0174] Figure 12 The HMD system is shown in more detail. In the example shown, the frame 1102 includes a power unit 1200 (e.g., battery power, adapter) that supplies power to the HMD system. The frame 1102 shown also includes a motion tracking module 1220 (e.g., accelerometer, gyroscope), where the motion tracking module 1220 provides motion tracking data, orientation data, and / or position data to the processor system 1204. The processor system 1204 can include a network adapter 1224 coupled to an I / O bridge 1206. The I / O bridge 1206 can enable communication between the network adapter 1224 and various components such as, for example, an audio input module 1210, an audio output module 1208, a display device 1207, an input camera 1202, and so on.

[0175] In the example shown, the audio input module 1210 includes a right audio input 1218 and a left audio input 1216, which detect sounds that can be processed to identify voice commands of the user as well as nearby individuals. The voice commands identified in the captured audio signal can enhance pose identification during mode switching and other applications. Also, the captured audio signal can provide 3D information for enhancing the immersive experience.

[0176] The audio output module 1208 may include a right audio output 1214 and a left audio output 1212. The audio output module 1208 may deliver sound to the ears of the user and / or other nearby individuals. The audio output module 1208 may be in the form of earbuds, on-ear speakers, over-ear speakers, loudspeakers, etc. or any combination thereof, and the audio output module 1208 may deliver stereo and / or 3D audio content to the user (e.g., spatial localization). The illustrated frame 1102 also includes a wireless module 1222 that facilitates communication between the HMD system and various other systems (e.g., computers, wearable devices, game consoles). In one example, the wireless module 1222 communicates with the processor system 1204 via a network adapter 1224.

[0177] The illustrated display device 1207 includes a left-eye display 1104 and a right-eye display 1106, where the virtual content presented on the displays 1104, 1106 may be obtained from the processor system 1204 via the I / O bridge 1206. The input cameras 1202 may include the left-looking camera 1116, the right-looking camera 1118, the lower-left-looking camera 1108, the left-front-looking camera 1112, the right-front-looking camera 1114, and the lower-right-looking camera 1110 that have been discussed.

[0178] Now turning to Figure 13 , a general processing cluster (GPC) 1300 is shown. The illustrated GPC 1300 may be incorporated into a processing system such as, for example, the processor system 1204 ( Figure 12 ) that has been discussed. The GPC 1300 may include a pipeline manager 1302 that communicates with a scheduler. In one example, the pipeline manager 1302 receives tasks from the scheduler and distributes the tasks to one or more streaming multiprocessors (SMs) 1304. Each SM 1304 may be configured to process a thread group, where a thread group may be considered multiple related threads that perform the same or similar operations on different input data. Thus, each thread in the thread group may be assigned to a particular SM 1304. In another example, the number of threads may be greater than the number of execution units in the SM 1304. In this regard, multiple threads in the thread group may operate in parallel. The pipeline manager 1302 may also specify the destination of the processed data to a work distribution crossbar 1308 that communicates with a memory crossbar.

[0179] Thus, when each SM 1304 sends a processed task to the work distribution crossbar 1308, the processed task can be provided to another GPC 1300 for further processing. The output of the SM 1304 can also be sent to a pre-raster operation (preROP) unit 1314, which in turn directs data to one or more raster operation units or performs other operations (e.g., performing address translation, organizing picture color data, blending colors, etc.). The SM 1304 can include an internal first-level (L1) cache (not shown), where the SM 1304 can store data. The SM 1304 can also have access to a second-level (L2) cache (not shown) via a memory management unit (MMU) 1310 and a first-and-a-half-level (L1.5) cache 1306. The MMU 1310 can map virtual addresses to physical addresses. In this regard, the MMU 1310 can include page table entries (PTEs) that are used to map virtual addresses to the physical addresses of tiles, memory pages, and / or cache line indices. The illustrated GPU 1300 includes a texture unit 1312.

[0180] Graphics Pipeline Architecture

[0181] Turning now to Figure 14 , a graphics pipeline 1400 is shown. In the illustrated example, the world space pipeline 1420 includes a primitive distributor (PD) 1402. The PD 1402 can collect vertex data associated with high-order services, graphics primitives, triangles, etc., and send the vertex data to a vertex attribute fetcher (VAF) 1404. The VAF 1404 can obtain vertex attributes associated with each incoming vertex from shared memory and store the vertex data and the associated vertex attributes together in shared memory.

[0182] The illustrated world space pipeline 1420 also includes a vertex, tessellation, geometry processing unit (VTG) 1406. The VTG 1406 can include, for example, a vertex processing unit, a tessellation initialization processing unit, a task distributor, a task generator, a topology generator, a geometry processing unit, a tessellation processing unit, etc., or any combination thereof. In one example, the VTG 1406 is a programmable execution unit configured to execute geometry programs, tessellation programs, and vertex shader programs. The programs executed by the VTG 1406 can process the vertex data and vertex attributes received from the VAF 1404. Moreover, the programs executed by the VTG 1406 can produce graphics primitives, color values, surface normal factors, and transparency values at each vertex of the graphics primitives for further processing within the graphics processing pipeline 1400.

[0183] The vertex processing unit of VTG 1406 can be a programmable execution unit that executes a vertex shader program to illuminate and transform vertex data as specified by the vertex shader program. For example, the vertex processing unit can be programmed to transform vertex data from an object-based coordinate representation (e.g., object space) to an alternative coordinate system-based representation such as world space or normalized device coordinate (NDC) space. Additionally, the vertex processing unit can read vertex data and vertex attributes stored in shared memory by VAF 1404 and process the vertex data and vertex attributes. In one example, the vertex processing unit stores the processed vertices in shared memory.

[0184] The tessellation initialization processing unit (e.g., hull shader, tessellation control shader) can execute a tessellation initialization shader program. In one example, the tessellation initialization processing unit processes the vertices generated by the vertex processing unit and generates graphics primitives sometimes referred to as "patches". The tessellation initialization processing unit can also generate various patch attributes, where the patch data and patch attributes are stored in shared memory. The task generation unit of VTG 1406 can obtain the data and attributes of vertices and patches from shared memory. In one example, the task generation unit generates tasks for processing vertices and patches for later stages in the graphics processing pipeline 1400.

[0185] The tasks generated by the task generation unit can be redistributed by the task distributor of VTG 1406. For example, the tasks generated by various instances of the vertex shader program and the tessellation initialization program can vary significantly between one graphics processing pipeline 1400 and another. Accordingly, the task distributor can redistribute these tasks so that each graphics processing pipeline 1400 has an almost identical workload at later pipeline stages.

[0186] As already discussed, VTG 1406 can also include a topology generation unit. In one example, the topology generation unit obtains the tasks distributed by the task distributor, indexes the vertices including those associated with the patches, and calculates the coordinates (UV) of the tessellation vertices and the indexes that connect the tessellation vertices to form graphics primitives. The indexed vertices can be stored in shared memory by the topology generation unit. The tessellation processing unit of VTG 1406 can be configured to execute a tessellation shader program (e.g., domain shader, tessellation evaluation shader). The tessellation processing unit can read input data from shared memory and write output data to shared memory. The output data can be passed from shared memory to the geometry processing unit (e.g., the next shader stage) as input data.

[0187] The geometry processing unit of VTG 1406 can execute a geometry shader program to transform graphics primitives (e.g., triangles, line segments, points, etc.). In one example, vertices are grouped to construct graphics primitives, where the geometry processing unit subdivides the graphics primitives into one or more new graphics primitives. The geometry processing unit can also compute parameters such as, for example, the plane equation coefficients that can be used to rasterize the new graphics primitives.

[0188] The shown world space pipeline 1420 also includes a viewport scaling, culling, and clipping unit (VPC) 1408 that obtains from the VTG 1406 the parameters and vertices that define the new graphics primitives. In one example, the VPC 1408 performs clipping, flanging, perspective correction, and viewport transformation to identify the graphics primitives that can potentially be viewed in the final rendered image. The VPC 1408 can also identify the graphics primitives that may not be viewable.

[0189] The graphics processing pipeline 1400 can also include a tiling unit 1410 coupled to the world space pipeline 1420. The tiling unit 1410 can be a graphics primitive sorting engine, where the graphics primitives are processed in the world space pipeline 1420 and then sent to the tiling unit 1410. In this regard, the graphics processing pipeline 1400 can also include a screen space pipeline 1422, where the screen space can be divided into cache tiles. Each cache tile can thus be associated with a portion of the screen space. For each graphics primitive, the tiling unit 1410 can identify a set of cache tiles that intersect (e.g., tile) the graphics primitive. After tiling several graphics primitives, the tiling unit 1410 can process the graphics primitives tile by cache tile. In one example, the graphics primitives associated with a particular cache tile are sent one tile at a time to a setup unit 1412 in the screen space pipeline 1422. Graphics primitives that intersect multiple cache tiles can be processed once in the world space pipeline 1420 and sent to the screen space pipeline 1422 multiple times.

[0190] In one example, the setup unit 1412 receives vertex data from the VPC 1408 via the tiling unit 1410 and computes the parameters associated with the graphics primitives. The parameters can include, for example, edge equations, bias plane equations, and depth plane equations. The screen space pipeline 1422 can also include a rasterizer 1414 coupled to the setup unit 1412. The rasterizer can scan convert the new graphics primitives and send fragment and coverage data to a pixel shader unit (PS) 1416. The rasterizer 1414 can also perform Z-culling and other Z-based optimizations.

[0191] The PS 1416 that can access the shared memory can execute a fragment shader program that transforms the fragments received from the rasterizer 1414. More specifically, the fragment shader program can shade the fragments at the pixel-level granularity (e.g., work as a pixel shader program). In another example, the fragment shader program shades the fragments at the sample-level granularity, where each pixel includes multiple samples and each sample represents a part of the pixel. Moreover, depending on the environment (e.g., sampling rate), the fragment shader program can shade the fragments at any other granularity. The PS 1416 can execute operations such as blending, shading, perspective correction, texture mapping, etc. to generate shaded fragments.

[0192] The shown screen space pipeline 1422 also includes a raster operation unit (ROP) 1418, which can execute operations such as stencil printing, Z-testing, blending, etc. The ROP 1418 can then send the pixel data as processed graphics data to one or more rendered targets (e.g., graphics memory). The ROP 1418 can be configured to compress the Z or color data written to the memory and decompress the Z or color data read from the memory. The position of the ROP 1418 can vary depending on the environment.

[0193] The graphics processing pipeline 1400 can be implemented by one or more processing elements. For example, the VTG 1406 and / or the PS 1416 can be implemented in one or more SMs, and the PD 1402, VAF 1408, tiling unit 1410, setup unit 1412, rasterizer 1414, and / or ROP 1418 can be implemented in the processing elements of a specific GPC in combination with the corresponding partition unit. The graphics processing pipeline 1400 can also be implemented in fixed-function hardware logic. In fact, the graphics processing pipeline 1400 can be implemented in a PPU.

[0194] Therefore, the shown world space pipeline 1420 processes the graphic objects in the 3D space, where the position of each graphic object relative to other graphic objects and relative to the 3D coordinate system is known. In contrast, the screen space pipeline 1422 can process the graphic objects that have been projected from the 3D coordinate system onto the 2D planar surface representing the surface of the display device. Additionally, the world space pipeline 1420 can be divided into an α-stage pipeline and a β-stage pipeline, where the α-stage pipeline includes the pipeline levels from the PD 1402 until the task generation unit. The β-stage pipeline includes the pipeline levels from the topology generation unit until the VPC 1408. In such a case, the graphics processing pipeline 1400 can execute a first set of operations (e.g., a single thread, a thread group, multiple thread groups acting in unison) in the α-stage pipeline and a second set of operations (e.g., a single thread, a thread group, multiple thread groups acting in unison) in the β-stage pipeline.

[0195] If multiple graphics pipelines 1400 are in use, vertex data and vertex attributes associated with a set of graphics objects can be partitioned so that each graphics processing pipeline 1400 has a similar workload throughout the alpha stage. Accordingly, the alpha stage processing can substantially expand the number of vertex data and vertex attributes, such that the number of vertex data and vertex attributes generated by the task generation unit is significantly greater than the number of vertex data and vertex attributes processed by the PD 1402 and the VAF 1404. Moreover, task generation units associated with different graphics processing pipelines 1400 can generate vertex data and vertex attributes with different quality levels, even when starting the alpha stage with the same number of attributes. In such a case, the task distributor can redistribute the attributes generated by the alpha stage pipeline so that each graphics processing pipeline 1400 has a roughly equal workload at the start of the beta stage pipeline.

[0196] Turning now to Figure 15 , a streaming multi-processor (SM) 1500 is shown. The illustrated SM 1500 includes a K scheduler unit 1504 coupled to an instruction cache 1502, where each scheduler unit 1504 receives an array of thread blocks from a pipeline manager (not shown) and manages the instruction scheduling for one or more thread blocks in each active thread block array. The scheduler unit 1504 can schedule threads for execution in parallel thread groups, where each group can be referred to as a "warp". Thus, each warp may include, for example, 64 threads. Additionally, the scheduler unit 1504 can manage multiple different thread blocks, allocating the thread blocks to warps for execution. The scheduler unit can then schedule instructions from multiple different warps on various functional units during each clock cycle. Each scheduler unit 1504 can include one or more instruction dispatch units 1522, where each dispatch unit 1522 sends instructions to one or more of the functional units. The number of dispatch units 1522 can vary depending on the environment. In the illustrated example, the scheduler unit 1504 includes two dispatch units 1522 that enable two different instructions from the same warp to be pending dispatch during each clock cycle.

[0197] The SM 1500 may also include a register file 1506. The register file 1506 includes a set of registers that are partitioned among the functional units such that each functional unit is assigned a dedicated portion of the register file 1506. The register file 1506 may also be partitioned among different warps being executed by the SM 1500. In one example, the register file 1506 provides temporary storage for operands of data paths connected to the functional units. The illustrated SM 1500 also includes L processing cores 1508, where L may be a relatively large number (e.g., 192). Each core 1508 may be a pipelined single-precision processing unit that includes a floating-point arithmetic logic unit (e.g., IEEE 754-2008) and an integer arithmetic logic unit.

[0198] The illustrated SM 1500 also includes M double-precision units (DPUs) 1510, N special function units (SFUs) 1512, and P load / store units (LSUs) 1514. Each DPU 1510 may implement double-precision floating-point arithmetic and each SFU 1512 may perform special functions such as, for example, rectangle copy pixel blend. Additionally, each LSU 1514 may perform load and store operations between the shared memory 1518 and the register file 1506. In one example, the load and store operations are performed via J texture units / L1 caches 1520 and an interconnect network 1516. In one example, the J texture units / L1 caches 1520 are also coupled to a crossbar switch (not shown). Thus, the interconnect network 1516 may connect each of the functional units to the register file 1506 and the shared memory 1518. In one example, the interconnect network 1516 serves as a crossbar switch that connects any one of the functional units to any register in the register file 1506.

[0199] The SM 1500 may be implemented within a graphics processor (e.g., a graphics processing unit / GPU), where the texture unit / L1 cache 1520 may access texture maps from memory and sample the texture maps to produce sampled texture values for use in shader programs. Texture operations performed by the texture unit / L1 cache include, but are not limited to, mipmap-based anti-aliasing.

[0200] Additional System Overview Examples

[0201] Figure 16FIG. 1600 is a block diagram of a processing system 1600 according to an embodiment. In various embodiments, system 1600 includes one or more processors 1602 and one or more graphics processors 1608, and may be a single-processor desktop computer system, a multi-processor workstation system, or a server system having a large number of processors 1602 or processor cores 1607. In one embodiment, system 1600 is a processing platform included in a system-on-chip (SoC) for use in a mobile device, a handheld device, or an embedded device.

[0202] Embodiments of system 1600 may include or may be included within: a server-based gaming platform, a game console (including a game and media console), a mobile game console, a handheld game console, or an online game console. In some embodiments, system 1600 is a mobile phone, a smartphone, a tablet computing device, or a mobile Internet device. Data processing system 1600 may also include, be coupled to, or be integrated within: wearable devices such as smartwatch wearable devices, smart glass devices, augmented reality devices, or virtual display devices. In some embodiments, data processing system 1600 is a television or set-top box device having one or more processors 1602 and a graphics interface generated by one or more graphics processors 1608.

[0203] In some embodiments, each of the one or more processors 1602 includes one or more processor cores 1607 for processing instructions that, when executed, perform the operations of system and user software. In some embodiments, each of the one or more processor cores 1607 is configured to process a specific instruction set 1609. In some embodiments, instruction set 1609 may facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction words (VLIW). Multiple processor cores 1607 may each process a different instruction set 1609, which may include instructions for facilitating the emulation of other instruction sets. Processor cores 1607 may also include other processing devices such as a digital signal processor (DSP).

[0204] In some embodiments, the processor 1602 includes a cache memory 1604. Depending on the architecture, the processor 1602 may have a single internal cache or multiple levels of internal caches. In some embodiments, the cache memory is shared among various components of the processor 1602. In some embodiments, the processor 1602 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC) (not shown), and the external cache can be shared among the processor cores 1607 using known cache coherence techniques. A register file 1606 is further included in the processor 1602, and the register file may include different types of registers for storing different types of data (e.g., integer registers, floating point registers, status registers, and instruction pointer registers). Some registers may be general-purpose registers, while other registers may be specific to the design of the processor 1602.

[0205] In some embodiments, the processor 1602 is coupled to a processor bus 1610 to transfer communication signals (such as address, data, or control signals) between the processor 1602 and other components in the system 1600. In one embodiment, the system 1600 uses an exemplary 'hub' system architecture, including a memory controller hub 1616 and an input / output (I / O) controller hub 1630. The memory controller hub 1616 facilitates communication between the memory device and other components of the system 1600, while the I / O controller hub (ICH) 1630 provides connections to I / O devices via a local I / O bus. In one embodiment, the logic of the memory controller hub 1616 is integrated within the processor.

[0206] The memory device 1620 can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or some other memory device with suitable performance to act as a process memory. In one embodiment, the memory device 1620 can operate as the system memory of the system 1600 to store data 1622 and instructions 1621 for use when one or more processors 1602 execute an application or a process. The memory controller hub 1616 is also coupled to an optional external graphics processor 1612, and the external graphics processor can be coupled to the graphics processor 1608 in the processor 1602 to perform graphics and media operations.

[0207] In some embodiments, the ICH 1630 enables peripheral devices to be connected to the memory device 1620 and the processor 1602 via a high-speed I / O bus. The I / O peripheral devices include, but are not limited to: an audio controller 1646, a firmware interface 1628, a wireless transceiver 1626 (e.g., Wi-Fi, Bluetooth), a data storage device 1624 (e.g., a hard disk drive, a flash memory, etc.), and a legacy I / O controller 1640 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system. One or more Universal Serial Bus (USB) controllers 1642 connect input devices (such as a keyboard and mouse 1644 combination). A network controller 1634 may also be coupled to the ICH 1630. In some embodiments, a high-performance network controller (not shown) is coupled to the processor bus 1610. It will be appreciated that the system 1600 shown is exemplary and not restrictive, as other types of data processing systems configured in different ways may also be used. For example, the I / O controller hub 1630 may be integrated within the one or more processors 1602, or the memory controller hub 1616 and the I / O controller hub 1630 may be integrated within a discrete external graphics processor (such as the external graphics processor 1612).

[0208] Figure 17 is a block diagram of an embodiment of a processor 1700 having one or more processor cores 1702A through 1702N, an integrated memory controller 1714, and an integrated graphics processor 1708. Figure 17 Those elements in [a figure] having the same reference numbers (or names) as elements in any other figure herein may operate or function in any manner similar to the ways described elsewhere herein, but are not limited thereto. The processor 1700 may include additional cores up to and including the additional core 1702N represented by the dashed box. Each of the processor cores 1702A through 1702N includes one or more internal cache units 1704A through 1704N. In some embodiments, each processor core is also capable of accessing one or more shared cache units 1706.

[0209] The internal cache units 1704A through 1704N and the shared cache units 1706 represent the cache memory hierarchy within the processor 1700. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of a shared intermediate-level cache (such as a level 2 (L2), level 3 (L3), level 4 (L4), or other level cache), where the highest-level cache in front of the external memory is classified as the LLC. In some embodiments, cache coherence logic maintains coherence between the various cache units 1706 and 1704A through 1704N.

[0210] In some embodiments, the processor 1700 may further include a set of one or more bus controller units 1716 and a system agent core 1710. The one or more bus controller units 1716 manage a set of peripheral buses, such as one or more Peripheral Component Interconnect buses (e.g., PCI, PCI Express buses). The system agent core 1710 provides management functions for various processor components. In some embodiments, the system agent core 1710 includes one or more integrated memory controllers 1714 for managing access to various external memory devices (not shown).

[0211] In some embodiments, one or more of the processor cores 1702A to 1702N include support for simultaneous multithreading. In such embodiments, the system agent core 1710 includes components for coordinating and operating the cores 1702A to 1702N during multithreaded processing. The system agent core 1710 may additionally include a Power Control Unit (PCU) that includes logic and components for regulating the power states of the processor cores 1702A to 1702N and the graphics processor 1708.

[0212] In some embodiments, the processor 1700 additionally includes a graphics processor 1708 for performing graphics processing operations. In some embodiments, the graphics processor 1708 is coupled with a set of shared cache units 1706 and the system agent core 1710 includes one or more integrated memory controllers 1714. In some embodiments, a display controller 1711 is coupled with the graphics processor 1708 to drive the graphics processor output to one or more coupled displays. In some embodiments, the display controller 1711 may be a separate module coupled to the graphics processor via at least one interconnect, or may be integrated within the graphics processor 1708 or the system agent core 1710.

[0213] In some embodiments, a ring-based interconnect unit 1712 is used to couple the internal components of the processor 1700. However, alternative interconnect units, such as point-to-point interconnects, switched interconnects, or other techniques, including those well known in the art, may be used. In some embodiments, the graphics processor 1708 is coupled to the ring interconnect 1712 via an I / O link 1713.

[0214] The exemplary I / O link 1713 represents at least one of a variety of I / O interconnects, including an on-package I / O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 1718, such as an eDRAM module. In some embodiments, each of the processor cores 1702 to 1702N and the graphics processor 1708 use the embedded memory module 1718 as a shared last-level cache.

[0215] In some embodiments, processor cores 1702A through 1702N are homogeneous cores that execute the same instruction set architecture. In another embodiment, processor cores 1702A through 1702N are heterogeneous with respect to instruction set architecture (ISA), where one or more of processor cores 1702A through 1702N execute a first instruction set and at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, processor cores 1702A through 1702N are heterogeneous with respect to microarchitecture, where one or more cores with relatively higher power consumption are coupled with one or more power cores with lower power consumption. Additionally, processor 1700 may be implemented on one or more chips or as a System-on-Chip (SoC) integrated circuit having the components shown in addition to other components.

[0216] Figure 18 is a block diagram of a graphics processor 1800, which may be a discrete graphics processing unit or may be a graphics processor integrated with multiple processing cores. In some embodiments, the graphics processor communicates with memory via a mapped I / O interface to registers on the graphics processor and using commands placed in processor memory. In some embodiments, graphics processor 1800 includes a memory interface 1814 for accessing memory. Memory interface 1814 may be an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory.

[0217] In some embodiments, graphics processor 1800 further includes a display controller 1802 for driving display output data to a display device 1820. Display controller 1802 includes hardware for one or more overlapping planes of a display and the composition of multi-layer video or user interface elements. In some embodiments, graphics processor 1800 includes a video codec engine 1806 for encoding, decoding, or trans-coding media between one or more media coding formats, including but not limited to: Moving Picture Experts Group (MPEG) formats such as MPEG-2, Advanced Video Coding (AVC) formats such as H.264 / MPEG-4 AVC, and Society of Motion Picture and Television Engineers (SMPTE) 421M / VC-1, and Joint Photographic Experts Group (JPEG) formats such as JPEG and Motion JPEG (MJPEG) formats.

[0218] In some embodiments, the graphics processor 1800 includes a block image transfer (BLIT) engine 1804 for performing two-dimensional (2D) rasterizer operations, such as bit boundary block transfers. However, in one embodiment, one or more components of the graphics processing engine (GPE) 1810 are used to perform 2D graphics operations. In some embodiments, the graphics processing engine 1810 is a computing engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0219] In some embodiments, the GPE 1810 includes a 3D pipeline 1812 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions for 3D primitive shapes (e.g., rectangles, triangles, etc.). The 3D pipeline 1812 includes programmable and fixed-function elements that perform various tasks in the elements and / or generated execution threads to the 3D / media subsystem 1815. Although the 3D pipeline 1812 can be used to perform media operations, embodiments of the GPE 1810 also include a media pipeline 1816 specifically for performing media operations, such as video post-processing and image enhancement.

[0220] In some embodiments, the media pipeline 1816 includes fixed-function or programmable logic units for performing one or more specialized media operations in place of or on behalf of the video codec engine 1806, such as video decoding acceleration, video deinterlacing, and video encoding acceleration. In some embodiments, the media pipeline 1816 further includes a thread generation unit to generate threads for execution on the 3D / media subsystem 1815. The generated threads perform computations for media operations on one or more graphics execution units included in the 3D / media subsystem 1815.

[0221] In some embodiments, the 3D / media subsystem 1815 includes logic for executing the threads generated by the 3D pipeline 1812 and the media pipeline 1816. In one embodiment, the pipeline sends thread execution requests to the 3D / media subsystem 1815, which includes thread dispatch logic for arbitrating and dispatching the requests to available thread execution resources. The execution resources include an array of graphics execution units for processing 3D and media threads. In some embodiments, the 3D / media subsystem 1815 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory (including registers and addressable memory) for sharing data between threads and storing output data.

[0222] 3D / Media Processing

[0223] Figure 19 is a block diagram of a graphics processing engine 1910 of a graphics processor according to some embodiments. In one embodiment, the GPE 1910 is Figure 18 a version of the GPE 1810 shown in Figure 19 Elements having the same reference numbers (or names) as elements in any other figure herein may operate or function in any manner similar to the manner described elsewhere herein, but are not limited thereto.

[0224] In some embodiments, the GPE 1910 is coupled to a command stream converter 1903 that provides a command stream to a 3D pipeline 1912 and a media pipeline 1916 of the GPE. In some embodiments, the command stream converter 1903 is coupled to a memory, which may be a system memory or one or more of an internal cache memory and a shared cache memory. In some embodiments, the command stream converter 1903 receives commands from the memory and sends the commands to the 3D pipeline 1912 and / or the media pipeline 1916. The commands are instructions fetched from a ring buffer storing commands for the 3D pipeline 1912 and the media pipeline 1916. In one embodiment, the ring buffer may additionally include a batch command buffer storing multiple batches of multiple commands. The 3D pipeline 1912 and the media pipeline 1916 process the commands by performing operations via logic within their respective pipelines or by dispatching one or more execution threads to an execution unit array 1914. In some embodiments, the execution unit array 1914 is scalable such that the array includes a variable number of execution units based on the target power and performance levels of the GPE 1910.

[0225] In some embodiments, a sampling engine 1930 is coupled to a memory (e.g., a cache memory or a system memory) and the execution unit array 1914. In some embodiments, the sampling engine 1930 provides a memory access mechanism for the execution unit array 1914 that allows the execution array 1914 to read graphics and media data from the memory. In some embodiments, the sampling engine 1930 includes logic for performing specialized image sampling operations for media.

[0226] In some embodiments, the specialized media sampling logic in the sampling engine 1930 includes a denoising / deinterleaving module 1932, a motion estimation module 1934, and an image scaling and filtering module 1936. In some embodiments, the denoising / deinterleaving module 1932 includes logic for performing one or more of a denoising or deinterleaving algorithm on the decoded video data. The deinterleaving logic combines the alternating fields of the interleaved video content into a single frame of the video. The denoising logic reduces or removes data noise from the video and image data. In some embodiments, the denoising and deinterleaving logic is motion adaptive and uses spatial or temporal filtering based on the amount of motion detected in the video data. In some embodiments, the denoising / deinterleaving module 1932 includes specialized motion detection logic (e.g., within the motion estimation engine 1934).

[0227] In some embodiments, the motion estimation engine 1934 provides hardware acceleration for video operations by performing video acceleration functions (such as motion vector estimation and prediction) on the video data. The motion estimation engine determines motion vectors that describe the transformation of image data between consecutive video frames. In some embodiments, the graphics processor media codec uses the video motion estimation engine 1934 to perform operations on macroblock-level video that would otherwise be too computationally intensive to perform using a general-purpose processor. In some embodiments, the motion estimation engine 1934 is generally available to the graphics processor components to assist with video decoding and processing functions that are sensitive or adaptive to the direction or magnitude of motion within the video data.

[0228] In some embodiments, the image scaling and filtering module 1936 performs image processing operations to improve the visual quality of the resulting images and videos. In some embodiments, the scaling and filtering module 1936 processes the image and video data during the sampling operation before providing the data to the execution unit array 1914.

[0229] In some embodiments, GPE 1910 includes a data port 1944 that provides an additional mechanism for the graphics subsystem to access memory. In some embodiments, data port 1944 facilitates memory access for operations including render target writes, constant buffer reads, temporary memory space reads / writes, and media surface access. In some embodiments, data port 1944 includes a cache memory space for caching access to memory. The cache memory can be a single data cache or separated into multiple caches for multiple subsystems accessing memory via the data port (e.g., render buffer cache, constant buffer cache, etc.). In some embodiments, threads executing on execution units in execution unit array 1914 communicate with the data port by exchanging messages via a data distribution interconnect that couples each subsystem of GPE 1910.

[0230] Execution Unit

[0231] Figure 20 is a block diagram of another embodiment of graphics processor 2000. Figure 20 Elements having the same reference numbers (or names) as elements in any other figure herein can operate or function in any manner similar to the ways described elsewhere herein, but are not limited thereto.

[0232] In some embodiments, graphics processor 2000 includes a ring interconnect 2002, a pipeline front end 2004, a media engine 2037, and graphics cores 2080A through 2080N. In some embodiments, ring interconnect 2002 couples the graphics processor to other processing units, including other graphics processors or one or more general processor cores. In some embodiments, the graphics processor is one of multiple processors integrated within a multi-core processing system.

[0233] In some embodiments, the graphics processor 2000 receives multiple batches of commands via a ring interconnect 2002. The incoming commands are translated by a command stream converter 2003 in a pipeline front end 2004. In some embodiments, the graphics processor 2000 includes scalable execution logic for performing 3D geometry processing and media processing via graphics cores 2080A through 2080N. For 3D geometry processing commands, the command stream converter 2003 supplies the commands to a geometry pipeline 2036. For at least some media processing commands, the command stream converter 2003 supplies the commands to a video front end 2034, which is coupled to a media engine 2037. In some embodiments, the media engine 2037 includes a video quality engine (VQE) 2030 for video and image post-processing and a multi-format encoding / decoding (MFX) 2033 engine for providing hardware-accelerated encoding and decoding of media data. In some embodiments, each of the geometry pipeline 2036 and the media engine 2037 generates execution threads for thread execution resources provided by at least one graphics core 2080A.

[0234] In some embodiments, the graphics processor 2000 includes scalable thread execution resources characterized by modular cores 2080A through 2080N (sometimes referred to as core slices), each modular core having multiple sub-cores 2050A through 2050N, 2060A through 2060N (sometimes referred to as corelets). In some embodiments, the graphics processor 2000 can have any number of graphics cores 2080A through 2080N. In some embodiments, the graphics processor 2000 includes a graphics core 2080A that has at least a first sub-core 2050A and a second sub-core 2060A. In other embodiments, the graphics processor is a low-power processor having a single sub-core (e.g., 2050A). In some embodiments, the graphics processor 2000 includes multiple graphics cores 2080A through 2080N, each graphics core including a set of first sub-cores 2050A through 2050N and a set of second sub-cores 2060A through 2060N. Each sub-core in the set of first sub-cores 2050A through 2050N includes at least a first set of execution units 2052A through 2052N and media / texture samplers 2054A through 2054N. Each sub-core in the set of second sub-cores 2060A through 2060N includes at least a second set of execution units 2062A through 2062N and samplers 2064A through 2064N. In some embodiments, each of the sub-cores 2050A through 2050N, 2060A - 2060N shares a set of shared resources 2070A through 2070N. In some embodiments, these shared resources include shared cache memory and pixel operation logic. Other shared resources may also be included in various embodiments of the graphics processor.

[0235] Figure 21Shows thread-executable logic 2100, including an array of processing elements employed in some embodiments of the GPE. Figure 21 Those elements having the same reference numbers (or names) as elements in any other figure herein may operate or function in any manner similar to the ways described elsewhere herein, but are not limited thereto.

[0236] In some embodiments, thread-executable logic 2100 includes a pixel shader 2102, a thread dispatcher 2104, an instruction cache 2106, a scalable array of execution units, including a plurality of execution units 2108A through 2108N, a sampler 2110, a data cache 2112, and a data port 2114. In one embodiment, the included components are interconnected via an interconnect structure that links to each of these components. In some embodiments, thread-executable logic 2100 includes one or more connections to memory (such as system memory or cache memory) via instruction cache 2106, data port 2114, sampler 2110, and one of execution unit arrays 2108A through 2108N. In some embodiments, each execution unit (e.g., 2108A) is an individual vector processor capable of executing multiple simultaneous threads and processing multiple data elements in parallel for each thread. In some embodiments, execution unit arrays 2108A through 2108N include any number of individual execution units.

[0237] In some embodiments, execution unit arrays 2108A through 2108N are primarily used to execute "shader" programs. In some embodiments, the execution units in arrays 2108A through 2108N execute an instruction set that includes native support for many standard 3D graphics shader instructions, such that shader programs from graphics libraries (e.g., Direct3D and OpenGL) are executed with minimal translation. The execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general-purpose processing (e.g., compute and media shaders).

[0238] Each execution unit in execution unit arrays 2108A through 2108N operates on an array of data elements. The number of data elements is the "execution size" or the number of channels for an instruction. Execution channels are logical execution units for data element access, masking, and flow control within an instruction. The number of channels may be independent of the number of physical arithmetic logic units (ALUs) or floating-point units (FPUs) for a particular graphics processor. In some embodiments, execution units 2108A through 2108N support integer and floating-point data types.

[0239] The execution unit instruction set includes single instruction multiple data (SIMD). Various data elements can be stored in registers as compressed data types, and the execution unit processes these elements based on the data sizes of the various elements. For example, when operating on a 256-bit wide vector, the 256-bit vector is stored in a register, and the execution unit operates on the vector as four separate 64-bit compressed data elements (quad-word (QW) sized data elements), eight separate 32-bit compressed data elements (double-word (DW) sized data elements), sixteen separate 16-bit compressed data elements (word (W) sized data elements), or thirty-two separate 8-bit data elements (byte (B) sized data elements). However, different vector widths and register sizes are possible.

[0240] One or more internal instruction caches (e.g., 2106) are included in the thread execution logic 2100 to cache thread instructions for the execution unit. In some embodiments, one or more data caches (e.g., 2112) are included for caching thread data during thread execution. In some embodiments, a sampler 2110 is included for providing texture sampling for 3D operations and media sampling for media operations. In some embodiments, the sampler 2110 includes specialized texture or media sampling functions to process texture or media data during the sampling process before providing the sampled data to the execution unit.

[0241] During execution, the graphics pipeline and the media pipeline send thread initiation requests to the thread execution logic 2100 via the thread generation and dispatch logic. In some embodiments, the thread execution logic 2100 includes a local thread dispatcher 2104 that arbitrates thread initiation requests from the graphics pipeline and the media pipeline and instantiates the requested threads on one or more execution units 2108A through 2108N. For example, the geometry pipeline (e.g., Figure 20 2036) dispatches vertex processing, tessellation, or geometry processing threads to the thread execution logic 2100 ( Figure 21 ). In some embodiments, the thread dispatcher 2104 can also process runtime thread generation requests from executing shader programs.

[0242] Once a set of geometric objects has been processed and rasterized into pixel data, the pixel shader 2102 is invoked to further compute output information and cause the results to be written to an output surface (e.g., a color buffer, a depth buffer, a stencil buffer, etc.). In some embodiments, the pixel shader 2102 computes values for vertex attributes that are interpolated across the rasterized objects. In some embodiments, the pixel shader 2102 then executes a pixel shader program supplied by an application programming interface (API). To execute the pixel shader program, the pixel shader 2102 dispatches threads to execution units (e.g., 2108A) via a thread dispatcher 2104. In some embodiments, the pixel shader 2102 uses texture sampling logic in a sampler 2110 to access texture data in a texture map stored in memory. Arithmetic operations on the texture data and the input geometry compute pixel color data for each geometric fragment, or discard one or more pixels for further processing.

[0243] In some embodiments, the data port 2114 provides a memory access mechanism for enabling the thread execution logic 2100 to output processed data to memory for processing on a graphics processor output pipeline. In some embodiments, the data port 2114 includes or is coupled to one or more cache memories (e.g., the data cache 2112) to cache data via the data port for memory access.

[0244] Figure 22 is a block diagram of a graphics processor instruction format 2200 according to some embodiments. In one or more embodiments, a graphics processor execution unit supports an instruction set having instructions of multiple formats. Solid boxes show components that are typically included in execution unit instructions, while the dashed boxes include optional or components that are only included in a subset of the instructions. In some embodiments, the described and shown instruction format 2200 is a macro-instruction as they are instructions supplied to the execution unit, as opposed to micro-operations generated from instruction decoding (once the instruction is processed).

[0245] In some embodiments, the graphics processor execution unit natively supports instructions in a 128-bit format 2210. A 64-bit compact instruction format 2230 may be used for some instructions based on the selected instruction, instruction options, and number of operands. The native 128-bit format 2210 provides access to all instruction options, while some options and operations are restricted in the 64-bit format 2230. The native instructions available in the 64-bit format 2230 vary according to embodiments. In some embodiments, a set of index values in an index field 2213 is used to partially compact the instruction. The execution unit hardware references a set of compression tables based on these index values and uses the compression table output to reconstruct the native instruction in the 128-bit format 2210.

[0246] For each format, the instruction opcode 2212 defines the operation to be performed by the execution unit. The execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an add instruction, the execution unit performs a simultaneous addition operation across each color channel representing a texture element or a picture element. By default, the execution unit executes each instruction across all data channels of the operand. In some embodiments, the instruction control field 2214 enables control of certain execution options, such as channel selection (e.g., predication) and data channel ordering (e.g., mixing). For 128-bit instructions 2210, the execution size field 2216 limits the number of data channels to be executed in parallel. In some embodiments, the execution size field 2216 is not available for 64-bit compact instruction formats 2230.

[0247] Some execution unit instructions have up to three operands, including two source operands src0 2220, src1 2222, and one destination 2218. In some embodiments, the execution unit supports dual-destination instructions, where one of the destinations is implicit. Data manipulation instructions may have a third source operand (e.g., SRC2 2224), where the instruction opcode 2212 determines the number of source operands. The last source operand of the instruction may be an immediate (e.g., hard-coded) value passed by the instruction.

[0248] In some embodiments, the 128-bit instruction format 2210 includes access / address mode information 2226 that specifies (e.g.) whether to use direct register addressing mode or indirect register addressing mode. When using direct register addressing mode, the register addresses of one or more operands are provided directly by bits in the instruction 2210.

[0249] In some embodiments, the 128-bit instruction format 2210 includes an access / address mode field 2226 that specifies the address mode and / or access mode of the instruction. In one embodiment, the access mode defines the data access alignment of the instruction. Some embodiments support access modes including 16-byte aligned access mode and 1-byte aligned access mode, where the byte alignment of the access mode determines the access alignment of the instruction operands. For example, when in the first mode, the instruction 2210 may use byte-aligned addressing for source and destination operands, and when in the second mode, the instruction 2210 may use 16-byte aligned addressing for all source and destination operands.

[0250] In one embodiment, the address mode portion of the access / address mode field 2226 determines whether the instruction will use direct addressing or indirect addressing. When using the direct register addressing mode, the bits in the instruction 2210 directly provide the register addresses of one or more operands. When using the indirect register addressing mode, the register addresses of one or more operands can be calculated based on the address register value and the address immediate field in the instruction.

[0251] In some embodiments, the instructions are grouped based on the opcode 2212 bit field to simplify opcode decoding 2240. For an 8-bit opcode, bits 4, 5, and 6 allow the execution unit to determine the type of opcode. The exact opcode grouping shown is merely exemplary. In some embodiments, the move and logic opcode group 2242 includes data move and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, the move and logic group 2242 share the five most significant bits (MSBs), where the move (mov) instruction takes the form 0000xxxxb and the logic instruction takes the form 0001xxxxb. The flow control instruction group 2244 (e.g., call, jmp) includes instructions that take the form 0010xxxxb (e.g., 0x20). The miscellaneous instruction group 2246 includes a mixture of instructions, which includes synchronization instructions (e.g., wait, send) that take the form 0011xxxxb (e.g., 0x30). The parallel math instruction group 2248 includes component-wise arithmetic instructions (e.g., add, mul) that take the form 0100xxxxb (e.g., 0x40). The parallel math group 2248 performs arithmetic operations in parallel across data channels. The vector math group 2250 includes arithmetic instructions (e.g., dp4) that take the form 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic such as a dot product calculation on vector operands.

[0252] Graphics Pipeline

[0253] Figure 23 is a block diagram of another embodiment of the graphics processor 2300. Figure 23 Elements having the same reference numbers (or names) as elements in any other figure herein can operate or function in any manner similar to the ways described elsewhere herein, but are not limited thereto.

[0254] In some embodiments, the graphics processor 2300 includes a graphics pipeline 2320, a media pipeline 2330, a display engine 2340, thread execution logic 2350, and a render output pipeline 2370. In some embodiments, the graphics processor 2300 is a graphics processor within a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or is controlled via commands issued to the graphics processor 2300 via the ring interconnect 2302. In some embodiments, the ring interconnect 2302 couples the graphics processor 2300 to other processing components, such as other graphics processors or general-purpose processors. Commands from the ring interconnect 2302 are translated by a command stream converter 2303, which supplies instructions to individual components of the graphics pipeline 2320 or the media pipeline 2330.

[0255] In some embodiments, the command stream converter 2303 directs the operation of a vertex fetcher 2305, which reads vertex data from memory and executes vertex processing commands provided by the command stream converter 2303. In some embodiments, the vertex fetcher 2305 provides vertex data to a vertex shader 2307, which performs coordinate space transformations and lighting operations on each vertex. In some embodiments, the vertex fetcher 2305 and the vertex shader 2307 execute vertex processing instructions by dispatching execution threads to execution units 2352A, 2352B via a thread dispatcher 2331.

[0256] In some embodiments, the execution units 2352A, 2352B are an array of vector processors having instruction sets for performing graphics and media operations. In some embodiments, the execution units 2352A, 2352B have additional L1 caches 2351 that are specific to each array or shared between the arrays. The cache can be configured as a data cache, an instruction cache, or a single cache that is partitioned to contain data and instructions in different partitions.

[0257] In some embodiments, the graphics pipeline 2320 includes a tessellation component for performing hardware-accelerated tessellation of 3D objects. In some embodiments, a programmable hull shader 2311 configures the tessellation operation. A programmable domain shader 2317 provides a backend evaluation of the tessellation output. The tessellator 2313 operates in the direction of the hull shader 2311 and includes dedicated logic for generating a detailed set of geometric objects based on a coarse geometric model that is provided as input to the graphics pipeline 2320. In some embodiments, if tessellation is not used, the tessellation components 2311, 2313, 2317 can be bypassed.

[0258] In some embodiments, a complete geometric object can be processed by the geometry shader 2319 via one or more threads dispatched to execution units 2352A, 2352B, or can proceed directly to the clipper 2329. In some embodiments, the geometry shader operates on an entire geometric object (as opposed to vertices or vertex patches as in previous stages of the graphics pipeline). If tessellation is disabled, the geometry shader 2319 receives input from the vertex shader 2307. In some embodiments, the geometry shader 2319 can be programmed by a geometry shader program to perform geometric tessellation when the tessellation unit is disabled.

[0259] Before rasterization, the clipper 2329 processes vertex data. The clipper 2329 can be a fixed-function clipper or a programmable clipper with clipping and geometry shader functionality. In some embodiments, the rasterizer 2373 (e.g., depth test component) in the render output pipeline 2370 dispatches pixel shaders to convert geometric objects into their per-pixel representation. In some embodiments, the pixel shader logic is included in the thread execution logic 2350. In some embodiments, an application can bypass the rasterizer 2373 and access the un-rasterized vertex data via the egress unit 2323.

[0260] The graphics processor 2300 has an interconnect bus, interconnect fabric, or some other interconnect mechanism that allows data and messages to be passed among the major components of the processor. In some embodiments, the execution units 2352A, 2352B and the associated cache(s) 2351, texture and media sampler 2354, and texture / sampler cache 2358 are interconnected via a data port 2356 to perform memory accesses and communicate with the render output pipeline components of the processor. In some embodiments, the sampler 2354, caches 2351, 2358, and execution units 2352A, 2352B each have separate memory access paths.

[0261] In some embodiments, the rendering output pipeline 2370 includes a rasterizer 2373 that converts vertex-based objects to associated pixel-based representations. In some embodiments, the rasterizer logic includes a windower / masker unit for performing fixed-function triangle and line rasterization. Associated rendering cache 2378 and depth cache 2379 are also available in some embodiments. Pixel operation component 2377 performs pixel-based operations on data, although in some examples, pixel operations associated with 2D operations (e.g., bit blit and blending) are performed by 2D engine 2341 or, at display time, by display controller 2343 using overlapping display planes. In some embodiments, shared L3 cache 2375 is available to all graphics components, allowing data to be shared without using main system memory.

[0262] In some embodiments, the graphics processor media pipeline 2330 includes a media engine 2337 and a video front end 2334. In some embodiments, the video front end 2334 receives pipeline commands from command stream converter 2303. In some embodiments, the media pipeline 2330 includes a separate command stream converter. In some embodiments, the video front end 2334 processes media commands before sending the commands to media engine 2337. In some embodiments, media engine 2337 includes a thread generation function for generating threads for dispatch to thread execution logic 2350 via thread dispatcher 2331.

[0263] In some embodiments, the graphics processor 2300 includes a display engine 2340. In some embodiments, the display engine 2340 is external to the processor 2300 and is coupled to the graphics processor via a ring interconnect 2302, or some other interconnect bus or fabric. In some embodiments, the display engine 2340 includes a 2D engine 2341 and a display controller 2343. In some embodiments, the display engine 2340 includes dedicated logic capable of operating independently of the 3D pipeline. In some embodiments, the display controller 2343 is coupled to a display device (not shown), which may be a system-integrated display device (such as in a laptop computer) or may be an external display device attached via a display device connector.

[0264] In some embodiments, the graphics pipeline 2320 and the media pipeline 2330 can be configured to perform operations based on multiple graphics and media programming interfaces and are not specific to any one application programming interface (API). In some embodiments, the driver software of the graphics processor converts API dispatches specific to a particular graphics or media library into commands that can be processed by the graphics processor. In some embodiments, support is provided for the Open Graphics Library (OpenGL) and Open Computing Language (OpenCL) from the Khronos Group, the Direct 3D library from Microsoft Corporation, or support can be provided for both OpenGL and D3D. Support can also be provided for the Open Source Computer Vision Library (OpenCV). Future APIs with compatible 3D pipelines will also be supported if a mapping can be made from the pipelines of future API calls to the pipelines of the graphics processor.

[0265] Graphics Pipeline Programming

[0266] Figure 24A is a block diagram of an exemplary graphics processor command format 2400 according to some embodiments. Figure 24B is a block diagram of an exemplary graphics processor command sequence 2410 according to an embodiment. Figure 24A The solid boxes in show components that are typically included in a graphics command, while the dashed boxes include optional or components included only in a subset of graphics commands. Figure 24A The exemplary graphics processor command format 2400 of includes data fields for identifying a target client 2402 of the command, a command operation code (opcode) 2404, and associated data 2406 of the command. A sub-opcode 2405 and a command size 2408 are also included in some commands.

[0267] In some embodiments, the client 2402 specifies the client unit of the graphics device that processes the command data. In some embodiments, the graphics processor command parser examines the client field of each command to adjust further processing of the command and route the command data to the appropriate client unit. In some embodiments, the graphics processor client units include a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline for processing commands. Once a command is received by a client unit, the client unit reads the opcode 2404 and (if present) the sub-opcode 2405 to determine the operation to be performed. The client unit uses the information in the data field 2406 to execute the command. For some commands, an explicit command size 2408 is expected to specify the size of the command. In some embodiments, the command parser automatically determines the size of at least some of the commands in the command based on the command opcode. In some embodiments, the commands are aligned by a multiple of the double-word length.

[0268] Figure 24B The process flow diagram therein shows an exemplary graphics processor command sequence 2410. In some embodiments, software or firmware of a data processing system characterized by an embodiment of a graphics processor uses a version of the shown command sequence to initiate, execute, and terminate a set of graphics operations. The sample command sequence is shown and described for illustrative purposes only, as embodiments are not limited to these specific commands or this command sequence. Additionally, the commands may be issued as a batch of commands in a command sequence such that the graphics processor will process the command sequence in at least a partially simultaneous manner.

[0269] In some embodiments, the graphics processor command sequence 2410 may begin with a pipeline flush clear command 2412 to cause any active graphics pipeline to complete the current outstanding commands of the pipeline. In some embodiments, the 3D pipeline 2422 and the media pipeline 2424 do not operate simultaneously. Executing the pipeline flush clear causes the active graphics pipeline to complete any outstanding commands. In response to the pipeline flush clear, the command parser of the graphics processor will pause command processing until the active rendering engine has completed the outstanding operations and the associated read caches are invalidated. Optionally, any data marked 'dirty' in the render cache may be flushed to memory. In some embodiments, the pipeline flush clear command 2412 may be used for pipeline synchronization or before placing the graphics processor in a low power state.

[0270] In some embodiments, a pipeline select command 2413 is used when the command sequence requires the graphics processor to make an explicit switch between pipelines. In some embodiments, only one pipeline select command 2413 is required in the execution context before issuing pipeline commands, unless the context is to issue commands for two pipelines. In some embodiments, a pipeline flush clear command 2412 is required immediately before making a pipeline switch via the pipeline select command 2413.

[0271] In some embodiments, a pipeline control command 2414 configures the graphics pipeline for operation and programs the 3D pipeline 2422 and the media pipeline 2424. In some embodiments, the pipeline control command 2414 configures the pipeline state of the active pipeline. In one embodiment, the pipeline control command 2414 is used for pipeline synchronization and for clearing data from one or more cache memories within the active pipeline before processing a batch of commands.

[0272] In some embodiments, the return buffer status command 2416 is used to configure a set of return buffers for enabling corresponding pipeline writes of data. Some pipeline operations require the allocation, selection, or configuration of one or more return buffers, which write intermediate data into the return buffers during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform cross-thread communication. In some embodiments, the return buffer status 2416 includes selecting the size and number of return buffers for a set of pipeline operations.

[0273] The remaining commands in the command sequence vary based on the active pipelines for the operations. Based on the pipeline determination 2420, the command sequence is customized according to the 3D pipeline 2422 and the media pipeline 2424, where the 3D pipeline starts with the 3D pipeline state 2430 and the media pipeline begins at the media pipeline state 2440.

[0274] The commands for the 3D pipeline state 2430 include 3D state setting commands for: vertex buffer status, vertex element status, constant color status, depth buffer status, and other state variables to be configured before processing 3D primitive commands. The values of these commands are determined at least in part based on the particular 3D API in use. In some embodiments, the 3D pipeline state 2430 commands can also selectively disable or bypass specific pipeline elements if those elements will not be used.

[0275] In some embodiments, the 3D primitive 2432 commands are used to submit 3D primitives to be processed by the 3D pipeline. The commands and associated parameters passed to the graphics processor via the 3D primitive 2432 are forwarded to the vertex fetch function in the graphics pipeline. The vertex fetch function uses the 3D primitive 2432 command data to generate vertex data structures. The vertex data structures are stored in one or more return buffers. In some embodiments, the 3D primitive 2432 commands are used to perform vertex operations on the 3D primitives via the vertex shader. To process the vertex shader, the 3D pipeline 2422 dispatches shader execution threads to the graphics processor execution units.

[0276] In some embodiments, the 3D pipeline 2422 is triggered by executing a 2434 command or event. In some embodiments, a register write triggers command execution. In some embodiments, execution is triggered via a 'go' or 'kick' command in a command sequence. In one embodiment, a pipeline synchronization command is used to trigger command execution to dump a clear command sequence through the graphics pipeline. The 3D pipeline will perform geometric processing on 3D primitives. Once the operations are complete, the resulting geometric objects are rasterized, and the pixel engine colors the resulting pixels. Additional commands for controlling pixel shading and pixel backend operations may also be included for those operations.

[0277] In some embodiments, when performing media operations, the graphics processor command sequence 2410 follows the media pipeline 2424 path. Generally, the specific use and programming of the media pipeline 2424 depend on the media or compute operation to be performed. During media decoding, specific media decoding operations may be offloaded to the media pipeline. In some embodiments, the media pipeline may also be bypassed, and resources provided by one or more general-purpose processing cores may be used to perform media decoding, either in whole or in part. In one embodiment, the media pipeline also includes elements for general-purpose graphics processing unit (GPGPU) operations, where the graphics processor is used to execute SIMD vector operations using a compute shader program that is not explicitly related to the rendering of graphics primitives.

[0278] In some embodiments, the media pipeline 2424 is configured in a manner similar to the 3D pipeline 2422. A set of media pipeline state commands 2440 are dispatched or placed into the command queue before the media object commands 2442. In some embodiments, the media pipeline state commands 2440 include data for configuring media pipeline elements that will be used to process media objects. This includes data for configuring video decoding and video encoding logic within the media pipeline (such as encoding or decoding modes). In some embodiments, the media pipeline state commands 2440 also support using one or more pointers for "indirect" state elements that contain a batch of state settings.

[0279] In some embodiments, the media object command 2442 supplies a pointer to a media object to be processed by a media pipeline. The media object includes a memory buffer containing video data to be processed. In some embodiments, all media pipeline states must be valid before the media object command 2442 is issued. Once the pipeline state is configured and the media object command 2442 is queued, the media pipeline 2424 is triggered via an execute command 2444 or an equivalent execution event (e.g., a register write). The output from the media pipeline 2424 can then be post-processed by operations provided by the 3D pipeline 2422 or the media pipeline 2424. In some embodiments, GPGPU operations are configured and executed in a manner similar to media operations.

[0280] Graphics Software Architecture

[0281] Figure 25 Exemplary graphics software architecture of a data processing system 2500 according to some embodiments is shown. In some embodiments, the software architecture includes a 3D graphics application 2510, an operating system 2520, and at least one processor 2530. In some embodiments, the processor 2530 includes a graphics processor 2532 and one or more general-purpose processor cores 2534. The graphics application 2510 and the operating system 2520 each execute in the system memory 2550 of the data processing system.

[0282] In some embodiments, the 3D graphics application 2510 includes one or more shader programs, which include shader instructions 2512. The shader language instructions can be in a high-level shader language, such as High-Level Shader Language (HLSL) or OpenGL Shading Language (GLSL). The application also includes executable instructions 2514 in machine language suitable for execution by the general-purpose processor cores 2534. The application also includes geometric objects 2516 defined by vertex data.

[0283] In some embodiments, the operating system 2520 is an operating system from Microsoft Corporation, an exclusive UNIX-like operating system using a variant of the Linux kernel, or an open-source UNIX-like operating system. When the Direct3D API is in use, the operating system 2520 uses a front-end shader compiler 2524 to compile any shader instructions 2512 in HLSL into a low-level shader language. The compilation can be Just-In-Time (JIT) compilation, or the application can perform shader pre-compilation. In some embodiments, during the compilation of the 3D graphics application 2510, high-level shaders are compiled into low-level shaders.

[0284] In some embodiments, the user-mode graphics driver 2526 includes a backend shader compiler 2527 that is used to convert shader instructions 2512 into a hardware-specific representation. When the OpenGL API is in use, shader instructions 2512 in the GLSL high-level language are passed to the user-mode graphics driver 2526 for compilation. In some embodiments, the user-mode graphics driver 2526 uses operating system kernel-mode functions 2528 to communicate with the kernel-mode graphics driver 2529. In some embodiments, the kernel-mode graphics driver 2529 communicates with the graphics processor 2532 to dispatch commands and instructions.

[0285] IP Core Implementation

[0286] One or more aspects of at least one embodiment can be implemented by representative code stored on a machine-readable medium that represents and / or defines logic within an integrated circuit, such as a processor. For example, the machine-readable medium can include instructions that represent the various logics within the processor. When read by the machine, the instructions can cause the machine to fabricate logic for performing the techniques described herein. Such representations (referred to as "IP cores") are reusable units of the logic of an integrated circuit that can be stored as a hardware model that describes the structure of the integrated circuit on a tangible, machine-readable medium. The hardware model can be supplied to various consumers or manufacturing facilities that load the hardware model on a manufacturing machine for fabricating the integrated circuit. The integrated circuit can be fabricated such that the circuit performs the operations described in connection with any of the embodiments described herein.

[0287] Figure 26 is a block diagram of an IP core development system 2600 according to an embodiment that can be used to fabricate an integrated circuit to perform operations. The IP core development system 2600 can be used to generate a modular, reusable design that can be incorporated into a larger design or used to build an entire integrated circuit (e.g., a SOC integrated circuit). The design facility 2630 can use a high-level programming language (e.g., C / C++) to generate a software simulation 2610 of the IP core design. The software simulation 2610 can be used to design, test, and verify the behavior of the IP core. Then, a register transfer level (RTL) design can be created or synthesized from the simulation model 2600. The RTL design 2615 is an abstraction of the behavior of an integrated circuit that models the flow of digital signals between hardware registers, including the associated logic executed using the modeled digital signals. In addition to the RTL design 2615, lower-level designs at the logic level or transistor level can also be created, designed, or synthesized. Thus, the specific details of the initial design and simulation can vary.

[0288] The RTL design 2615 or equivalent can be further synthesized by a design facility into a hardware model 2620, which can be in a hardware description language (HDL) or some other representation of physical design data. The HDL can be further simulated or tested to verify the IP core design. A non-volatile memory 2640 (e.g., a hard disk, flash memory, or any non-volatile storage medium) can be used to store the IP core design for delivery to a third-party manufacturing facility 2665. Alternatively, the IP core design can be transmitted (e.g., via the Internet) through a wired connection 2650 or a wireless connection 2660. The manufacturing facility 2665 can then manufacture an integrated circuit that is at least partially based on the IP core design. The manufactured integrated circuit can be configured to perform operations in accordance with at least one embodiment described herein.

[0289] Figure 27 is a block diagram of an exemplary system-on-chip integrated circuit 2700 according to an embodiment, and the system-on-chip integrated circuit can be manufactured using one or more IP cores. The exemplary integrated circuit includes one or more application processors 2705 (e.g., CPUs), at least one graphics processor 2710, and can additionally include an image processor 2715 and / or a video processor 2720, any of which can be a modular IP core from the same or multiple different design facilities. The integrated circuit includes peripheral or bus logic, including a USB controller 2725, a UART controller 2730, an SPI / SDIO controller 2735, I 2 S / I 2 C controller 2740. Additionally, the integrated circuit can include a display device 2745 that is coupled to one or more of a high-definition multimedia interface (HDMI) controller 2750 and a mobile industry processor interface (MIPI) display interface 2755. Storage can be provided by a flash memory subsystem 2760 (including flash memory and a flash memory controller). A memory interface can be provided via a memory controller 2765 for accessing SDRAM or SRAM memory devices. Some integrated circuits additionally include an embedded security engine 2770.

[0290] Additionally, other logic and circuitry can be included in the processors of the integrated circuit 2700, and these logic and circuitry include additional graphics processors / kernels, peripheral interface controllers, or general-purpose processor cores.

[0291] In one example, the graphics processing pipeline 500( Figure 5 ), the graphics processing pipeline 1400, and / or the VTG 1406( Figure 14 ) operate as described with respect to the graphics pipeline device 604 and the hardware fixed-function tessellator unit 606( Figure 6 ), respectively.

[0292] Additional Notes and Examples

[0293] Example 1 may include an adaptive sub - tessellation system, including: a power supply for supplying power to the system; and a graphics pipeline device including a hull shader core for generating sub - tessellations for a subdivision surface associated with a tessellation, where each sub - tessellation includes a sub - tessellation factor. The system may include: a hardware fixed - function tessellator for generating a sub - tessellation of the sub - tessellation based on the sub - tessellation factor and generating a sub - tessellation specification based on the sub - tessellation. The system may include: a display subsystem communicatively coupled to the graphics pipeline device, where the display subsystem visually presents one or more scenes associated with the sub - tessellation and the sub - tessellation specification.

[0294] Example 2 may include the system as described in Example 1, where the sub - tessellation specification includes control points, and where the system further includes: a domain shader for converting the sub - tessellation specification into a digital rendered scene using a displacement map. The hull shader core generates values of sub - tessellation parameters that identify sub - tessellation attributes in each dimension of an N - dimensional sub - tessellation. One or more of the sub - tessellation parameters include one or more values that identify a start sub - tessellation boundary and an end sub - tessellation boundary. The tessellation and the sub - tessellation include one or more of a quadrilateral tessellation type or a triangle tessellation type, where the tessellation and the sub - tessellation identify one or more domains, where the one or more domains may be subdivided into triangular domains or quadrilateral domains, and where the tessellation and the sub - tessellation include outer edges and inner edges.

[0295] Example 3 may include the system as described in Example 2, where the tessellation factor specifies the number of segments into which the outer edge or the inner edge is to be divided.

[0296] Example 4 may include the system as described in Example 2, where the outer - edge tessellation factors of adjacent sub - tessellations use equal tessellation factors with respect to each other to eliminate cracks between the adjacent sub - tessellations.

[0297] Example 5 may include the system as described in Example 4, where the hull shader core determines a transition region for connecting adjacent outer edges or inner edges to an irregular triangle strip.

[0298] Example 6 may include the system as described in Example 2, where when one of the tessellation or the sub - tessellation exhibits perspective distortion based on a perspective projection, the hull shader core causes the size of the tessellation within the interior region of the one of the tessellation or the sub - tessellation to diverge based on the position of each of the tessellations within the one of the tessellation or the sub - tessellation.

[0299] Example 7 may include the system as described in Example 6, wherein the sub - patch tessellation factor identifies the granularity of the tessellation of the sub - patch.

[0300] Example 8 may include the system as described in any one of Examples 1 to 7, wherein the hardware fixed - function tessellator provides geometric compression by adaptively generating the sub - patch tessellation of the sub - patch based on the sub - patch tessellation factor. The hull shader kernel is used to determine the granularity of the sub - patch tessellation based on the perspective projection of one or more of the patch or the sub - patches.

[0301] Example 9 may include a graphics pipeline device, comprising: a hull shader kernel for generating sub - patches for a tessellated surface of a patch, wherein each of the sub - patches has a sub - patch tessellation factor; and a hardware fixed - function tessellator for generating the sub - patch tessellation of the sub - patch based on the sub - patch tessellation factor and generating a sub - patch specification based on the sub - patch tessellation.

[0302] Example 10 may include the device as described in Example 9, wherein the sub - patch specification includes control points. The sub - patch specification can be converted into a digital rendered scene by a domain shader using a displacement map. The hull shader kernel generates values of sub - patch parameters that identify the sub - patch attributes in each dimension of an N - dimensional sub - patch, wherein one or more of the sub - patch parameters include one or more values that identify a start sub - patch boundary and an end sub - patch boundary. The patch and the sub - patches include one or more of a quadrilateral patch type or a triangle patch type, wherein the patch and the sub - patches identify one or more domains, wherein the one or more domains can be subdivided into triangular domains or quadrilateral domains, and wherein the patch and the sub - patches include outer edges and inner edges.

[0303] Example 11 may include the device as described in Example 10, wherein the tessellation factor specifies the number of segments into which the outer edge or the inner edge is to be divided.

[0304] Example 12 may include the device as described in Example 10, wherein the outer - edge tessellation factors of adjacent sub - patches use equal tessellation factors with each other to eliminate cracks between the adjacent sub - patches.

[0305] Example 13 may include the device as described in Example 12, wherein the hull shader kernel determines a transition region for connecting adjacent outer edges or inner edges to an irregular triangle strip.

[0306] Example 14 may include the device as described in Example 13, wherein when perspective distortion based on perspective projection is presented in one of the patches or sub-patches, the hull shader kernel causes the tessellation size within the interior region of the one of the patches or sub-patches to diverge based on the position of each of the tessellations within the patch or sub-patch.

[0307] Example 15 may include the device as described in Example 10, wherein the sub-patch tessellation factor identifies the granularity of the tessellation of the sub-patch.

[0308] Example 16 may include the device as described in Example 15, wherein the hardware fixed-function tessellator provides geometric compression by adaptively generating the sub-patch tessellation of the sub-patch based on the sub-patch tessellation factor.

[0309] Example 17 may include the device as described in any one of Examples 9 to 16, wherein the hull shader kernel is configured to determine the granularity of the sub-patch tessellation based on the perspective projection of one or more of the patches or sub-patches.

[0310] Example 18 may include a method of generating sub-patches for tessellation, the method comprising: generating sub-patches for a subdivision surface associated with a patch, wherein each sub-patch includes a sub-patch tessellation factor; generating the sub-patch tessellation of the sub-patch based on the sub-patch tessellation factor; and generating a sub-patch specification based on the sub-patch tessellation.

[0311] Example 19 may include the method as described in Example 18, wherein the sub-patch specification includes control points, and wherein the method further comprises: using a displacement map to convert the sub-patch specification into a digital rendering scene; and generating values of sub-patch parameters that identify sub-patch attributes in each dimension of an N-dimensional sub-patch. One or more of the sub-patch parameters include one or more values that identify a start sub-patch boundary and an end sub-patch boundary. The patch and the sub-patch include one or more of a quadrilateral patch type or a triangle patch type. The patch and the sub-patch identify one or more domains, and wherein generating the sub-patch tessellation further comprises: subdividing the one or more domains into triangular domains or quadrilateral domains, and wherein the patch and the sub-patch include outer edges and inner edges.

[0312] Example 20 may include the method as described in Example 19, wherein the tessellation factor specifies the number of segments into which one or more of the outer edges or the inner edges are to be divided.

[0313] Example 21 may include the method as described in Example 19, wherein the outer edge tessellation factors of adjacent sub-fragments use equal tessellation factors with each other to eliminate the gaps between the adjacent sub-fragments.

[0314] Example 22 may include the method as described in Example 21, further comprising: determining a transition region for connecting adjacent outer edges or inner edges to an irregular triangle strip.

[0315] Example 23 may include the method as described in Example 22, wherein when one of the fragments or sub-fragments exhibits perspective distortion based on perspective projection, the method further comprises: diverging the tessellation size in the inner region of the one of the fragments or sub-fragments based on the position of each of the tessellations within the fragment or sub-fragment.

[0316] Example 24 may include the method as described in Example 19, wherein the sub-fragment tessellation factor identifies the granularity of the tessellation of the sub-fragment.

[0317] Example 25 may include the method as described in any one of Examples 18 to 24, further comprising: determining the granularity of the sub-fragment tessellation based on the perspective projection of one or more of the fragments or sub-fragments, wherein generating the sub-fragment tessellation of the sub-fragment based on the sub-fragment tessellation factor provides geometric compression.

[0318] Example 26 may include an adaptive sub-fragment system, comprising means for performing the method as described in any one of Examples 18 to 24, the system further comprising: means for determining the granularity of the sub-fragment tessellation based on the perspective projection of one or more of the fragments or sub-fragments, wherein generating the sub-fragment tessellation of the sub-fragment based on the sub-fragment tessellation factor provides geometric compression.

[0319] The embodiments are applicable to all types of semiconductor integrated circuit (“IC”) chips. Examples of such IC chips include, but are not limited to, processors, controllers, chipset components, programmable logic arrays (PLAs), memory chips, network chips, system-on-a-chip (SoC), SSD / NAND controller ASICs, etc. Additionally, in some of the figures, signal conductor lines are represented by lines. Some of the lines may be different to indicate more composed signal paths, having numerical markings to indicate the numbers of the composed signal paths and / or having arrows at one or more ends to indicate the primary information flow direction. However, this should not be construed in a limiting manner. Rather, such additional details may be used in conjunction with one or more exemplary embodiments to help more easily understand the circuits. Any represented signal line, whether or not having additional information, may actually include one or more signals that may travel in multiple directions and may be implemented using any suitable type of signal scheme, such as digital or analog lines implemented using differential pairs, fiber optic lines, and / or single-ended lines.

[0320] Example sizes / models / values / ranges may have been given, although the embodiments are not limited thereto. As manufacturing technologies (e.g., lithography) mature over time, it is expected that devices of smaller sizes can be manufactured. Additionally, well-known power / ground connections to the IC chips and other components may or may not be shown in the figures, for simplicity of presentation and discussion and so as not to obscure certain aspects of the embodiments. Further, the arrangements may be shown in block diagram form to avoid obscuring the embodiments and also in view of the fact that details regarding how such block diagram arrangements are implemented are highly dependent on the computing system in which the embodiments are implemented, i.e., such details should be entirely within the purview of those skilled in the art. In cases where specific details (e.g., circuits) are set forth in order to describe exemplary embodiments, it should be apparent to those skilled in the art that the embodiments may be practiced with or without variations of these specific details. The description is thus to be regarded as illustrative rather than restrictive.

[0321] The term “coupled” may be used herein to refer to any type of direct or indirect relationship between the components discussed and may apply to electrical, mechanical, fluid, optical, electromagnetic, electromechanical, or other connections. Additionally, the terms “first,” “second,” etc. may be used herein solely to facilitate discussion and do not carry any specific significance of a temporal or chronological order, unless otherwise specified. Moreover, it should be understood that the indefinite articles “a” or “an” carry the meaning of “one or more” or “at least one.”

[0322] As used in this application and the claims, a list of items described by the phrase "one or more" can mean any combination of the listed items. For example, the phrase "one or more of A, B, and C" can mean A, B, C; A and B; A and C; B and C; or A, B, and C.

[0323] The embodiments have been described above with reference to specific examples. However, those skilled in the art will understand that various modifications and changes can be made thereto without departing from the broader spirit and scope of the embodiments as set forth in the appended claims. Accordingly, the foregoing description and drawings are to be regarded as illustrative rather than restrictive.

Claims

1. An adaptive sub - patch system, comprising: A power supply for providing power to the system; A graphics pipeline device including a hull shader core for generating sub - patches for a tessellated surface associated with a patch, the hull shader core being used to specify the decomposition of the patch, wherein each sub - patch includes a sub - patch tessellation factor; A hardware fixed - function tessellator for generating a sub - patch tessellation of the sub - patch based on the sub - patch tessellation factor and generating a sub - patch specification based on the sub - patch tessellation; and A display subsystem communicatively coupled to the graphics pipeline device, wherein the display subsystem visually presents one or more scenes associated with the sub - patch tessellation and the sub - patch specification.

2. The system according to claim 1, wherein, The sub - patch specification includes control points, and the system further includes: A domain shader for converting the sub - patch specification into a digital rendered scene using a displacement map, wherein the hull shader core generates values of sub - patch parameters that identify sub - patch attributes in each dimension of an N - dimensional sub - patch, and wherein one or more of the sub - patch parameters include one or more values that identify a start sub - patch boundary and an end sub - patch boundary, wherein the patch and the sub - patch include one or more of a quadrilateral patch type or a triangle patch type, wherein the patch and the sub - patch identify one or more domains, and wherein the one or more domains are subdivided into triangle domains or quadrilateral domains, and wherein the patch and the sub - patch include outer edges and inner edges.

3. The system according to claim 2, wherein, The tessellation factor specifies the number of segments into which the outer edge or the inner edge is to be divided.

4. The system according to claim 2, wherein The outer - edge tessellation factors of adjacent sub - patches use equal tessellation factors with each other to eliminate cracks between the adjacent sub - patches.

5. The system according to claim 4, wherein, The hull shader core determines a transition region for connecting adjacent outer edges or inner edges to an irregular triangle strip.

6. The system according to claim 2, wherein When one of the patch or the sub - patch exhibits perspective distortion based on a perspective projection, the hull shader core causes the size of the tessellation within the inner region of the one of the patch or the sub - patch to diverge based on the position of each of the tessellations within the patch or the sub - patch.

7. The system according to claim 6, wherein The sub - patch tessellation factor identifies the granularity of the tessellation of the sub - patch.

8. The system according to any one of claims 1 to 7, wherein The hardware fixed - function tessellator provides geometric compression by adaptively generating the sub - patch tessellation of the sub - patch based on the sub - patch tessellation factor, and wherein the hull shader core is used to determine the granularity of the sub - patch tessellation based on a perspective projection of one or more of the patch or the sub - patch.

9. A graphics pipeline device, comprising: A hull shader core for generating sub - patches for a tessellated surface of a patch, wherein each of the sub - patches has a sub - patch tessellation factor and wherein the hull shader core is used to specify the decomposition of the patch; and A hardware-fixed function tessellator for generating a sub-tessellation of the sub-patch based on the sub-patch tessellation factor and generating a sub-patch specification based on the sub-patch tessellation.

10. The device according to claim 9, wherein, The sub-patch specification includes control points, wherein the sub-patch specification is converted into a digital rendering scene by a domain shader using a displacement map, wherein the hull shader kernel generates values of sub-patch parameters that identify sub-patch attributes in each dimension of an N-dimensional sub-patch, and wherein one or more of the sub-patch parameters include one or more values that identify a start sub-patch boundary and an end sub-patch boundary, wherein the patch and the sub-patch include one or more of a quadrilateral patch type or a triangle patch type, wherein the patch and the sub-patch identify one or more domains, and wherein the one or more domains are subdivided into triangular domains or quadrilateral domains, and wherein the patch and the sub-patch include outer edges and inner edges.

11. The device according to claim 10, wherein, The tessellation factor specifies the number of segments into which the outer edge or the inner edge is to be divided.

12. The device according to claim 10, wherein, The outer edge tessellation factors of adjacent sub-patches use equal tessellation factors with each other to eliminate cracks between the adjacent sub-patches.

13. The device according to claim 12, wherein, The hull shader kernel determines a transition region for connecting adjacent outer edges or inner edges to an irregular triangle strip.

14. The device according to claim 13, wherein, When a perspective distortion based on a perspective projection occurs in one of the patch or the sub-patch, the hull shader kernel causes the size of the tessellation within the inner region of the one of the patch or the sub-patch to diverge based on the position of each of the tessellations within the patch or the sub-patch.

15. The device according to claim 10, wherein, The sub-patch tessellation factor identifies the granularity of the tessellation of the sub-patch.

16. The device according to claim 15, wherein, The hardware-fixed function tessellator provides geometric compression by adaptively generating the sub-tessellation of the sub-patch based on the sub-patch tessellation factor.

17. The device according to any one of claims 9 to 16, wherein The hull shader kernel is used to determine the granularity of the sub-patch tessellation based on a perspective projection of one or more of the patch or the sub-patch.

18. A method for managing adaptive sub-patches, the method comprising: generating sub-patches for a subdivided surface associated with a patch, wherein each sub-patch includes a sub-patch tessellation factor, and wherein a hull shader kernel is used to specify the decomposition of the patch; generating a sub-tessellation of the sub-patch based on the sub-patch tessellation factor; and generating a sub-patch specification based on the sub-patch tessellation.

19. The method according to claim 18, wherein, The sub-patch specification includes control points, and the method further comprises: using a displacement map to convert the sub-patch specification into a digital rendering scene; and generating values of sub-patch parameters that identify sub-patch attributes in each dimension of an N-dimensional sub-patch, wherein one or more of the sub-patch parameters include one or more values that identify a start sub-patch boundary and an end sub-patch boundary, Wherein, the patches and the sub-patches include one or more of a quadrilateral patch type or a triangular patch type, wherein the patches and the sub-patches identify one or more domains, and wherein generating the sub-patch tessellation further includes subdividing the one or more domains into triangular domains or quadrilateral domains, and wherein, the patches and the sub-patches include outer edges and inner edges.

20. The method according to claim 19, wherein, The tessellation factor specifies the number of segments into which one or more of the outer edges or the inner edges are to be divided.

21. The method according to claim 19, wherein, The outer edge tessellation factors of adjacent sub-patches use equal tessellation factors with each other to eliminate gaps between the adjacent sub-patches.

22. The method according to claim 21, further comprising: Determine a transition region for connecting adjacent outer or inner edges to an irregular triangular strip.

23. The method according to claim 22, wherein, When one of the patches or the sub-patches exhibits perspective distortion based on a perspective projection, the method further includes: diverging the size of the tessellation within the interior region of the one of the patches or the sub-patches based on the position of each of the tessellations within the patch or the sub-patch.

24. The method according to claim 19, wherein, The sub-patch tessellation factor identifies the granularity of the tessellation of the sub-patch.

25. An adaptive sub-patch system, comprising means for performing the method according to any one of claims 18 to 24.

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