Bit reordering of storage devices

Abstract

A storage device including a controller for bit reordering is disclosed. The controller receives an input bit sequence including a plurality of bits having a first bit order. The controller identifies physical locations of non-volatile storage elements in the storage device and determines a correspondence between the first bit order and a second bit order based on the physical locations. The controller generates an output bit sequence including a plurality of bits having the second bit order based on the correspondence.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to bit reordering of storage devices such as solid-state drives (SSDs). Background Art

[0002] Compared to traditional hard disk drives (HDDs), flash SSDs have advantages in that they have higher throughput, lower read / write latency, and lower power consumption. Compared to other non-volatile memories (NVMs), NAND flash memory in particular has a low price and large capacity.

[0003] In an SSD system, NAND die are connected to a memory controller, such as a NAND controller, via a parallel data bus. Each data bus includes multiple bus lines to connect the NAND die to the NAND controller. Crossing bus lines may require additional vertical interconnect access (VIA) and board layers, and thus may increase the manufacturing cost of the SSD system. To avoid crossing bus lines, it is necessary to reorder the bits transmitted on the data bus between the NAND die and the NAND controller.

[0004] Bit reordering can be performed on the NAND die. One method of bit reordering is to use a swap circuit integrated into each NAND die. The swap circuit can reorder bits at the bus interface of the NAND die according to a predetermined bit order. For example, the swap circuit can reorder the most significant bit (MSB) to the least significant bit (LSB). However, the swap circuit integrated into each NAND die cannot reorder bits in any arbitrary bit order.

[0005] Therefore, there is a need to perform arbitrary reordering of the bits transferred on the data bus between the NAND die and the NAND controller. Summary of the Invention

[0006] One embodiment of the present disclosure discloses a storage device. The storage device includes: a plurality of non-volatile storage elements configured to process a plurality of read and / or write operations; and a controller connected to the plurality of non-volatile storage elements via one or more buses, wherein the one or more buses are configured to connect at least two of the plurality of non-volatile storage elements to the controller. The controller is configured to: receive an input bit sequence including a plurality of bits having a first bit sequence, wherein the controller writes the input bit sequence to one of the plurality of non-volatile storage elements; identify the physical location of the non-volatile storage element in the storage device; determine a correspondence between the first bit sequence and the second bit sequence based on the physical location; and generate an output bit sequence including a plurality of bits having a second bit sequence based on the correspondence.

[0007] Another embodiment of the present disclosure discloses a storage device. The storage device includes: a plurality of processing devices configured to process a plurality of read and / or write operations; and a control device connected to the plurality of processing devices via one or more buses, wherein each of the one or more buses is configured to connect at least two of the plurality of processing devices to the control device. The control device is configured to: receive an input bit sequence including a plurality of bits having a first bit sequence, wherein the control device writes the input bit sequence to one of the plurality of processing devices; identify the physical location of the processing device in the storage device; determine a correspondence between the first bit sequence and the second bit sequence based on the physical location; and generate an output bit sequence including a plurality of bits having a second bit sequence based on the correspondence.

[0008] Another embodiment of the present disclosure discloses a storage device. The storage device includes: a plurality of non-volatile storage elements configured to process a plurality of read and / or write operations; and a controller connected to the plurality of non-volatile storage elements via one or more buses, wherein each of the one or more buses is configured to connect at least two of the plurality of non-volatile storage elements to the controller. The controller is configured to: receive an input bit sequence including a plurality of bits having a first bit sequence, wherein the controller reads the input bit sequence from one of the plurality of non-volatile storage elements; identify the physical location of the non-volatile storage element in the storage device; determine a correspondence between the first bit sequence and the second bit sequence based on the physical location; generate an output bit sequence including a plurality of bits having a second bit sequence based on the correspondence; and transmit the output bit sequence to a processor in the controller for processing.

[0009] Another embodiment of the present disclosure discloses a storage device. The storage device includes: a plurality of processing devices configured to process a plurality of read and / or write operations; and a control device connected to the plurality of processing devices via one or more buses, wherein each of the one or more buses is configured to connect at least two of the plurality of processing devices to the control device. The control device is configured to: receive an input bit sequence including a plurality of bits having a first bit sequence, wherein the control device reads the input bit sequence from one of the plurality of processing devices; identify the physical location of the processing device in the storage device; determine the correspondence between the first bit sequence and the second bit sequence based on the physical location; generate an output bit sequence including a plurality of bits having a second bit sequence based on the correspondence; and transmit the output bit sequence to a processor in the control device for processing.

[0010] Another embodiment of the disclosure discloses a method. The method includes: receiving, by a controller in a storage device, an input bit sequence including a plurality of bits having a first bit order, wherein the controller writes the input bit sequence to one of a plurality of non-volatile storage elements in the storage device; identifying a physical location of the non-volatile storage elements in the storage device; determining a correspondence between the first bit order and a second bit order based on the physical location; and generating an output bit sequence including a plurality of bits having the second bit order based on the correspondence.

[0011] Another embodiment of the disclosure discloses a method. The method includes: receiving, by a controller in a storage device, an input bit sequence including a plurality of bits having a first bit order, wherein the controller writes the input bit sequence to one of a plurality of non-volatile storage elements in the storage device; identifying a physical location of the non-volatile storage elements in the storage device; determining a correspondence between the first bit order and a second bit order based on the physical location; and generating an output bit sequence including a plurality of bits having the second bit order based on the correspondence. BRIEF DESCRIPTION OF DRAWINGS

[0012] As a result, a more particular description of the above-mentioned features of the disclosure briefly summarized above can be obtained by reference to the embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of the disclosure and are therefore not to be considered limiting of its scope, for the disclosure can admit to other equally effective embodiments. Among the

[0013] Figure 1 An SSD system including a NAND controller is shown in accordance with one embodiment herein;

[0014] Figure 2 An SSD system including a NAND controller is shown in accordance with another embodiment herein;

[0015] Figure 3 A lookup table is shown in accordance with one embodiment herein;

[0016] Figure 4A A swap circuit is shown in accordance with one embodiment herein;

[0017] Figure 4B A swap circuit is shown in accordance with another embodiment herein;

[0018] Figure 5 A flowchart showing a method for bit reordering in accordance with one embodiment herein is shown. DETAILED DESCRIPTION

[0019] To facilitate understanding, identical reference numerals have been used, where practical, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation.

[0020] In the following, reference is made to embodiments of the present disclosure. However, it should be understood that the present disclosure is not limited to the specifically described embodiments. On the contrary, any combination of the following features and elements, whether or not related to different embodiments, is contemplated for implementing and practicing the present disclosure. In addition, although embodiments of the present disclosure may achieve advantages over other feasible solutions and / or prior art, whether or not a given embodiment achieves a particular advantage is not a limitation of the present disclosure. Therefore, the following aspects, features, embodiments and advantages are merely illustrative and are not considered to be elements or limitations of the appended claims unless expressly stated in the claims. Similarly, reference to "the present disclosure" should not be interpreted as a summary of any inventive subject matter disclosed herein and should not be considered to be elements or limitations of the appended claims unless expressly stated in the claims. It should be understood that although reference will be made to NAND devices, the present disclosure is equally applicable to other NVMs and therefore should not be limited to NAND devices unless expressly stated.

[0021] Figure 1 FIG. 1 shows an SSD system 100 according to one embodiment of the present invention. Figure 1 As shown, SSD system 100 includes a controller 101 and multiple die, such as two die 111 and 112. In one embodiment, controller 101 is a NAND controller, and die 111 and 112 are NAND die. Dies 111 and 112 are connected to controller 101 via a shared data bus 120. That is, die 111 and die 112 communicate data with controller 101 via bus 120 at different time periods, rather than simultaneously. Shared data bus 120 includes eight bus lines that form an 8-bit channel between die 111, 112 and controller 101. Therefore, in each bus transaction (e.g., a data transfer via bus 120 within a time period), eight bits are transferred on bus 120 from die 111, 112 to controller 101, or from controller 101 to die 111, 112.

[0022] In each bus transaction, the die 111, 112 communicates 8 bits with the controller 101 using 8 endpoints (eg, I / O pads or terminals) at the bus interface of the die 111, 112. For example, Figure 1As shown, die 111 communicates 8 bits per bus transaction with controller 101 via bus 120 using eight endpoints P30-P37. Similarly, die 112 communicates 8 bits per bus transaction with controller 101 via bus 120 using eight endpoints P40-P47.

[0023] Each of the eight endpoints used by each die 111, 112 corresponds to a unique bit valid value. Figure 1 As shown, P30 on the bare die 111 corresponds to the MSB, as shown by DQ(7), and P37 on the bare die 111 corresponds to the LSB, as shown by DQ(0). P31-P36 correspond to the bit significance values ​​from DQ(6) to DQ(1), respectively. That is, the bit order of P30-P37 is from MSB to LSB (from DQ(7) to DQ(0)). Therefore, for example, when the bare die 111 uses P30-P37 to send the 8-bit sequence "00100111" (a byte with a decimal value of 39) to the controller 101 via the bus 120 (e.g., a read operation), P30 sends "0", P31 sends "0", P32 sends "1", P33 sends "0", P34 sends "0", P35 sends "1", P36 sends "1", and P37 sends "1". Similarly, each of P40-P47 also has a corresponding unique bit significance value. In one embodiment, the bit validity value of each endpoint on the die 111 , 112 is predetermined or pre-configured by the manufacturer of the die 111 , 112 and cannot be changed after the die 111 , 112 is manufactured.

[0024] like Figure 1 As shown, the controller 101 also uses the eight endpoints P20-P27 at the bus interface to communicate data with the eight endpoints on the bare cores 111 and 112. Similarly, each of the eight endpoints P20-P27 used by the controller 101 corresponds to a unique bit valid value. In one embodiment, the bit valid value of each of P20-P27 is predetermined or pre-configured by the manufacturer of the SSD system 100, which cannot be changed after the SSD system is manufactured. In one example, P20 on the controller 101 corresponds to the LSB, and P27 on the controller 101 corresponds to the MSB. That is, as Figure 1As shown, the bit order of P20-P27 is from LSB to MSB (from DQ(0) to DQ(7)). In this example, to correctly communicate data between NAND die 111 and controller 101, one method is to connect P20 to P37 using a bus line of bus 120, because both P20 and P37 correspond to LSBs; and to connect P27 to P30 using another bus line of bus 120, because both P27 and P30 correspond to MSBs. However, the above method results in the crossing of the bus lines connecting die 111 to controller 101, which is undesirable.

[0025] In one embodiment of the present disclosure, the eight endpoints on die 111 or die 112 can be connected to P20-P27 on controller 101 via bus 120 in any manner to avoid or reduce bus line crossings. This is achieved by bit reordering performed by controller 101, which will be described in detail below.

[0026] like Figure 1 As shown, controller 101 includes processor 102, memory 103, and switch unit 104. Processor 102 can be any computer processor capable of performing the functions described herein. Memory 103 can include one or more memory blocks associated with physical addresses, such as random access memory (RAM). Switch unit 104 reorders the 8 bits transmitted on bus 120 between die 111, 112 and controller 101.

[0027] like Figure 1 As shown, in one embodiment, to avoid crossing of bus lines, P30 is connected to P20, P31 is connected to P21, P32 is connected to P22, P33 is connected to P23, P34 is connected to P24, P35 is connected to P25, P36 is connected to P26, and P37 is connected to P27. In this way, there is no crossing of bus lines connecting bare die 111 to controller 101. Figure 1 As shown, there is only a straight bus line connection between the bare die 111 and the controller 101. Figure 1 As shown, there is no crossing of the bus lines connecting the die 112 to the controller 101 .

[0028] However, in Figure 1With the bus lines connected as shown, the 8 bits received at P20-P27 are not in the correct bit order for processing by processor 102. For example, when die 111 sends the 8-bit sequence "00100111" to controller 101 via bus 120 using P30-P37, P20 receives a "0," P21 receives a "0," P22 receives a "1," P23 receives a "0," P24 receives a "0," P25 receives a "1," P26 receives a "1," and P27 receives a "1." Because the bit order of P20-P27 is from DQ(0) to DQ(7), controller 101 receives the 8-bit sequence "11100100" at P20-P27. Therefore, if processor 102 directly processes the 8-bit sequence received at P20-P27, processor 102 will process "11100100" (from P27-P20), while bare die 111 actually sends "00100111" (from P30-P37) to controller 101, which causes an error.

[0029] In one embodiment, the exchange unit 104 reorders the 8-bit sequence received at P20-P27 in the correct bit order for processing by the processor 102. In one embodiment, the correct bit order is the same as the bit order of the die 111, 112, such as the bit order of P30-P37 of the die 111. For the bit order P30-P37, the processor 102 checks the lookup table (LUT) 105 in the memory 103. In one embodiment, the LUT 105 stores a mapping or correspondence between the bit order of P30-P37 and the bit order of P20-P27 based on the die address (i.e., physical location) of the die 111 in the SSD system 100.

[0030] In one embodiment, the processor 102 sends the die address of the die 111 as input to the LUT 105, and the LUT 105 outputs the bit order of P30-P37 to the switching unit 104. The switching unit 104 reorders the 8-bit sequence received at P20-P27 according to the bit order of P30-P37 provided by the LUT 105. For example, according to the bit order of P20-P27, the 8-bit sequence received at P20-P27 is "11100100", and the switching unit 104 reorders "11100100" according to the correct bit order (i.e., the bit order of P30-P37 provided by the LUT 105) to generate "00100111". For example, the LSB bit "0" received at P20 is reordered to the MSB (DQ(7)), and the MSB bit "1" received at P27 is reordered to the LSB (DQ(0)). Thus, after reordering, "11100100" is reordered to "00100111".

[0031] like Figure 1 As shown, after generating the reordered 8-bit sequence, the switching unit 104 uses 8 endpoints P10-P17 to send the reordered 8-bit sequence to the processor 102. In one embodiment, as shown in FIG. Figure 1 As shown, the bit order of P10-P17 is predetermined, for example, from DQ(7) to DQ(0). Therefore, the switching unit 104 sends "00100111" from P10-P17 to the processor 102.

[0032] Figure 1 Only one embodiment is shown. In other embodiments, the bit order of P10-P17 can be from DQ(0) to DQ(7), the bit order of P20-P27 can be from DQ(7) to DQ(0), and P30-P37 can be from DQ(0) to DQ(7). In another embodiment, the bare core 112 sends the 8-bit sequence from P40-P47 to P20-P27 via bus 120. Similar to the above, the switching unit 104 reorders the 8-bit sequence received at P20-P27. The bit order of P40-P47 can be the same as or different from the bit order of P30-P37. In another embodiment, the 8 endpoints of bare core 111 or bare core 112 can be connected to P20-P27 on the controller 101 in any manner to avoid or reduce the crossing of bus lines.

[0033] The above embodiment describes bit reordering for a read operation, for example, where an 8-bit sequence is transmitted from die 111 to controller 101. In another embodiment, an 8-bit sequence is transmitted from controller 101 to die 111, 112, such as die 111, for a write operation. In this embodiment, the 8-bit sequence is transmitted from processor 102 to P10-P17, and switching unit 104 reorders the 8-bit sequence received at P10-P17 in the correct bit order and transmits the reordered 8-bit sequence to P30-P37 using P20-P27, as described in detail below.

[0034] Figure 2 FIG. 2 shows an SSD system 200 according to an embodiment of the present invention. The SSD system 200 includes a controller 201. Figure 2 As shown, the controller 201 is connected to 128 bare cores via 8 buses, namely from BUS0 to BUS7. In one embodiment, as described above, each of the 8 buses constructs an 8-bit channel. That is, Figure 2 Each bus in the consists of 8 bus lines.

[0035] In one embodiment, 128 die are packaged in Figure 21, 212, 213, and 214 in the diagram. Each BGA package includes 32 bare cores connected to the controller 201 via two buses. For example, the 32 bare cores in the BGA package 211 are connected to the controller 201 via BUS0 and BUS1. In one embodiment, the 16 bare cores in each BGA package share the same bus. For example, the 16 bare cores in the upper portion of the BGA package 211 share BUS0, and the 16 bare cores in the lower portion of the BGA package 211 share BUS1. In one embodiment, each of the 128 bare cores is connected to the controller 201 via a corresponding shared bus using its corresponding 8 endpoints, similar to Figure 1 For ease of illustration, Figure 2 The terminals on each die are not shown.

[0036] In one embodiment, for each bus, the controller 201 uses 8 endpoints to connect to corresponding 8 endpoints on each of the 16 die sharing the bus, similar to Figure 1 Therefore, in one embodiment, the controller 201 has a total of 64 endpoints for 8 buses. To simplify the description, the endpoints on the controller 201 are not shown in FIG. Figure 2 Shown in.

[0037] In one embodiment, for each bus, the controller 201 includes a corresponding LUT 220-227 and a corresponding switch unit 230-237. For example, for BUS0, the controller 201 includes a LUT 220 and a switch unit 230 stored in the memory of the SSD system 200. For simplicity of description, the memory of the SSD system 200 is not shown in FIG. Figure 2 By using LUTs and switching units for each bus, each of the 16 die sharing the bus can be connected to the controller 201 in any manner to avoid or reduce crossing of the bus lines connecting the die to the controller 201.

[0038] In one embodiment, when one of the 16 die sends an 8-bit sequence to the controller 201 via the shared bus for a read operation, the controller 201 reorders the received 8-bit sequence by using the corresponding LUT and swap unit, similar to the above. Figure 1 For example, when one of the 16 bare cores sharing BUS0 transmits an 8-bit sequence to the controller 201 via any bus line connection. The processor ( Figure 2The processor 200 (not shown) sends the die address of the die as input to the LUT 220, and the LUT 220 outputs the correct bit sequence of the die to the switching unit 230. The switching unit 230 reorders the received 8-bit sequence to generate an 8-bit sequence with the correct bit sequence and sends the reordered 8-bit sequence to the processor.

[0039] In another embodiment, when the controller 201 transmits an 8-bit sequence to one of the 16 die for a write operation via a shared bus, the controller 201 reorders the transmitted 8-bit sequence by using corresponding LUTs and switching units to generate an 8-bit sequence with a correct bit order and sends the reordered 8-bit sequence to the die.

[0040] Figure 2 Only one embodiment is shown. In other embodiments, the controller 201 can be connected to a different number of bare die via a different number of buses. In other embodiments, each BGA package can include a different number of bare die and the bare die can be wired inside the BGA package. In other embodiments, each bus can be shared by a different number of bare die.

[0041] Figure 3 FIG. 3 shows a LUT 300 according to one embodiment of the present invention. Figure 3 In this example, LUT 300 is used for one bus. For example, suppose LUT 300 is used for Figure 1 That is, LUT 300 is Figure 1 In one embodiment, LUT 300 stores the correspondence between the input bit sequence and the output bit sequence of each of the plurality of die (e.g., die 111 and 112) connected to controller 101 via bus 102. In one embodiment, the correspondence between the input bit sequence and the output bit sequence of the die is determined based on the die address, i.e., the physical location of the die in SSD system 100. Dies at different physical locations are connected to controller 101 via different bus connections to avoid or reduce crossing of bus lines. Therefore, the die at different physical locations have different correspondences between the input bit sequence and the output bit sequence.

[0042] In one embodiment, LUT 300 stores the correspondence between the input bit sequence and the output bit sequence of each of the bare cores connected to controller 101 via bus 102 for use in read operations. For example, when bare core 111 transmits an 8-bit sequence to controller 101, processor 102 can recognize, for example, based on information in a command and / or address phase that the 8-bit sequence comes from bare core 111 and that bare core 111 has address 1. Processor 102 sends address 1 to LUT 300 to retrieve the correspondence for bare core 111. Figure 3 As shown, for address 1, the input bit order is from DQ(0) to DQ(7), expressed as DQ(0 1 2 3 4 5 6 7), and the corresponding output bit order is from DQ(7) to DQ(0), expressed as DQ(7 6 5 4 3 2 1 0). That is, DQ(0) in the input bit sequence is reordered to DQ(7) in the output bit sequence, DQ(1) in the input bit sequence is reordered to DQ(6) in the output bit sequence, DQ(2) in the input bit sequence is reordered to DQ(5) in the output bit sequence, DQ(3) in the input bit sequence is reordered to DQ(4) in the output bit sequence, DQ(4) in the input bit sequence is reordered to DQ(3) in the output bit sequence, DQ(5) in the input bit sequence is reordered to DQ(2) in the output bit sequence, DQ(6) in the input bit sequence is reordered to DQ(1) in the output bit sequence, and DQ(7) in the input bit sequence is reordered to DQ(0) in the output bit sequence. Therefore, in one embodiment, the correspondence is a bit-for-bit correspondence between each bit in the input bit sequence and each bit in the output bit sequence.

[0043] LUT 300 provides the correspondence of the die with address 1 (i.e., die 111) to the switching unit 104 to reorder the input bit sequence to generate the correct output bit sequence. For example, die 111 transmits the 8-bit sequence "00100111" from P30-P37 to the controller 101. Controller 101 receives the 8-bit input sequence "11100100" from die 111 at P20-P27 (MSB "1" is received at P27 and LSB "0" is received at P20). Based on the correspondence of address 1 in LUT 300, the 8-bit output sequence to processor 102 is "00100111", which is the same as the 8-bit sequence actually transmitted from die 111. Therefore, switching unit 104 transmits "00100111" to processor 102 (MSB "0" is transmitted at P10 and LSB "1" is transmitted at P17).

[0044] In another embodiment, LUT 300 stores the correspondence between the input bit sequence and the output bit sequence of each of the bare cores connected to controller 101 via bus 102 for use in write operations. For example, when controller 101 transmits the 8-bit sequence "00100111" from processor 102 to bare core 111, P10-P17 receive the 8-bit input sequence "00100111" (MSB "0" is received at P10 and LSB "1" is received at P17). Based on the correspondence of address 1 in LUT 300, the 8-bit output sequence is "11100100". Therefore, P20-P27 transmit "11100100" to P30-P37 (MSB "1" is transmitted at P27 and LSB "0" is transmitted at P20). Therefore, P30-P37 receives the same 8-bit sequence "00100111" as the actual transmitted 8-bit sequence from processor 102.

[0045] In LUT 300, address 2 (the address of die 112) has a different correspondence. Figure 3 As shown, for address 2, the input bit sequence is from DQ(0) to DQ(7), expressed as DQ(0 1 2 3 4 5 6 7), and the corresponding output bit sequence is also from DQ(0) to DQ(7), expressed as DQ(0 1 2 3 4 5 6 7). As described above, bare die 112 can use different bus lines to connect to controller 101. Therefore, bare die 112 has a different correspondence relationship than bare die 111.

[0046] The correspondence relationship can be any correspondence relationship. For example, Figure 3 As shown, for a bare die with address 3, the input bit sequence may be from DQ(0) to DQ(7), expressed as DQ(0 1 2 3 4 5 6 7), and the corresponding output bit sequence may be: DQ(3), DQ(4), DQ(7), DQ(5), DQ(1), DQ(2), DQ(0), DQ(6), expressed as DQ(3 4 7 5 1 2 0 6). That is, DQ(0) in the input bit sequence is reordered to DQ(3) in the output bit sequence, and DQ(7) in the input bit sequence is reordered to DQ(6) in the output bit sequence.

[0047] In one embodiment, when the layout of the SSD system 100 is designed, the LUT 300 is programmed into the memory 103 of the NAND controller 101. For example, when the layout of the SSD system 100 is designed, the manner in which the bus lines are connected (e.g., routed) for each die to avoid crossing bus lines depends on the physical location (die address) of the die in the SSD system 100. Furthermore, the manner in which the bus lines of each die are connected determines the corresponding relationship for bit reordering of the die. Therefore, when the layout of the SSD system 100 is designed, the die addresses and corresponding relationship for bit reordering can be determined and stored in the memory 103 of the controller 101 for future use. When the memory 103 is initialized, the LUT 300 is ready for use. Therefore, when the NAND controller 101 needs to perform bit reordering, the controller 101 does not need to create the LUT 300.

[0048] Figure 3 Only one embodiment of a read operation or a write operation is shown. In other embodiments, the LUT 300 includes two different sub-tables for read operations and write operations, respectively. In other embodiments, the LUT 300 may include correspondences for more than two bare cores. For example, Figure 2 As shown, LUT 300 may include 16 corresponding relationships of 16 bare cores in BGA 211 connected to controller 201 via BUS0. In other words, LUT 300 is Figure 2 In other embodiments, LUT 300 may include any correspondence between input bit order and output bit order.

[0049] Figure 4A FIG. 4 shows a switching circuit 400 for a read operation according to an embodiment of the present invention. The switching circuit 400 is included in a switching unit, such as Figure 1 The switching unit 104 or Figure 2 The switching unit 220 in FIG. Figure 4A As shown, the switching circuit 400 includes 8 selectors, such as selector 401 and selector 408 (for simplicity of description, the other 6 selectors are not shown in FIG). Figure 4A ). In one embodiment, each of the eight selectors comprises an 8-to-1 selector to generate one output bit. For example, selector 401 generates an output bit of DQ(0) (i.e., LSB) in an 8-bit output sequence, and selector 408 generates an output bit of DQ(7) (i.e., MSB) in an 8-bit output sequence. In one embodiment, the swap circuit 400 reorders the 8-bit input sequence based on one or more die addresses input to the LUT 300.

[0050] In one example described below, it is assumed that the switching circuit 400 is included in the switching unit 104 for a read operation between the bare die 111 and the controller 101. Figure 1 As described in Figure 4A As shown, an 8-bit input sequence is input from the bare die 111 to each of the 8 selectors in the switching circuit 400 in a bit order from DQ(7) to DQ(0). The 8-bit input sequence is received at P20-P27. The processor 102 can recognize that the bare die 111 has address 1 and send address 1 to the LUT 300. The LUT 300 provides a corresponding bit-to-bit correspondence of address 1 to each of the 8 selectors. For example, as shown by arrow 411, the LUT 300 provides a corresponding bit-to-bit correspondence to the selector 401. Figure 3 As shown, for address 1, input bit DQ(7) in the input 8-bit sequence corresponds to output bit DQ(0) in the output 8-bit sequence. Therefore, selector 401 selects input bit DQ(7) in the 8-bit input sequence as output bit DQ(0) in the 8-bit output sequence. Similarly, as shown by arrow 418, LUT 300 provides the corresponding bit-to-bit correspondence to selector 408. Selector 408 selects input bit DQ(0) in the 8-bit input sequence as output bit DQ(7) in the 8-bit output sequence. For example, if the 8-bit input sequence received at P20-P27 is "11100100", selector 401 selects input bit 1 (DQ(7)) in "11100100" as output bit DQ(0) in the 8-bit output sequence, and selector 408 selects input bit 0 (DQ(0)) in "11100100" as output bit DQ(7) in the 8-bit output sequence. Each of the other six selectors similarly generates a corresponding output bit. Thus, the swap circuit 400 generates an 8-bit output sequence "00100111" and sends the 8-bit output sequence from P10-P17 to the processor 102 for a read operation.

[0051] Figure 4A Only one embodiment is shown. In other embodiments, based on the bit-to-bit correspondence provided by LUT 300, each selector in swap circuit 400 can generate output bits according to any arbitrary bit-to-bit correspondence between input bits in the input bit sequence and output bits in the output bit sequence, as will be understood by those skilled in the art.

[0052] Figure 4B FIG. 4 shows a switching circuit 420 for a write operation according to an embodiment of the present invention. The switching circuit 420 is also included in the switching unit, for example Figure 1 The switching unit 104 or Figure 2 The switching unit 220 in . Similar to Figure 4AThe exchange circuit 420 includes eight selectors, such as selector 421 and selector 428, as shown (for simplicity, the other six selectors are not shown in Figure 4B Figure 4B In one embodiment, each of the eight selectors includes an 8-to-l selector to generate one output bit. For example, the selector 421 generates the output bit for DQ(7) (i.e., the MSB) in the 8-bit output sequence, and the selector 428 generates the output bit for DQ(0) (i.e., the LSB) in the 8-bit output sequence. In one embodiment, the exchange circuit 420 reorders the 8-bit input sequence based on one or more die addresses input to the LUT 300.

[0053] In one example, described below, assume that the exchange circuit 420 is included in the exchange unit 104 for a write operation between the NAND die 111 and the NAND controller 101, as described in Figure 1 Figure 4B As shown, the 8-bit input sequence is input from the processor 102 to each of the eight selectors in the exchange circuit 420 in bit order from DQ(0) to DQ(7). The 8-bit input sequence is received at P10-P17. The processor 102 sends the address 1 of the NAND die 111 to the LUT 300. The LUT 300 provides a respective bit-to-bit correspondence for the address 1 to each of the eight selectors. For example, as shown by arrow 431, the LUT 300 provides the respective bit-to-bit correspondence to the selector 421. Based on the bit-to-bit correspondence, the selector 421 selects the input bit DQ(0) in the 8-bit input sequence as the output bit DQ(7) in the 8-bit output sequence. Similarly, as shown by arrow 438, the LUT 300 provides the respective bit-to-bit correspondence to the selector 428. The selector 428 selects DQ(7) in the 8-bit input sequence as the output bit DQ(0) in the 8-bit output sequence. For example, if the 8-bit input sequence received at P10-P17 is “01000111”, the selector 421 selects the input bit 1 (DQ(0)) in “01000111” as the output bit DQ(7) in the 8-bit output sequence and the selector 428 selects the input bit 0 (DQ(7)) in “01000111” as the output bit DQ(0) in the 8-bit output sequence. Each of the other six selectors similarly generates a respective output bit. The exchange circuit 420 generates the 8-bit output sequence “11100010” and sends the 8-bit output sequence from P20-P27 to the NAND die 111 for the write operation.

[0054] Figure 4B ​​This is only one embodiment. In other embodiments, based on the bit-for-bit correspondence provided by LUT 300, each selector in swap circuit 420 can generate output bits according to any arbitrary bit-for-bit correspondence between input bits in the input bit sequence and output bits in the output bit sequence, as will be understood by one of ordinary skill in the art.

[0055] In one embodiment, for a read operation, the controller first sends the bits in the command and address cycles to the die, and then receives the bits in the data cycles from the die. When sending the bits in the command and address cycles to the die, the controller uses the switching circuit 420 to generate an output bit sequence to send to the die. When receiving the bits in the data cycles from the die, the controller uses the switching circuit 400 to generate an output bit sequence to send to the processor in the controller. Thus, for a read operation, the controller uses both the switching circuit 400 and the switching circuit 420 in the switching unit. In another embodiment, for a write operation, the controller sends the bits in the command, address, and data cycles to the die by using the switching circuit 420.

[0056] Figure 5 1 is a flowchart illustrating a method 500 for bit reordering according to one embodiment of the present invention. At block 501, a controller in a storage device receives an input bit sequence including a plurality of bits having a first bit sequence. For example, the controller 101 in the SSD system 100 receives an input bit sequence having a first bit sequence (e.g., "11100100") from the bare die 111. At block 502, the controller identifies the physical location of a non-volatile storage element in the storage device. For example, the processor 102 in the controller 101 identifies that 111 has an address of 1. At block 503, the controller determines a correspondence between the first bit sequence and the second bit sequence based on the physical location. For example, the LUT 105 in the controller 101 determines a correspondence between the first bit sequence and the second bit sequence based on the address of 1 and provides the correspondence to the switching unit 104. At block 504, the controller generates an output bit sequence based on the correspondence, the output bit sequence including a plurality of bits having a second bit sequence. For example, the switching unit 104 reorders the input bit sequence based on the correspondence provided by the LUT 105 and generates an output bit sequence having a second bit order (eg, “00100111”). The switching unit 104 sends the generated output bit sequence to the processor 102 .

[0057] By using the switch unit and LUT, the controller can arbitrarily reorder the bits transmitted on the data bus between the bare die and the controller. Therefore, crossing of bus lines can be avoided or reduced, thus saving the manufacturing cost of the SSD system.

[0058] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure can be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

1. A storage device comprising: a plurality of non-volatile storage elements configured to handle a plurality of read and / or write operations; and a controller connected to the plurality of non-volatile storage elements via one or more buses, wherein each of the one or more buses is configured to connect at least two of the plurality of non-volatile storage elements to the controller; Wherein, the controller is configured as follows: receiving an input bit sequence from a first non-volatile storage element of the plurality of non-volatile storage elements, the input bit sequence comprising a plurality of bits having a first order, wherein die positions and corresponding relationships for bit reordering are stored in a memory of the controller; identifying a physical location of the first non-volatile storage element in the storage device; Based on the physical location, determining a correspondence between the first bit sequence and the second bit sequence; and An output bit sequence is generated based on the corresponding relationship, the output bit sequence including a plurality of bits having the second bit order.

2. The storage device according to claim 1, wherein The correspondence between the first bit order and the second bit order represents a bit-for-bit correspondence between each bit in the input bit sequence and each bit in the output bit sequence.

3. The storage device according to claim 1, wherein The controller is further configured to store the correspondence between the first bit sequence and the second bit sequence in a lookup table, which is stored in the memory in the controller. The storage device according to claim 1 , wherein: The input bit sequence is received from the controller, and the output bit sequence is transferred to the non-volatile storage element.

5. A storage device comprising: a plurality of processing devices configured to process a plurality of read and / or write operations; and a control device connected to the plurality of processing devices via one or more buses, wherein each of the one or more buses is configured to connect at least two processing devices of the plurality of processing devices to the control device; Wherein, the control device is configured as follows: receiving an input bit sequence from a first processing device among the plurality of processing devices, the input bit sequence comprising a plurality of bits having a first order, wherein die positions and corresponding relationships for bit reordering are stored in a memory of the control device; identifying a physical location of the first processing component in the storage device; Based on the physical location, determining a correspondence between the first bit sequence and the second bit sequence; and An output bit sequence is generated based on the corresponding relationship, the output bit sequence including a plurality of bits having the second bit order. The storage device according to claim 5 , wherein: The storage device includes a solid state drive (SSD). The storage device according to claim 5 , wherein: The correspondence between the first bit order and the second bit order represents a bit-for-bit correspondence between each bit in the input bit sequence and each bit in the output bit sequence. The storage device according to claim 5 , wherein: The control device is further configured to store the correspondence between the first bit sequence and the second bit sequence in a lookup table, which is stored in the memory in the control device.

9. The storage device according to claim 5, wherein: The corresponding relationship between the first bit sequence and the second bit sequence includes an arbitrary corresponding relationship.

10. The storage device according to claim 5, wherein The input bit sequence is received from the control device, and the output bit sequence is transmitted to the processing device.

11. A storage device comprising: a plurality of non-volatile storage elements configured to handle a plurality of read and / or write operations; and a controller connected to the plurality of non-volatile storage elements via one or more buses, wherein each of the one or more buses is configured to connect at least two of the plurality of non-volatile storage elements to the controller; Wherein, the controller is configured as follows: receiving an input bit sequence from a first non-volatile storage element of the plurality of non-volatile storage elements, the input bit sequence comprising a plurality of bits having a first order, wherein die positions and corresponding relationships for bit reordering are stored in a memory of the controller; identifying a physical location of the first non-volatile storage element in the storage device; determining a correspondence between the first bit sequence and the second bit sequence based on the physical location; generating an output bit sequence based on the corresponding relationship, the output bit sequence including a plurality of bits having the second bit order; and The output bit sequence is transmitted to a processor in the controller for processing.

12. The storage device according to claim 11, wherein The input bit sequence is received from the first non-volatile storage element.

13. The storage device according to claim 11, wherein: The controller includes one or more selectors to generate the output bit sequence. The storage device according to claim 11 , wherein: Each of the one or more buses constructs an 8-bit channel between the controller and the plurality of non-volatile storage elements.

15. A storage device comprising: a plurality of processing devices configured to process a plurality of read and / or write operations; and a control device connected to the plurality of processing devices via one or more buses, wherein each of the one or more buses is configured to connect at least two processing devices of the plurality of processing devices to the control device; Wherein, the control device is configured as follows: receiving an input bit sequence from a first processing device among the plurality of processing devices, the input bit sequence including a plurality of bits having a first order, wherein the control device reads the input bit sequence from a processing device among the plurality of processing devices, wherein die positions and corresponding relationships for bit reordering are stored in a memory of the control device; identifying a physical location of the first processing component in the storage device; determining a correspondence between the first bit sequence and the second bit sequence based on the physical location; generating an output bit sequence based on the corresponding relationship, the output bit sequence including a plurality of bits having the second bit order; and The output bit sequence is transmitted to a processor in the control device for processing. The storage device according to claim 15 , wherein: The storage device includes a solid state drive (SSD).

17. The storage device according to claim 15, wherein: The correspondence between the first bit order and the second bit order represents a bit-for-bit correspondence between each bit in the input bit sequence and each bit in the output bit sequence.

18. The storage device according to claim 15, wherein The control device is further configured to store the correspondence between the first bit sequence and the second bit sequence in a lookup table, which is stored in the memory in the control device.

19. The storage device according to claim 15, wherein The corresponding relationship between the first bit sequence and the second bit sequence includes an arbitrary corresponding relationship.

20. The storage device according to claim 15, wherein The input bit sequence is received from the first processing device.

21. A method of operating a storage device, comprising: receiving, by a controller in a memory device, an input bit sequence from a first non-volatile memory element among a plurality of non-volatile memory elements, the input bit sequence comprising a plurality of bits having a first order, wherein die positions and corresponding relationships for bit reordering are stored in a memory of the controller; identifying a physical location of the first non-volatile storage element in the storage device; determining a correspondence between the first bit sequence and the second bit sequence based on the physical location; and An output bit sequence is generated based on the corresponding relationship, the output bit sequence including a plurality of bits having the second bit order.

22. The method according to claim 21, wherein The storage device includes a solid state drive (SSD).

23. The method according to claim 21, wherein Each of the non-volatile storage elements includes a NAND die.

24. The method according to claim 21, wherein The controller includes a NAND controller.

25. A method of operating a storage device, comprising: receiving, by a controller in a memory device, an input bit sequence from a first non-volatile memory element among a plurality of non-volatile memory elements, the input bit sequence comprising a plurality of bits having a first order, wherein the controller reads the input bit sequence from the first non-volatile memory element among the plurality of non-volatile memory elements in the memory device, wherein die positions and corresponding relationships for bit reordering are stored in a memory of the controller; identifying a physical location of the first non-volatile storage element in the storage device; determining a correspondence between the first bit sequence and the second bit sequence based on the physical location; generating an output bit sequence based on the corresponding relationship, the output bit sequence including a plurality of bits having the second bit order; and The output bit sequence is transmitted to a processor in the controller for processing.

26. The method according to claim 25, wherein The corresponding relationship between the first bit sequence and the second bit sequence includes an arbitrary corresponding relationship.

27. The method according to claim 25, wherein The plurality of non-volatile storage elements are packaged in one or more ball grid array (BGA) packages.

28. The method according to claim 25, wherein The controller is connected to the plurality of nonvolatile storage elements via a plurality of buses.

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