Low Dropout Linear Regulators

Abstract

A low voltage difference linear regulator includes: a P-type power tube, the source end of the P-type power tube is connected to the first input power supply end, the drain end of the P-type power tube is connected to the output voltage end, the P-type power tube has a back gate, the back gate of the P-type power tube is connected to the source end of the P-type power tube; a driving circuit, the output end of the driving circuit is connected to the gate of the P-type power tube; an error amplifier, the output end of the error amplifier is connected to the input end of the driving circuit; a ripple introduction unit, the ripple introduction unit is connected between the output end of the error amplifier and the input end of the driving circuit. The low voltage difference linear regulator improves the power supply rejection ratio.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and in particular to a low voltage difference linear regulator. Background Art

[0002] Low dropout regulator (LDO) can provide a stable output voltage that is independent of the power supply and environment, and has a certain load capacity. It has been widely used in various chips.

[0003] Compared with traditional linear regulators, low-dropout linear regulators that use PMOS tubes as power tubes can make the voltage difference between the input voltage and the output voltage as small as the product of the load current and the on-resistance of the PMOS tube. It can be seen that the extremely small on-resistance makes the corresponding low-dropout linear regulator voltage difference very low. In this case, when the system input voltage and output voltage are close, very high efficiency can be achieved.

[0004] An important parameter of a low-dropout linear regulator is the power supply rejection ratio (PSRR), which is the ratio of the input voltage to the output voltage change. Since factors such as environmental noise can cause glitches in the input voltage, thus affecting the stability of the output voltage, a larger power supply rejection ratio can make the low-dropout linear regulator have a more stable output.

[0005] Therefore, improving the power supply rejection ratio of low-dropout linear regulators has become an industry expectation. Summary of the invention

[0006] The problem solved by the invention is to provide a low voltage difference linear regulator to improve the power supply rejection ratio of the low voltage difference linear regulator.

[0007] To solve the above problems, the present invention provides a low voltage difference linear regulator, comprising: a P-type power tube, wherein the source end of the P-type power tube is connected to the first input power supply end, the drain end of the P-type power tube is connected to the output voltage end, the P-type power tube has a back gate, and the back gate of the P-type power tube is connected to the source end of the P-type power tube; a driving circuit, wherein the output end of the driving circuit is connected to the gate of the P-type power tube; an error amplifier, wherein the output end of the error amplifier is connected to the input end of the driving circuit; and a ripple introduction unit, wherein the ripple introduction unit is connected between the output end of the error amplifier and the input end of the driving circuit.

[0008] Optionally, the ripple introducing unit includes an NMOS tube, and the NMOS tube has a back gate.

[0009] Optionally, the ripple introducing unit further includes a first resistor and a capacitor.

[0010] Optionally, the back gate of the NMOS tube is connected to the ground through the first resistor, and the back gate of the NMOS tube is connected to the second input power supply terminal through the capacitor.

[0011] Optionally, the gate of the NMOS tube is connected to a bias voltage terminal, and the bias voltage terminal is independent of the first input power supply terminal.

[0012] Optionally, the low voltage dropout linear regulator further includes a sampling resistor network, and the sampling resistor network is connected between the output voltage terminal and ground.

[0013] Optionally, the inverting input terminal of the error amplifier is connected to the reference voltage input terminal, and the non-inverting input terminal of the error amplifier is connected to the sampling voltage terminal of the sampling resistor network.

[0014] Optionally, the sampling resistor network includes a second resistor and a third resistor connected in series, and the sampling voltage terminal is located between the second resistor and the third resistor.

[0015] In one aspect of the technical solution of the present invention, a ripple introduction unit is added to the circuit, and the back gate effect inside the ripple introduction unit is used to detect the input power disturbance, thereby affecting the loop, offsetting the interference of the input power disturbance on the output voltage, and improving the power supply rejection ratio.

[0016] Furthermore, through the capacitive coupling effect of the ripple introduction unit, the input power supply ripple is injected into the back gate of the NMOS tube and affects the output of the error amplifier. The gate voltage of the P-type power tube is adjusted through the feedback loop to stabilize the output voltage and improve the power supply rejection ratio. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A circuit diagram of a low voltage drop linear regulator of a traditional architecture;

[0018] Figure 2 for Figure 1 The schematic diagram of the input voltage and corresponding output voltage of the low-dropout linear regulator is shown;

[0019] Figure 3 It is another circuit diagram of a low voltage drop linear regulator of a traditional architecture;

[0020] Figure 4 A circuit diagram of a low voltage dropout linear regulator provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0021] A circuit diagram of a traditional low voltage dropout linear regulator is shown in Figure 1As shown, it includes an error amplifier 101, a driving circuit 102, a P-type power tube 103 and a sampling resistor network 104 (indicated by a dotted box). When the circuit is working, the change of the input power supply (Vin) is transmitted to the output voltage (Vout) through the P-type power tube 103. It is transmitted to the error amplifier 101 through the sampling resistor network 104 to generate a driving signal. The gate voltage of the P-type power tube 103 is controlled by the driving circuit 102 to form a negative feedback loop for stabilizing the output voltage. The P-type power tube 103 has a back gate, which is connected to the input power supply. Combined with Figure 2 The voltage diagram shows that Figure 1 When the input power (input voltage) of this conventional low voltage drop linear regulator fluctuates up and down, it will affect the P-type power tube 103, causing the output voltage to fluctuate, and the error amplifier 101 is relied upon to restore the original level.

[0022] Figure 3 is another circuit diagram of a low dropout linear regulator. Figure 1 Based on the conventional low voltage drop linear regulator shown in FIG. 1 , the back gate of the P-type power tube 103 is connected to another input power supply through a resistor 105. Other aspects are similar to those of FIG. Figure 1 same.

[0023] Due to the intervention of resistor 105, the V BS (B is the back gate, S is the source) is not 0, resulting in a back gate effect, which makes the threshold voltage (V TH ) with the back gate-source voltage (V BS ) changes. When the first input power source is disturbed up and down, assuming that the gate voltage of the P-type power tube 103 remains unchanged, the gate-source voltage (V GS ) changes, will cause the corresponding output current changes, thereby affecting the output voltage (Vout). The back gate effect is introduced by resistor 105, and the input power disturbance will cause the threshold voltage of the P-type power tube to change. However, since the current of the P-type power tube 103 is related to the gate-source voltage and the threshold voltage, the introduction of the back gate effect will reduce the output current change of the P-type power tube 103, thereby making the output voltage more stable.

[0024] However, in Figure 3 In the low voltage difference linear regulator shown, the introduction of resistor 105 is equivalent to increasing the substrate resistance of the P-type power tube 103, which makes it easier for (the P-type power tube 103) to cause a latch effect, generate a through current from the power supply to the ground, and damage the corresponding chip.

[0025] To this end, the present invention provides a low voltage drop linear regulator which can improve the power supply rejection ratio and reduce the interference of input voltage disturbance on output voltage.

[0026] For a clearer representation, the present invention is described in detail below with reference to the accompanying drawings.

[0027] The embodiment of the present invention provides a low voltage drop linear regulator, please refer to Figure 4 .

[0028] The low voltage drop linear regulator includes a P-type power tube 203 , a driving circuit 202 , an error amplifier 201 and a ripple introduction unit 205 .

[0029] The source end of the P-type power tube 203 is connected to the first input power supply terminal Vin, the drain end of the P-type power tube 203 is connected to the output voltage terminal Vout, and the P-type power tube 203 has a back gate, and the back gate of the P-type power tube 203 is connected to the source end of the P-type power tube 203, that is, the back gate of the P-type power tube 203 is also connected to the first input power supply terminal Vin. In addition, there is no resistance between the back gate of the P-type power tube 203 and the first input power supply terminal Vin.

[0030] The output end of the driving circuit 202 is connected to the gate of the P-type power transistor 203 .

[0031] An output terminal of the error amplifier 201 is connected to an input terminal of the driving circuit 202 .

[0032] The ripple introducing unit 205 is connected between the output terminal of the error amplifier 201 and the input terminal of the driving circuit 202 .

[0033] Please continue to refer to Figure 4 The low voltage dropout linear regulator further includes a sampling resistor network 204, and the sampling resistor network 204 is connected between the output voltage terminal and the ground (not marked).

[0034] The inverting input terminal of the error amplifier 201 is connected to the reference voltage input terminal Vref, and the non-inverting input terminal of the error amplifier 201 is connected to the sampling voltage terminal (not marked) of the sampling resistor network 204 .

[0035] In this embodiment, the sampling resistor network 204 includes a second resistor 2041 and a third resistor 2042 connected in series, and the sampling voltage terminal is located between the second resistor 2041 and the third resistor 2042. One end of the second resistor 2041 not connected to the third resistor 2042 is connected to the output voltage terminal Vout, and one end of the third resistor 2042 not connected to the second resistor 2041 is grounded.

[0036] In this embodiment, the ripple introduction unit 205 may include an NMOS transistor 2051, and the NMOS transistor 2051 has a back gate. The back gate further cooperates with other structures of the ripple introduction unit 205, which will be further described later.

[0037] In this embodiment, the ripple introduction unit 205 may further include a first resistor 2052 and a capacitor 2053. The back gate of the NMOS tube 2051 of the ripple introduction unit 205 is connected to the ground (not marked) through the first resistor 2052, and the back gate of the NMOS tube 2051 is connected to the second input power supply terminal (not marked) through the capacitor 2053. The gate of the NMOS tube 2051 of the ripple introduction unit 205 is connected to the bias voltage terminal Vbias, and the bias voltage terminal Vbias is independent of the first input power supply terminal Vin.

[0038] In the low voltage difference linear regulator provided in this embodiment, a ripple introduction unit 205 is added between the driving circuit 202 and the error amplifier 201. The ripple introduction unit 205 includes an NMOS tube 2051, a first resistor 2052 and a capacitor 2053. In addition, the drain end of the NMOS tube 2051 is connected to the node between the output end of the error amplifier 201 and the input end of the driving circuit 202, and the source end of the NMOS tube 2051 is grounded, the gate of the NMOS tube 2051 is connected to a fixed bias voltage Vbias, the back gate of the NMOS tube 2051 is connected to the first resistor 2052 and the capacitor 2053 respectively, the other end of the first resistor 2052 is grounded, and the other end of the capacitor 2053 is connected to the second input power supply end.

[0039] When working, the output voltage (Vout) generated by the circuit output voltage terminal Vout and the sampling voltage terminal voltage (FB) of the sampling resistor network satisfy the following relationship (it should be noted that in this specification, Vin and Vout are both used as labels and as representations of corresponding voltages):

[0040]

[0041] Wherein, R2 is the resistance value of the second resistor 2041 , and R3 is the resistance value of the third resistor 2042 .

[0042] In this case, the output of the error amplifier 201 is superimposed with the pull-down current of the NMOS tube 2051 of the ripple introduction unit 205 to generate a driving signal, and the gate voltage of the P-type power tube 203 is controlled by the driving circuit 202. The gate voltage of the NMOS tube 2051 is a fixed bias voltage (Vbias) that is independent of the input power supply (Vin). The NMOS tube 2051 works in the saturation region, and its drain current satisfies the following relationship:

[0043]

[0044] The above formula (2) is a known formula, μ n is the electron mobility of NMOS tube 2051, C OXis the gate oxide capacitance of the NMOS tube 2051, W is the channel width of the NMOS tube 2051, L is the channel length of the NMOS tube 2051, V GS is the gate-source voltage of the NMOS tube 2051 (fixed to Vbias in this embodiment), V TH is the threshold voltage of the NMOS tube 2051.

[0045] It can be seen that the drain current of NMOS tube 2051 is related to its threshold voltage V TH Related.

[0046] The back gate of the NMOS tube 2051 is grounded through the first resistor 2052. When the power supply is stable, its back gate voltage (V BS ) is 0. When the power supply is disturbed, the power supply disturbance is coupled through capacitor 2053 to cause the back gate potential to change. The back gate voltage V BS is not 0, resulting in a MOS tube back gate effect, making the threshold voltage (V TH ) changes accordingly, thereby affecting the drain current of the NMOS tube 2051.

[0047] It can be seen that when the input power (Vin) of the first input power terminal Vin is disturbed, through the back gate effect of the NMOS tube 2051, the node between the error amplifier 201 and the driving circuit 202 will sense the input power change in advance, and the gate voltage of the P-type power tube 203 will be adjusted accordingly in advance through the driving circuit 202, thereby reducing the output voltage (Vout) disturbance.

[0048] Based on the above content, it can be seen that this embodiment adds a ripple introduction unit in the circuit, uses the back gate effect inside the ripple introduction unit to detect the input power disturbance, thereby affecting the loop, offsetting the interference of the input power disturbance on the output voltage, and improving the power supply rejection ratio.

[0049] Furthermore, in this embodiment, the input power supply ripple is injected into the back gate of the NMOS tube 2051 through the capacitive coupling effect inside the ripple introduction unit, and affects the output of the error amplifier 201. The gate voltage of the P-type power tube 203 is adjusted through the feedback loop to stabilize the output voltage and improve the power supply rejection ratio.

[0050] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A low voltage dropout linear regulator, characterized in that: include: A P-type power tube, wherein a source end of the P-type power tube is connected to a first input power supply end, a drain end of the P-type power tube is connected to an output voltage end, and the P-type power tube has a back gate, and the back gate of the P-type power tube is connected to a source end of the P-type power tube; A driving circuit, wherein an output end of the driving circuit is connected to a gate of the P-type power tube; an error amplifier, wherein an output terminal of the error amplifier is connected to an input terminal of the driving circuit; A ripple introduction unit, the ripple introduction unit is connected between the output end of the error amplifier and the input end of the drive circuit; the ripple introduction unit includes an NMOS tube, and the NMOS tube has a back gate; the ripple introduction unit also includes a first resistor and a capacitor; the back gate of the NMOS tube is connected to the ground through the first resistor, and the back gate of the NMOS tube is connected to the second input power supply terminal through the capacitor; the gate of the NMOS tube is connected to the bias voltage terminal, and the bias voltage terminal is independent of the first input power supply terminal; the drain of the NMOS tube is connected to the common end of the error amplifier and the drive circuit; It also includes a sampling resistor network, which is connected between the output voltage terminal and the ground; the inverting input terminal of the error amplifier is connected to the reference voltage input terminal, and the in-phase input terminal of the error amplifier is connected to the sampling voltage terminal of the sampling resistor network.

2. The low voltage dropout linear regulator according to claim 1, characterized in that: The sampling resistor network includes a second resistor and a third resistor connected in series, and the sampling voltage terminal is located between the second resistor and the third resistor.

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