Electro-optical device, method for driving electro-optical device, and electronic device

Abstract

The present invention relates to an electro-optical device, a driving method of an electro-optical device, and an electronic apparatus. The electro-optical device has: a first pixel circuit provided corresponding to a position where one scan line and a first data line intersect; a second pixel circuit provided corresponding to a position where the one scan line and a second data line intersect; a first level shift unit circuit that shifts a potential of a first data signal in a manner that compresses a potential amplitude of the first data signal at a first compression rate, and supplies the first data signal to the first data line; and a second level shift unit circuit that shifts a potential of a second data signal in a manner that compresses a potential amplitude of the second data signal at a second compression rate different from the first compression rate, and supplies the second data signal to the second data line.

Description

[0001] This application is a divisional application of the application No. 201310093783.8, filed on March 22, 2013, with the title of "Electro-Optical Device, Driving Method of Electro-Optical Device, and Electronic Device" in the State Intellectual Property Office of the People's Republic of China. TECHNICAL FIELD

[0002] Several embodiments of the present application relate to, for example, a technology when displaying a color image with a plurality of electro-optical elements. BACKGROUND

[0003] In recent years, various electro-optical devices using light emitting elements such as Organic Light Emitting Diode (hereinafter referred to as "OLED") elements have been proposed. In the electro-optical device, a pixel circuit including the light emitting element, a transistor, and the like is provided corresponding to a pixel of an image to be displayed, in correspondence with the intersection of a scan line and a data line. In such a configuration, if a data signal of a potential corresponding to the gradation of the pixel is applied to the gate of the transistor, the transistor supplies a current corresponding to the voltage between the gate and the source to the light emitting element. Thereby, the light emitting element emits light with a luminance corresponding to the gradation. At this time, if the characteristics of the transistor such as the threshold voltage deviate in each pixel circuit, display unevenness that deteriorates the consistency of the display image occurs.

[0004] Therefore, a technology of compensating the characteristics of the transistor of the pixel circuit has been proposed (for example, refer to Patent Literature 1).

[0005] Patent Literature 1: Japanese Patent Application Publication No. 2011-53635

[0006] However, in the case of displaying a color image with the electro-optical device, the electro-optical element is configured to correspond to, for example, any one of RGB, and the color of one point is expressed by the light emission of three electro-optical elements corresponding to RGB. SUMMARY

[0007] One of the objects of several embodiments of the present application is to provide a technology capable of solving the problems when displaying a color image.

[0008] To achieve the above object, the electro-optical device according to the aspect of the present application is characterized by comprising: a plurality of scan lines; a plurality of data lines; a first pixel circuit provided corresponding to a position where one of the plurality of scan lines and a first data line of the plurality of data lines intersect; a second pixel circuit provided corresponding to a position where the one of the plurality of scan lines and a second data line of the plurality of data lines intersect; a first level shift unit circuit that shifts a potential of a first data signal supplied to a first input terminal corresponding to the first data line at a first compression rate, and supplies the first data signal to the first data line when the one of the plurality of scan lines is selected; and a second level shift unit circuit that shifts a potential of a second data signal supplied to a second input terminal corresponding to the second data line at a second compression rate different from the first compression rate, and supplies the second data signal to the second data line when the one of the plurality of scan lines is selected, the first pixel circuit and the second pixel circuit each including: a light emitting element; and a drive transistor that supplies a current corresponding to a voltage between a gate and a source when the one of the plurality of scan lines is selected to the light emitting element.

[0009] According to the aspect of the present application, even if a potential amplitude of the first data signal is the same as a potential amplitude of the second data signal, the potential amplitude when supplied to the first data line and the potential amplitude when supplied to the second data line can be made different from each other.

[0010] In the above aspect, the first structure can be such that a first holding section that holds a potential of the first data line and a second holding section that holds a potential of the second data line are provided, the first level shift circuit includes a first capacitor element electrically interposed between the first input terminal and the first data line, and a third holding section that holds a potential of the first input terminal, and the second level shift circuit includes a second capacitor element electrically interposed between the second input terminal and the second data line, and a fourth holding section that holds a potential of the second input terminal.

[0011] In the above aspect, the second structure can be such that a first holding section that holds a potential of the first data line and a second holding section that holds a potential of the second data line are provided, the first level shift circuit includes a first capacitor element electrically interposed between the first input terminal and the first data line, and the second level shift circuit includes a second capacitor element electrically interposed between the second input terminal and the second data line.

[0012] In addition, in the above-described aspect, the multi-path signal separator can be configured to supply, as the first data signal, a data signal supplied to the common terminal to the first input terminal during a first period, and to supply, as the second data signal, the data signal supplied to the common terminal to the second input terminal during a second period different from the first period, and the first pixel circuit and the second pixel circuit can correspond to mutually different colors.

[0013] According to this configuration, the first pixel circuit and the second pixel circuit correspond to mutually different colors, and even if the potential amplitude of the first data line and the potential amplitude of the second data line are different, the data signal supplied to the common terminal can be distributed by the multi-path signal separator.

[0014] In the above-described configuration, it is preferable that the first data signal and the second data signal be signals obtained by converting digital data of the same number of bits into analog signals.

[0015] Thus, even if the potential amplitude of the first data line and the potential amplitude of the second data line are different, a D / A converter that converts digital data into an analog signal can be shared.

[0016] Further, in the aspect of the present application, a driving method of an electro-optical device, an electronic device having the electro-optical device, in addition to the electro-optical device, can be adopted. As the electronic device, a display device such as a head-mounted display (HMD), an electronic viewfinder, and the like can be typically cited. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 is a perspective view showing the configuration of an electro-optical device to which an embodiment of the present application relates.

[0018] Figure 2 is a view showing the configuration of the electro-optical device.

[0019] Figure 3 is a view showing a pixel circuit in the electro-optical device.

[0020] Figure 4 is a timing chart showing the operation of the electro-optical device.

[0021] Figure 5 is an operation explanatory view of the electro-optical device.

[0022] Figure 6 is an operation explanatory view of the electro-optical device.

[0023] Figure 7 is an operation explanatory view of the electro-optical device.

[0024] Figure 8is an explanatory diagram of the operation of the electro-optical device.

[0025] Figure 9 is a diagram showing an equivalent circuit of the periphery of a data line in the electro-optical device.

[0026] Figure 10 is a diagram showing various capacitances in the equivalent circuit.

[0027] Figure 11 is a diagram simply showing the operation of various capacitances in the equivalent circuit.

[0028] Figure 12 is a diagram showing the potential and the like of each section in the various capacitances.

[0029] Figure 13 is a diagram showing a setting condition of level shift in the electro-optical device.

[0030] Figure 14 is a diagram showing the characteristics of a transistor in the electro-optical device.

[0031] Figure 15 is a perspective view of an HMD using the electro-optical device involved in the embodiments and the like.

[0032] Figure 16 is a diagram showing the optical configuration of the HMD.

[0033] Figure 17 is a diagram showing the voltage required for each RGB of the OLED. DETAILED DESCRIPTION

[0034] Hereinafter, with reference to the drawings, a mode for carrying out the present application will be described.

[0035] Figure 1 is a perspective view showing the configuration of an electro-optical device 10 involved in the embodiments of the present application.

[0036] The electro-optical device 10 is, for example, a micro display that displays a color image in an HMD (Head Mount Display) or the like. The details of the electro-optical device 10 will be described later, and is an organic EL device in which a plurality of pixel circuits, a drive circuit that drives the pixel circuit, and the like are formed in a semiconductor silicon substrate, for example, in which an OLED that is one example of a light emitting element is used in the pixel circuit.

[0037] The electro-optical device 10 is housed in a frame-shaped case 72 opened due to a display region, and one end of an FPC (Flexible Printed Circuits) substrate 74 is connected. A plurality of terminals 76 are provided at the other end of the FPC substrate 74, and connected to a higher-level circuit omitted from illustration. On the FPC substrate, a control circuit 5 of a semiconductor chip is mounted by a COF (Chip On Film) technique, and image (picture) data is supplied from the higher-level circuit in synchronization with a synchronization signal via the plurality of terminals 76. The synchronization signal includes a vertical synchronization signal, a horizontal synchronization signal, and a dot clock signal. In addition, the image data specifies a gradation of a pixel of an image to be displayed, for example, in 8 bits per RGB.

[0038] The control circuit 5 functions as a power supply circuit and a data signal output circuit of the electro-optical device 10. That is, the control circuit 5 supplies various control signals and various potentials (voltages) generated in accordance with the synchronization signal to the electro-optical device 10, and also converts digital image data into an analog data signal to supply to the electro-optical device 10.

[0039] The OLED corresponds to any one of R (red), G (green), and B (blue), and a 1-dot of a color image to be displayed is expressed by three pixels adjacent to each other. That is, in the present embodiment, the color of a 1-dot is expressed by additive color mixing by light emission of the OLED corresponding to RGB.

[0040] Although a detailed configuration of the OLED is omitted, in outline, a white organic EL layer is sandwiched by a pixel electrode (anode) provided for each pixel circuit and a common electrode (cathode) common to all of the pixel circuits and having light-transmitting properties. Further, a color filter corresponding to any one of RGB is overlapped on the emission side (cathode side) of the OLED. In such an OLED, if a current flows from the anode to the cathode, white light is generated in the organic EL layer. The white light generated at this time is transmitted through the cathode, and is visually confirmed on the observer side after coloring based on the color filter.

[0041] In such a configuration, even if a uniform voltage is applied between the anode and the cathode of the OLED to flow the same current throughout RGB, white (gray) cannot be expressed. The reason is mainly because the relative visual sensitivity differs by the wavelength region of RGB. In detail, even if the physical brightness of RGB is constant, the relative visual sensitivity of the human feeling of brightness differs in the order of G > R > B. Therefore, in the case of expressing white by light emission of the OLED, it is necessary to make the applied voltage when the OLED emits light at the highest brightness in the order of B > R > G in inverse proportion to the relative visual sensitivity.

[0042] Further, as a reason why the applied voltage to the OLED differs for each RGB, in addition to the relative visual sensitivity, the optical characteristics (wavelength / transmittance characteristics, cut-off frequency in the characteristics, etc.) of the color filter applied can be cited as differing for each RGB.

[0043] The applied voltage to the OLED, in other words the current flowing in the OLED, is as is well known determined by the potential of the data line at the time of selection by the scan line, in detail by the voltage between the gate and source of the transistor that supplies current to the OLED. Therefore, in the case where the applied voltage when causing the OLED to emit light at the highest brightness becomes higher in the order of B>R>G, the amplitude of the potential of the data line, in detail the amplitude from the potential of the data line in the darkest state to the potential of the data line in the brightest state, also becomes in the order of B>R>G in size.

[0044] Here, in the case where the gray scale of the pixel of the image that should be displayed is expressed in 256 gray scales (1677 million colors when viewed in 1 dot) for each RGB, for example, in 8 bits, the potential of the data line, in other words the gate potential of the above-mentioned transistor, needs to be carved in 256 gray scales for each RGB.

[0045] As mentioned above, the amplitude of the potential of the data line differs among RGB. Therefore, in the case where the D / A converter that converts the image data of RGB into an analog signal is shared among RGB, it is configured so that the maximum amplitude is specified in more than 8 bits, for example 10 bits, in a manner that the potential of the data line is carved in 256 gray scales even in the smallest amplitude.

[0046] In detail, as shown in Figure 17 , for the potential of the data line (the gate potential of the transistor), in order to carve in 256 gray scales even in the smallest amplitude of G (green), it is configured so that the maximum amplitude of B (blue) is specified in more than 8 bits, for example 10 bits (1024 gray scales), and 256 gray scales corresponding to the gray scale are selected therefrom. For R (red), G (green), 256 gray scales corresponding to the gray scale are appropriately selected from among those specified in 10 bits (1024 gray scales).

[0047] Here, in Figure 17 , the potential of the data line corresponding to the gray scale "0" (the smallest brightness) is marked as R(min), G(min), B(min) for each RGB, respectively. In addition, the potential of the data line corresponding to the gray scale "255" (the largest brightness) is marked as R(max), G(max), B(max) for each RGB, respectively. Here, the reason why it becomes R(min)>R(max), G(min)>G(max), B(min)>B(max) when viewed in potential is because the transistor that controls the current flowing in the OLED is set to the P-channel type as described later.

[0048] In such a configuration, it is necessary to convert 8 bits of digital data of a prescribed gray scale of RGB to 10 bits respectively before analog conversion by a D / A converter. This bit conversion is generally configured by referring to a look up table in which a correspondence before and after conversion is stored in advance.

[0049] However, in such a configuration, not only three look up tables of RGB are required as look up tables, but also a 10-bit transmission path is required, and the configuration becomes quite complicated.

[0050] In view of this, in the present embodiment, it is configured that the gray scale of RGB is commonly 8 bits, and the potential amplitude of a data signal after digital data of the 8 bits is converted is moved in a manner that is compressed at different rates according to a voltage applied to an OLED by RGB, and is supplied to a data line.

[0051] Figure 2 is a diagram showing a configuration of an electro-optical device 10 to which the embodiment relates. As shown in the diagram, the electro-optical device 10 generally includes a scan line drive circuit 20, a multiplexer 30, a level shift circuit 40, and a display portion 100.

[0052] In the display portion 100, pixel circuits 110 corresponding to pixels of an image to be displayed are arranged in a matrix. In detail, in the display portion 100, m rows of scan lines 12 are provided to extend in the horizontal direction in the diagram, and, for example, (3n) columns of data lines 14 are provided to extend in the vertical direction in the diagram in groups of 3 columns each, and are provided to cross the respective scan lines 12 while maintaining electrical insulation therefrom. Further, the pixel circuits 110 are provided at positions corresponding to the intersections of the m rows of scan lines 12 and the (3n) columns of data lines 14.

[0053] Here, m and n are both natural numbers. In order to distinguish the rows in the matrix of the scan lines 12 and the pixel circuits 110, the rows are sometimes referred to as 1, 2, 3, …, (m-1), m rows in order from the top to the bottom in the diagram. Similarly, in order to distinguish the columns in the matrix of the data lines 14 and the pixel circuits 110, the columns are sometimes referred to as 1, 2, 3, …, (3n-1), (3n) columns in order from the left to the right in the diagram. Further, in order to generalize the groups of the data lines 14, if an integer j of 1 or more and n or less is used, the data lines 14 of the (3j-2)th column, the (3j-1)th column, and the (3j)th column belong to the jth group from the left.

[0054] Among them, the three pixel circuits 110 corresponding to the intersection of the same row of the scan line 12 and the three data lines 14 belonging to the same group correspond to the pixels of R, G, and B, respectively. Therefore, in the present embodiment, the matrix arrangement of the pixel circuits 110 is m rows by (3n) columns in the vertical direction, and m rows by n columns in the horizontal direction from the point of view of the pixel arrangement of the display image.

[0055] For the convenience of explanation, for example, when the (3j-2)th column of the data line 14 corresponding to R is set as the first data line, the (3j-1)th column of the data line 14 corresponding to G is referred to as the second data line. For the pixel circuit 110, the pixel circuit corresponding to the data line 14 of R (first data line) becomes the first pixel circuit, and the pixel circuit corresponding to the data line 14 of G (second data line) becomes the second pixel circuit.

[0056] The electro-optical device 10 is supplied with the following control signals from the control circuit 5. Specifically, the electro-optical device 10 is supplied with a control signal Ctr for controlling the scan line drive circuit 20; control signals Sel(l), Sel(2), Sel(3) for controlling the selection in the multiplexer 30; control signals / Sel(l), / Sel(2), / Sel(3) in a logically inverted relationship with these signals; control signals Gini, Gref, Gcpl for controlling the level shift circuit 40; and a control signal / Gcpl in a logically inverted relationship with the control signal Gcpl. Among them, the control signal Ctr actually includes a plurality of signals such as a pulse signal, a clock signal, and an enable signal.

[0057] In addition, the data signals Vd_1, Vd_2,..., Vd_n are supplied from the control circuit 5 to the electro-optical device 10 via the common terminals 78 corresponding to the 1st, 2nd,..., nth groups in accordance with the selection timing of the multiplexer 30.

[0058] Here, in the present embodiment, when the gradation levels prescribed in accordance with the gradation of the pixel to be displayed are designated, for example, as a range from the darkest 0 level to the brightest 255 level, the data signals Vd_1 to Vd_n can be obtained in stages in a range from the potential V(0) corresponding to the 0 level to the potential V(255) corresponding to the 255 level. Here, because the transistor that controls the current to the OLED is of the P-channel type, the brighter the gradation level designated, the lower the data signal from the potential V(0). Among them, for the convenience of explanation, the potential of the data signal in the case where the gradation level "s" is designated is denoted as V(s). Here, s is any one of 0, 1, 2, 3,..., 255.

[0059] In addition, a holding capacitor 50 is provided for each data line 14. One end of the holding capacitor 50 is connected to the data line 14, and the other end of the holding capacitor 50 is commonly connected to a supply line 16 of a fixed potential, for example, potential Vorst. Thus, the holding capacitor 50 functions as a holding section that holds the potential of the data line 14.

[0060] In this case, the holding capacitor 50 corresponding to the data line 14 of R (first data line) becomes a first holding section, and the holding capacitor 50 corresponding to the data line 14 of G (second data line) becomes a second holding section.

[0061] As the holding capacitor 50, a parasitic capacitor of the data line 14 can be used, and a combined capacitor of the parasitic capacitor and a capacitor element formed by sandwiching an insulator (dielectric) with a wiring constituting the data line 14 and a wiring provided separately can also be used. Here, the capacitance of the holding capacitor 50 is denoted as Cdt.

[0062] The scan line drive circuit 20 generates a scan signal for sequentially scanning the scan lines 12 by one row during a period of a frame in accordance with a control signal Ctr. Here, the scan signals supplied to the scan lines 12 of the 1st, 2nd, 3rd,..., (m-1)st, and mth rows are denoted as Gwr(l), Gwr(2), Gwr(3),..., Gwr(m-1), and Gwr(m), respectively.

[0063] In addition, the scan line drive circuit 20 generates various control signals synchronized with the scan signals Gwr(l) to Gwr(m) by one row in addition to the scan signals Gwr(l) to Gwr(m) and supplies them to the display section 100, but the illustration thereof is omitted in Figure 2 The period of a frame means a time required for the electro-optical device 10 to display an image of one shot (picture) size, for example, 8.3 milliseconds of one cycle size of a vertical synchronization signal included in a synchronization signal at a frequency of 120 Hz.

[0064] The multiplexer 30 is a collection of transmission gates 34 provided by one column. The input terminals of the transmission gates 34 corresponding to the (3j-2)th, (3j-1)th, and (3j)th columns belonging to the jth group are commonly connected to the common terminal 78, and the data signal Vd_j is supplied thereto in a time-division manner.

[0065] The transfer gate 34 in the jth group provided in the (3j-2)th column as a left end column is turned on (conducts) when the control signal Sel(l) is at the H level, i.e., the control signal / Sel(l) is at the L level, during the first period. Likewise, the transfer gate 34 in the jth group provided in the (3j-l)th column as a center column is turned on when the control signal Sel(2) is at the H level, i.e., the control signal / Sel(2) is at the L level, during the second period, and the transfer gate 34 in the jth group provided in the (3j)th column as a right end column is turned on when the control signal Sel(3) is at the H level, i.e., the control signal / Sel(3) is at the L level.

[0066] The level shift circuit 40 is a device that shifts the potential of a data signal output from the output terminal of the transfer gate 34 of each column, in which the amplitude of the potential of the data signal is compressed. Therefore, the level shift circuit 40 has, per column, a group of a holding capacitor 41, a transfer gate 42, an N-channel transistor 43, a holding capacitor 44, and a P-channel transistor 45.

[0067] Among them, for the level shift circuit 40, the holding capacitor 41, the transfer gate 42, the transistor 43, the holding capacitor 44, and the transistor 45 corresponding to the column of R become a first level shift unit circuit, and the holding capacitor 41, the transfer gate 42, the transistor 43, the holding capacitor 44, and the transistor 45 corresponding to the column of G become a second level shift unit circuit, in the case of distinguishing by column.

[0068] In each column, the output terminal of the transfer gate 34 of the multiplexer 30 is connected to a node n in each column of the level shift circuit 40. Here, the node n is a connection point of one end of the holding capacitor 41 and the input terminal of the transfer gate 42 in the level shift circuit 40.

[0069] Among them, for the node n, the node corresponding to the column of R becomes a first input terminal, and the node corresponding to the column of G becomes a second input terminal, in the case of distinguishing by column.

[0070] The other end of the holding capacitor 41 is commonly grounded as a fixed potential Gnd in each column. In the case of distinguishing by column, the holding capacitor 41 corresponding to the data line 14 (first data line) of R becomes a third holding section, and the holding capacitor 41 corresponding to the data line 14 (second data line) of G becomes a fourth holding section. For ease of explanation, the capacitance of the holding capacitor 41 is set to Cref2.

[0071] Further, for the voltage, the potential Gnd is set to 0 volts as a reference, as long as it is not particularly limited like the voltage across both ends of the holding capacitor, the voltage across the gate / source, and the voltage across the anode / cathode of the OLED 130.

[0072] The transfer gate 42 of each column is turned on when the control signal Gcpl is at the H level (and turned off when the control signal Gcpl is at the L level). The output of the transfer gate 42 is connected to the data line 14 via the holding capacitor 44.

[0073] Here, for the holding capacitor 44, one end is taken as the data line 14 side and the other end is taken as the transfer gate 42 side for the sake of explanation. At this time, one end of the holding capacitor 44 is connected to the drain node of the transistor 45 in addition to the data line 14, and the other end of the holding capacitor 44 is connected to the drain node of the transistor 43. Here, the capacitance of the holding capacitor 44 is taken as Crefl and the other end of the holding capacitor 44 is taken as node h for the sake of explanation. In addition, in the case where the holding capacitor 44 is distinguished by column, the holding capacitor 44 corresponding to the column of R becomes a first capacitive element and the holding capacitor 44 corresponding to the column of G becomes a second capacitive element.

[0074] For the transistor 43, the source node is commonly connected to a supply line 62 that supplies a potential Vref as a prescribed reference potential throughout the columns, and the gate node is commonly connected to a control line 64 that supplies a control signal Gref throughout the columns. Therefore, the node h and the supply line 62 are electrically connected when the control signal Gref is at the H level due to the turn-on of the transistor 45, and are not electrically connected when the control signal Gref is at the L level due to the turn-off of the transistor 45.

[0075] In addition, for the transistor 45, the source node is commonly connected to a supply line 61 that supplies a potential Vini as an initial potential throughout the columns, and the gate node is commonly connected to a control line 63 that supplies a control signal Gini throughout the columns. Therefore, the data line 14 and the supply line 61 are electrically connected when the control signal Gini is at the L level due to the turn-on of the transistor 45, and are not electrically connected when the control signal Gini is at the H level due to the turn-off of the transistor 45.

[0076] In the present embodiment, the scan line drive circuit 20, the multiplex signal separator 30, and the level shift circuit 40 are separated for the sake of explanation, but these components can be unified into a drive circuit that drives the pixel circuit 110.

[0077] Reference Signs Figure 3 The pixel circuit 110 will be described. Since each pixel circuit 110 is of the same configuration from an electrical aspect, the pixel circuit 110 of the i-th row (3j-2) column in the left end column of the j-th group will be described as an example here.

[0078] where i is a symbol that generally indicates the row in which the pixel circuit 110 is arranged, and is an integer of 1 or more and m or less.

[0079] like Figure 3 As shown, the pixel circuit 110 includes P-channel transistors 121-125, an OLED 130, and a holding capacitor 132. This pixel circuit 110 is supplied with a scan signal Gwr(i), control signals Gel(i), Gcmp(i), and Gorst(i). Here, the scan signal Gwr(i), control signals Gel(i), Gcmp(i), and Gorst(i) are supplied by the scan line drive circuit 20, each corresponding to the i-th row. Therefore, if it is the i-th row, the scan signal Gwr(i), control signals Gel(i), Gcmp(i), and Gorst(i) are also commonly supplied to the pixel circuits of the columns other than the (3j-2) columns being viewed. Furthermore, the pixel circuits 110 of rows other than the i-th row are supplied with the scan signal and control signal corresponding to that row.

[0080] In the pixel circuit 110 of row i (3j-2) columns, transistor 122 is equivalent to a selection transistor. Its gate node is connected to the scan line 12 of row i, and one of its drain or source nodes is connected to the data line 14 of column (3j-2). The other node is connected to the gate node of transistor 121, one end of holding capacitor 132, and the drain node of transistor 123, respectively. Here, the gate node of transistor 121 is marked as g to distinguish it from other nodes.

[0081] In transistor 121, the source node is connected to power supply line 116, and the drain node is connected to the source nodes of transistors 123 and 124, respectively. Here, the potential Vel, which serves as the high-side power supply in pixel circuit 110, is supplied to power supply line 116.

[0082] Additionally, the drain node of transistor 121 is electrically connected to the anode Ad of OLED 130 via transistor 123. When transistor 121 operates in the saturation region, it supplies current to OLED 130 corresponding to the voltage between the gate and source.

[0083] Therefore, transistor 121 is equivalent to a driving transistor.

[0084] The control signal Gcmp(i) is supplied to the gate node of transistor 123.

[0085] In transistor 124, the gate node is supplied with a control signal Gel(i), and the drain node is connected to the source node of transistor 125 and the anode Ad of OLED 130, respectively.

[0086] In transistor 125, the gate node is supplied with the control signal Gorst(i) corresponding to the i-th row, and the drain node is connected to the power supply line 16 supplying the potential Vorst.

[0087] Further, in the transistors 121 to 125, although the drain node or the source node is described as being electrically connected to other constituent elements, in the case where the potential relationship is changed, the node described as the drain node can become the source node, and the node described as the source node can become the drain node. For example, the source node and either one of the drain nodes of the transistor 121 can be electrically connected to the power supply line 116, and the arbitrary other one can be electrically connected to the anode Ad of the OLED 130 via the transistor 123.

[0088] The other end of the holding capacitor 132 is connected to the power supply line 116. Thus, the holding capacitor 132 holds the voltage between the gate and the source of the transistor 121. Here, the capacitance of the holding capacitor 132 is denoted as Cpix.

[0089] Here, as the holding capacitor 132, a parasitic capacitance of the gate node g of the transistor 121 can be used, or a capacitor formed by sandwiching an insulating layer with mutually different conductive layers on a silicon substrate can be used.

[0090] Further, in the present embodiment, because the electro-optical device 10 is formed on a silicon substrate, the substrate potential of the transistors 121 to 125 is Figure 3 is omitted, but is set to the potential Vel.

[0091] In the pixel circuit 110, the anode Ad of the OLED 130 is a pixel electrode which is provided independently for each pixel circuit 110. In contrast to this, the cathode of the OLED 130 is a common electrode 118 which is common to all of the pixel circuits 110, and is held at the potential Vct which is the low side of the power supply in the pixel circuit 110.

[0092] In the above-described silicon substrate, the OLED 130 is an element which sandwiches a white organic EL layer with an anode and a cathode having light-transmitting properties, and a color filter corresponding to the color of RGB is overlapped on the emission side (cathode side) of the OLED 130. In such an OLED 130, if a current flows from the anode to the cathode, holes injected from the anode and electrons injected from the cathode recombine in the organic EL layer to generate an exciton, and white light is generated. The white light generated at this time is transmitted through the cathode on the side opposite to the silicon substrate (anode), and is colored based on the color filter, so that it is visible on the observer side.

[0093] Here, as a stage before the potential shift of the data signal is described, an equivalent circuit from the node n in the level shift circuit 40 to the data line 14 and the gate node g is described.

[0094] Figure 9 is a signal line which is connected to the gate node g of the transistor 121 of the (3j - 2)th column (refer to FIG. 1). Figure 2Fig. 2 is a diagram of an equivalent circuit of the level shift circuit 40, the data line 14, and the pixel circuit 110 in the i-th row (3j-2)-th column during which the transistor 122 in the pixel circuit 110 is turned on, i.e., during the compensation period to be described later.

[0095] As shown in this figure, the hold capacitor 132 in the pixel circuit 110 and the hold capacitors 44, 50 of the (3j-2)-th column can be represented by a resultant capacitance Cl. Here, as in formula (1) in Figure 10

[0096] In addition, at times the capacitance Cpix is so small relative to the capacitances Crefl, Cdt that it can be ignored. In this case, the capacitance Cl represented by formula (1) can be approximated as Crefl•Cdt / (Crefl+Cdt).

[0097] In addition, for ease of explanation, as in formula (2) in Figure 10

[0098] In the present embodiment, k is represented as a ratio of the capacitance C2 to the sum of the resultant capacitance Cl and the capacitance C2, as in the following formula (3).

[0099] k = C2 / (Cl + C2)... (3)

[0100] <Operation of Embodiment>

[0101] Referring to Figure 4 The operation of the electro-optical device 10 will be described. Figure 4 is a timing chart for describing the operation of each part in the electro-optical device 10.

[0102] As shown in this figure, the scan signals Gwr(l) to Gwr(m) are sequentially switched to the L level, and the scan lines 12 of the 1st to m-th rows are sequentially scanned per horizontal scan period (H) during 1 frame.

[0103] The operation in 1 horizontal scan period (H) is the same in the pixel circuits 110 of each row. In view of this, the operation will be described below in the scan period in which the i-th row is horizontally scanned, with particular attention to the pixel circuit 110 of the i-th row (3j-2)-th column.

[0104] In the present embodiment, the scan period of the i-th row is as in Figure 4 ​​As shown, the period is roughly divided into: (b) the initialization period, (c) the compensation period, and (d) the writing period. Further, after the writing period (d), an interval is provided to become the light emission period shown in (a), and after the period of 1 frame, the scanning period of the i-th row is reached again. Thus, in terms of time sequence, the cycle of (light emission period) -> initialization period -> compensation period -> writing period -> (light emission period) is repeated repeatedly.

[0105] wherein, in Figure 4 the scanning signal Gwr(i-1), the control signal Gel(i-1), Gcmp(i-1), Gorst(i-1) corresponding to the (i-1)-th row which is one row before the i-th row become waveforms which are 1 horizontal scanning period (H) earlier in time than the scanning signal Gwr(i), the control signal Gel(i), Gcmp(i), Gorst(i) corresponding to the i-th row.

[0106] <light emission period>

[0107] For ease of explanation, the light emission period which is a prerequisite for the initialization period will be described. As shown in Figure 4 the light emission period of the i-th row, the scanning signal Gwr(i) is at the H level. Further, of the control signals Gel(i), Gcmp(i), Gorst(i) which are logic signals, the control signal Gel(i) is at the L level, and the control signals Gcmp(i), Gorst(i) are at the H level.

[0108] Thus, as shown in Figure 5 the pixel circuit 110 of the i-th row (3j-2)-th column, the transistor 124 is on, and on the other hand, the transistors 122, 123, 125 are off. Thus, the current Ids corresponding to the voltage Vgs between the gate and the source in the transistor 121 is supplied to the OLED 130. As will be described later, in the present embodiment, the voltage Vgs in the light emission period is a value which has moved from the threshold voltage of the transistor 121 by an amount corresponding to the potential shift amount of the node h, and the potential shift amount of the node h is determined by the potential of the data signal and the constant potential Vre. Thus, the current corresponding to the gradation is supplied to the OLED 130 in a state in which the threshold voltage of the transistor 121 is compensated.

[0109] Further, because the light emission period of the i-th row is a period in which the i-th row is scanned horizontally, the potential of the data line 14 is changed appropriately. However, in the pixel circuit 110 of the i-th row, because the transistor 122 is off, the potential fluctuation of the data line 14 does not need to be considered here.

[0110] Further, in Figure 5 the important paths in the operation explanation are shown in bold lines (hereinafter, the Figures 6-8(The same applies to China).

[0111] During initialization

[0112] Next, if the scan period reaches the i-th row, then the initialization period of (b) begins. Figure 4 As shown, compared with the emission period of (a), during the initialization period of (b), the control signal Gel(i) becomes H level and the control signal Gorst(i) becomes L level.

[0113] Therefore, as Figure 6 As shown, in the pixel circuit 110 of row i (3j-2) column, transistor 124 is turned off and transistor 125 is turned on. As a result, the path of current Ids supplied to OLED 130 is cut off, and the anode Ad of OLED 130 is reset to potential Vorst.

[0114] As described above, because the OLED 130 is constructed by holding the organic EL layer between the anode (Ad) and cathode, a parasitic capacitance (Coled) is connected in parallel between the anode and cathode, as shown by the dotted line in the figure. During light emission, when current flows through the OLED 130, the voltage across the anode and cathode of the OLED 130 is maintained by this capacitance (Coled), and this maintained voltage is reset when the transistor 125 is turned on. Therefore, in this embodiment, when current flows through the OLED 130 again during a subsequent light emission period, it is less susceptible to the influence of the voltage maintained by this capacitance (Coled).

[0115] In detail, for example, if the display does not reset when transitioning from a high-brightness to a low-brightness state, the high voltage during high brightness (i.e., when a large current flows) is maintained by the capacitor Coled. Therefore, even if a small current is to flow subsequently, excessive current will flow, making it difficult to achieve the desired low-brightness display state. In contrast, in this embodiment, because the potential of the anode Ad of the OLED 130 is reset by turning on the transistor 125, it is easy to achieve the desired low-brightness display state.

[0116] Furthermore, in this embodiment, the potential Vorst is set such that the difference between Vorst and the potential Vct of the common electrode 118 is lower than the light emission threshold voltage of the OLED 130. Therefore, during initialization (the compensation period and the write period described below), the OLED 130 is in an off (non-light-emitting) state.

[0117] On the other hand, during initialization, the control signal / Gini becomes low level, the control signal Gref becomes high level, and the control signal Gcpl becomes low level (the control signal / Gcpl becomes high level). Therefore, in the level shifting circuit 40, as... Figure 6As shown, transistors 45 and 43 are turned on, and transmission gate 42 is turned off. Therefore, data line 14, which is one end of holding capacitor 44, is initialized to potential Vini, and node h, which is the other end of holding capacitor 44, is initialized to potential Vref.

[0118] Furthermore, in this embodiment, the potential Vref is set to be consistent with the potential V(0) which is the highest value of the data signal, i.e., V(0) = Vref…(4).

[0119] Furthermore, in this embodiment, the control circuit 5 supplies data signals during the initialization period of (b) to the compensation period of (c) as follows. That is, taking the j-th group as an example, the control circuit 5 sequentially switches the data signal Vd_j to the potential after transforming the 8-bit digital data of the grayscale level of the pixels in the specified i-th row (3j-2), i-th row (3j-1), and i-th row (3j) columns. On the other hand, according to the switching of the data signal potential, the control signals Sel(1), Sel(2), and Sel(3) are sequentially and exclusively set to H level. Thus, in the multiplexer 30, the transmission gates 34 in each group are turned on in the order of the left column, the middle column, and the right column, respectively.

[0120] Here, during initialization, when the transmission gate 34 belonging to the left column of the j-th group is turned on based on the control signal Sel(1), as follows: Figure 6 As shown, the data signal Vd_j is supplied to node n, which is one end of the holding capacitor 41, and is held by the holding capacitor 41.

[0121] During initialization (and subsequent compensation), the control signal Gcpl is at level L because the transmission gates 42 in each column are open, so the supply of data signals does not affect the potential of node h.

[0122] In this embodiment, the potential Vini is set to be smaller than the value of the threshold voltage |Vth| of transistor 121 minus the potential Vel from the high-side of the power supply, that is, it is set to Vini < Vel - |Vth|...(5).

[0123] As described above, transistor 121 is a P-channel type. In transistor 121, the threshold voltage Vth, which is based on the potential of the source node, is negative. To prevent confusion in the description of high and low relationships, the threshold voltage is represented by the absolute value |Vth| and specified in terms of magnitude.

[0124] <Compensation Period>

[0125] During the scan period of the i-th row, the compensation period of (c) follows the initialization period of (b). Figure 4As shown, in the compensation period (c), the scan signal Gwr(i) and the control signal Gcmp(i) become the L level, and the control signal Gref is maintained at the H level, and the control signal Gini becomes the H level.

[0126] Thus, as Figure 7 As shown, in the level shift circuit 40, because the transistor 43 continues to be on, the node h is maintained at the potential Vref.

[0127] On the other hand, because the transistor 45 is off, the transistor 122 in the pixel circuit 110 of the i row (3j - 2) column is on, so that the gate node g is electrically connected to the data line 14, and the path from the data line 14 to the gate node g initially becomes the potential Vini at the start of the compensation period.

[0128] Here, because the transistor 12 is on in the compensation period, the transistor 121 becomes a diode connection. In addition, the path from the data line 14 to the gate node g initially is the potential Vini satisfying the equation (5) at the start of the compensation period.

[0129] Thus, the drain current flows through the transistor 121, and the gate node g and the data line 14 are charged. In detail, the current flows in the path of the supply line 116 → the transistor 121 → the transistor 123 → the transistor 122 → the data line 14 of the (3j - 2) column. Thus, the path from the data line 14 to the gate node g, which is in the state of being connected to each other due to the on of the transistor 121, rises from the potential Vini.

[0130] However, because the current flowing in the above path is difficult to flow as the gate node g approaches the potential (Vel - |Vth|), the data line 14 and the gate node g are saturated at the potential (Vel - |Vth|) until the end of the compensation period. Thus, the voltage held by both ends of the holding capacitor 132, that is, the voltage between the gate and the source of the transistor 121 becomes the threshold voltage |Vth| of the transistor 121 until the end of the compensation period.

[0131] Figure 11 is a diagram for explaining the potentials of the node n, the node h, and the gate node g in the compensation period and the write period.

[0132] In the compensation period, because the control signal Gcpl is the L level following the initialization period (because the control signal Gcpl is the H level), the transmission gate 42 is off. In addition, the data signal Vd_j supplied via the multiplex signal separator 30 is held by the holding capacitor 41. At this time, if the potential of the data signal Vd_j is Vdata, as Figure 11(a) As shown, the node n, which is one end of the holding capacitor 41, becomes the potential Vdata.

[0133] where the other end of the holding capacitor 44, i.e., the node h, which is one end of the synthetic capacitor Cl, becomes the potential Vref due to the turn-on of the transistor 43. Further, at the end of the compensation period, as described above, and as shown in Figure 11 (b) As shown, the gate node g is saturated at the potential (Vel - |Vth|).

[0134] <Write period>

[0135] In the scan period of the i-th row, the compensation period of (c) becomes the write period of (d) after that. As shown in Figure 4 In the write period of (d), the control signal Gref becomes the L level, and on the other hand, the control signal Gcpl becomes the H level (the control signal / Gcpl becomes the L level).

[0136] Further, in the present embodiment, the control signals Sel(l), Sel(2), Sel(3) do not become the H level (the control signals / Sel(l), / Sel(2), / Sel(3) do not become the L level) in the write period.

[0137] Therefore, as shown in Figure 8 In each column, since the pass transistor 42 is turned on in the state where the pass transistor 34 is turned off, the node h, which is one end of the synthetic capacitor Cl, moves from the potential Vref in the compensation period.

[0138] Here, the movement of the potential at the node h is described with reference to Figure 11 (c) In the write period, due to the turn-on of the pass transistor 42, the node n and the node h become the same potential Vnode.

[0139] Therefore, since the charge accumulated by the holding capacitor 41, and in detail, the charge corresponding to the product of the potential Vdata and the capacitor C2, is redistributed to the synthetic capacitor Cl, which has accumulated the charge corresponding to the potential Vref, and the capacitor C2 itself due to the turn-on of the pass transistor 42, the following equation (6) holds. Figure 12

[0140] If the equation (6) is solved with respect to Vnode, it can be expressed as shown in the equation (7) in the figure.

[0141] Here, when the amount of movement of the potential from the initialization period to the write period of the node h is set as ΔVh, Vnode can be expressed as shown in the equation (8).

[0142] ​Here, for the potential shift amount ΔVh, when the rising direction is set to be positive, in the present embodiment, since the falling direction is changed, it is negative.

[0143] If the potential shift amount ΔVh is calculated from the formula (7) and the formula (8), the formula (9) is derived. When C2 / (C1+C2) in the formula (9) is set to the ratio k as shown in the formula (3), the potential shift amount ΔVh at the node h can be expressed as the formula (10).

[0144] Further, during the writing period, as shown in Figure 4 , the control signal Gcmp(i) is H level. Therefore, as shown in Figure 8 , the diode connection of the transistor 121 is released. On the other hand, the gate node g continues to be connected to one end of the holding capacitor 44 via the data line 14 from the state during the compensation period. Therefore, the gate node g moves from the potential (Vel-|Vth|) during the compensation period by the potential shift amount ΔVh at the node h multiplied by the value of the coefficient p.

[0145] Here, if referring to Figure 11 (d), for the potential shift amount ΔVg, since it becomes a value in which the potential shift amount ΔVh at the node h is divided by the parallel capacitance (Cdt+Cpix) of the holding capacitors 50, 132 and the capacitance Cref1 of the holding capacitor 44, it can be expressed as the formula (11). Figure 12

[0146] That is, as shown in the formula (11), the potential shift amount ΔVg is determined by the capacitances Cdt, Cref1, Cpix, and the potential shift amount ΔVh at the node h. The potential shift amount ΔVh is determined by the potentials Vdata, Vref, and the ratio k as shown in the formula (10). Here, the potential Vdata is the potential of the data signal, which changes from V(0) corresponding to the gray scale "0" to V(255) corresponding to the gray scale "255" in stages, and since it is a constant value other than this, the potential shift amount ΔVg is determined in correspondence with the gray scale.

[0147] If the coefficient of ΔVh in the formula (11) is set to p, the potential shift amount ΔVg at the gate node g can be expressed as the formula (12) in a simplified manner. Therefore, the potential Vg of the moved gate node g can be expressed as the formula (13) or the formula (14). Figure 11 (d), or Figure 12

[0148] ​​The potential shift amount AVg at the gate node g can be expressed as formula (13) from formula (9) and formula (11). When the rising direction of the potential shift amount AVg is set as positive, in this embodiment, the same as the potential shift amount AVh, because it changes in the falling direction, it is negative.

[0149] In addition, at the end of the compensation period, the voltage Vgs of the transistor 121 becomes the shift value of the potential shift amount of the gate node g from the threshold voltage |Vth| (|Vth| - p AVh).

[0150] <Light emission period>

[0151] After the end of the write period of the i-th row, the time interval of 1 horizontal scanning period reaches the light emission period. In this light emission period, since the signal Gel(i) is controlled to be the L level as described above, in the pixel circuit 110 of the i-th row (3j-2)th column, the transistor 124 is turned on.

[0152] The voltage Vgs between the gate and the source is (|Vth| - p AVh), which is a value shifted from the threshold voltage of the transistor 121 by an amount corresponding to the potential of the data signal. Therefore, as in the Figure 5 As shown, the current corresponding to the gray scale is supplied to the OLED 130 in a state in which the threshold voltage of the transistor 121 is compensated.

[0153] Such an operation from the initialization period to the light emission period is also performed in time series in the other pixel circuits 110 of the i-th row except for the pixel circuit 110 of the (3j-2)th column in the scanning period of the i-th row. However, in the multiplex signal separator 30, since the selection signals Sel(1), Sel(2), Sel(3) become the H level in this order, if it is said in terms of the j-th group, the potential of the data signal is held by the hold capacitor 41 in the order of the 3(j-2)th column, the 3(j-1)th column, and the (3j)th column.

[0154] Also, such an operation of the i-th row is actually performed in the order of the 1st, 2nd, 3rd,..., (m-1)th, and m-th rows in the period of 1 frame, and is repeated every frame.

[0155] In this embodiment, since the current Ids supplied from the transistor 121 to the OLED 130 can offset the influence of the threshold voltage, even if the threshold voltage of the transistor 121 has a deviation for each pixel circuit 110, the deviation is compensated, and the current corresponding to the gray scale is supplied to the OLED 130. Therefore, according to this embodiment, it is possible to suppress the generation of display unevenness such as the consistency of the display image, and as a result, it is possible to achieve high-quality display.

[0156] Reference Signs List Figure 14The compensation will be described. As shown in the figure, the transistor 121 operates in a weak inversion region (subthreshold region) in order to control a minute current supplied to the OLED 130.

[0157] In the figure, A indicates a transistor with a large threshold voltage |Vth|, and B indicates a transistor with a small threshold voltage |Vth|. Among them, in the transistor A, the threshold voltage |Vth| is large, and in the transistor B, the threshold voltage |Vth| is small. Figure 14 In the figure, the difference between the characteristic indicated by the solid line and the potential Vel is the voltage Vgs between the gate and the source. In addition, in the figure, the current of the vertical scale is indicated by a logarithm with the direction from the source toward the drain set as positive (up).

[0158] During the compensation, the gate node g changes from the potential Vini of the data line 14 to the potential (Vel - |Vth|). Therefore, in the transistor A with a large threshold voltage |Vth|, the operation point moves from S to Aa, and on the other hand, in the transistor B with a small threshold voltage |Vth|, the operation point moves from S to Ba.

[0159] Next, when the potential of the data signal to the pixel circuit 110 to which the two transistors belong is the same, that is, the same gray scale is designated, during the writing, the potential moving amount from the operation points Aa, Ba is the same |ΔVg| (= |p · ΔVh|). Therefore, for the transistor A, the operation point moves from Aa to Ab, and for the transistor B, the operation point moves from Ba to Bb, and regarding the current at the operation point after the potential moves, the transistors A, B are almost the same Ids and consistent.

[0160] In addition, in the present embodiment, regarding the amplitude of the data signal, the ratio (compression rate) of the amplitude of the potential of the data line 14 (gate node g) which is compressed is set to be different for each RGB column. In detail, the compression rate is higher in the order of G, R, B, that is, the amplitude of the potential of the data line 14 (gate node g) is smaller in the order of G, R, B.

[0161] Figure 13 is a figure indicating the relationship of the potential amplitude of the data signal, the potential amplitude of each RGB node h, and the potential amplitude of the gate node g. In the figure, the potential amplitude of the node h is indicated by a solid line, and the potential amplitude of the gate node g is indicated by a dashed line.

[0162] When the data signal Vd_j is supplied with the potential Vdata from the control circuit 5 as described above, the potential shift ΔVh at the node h is shown in Expression (10). Here, the potential Vdata of the data signal varies from V(0) to V(255). Among them, since the potential Vref is set to coincide with V(0) of the data signal as shown in Expression (4), the right side bracket of Expression (10) is 0 when the potential Vdata of the data signal is V(0). Therefore, if the potential of the data signal is V(0), since the potential shift ΔVh is also 0, the potential of the node h is not shifted from the potential (Vref) at the end of the compensation period as shown in Expression (11). Figure 13 As shown in Expression (12), the potential shift ΔVg of the gate node g is also 0 for each RGB.

[0163] Therefore, since the potential shift ΔVg shown in Expression (12) is also 0, the potential Vg of the gate node g shown in Expression (13) does not vary from the potential (Vel - |Vth|) at the end of the compensation period. Therefore, if the potential of the data signal is V(0), since no current flows in each color OLED 130 throughout the RGB during the light emission period, good black display can be achieved.

[0164] On the other hand, when the potential of the data signal is the lowest V(255), the potential shift ΔVh at the node h is shown in Expression (10) or Figure 13 As shown in Expression (12), the potential shift ΔVg of the gate node g is also 0 for each RGB. Figure 13 As shown in Expression (12), the potential shift ΔVg of the gate node g is also 0 for each RGB.

[0165] Since the potential shift ΔVg of the gate node g is also proportional to ΔVh of the right side of Expression (11), the potential of the gate node g is lowered with respect to Vref in the order of B, R, and G as shown in Expression (13). Figure 13 As shown in Expression (12), the potential shift ΔVg of the gate node g is also 0 for each RGB.

[0166] Therefore, even if the range from the potential V(0) to the potential V(255) as the potential amplitude of the data signal is common throughout the RGB, the potential amplitude of the gate node g is compressed to be different for each RGB with V(0), Vref as a reference. In other words, if the potential of the gate node g when the OLED emits light at the highest brightness is set, the potential amplitude of the data signal can be common in the RGB.

[0167] Here, because the potential shift ΔVg of the gate node g is shown by the equation (13), it is sufficient to set the coefficient part determined by the synthetic capacitance CI and the capacitance C2 (= Cref2) for each RGB.

[0168] For example, the potential shift ΔVh at the potential V(255) of the data signal corresponding to the gray scale "255" becomes the value of multiplying {V(255) - Vref} by the ratio kR, kG, kB of the capacitances for each RGB as shown in the equation (9) or Figure 13 Here, in the case where the synthetic capacitance CI is unified for each RGB, it is sufficient to set the capacitance Cref2 of the holding capacitance 41 according to the potential Vg of the gate node g required for each RGB in the manner of the ratio kG < kR < kB.

[0169] Thus, according to the present embodiment, because the data signal common to the RGB is level-shifted at different compression rates in the RGB to be supplied to the data line 14 and the gate node g, it is not necessary to process with the number of bits more than 8 bits of the prescribed gray scale. Therefore, according to the present embodiment, it is possible to avoid complication of the configuration.

[0170] Further, when the pixel circuit is miniaturized, the change of the drain current with respect to the voltage Vgs between the gate and the source in the transistor 121 changes in the manner of an exponential function, and in the present embodiment, because the potential amplitude of the data signal is compressed to be supplied to the data line 14 and the gate node g, it is possible to control the current supplied to the OLED 130 with high precision with respect to the potential change of the data signal.

[0171] Further, in the present embodiment, it is configured that the data signal supplied from the control circuit 5 during the initialization period and the compensation period is sequentially held by the holding capacitance 41 of 3 columns in each group, and is collectively potential-shifted to be supplied to the data line 14 of each column by the turn-on of the transfer gate 42 during the writing period. Therefore, in the present embodiment, it is configured that, regardless of the configuration of the data signal allocated by the multiplexer 30, because the data lines 14 of the same group are difficult to generate a difference when compared with each other, it is difficult to display unevenness.

[0172] <Applications, Modified Examples>

[0173] The present application is not limited to the above-described embodiments, application examples, and the like, and various modifications can be made, for example, as follows. Further, in the following modified examples, one or more of the arbitrary selection can be appropriately combined.

[0174] <Omission of the Capacitance Cref2>

[0175] In the embodiment, the holding capacitor 41 (capacitance Cref2) and the transfer gate 42 are provided in each column, but these components are not essential. This is because the potential of the data line 14 (gate node g) changes from the potential shift amount AVh at the node h via the holding capacitor 44, that is, the amount of shift of (Vdata - Vref) multiplied by the coefficient p in this configuration, as long as the potential of the data line 14 (gate node g) changes according to the potential change at the node h via the holding capacitor 44.

[0176] Even in the case where the holding capacitor 41 and the transfer gate 42 are not provided in each column, the potential Vg of the data line 14 (gate node g) moves from (Vel - |Vth|) at the end of the compensation period, that is, the amount of shift of (Vdata - Vref) multiplied by the coefficient p in this configuration, as shown in Expression (14). Here, the coefficient p is the coefficient part of AVh in the right side of Expression (11).

[0177] Therefore, when the capacitance Cpix of the holding capacitor 132 is small enough to be negligible in this configuration, it is sufficient to appropriately set the ratio of the capacitance Crefl to the capacitance Cdt.

[0178] Further, in the case where the holding capacitor 41 and the transfer gate 42 are not provided, it is configured to turn on the transfer gates 34 in each group in the order of the left end column, the center column, and the right end column to distribute the supply of the data signal during the write period. Therefore, in this configuration, the write period needs to be lengthened compared to the embodiment in which the transfer gates 42 are turned on all at once during the write period, and as a result, the compensation period is correspondingly shortened.

[0179] <Control circuit>

[0180] In the embodiment, the control circuit 5 that supplies the data signal is independent of the electro-optical device 10, but the control circuit 5 can also be integrated with the scan line drive circuit 20, the multiplex signal separator 30, and the level shift circuit 40 to a semiconductor silicon substrate.

[0181] <Substrate>

[0182] In the embodiment, the electro-optical device 10 is configured to be integrated to a semiconductor silicon substrate, but can also be integrated to other semiconductor substrates. For example, it can also be an SOI substrate. In addition, it can also be formed on a glass substrate or the like using a polysilicon process.

[0183] <Control signal Gcmp(i)>

[0184] In the embodiment, the control signal Gcmp(i) is set to the H level during the write period if it is the ith row, but can also be set to the L level. That is, it can also be configured to perform the threshold compensation achieved by turning on the transistor 123 in parallel with the write to the node gate g.

[0185] <Multiplex signal separator>

[0186] In the embodiment, the data lines 14 are grouped by every 3 columns, and the data lines 14 in each group are sequentially selected to supply the data signal, but the number of data lines constituting a group can also be "2", and can also be "4" or more.

[0187] In addition, even if the configuration in which the data signal is distributed by the multiplexer 30 is not adopted, a configuration in which the data signal supplied from the control circuit 5 is temporarily held in the holding capacitor 41, and then supplied to the data line 14 via the holding capacitor 44 by the ON of the transmission gate 42 can also be adopted. In addition, if the holding capacitor 41 and the transmission gate 42 are not provided, a configuration in which the data signal is supplied to the node h initialized to the potential Vref during the writing period can also be adopted.

[0188] <Channel type of transistor>

[0189] In the above embodiment and the like, the transistors 121 to 125 in the pixel circuit 110 are unified as P-channel type, but can also be unified as N-channel type. In addition, the P-channel type and the N-channel type can also be appropriately combined.

[0190] <Others>

[0191] In the embodiment and the like, in order to perform color display, the OLED is made to correspond to the three colors of RGB, but can also be, for example, four colors including Y (yellow), and can also be a color other than RGB. In addition, in a case where it is not necessary to display a full-color image, for example, in a case where it is necessary to display text information like an electric signboard, it can also be, for example, two colors of GR.

[0192] In the embodiment and the like, as the electro-optical element, the OLED as a light-emitting element is exemplified, but for example, a component that emits light at a luminance corresponding to a current, such as an inorganic light-emitting diode, an LED (Light Emitting Diode), or the like can also be used.

[0193] <Electronic device>

[0194] Next, an electronic device to which the electro-optical device 10 according to the embodiment and the like, and the application example are applied will be described. The electro-optical device 10 is used for a display use in which the pixel is small in size and high in precision. In view of this, an HMD will be described as an example of the electronic device.

[0195] Figure 15 is a diagram showing the appearance of the HMD, Figure 16 is a diagram showing the optical configuration thereof. First, as shown in Figure 15 on the appearance, the HMD 300 has a frame 310, a bridge 320, lenses 301L, 301R like ordinary glasses. In addition, as shown in Figure 16As shown, the HMD 300 is provided with the electro-optical device 10L for the left eye and the electro-optical device 10R for the right eye near the mirror beam 320 and inside (lower side in the drawing) of the lenses 301L, 301R.

[0196] The image display surface of the electro-optical device 10L is arranged on the left side in the drawing. Thus, the display image of the electro-optical device 10L is emitted toward the 9 o'clock direction in the drawing via the optical lens 302L. The half mirror 303L reflects the display image of the electro-optical device 10L toward the 6 o'clock direction, and on the other hand, transmits the light incident from the 12 o'clock direction. Figure 16

[0197] The image display surface of the electro-optical device 10R is arranged on the right side opposite to the electro-optical device 10L. Thus, the display image of the electro-optical device 10R is emitted toward the 3 o'clock direction in the drawing via the optical lens 302R. The half mirror 303R reflects the display image of the electro-optical device 10R toward the 6 o'clock direction, and on the other hand, transmits the light incident from the 12 o'clock direction.

[0198] In this configuration, the wearer of the HMD 300 can observe the display images of the electro-optical devices 10L, 10R in an intuitive state superimposed with the outside situation.

[0199] In addition, in this HMD 300, if the left eye image in the two-eye image accompanying the parallax is displayed on the electro-optical device 10L and the right eye image is displayed on the electro-optical device 10R, the wearer can feel that the displayed image has a sense of depth and a stereoscopic sense (3D display).

[0200] Further, the electro-optical device 10 can be applied to an electronic viewfinder in a video recorder, a lens exchangeable digital camera, and the like, in addition to the HMD 300.

[0201] REFERENCE NUMERALS: 10... electro-optical device; 12... scan line; 14... data line; 20... scan line drive circuit; 30... multiplexer; 40... level shift circuit; 41, 44, 50... holding capacitor; 100... display portion; 110... pixel circuit; 116... power supply line; 118... common electrode; 121-125... transistor; 130... OLED; 132... holding capacitor; 300... HMD.​

Claims

1. An electro-optical device, characterized in that, have: The control circuit converts digital image data into analog data signals containing a first data signal and a second data signal, and outputs the aforementioned data signals. The first transmission gate has a first input terminal and a first output terminal to be supplied with the aforementioned first data signal; The second transmission gate has a second input terminal and a second output terminal to which the aforementioned second data signal is supplied; The first holding capacitor has a first terminal that is electrically connected to the first output terminal of the first transmission gate. The second holding capacitor has a second terminal that is electrically connected to the second output terminal of the second transmission gate. The third transmission gate has a third input terminal and a third output terminal that are electrically connected to the first terminal of the first holding capacitor. The fourth transmission gate has a fourth input terminal and a fourth output terminal that are electrically connected to the second terminal of the second holding capacitor. The third holding capacitor has a third terminal and a fourth terminal that are electrically connected to the third output terminal of the third transmission gate. The fourth holding capacitor has a fifth terminal and a sixth terminal that are electrically connected to the fourth output terminal of the fourth transmission gate. The first data line is electrically connected to the fourth terminal of the third holding capacitor. The second data line is electrically connected to the sixth terminal of the fourth holding capacitor. The fifth holding capacitor has one end electrically connected to the first data line and the other end electrically connected to the power supply line; The sixth holding capacitor has one end electrically connected to the second data line and the other end electrically connected to the power supply line; Scan lines; The first pixel circuit is set at a first position corresponding to the intersection of the first data line and the scan line mentioned above. as well as The second pixel circuit is configured at a second position corresponding to the intersection of the second data line and the scan line. The first transmission gate and the second transmission gate are controlled by a control signal from the control circuit and a signal that has a logical inversion relationship with the control signal. They are turned on when the control signal is high and the signal that has a logical inversion relationship with the control signal is low. The other ends of the first holding capacitor and the second holding capacitor mentioned above are grounded in a common manner in each column. The first pixel circuit and the second pixel circuit mentioned above each include: Light-emitting elements; The driving transistor has its source electrically connected to the power supply line, and controls the current supplied to the light-emitting element when it is electrically connected to the light-emitting element. The selection transistor has its gate electrically connected to the scan line, one of its drain and source electrically connected to the data line, and the other of its drain and source electrically connected to the gate of the driving transistor. The selection transistor is configured between the first data line or the second data line and the gate of the driving transistor to control the connection and disconnection of the first data line or the second data line and the gate of the driving transistor. The capacitor is held in place, with one end electrically connected to the gate of the driving transistor and the other end electrically connected to the power supply line. The first transistor has its drain electrically connected to the gate of the aforementioned driving transistor, its source electrically connected to the drain of the aforementioned driving transistor, and its gate is supplied with a first control signal. The second transistor has its drain electrically connected to the anode of the aforementioned light-emitting element, its source electrically connected to the drain of the aforementioned driving transistor, and its gate supplied with a second control signal; and The third transistor has its drain electrically connected to the power supply line, its source electrically connected to the anode of the aforementioned light-emitting element, and its gate supplied with a third control signal. The first data signal supplied to the first holding capacitor is compressed by the first holding capacitor, the third transmission gate, the third holding capacitor, the first data line, and the fifth holding capacitor at a first compression ratio and then supplied to the gate of the driving transistor of the first pixel circuit. The second data signal supplied to the second holding capacitor is compressed by the second holding capacitor, the fourth transmission gate, the fourth holding capacitor, the second data line, and the sixth holding capacitor at a second compression rate different from the first compression rate and then supplied to the gate of the driving transistor of the second pixel circuit.

2. The electro-optical device according to claim 1, characterized in that, The ratio of the capacitance value of the third holding capacitor to the capacitance value of the fifth holding capacitor is a different ratio than the ratio of the capacitance value of the fourth holding capacitor to the capacitance value of the sixth holding capacitor.

3. The electro-optical device according to claim 1 or 2, characterized in that, The potential shift of the gate of the driving transistor in the first pixel circuit is the potential shift of the third terminal of the third holding capacitor divided by the parallel capacitance of the holding capacitor and the fifth holding capacitor of the first pixel circuit and the internal capacitance of the third holding capacitor.

4. The electro-optical device according to claim 1 or 2, characterized in that, The control circuit turns on the third transmission gate and redistributes the first charge stored in the third terminal of the third holding capacitor and the second charge stored in the first terminal of the first holding capacitor, which is equivalent to the first data signal, to the first holding capacitor, the third holding capacitor, the fifth holding capacitor, and the holding capacitor of the first pixel circuit.

5. An electronic device, characterized in that, The device comprises the electro-optical device according to any one of claims 1 to 4.

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