High Radix Subset Code Multiplier Architecture

Abstract

Systems, methods, and devices are provided for enhancing the performance / efficiency of soft multiplier implementations. More specifically, methods are provided for implementing soft multipliers using a high-radix subset code architecture. The techniques provided herein enable smaller multipliers that occupy less area, improve packaging, consume less power, and improve routing on integrated circuits.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is a non-provisional application claiming priority to U.S. Provisional Patent Application No. 62 / 522,546, filed on June 20, 2017, and entitled “High Radix Subset Code Multiplier Architecture,” which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to integrated circuits, such as field programmable gate arrays (FPGAs). More particularly, the present disclosure relates to soft multiplier logic implemented on an integrated circuit (eg, an FPGA). Background Art

[0004] This section is intended to introduce the reader to various aspects of the art that may be relevant to various aspects of the present disclosure, which will be described and / or claimed below. This discussion is believed to be helpful in providing the reader with background information that will facilitate a better understanding of various aspects of the present disclosure. Therefore, it should be understood that these statements are to be understood from this perspective and are not admitted to be prior art.

[0005] Machine learning is becoming an increasingly important application area. For example, machine learning can be used in natural language processing, object recognition, bioinformatics, and economics, among other fields and applications. Therefore, improved machine learning implementations across different types of platforms, including FPGAs, application-specific standard products (ASSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), and the like, may be desirable.

[0006] Many computations involved in machine learning are inferential, regardless of the platform. That is, systems involved in machine learning can make predictions based on previously available data. Therefore, to run faster and more efficiently, systems can rely on many low-precision (i.e., fixed-point) calculations rather than slower, full-precision (i.e., floating-point) calculations. Consequently, smaller, more efficient multipliers have become integral to performing the operations involved in machine learning.

[0007] Modern FPGA architectures can include soft multipliers, which are memory-based multipliers that take advantage of the large internal memory I / O bandwidth to increase the number of available multipliers. Unfortunately, however, soft multipliers can be very expensive to use. Soft multipliers consume significant area, power, routing, and / or packaging resources of the integrated circuit, and therefore, are not very efficient for machine learning applications. Summary of the Invention

[0008] The following describes a summary of some embodiments disclosed herein. It should be understood that these aspects are provided only to provide a brief overview of these embodiments to the reader, and these aspects are not intended to limit the scope of this disclosure. In fact, this disclosure may encompass various aspects not described below.

[0009] The present embodiments relate to systems, methods, and devices for enhancing the performance / efficiency of soft multiplier implementations. Specifically, a method for mapping high Booth radix-8 subset encodings to a single-stage FPGA logic is provided.

[0010] The techniques presented herein enable smaller multipliers that can occupy less area on an integrated circuit. Furthermore, packaging can be improved for high-density circuits. Furthermore, using the disclosed techniques, soft multipliers can be packaged onto a single stage of logic, utilizing a smaller area and exhibiting lower latency. Furthermore, these soft multipliers can reduce power consumption and significantly improve routability.

[0011] Various refinements of the features described above may exist with respect to various aspects of the present disclosure. Additional features may also be incorporated into these various aspects. These refinements and additional features may exist individually or in any combination. For example, the individual features described below with respect to one or more of the illustrated embodiments may be incorporated into any of the above-described aspects of the present invention individually or in any combination. Again, the brief overview presented above is intended only to familiarize the reader with certain aspects and background of the embodiments of the present disclosure and does not limit the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Various aspects of the present disclosure may be better understood upon reading the following detailed description and referring to the accompanying drawings, in which:

[0013] Figure 1 is a block diagram of a system for implementing a soft multiplier according to an embodiment;

[0014] Figure 2 is a block diagram of an integrated circuit in which a soft multiplier may be implemented according to an embodiment;

[0015] Figure 3 is a block diagram of an Nx3 multiplier optimized according to the disclosed techniques, according to an embodiment;

[0016] Figure 4 is a block diagram illustrating an Nx6 multiplier optimized according to the disclosed techniques, according to an embodiment;

[0017] Figure 5 is a block diagram illustrating an Nx9 multiplier according to an embodiment; and

[0018] Figure 6 is a block diagram illustrating a correction factor added to the output of a multiplier, according to an embodiment. DETAILED DESCRIPTION

[0019] One or more specific embodiments will be described below. To provide a brief description of these embodiments, not all features of actual implementations are described in this specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, several implementation-specific decisions may be made to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which may vary from implementation to implementation. Furthermore, it should be appreciated that such development efforts may be complex and time-consuming, but remain a routine task of design, fabrication, and production for those of ordinary skill having the benefit of this disclosure.

[0020] As described in further detail below, embodiments of the present disclosure generally relate to circuits for enhancing soft multipliers implemented on integrated circuits (ICs). In particular, in some embodiments, high Booth radix-8 subset encoding can be mapped to a single stage of FPGA logic, which can result in reduced soft multiplier size and / or other benefits.

[0021] Looking back at what was said before, Figure 1 A block diagram of a system 10 for implementing a machine-implemented program using soft multiplier logic is shown. A designer may wish to implement functionality on an integrated circuit 12 (IC, such as a field programmable gate array (FPGA)). The designer may specify that a high-level program, such as an OpenCL program, be implemented, which may enable the designer to more efficiently and easily provide programming instructions for implementing a set of programmable logic for the IC 12 without requiring specific knowledge of a low-level computer programming language (e.g., Verilog or VHDL). For example, because OpenCL is very similar to other high-level programming languages, such as C++, designers of programmable logic familiar with these programming languages ​​may have a reduced learning curve compared to designers who need to learn an unfamiliar low-level programming language to implement new functionality on the IC.

[0022] Designers can use Altera TMThe high-level design can be implemented using the Quartus II design software 14. The design software 14 can use a compiler 16 to convert the high-level program into a low-level program. The compiler 16 can provide machine-readable instructions representing the high-level program to the host computer 18 and the IC 12. For example, the IC 12 can receive one or more kernel programs 20 that describe the hardware implementation to be stored in the IC. The host computer 18 can receive a host program 22 that can be implemented by the kernel program 20. To implement the host program 22, the host computer 18 can transmit instructions from the host program 22 to the IC 12 via a communication link 24, which can be, for example, direct memory access (DMA) communication or peripheral component interconnect express (PCIe) communication. In some embodiments, the kernel program 20 and the host computer 18 can implement multiplication via a multiplier 26, which can be stored on the IC 12 and controlled by the host computer 18. The multiplier 26 can be implemented as a soft multiplier or as a memory-based multiplier that can take advantage of the large internal memory I / O bandwidth within the IC 12 to increase the number of available multipliers.

[0023] Now turning to a more detailed description of IC 12, Figure 2 An IC device 12 is shown, which may be a programmable logic device, such as a field programmable gate array (FPGA) 40. For the purposes of this example, the device 40 is referred to as an FPGA, but it should be understood that the device may be any type of programmable logic device (e.g., an application-specific integrated circuit and / or an application-specific standard product). As shown, the FPGA 40 may have input / output circuits 42 for driving signals out of the device 40 and for receiving signals from other devices via input / output pins 44. Interconnect resources 46 (such as global and local vertical and horizontal wires and buses) may be used to route signals on the device 40. In addition, the interconnect resources 46 may include fixed interconnects (wires) and programmable interconnects (i.e., programmable connections between various fixed interconnects). Programmable logic 48 may include combinational and sequential logic circuits. For example, the programmable logic 48 may include lookup tables, registers, and multiplexers. In various embodiments, the programmable logic 48 may be configured to perform custom logic functions. The programmable interconnects associated with the interconnect resources may be considered part of the programmable logic 48. As described in further detail below, FPGA 40 may also include efficient soft multipliers that may rely on high Booth radix-8 subset codes to define their architecture.

[0024] A programmable logic device, such as FPGA 40, may include a programmable element 50 having programmable logic 48. For example, as described above, a designer (e.g., a customer) may program (e.g., configure) the programmable logic 48 to perform one or more desired functions. By way of example, some programmable logic devices may be programmed by configuring their programmable elements 50 using a mask programming arrangement that is performed during semiconductor fabrication. Other programmable logic devices may be configured after semiconductor fabrication operations have been completed, such as by programming their programmable elements 50 using electrical programming or laser programming. In general, the programmable element 50 may be based on any suitable programmable technology, such as fuses, antifuses, electrically programmable read-only memory technology, random access memory cells, mask-programmable elements, and the like.

[0025] Most programmable logic devices are electrically programmed. With an electrically programmed arrangement, the programmable element 50 can be formed from one or more memory cells. For example, during programming, configuration data is loaded into the memory cell 50 using pins 44 and input / output circuits 42. In one embodiment, the memory cell 50 can be implemented as a random access memory (RAM) cell. The use of the memory cell 50 based on RAM technology described herein is intended to be an example only. In addition, because these RAM cells are loaded with configuration data during programming, they are sometimes referred to as configuration RAM cells (CRAM). These memory cells 50 can each provide a corresponding static control output signal that controls the state of the associated logic component in the programmable logic 48. For example, in some embodiments, the output signal can be applied to the gate of a metal oxide semiconductor (MOS) transistor within the programmable logic 48.

[0026] The circuitry of FPGA 40 can be organized using any suitable architecture. As an example, the logic of FPGA 40 can be organized in a series of rows and columns of larger programmable logic regions, each of which can contain multiple smaller logic regions. The logic resources of FPGA 40 can be interconnected via interconnection resources 46, such as associated vertical and horizontal conductors. For example, in some embodiments, these conductors can include global wires that span substantially all of FPGA 40, fractional wires such as half-wires or quarter-wires that span a portion of device 40, staggered wires of a specific length (e.g., sufficient to interconnect several logic regions), smaller local wires, or any other suitable arrangement of interconnection resources. Furthermore, in other embodiments, the logic of FPGA 40 can be arranged in multiple levels or layers, with multiple larger regions interconnected to form additional larger portions of logic. Furthermore, other device arrangements can use logic that is not arranged in a manner other than rows and columns.

[0027] As described above, FPGA 40 allows designers to create custom designs capable of executing and implementing custom functions. Each design can have its own hardware implementation implemented on FPGA 40. In some instances, it may be desirable to enhance the performance of soft multipliers implemented on the IC. In particular, in some embodiments, high Booth radix-8 subset encoding can be utilized and mapped to a single stage of FPGA logic.

[0028] In some embodiments, the soft multiplier can utilize a modified Booth algorithm to implement efficient multiplication operations. The modified Booth algorithm can be used to perform high-speed multiplication by dividing the bits of the multiplier into groups. Each group of multiplier bits can be decoded into a multiplication operation, which can be further decomposed into a shift operation and an addition operation in the soft multiplier architecture implementation. The resulting multiplication operation can be applied to the multiplicand to generate multiple partial products. These partial products can be shifted and summed to obtain the final, low-precision result of the multiplication of the multiplier and the multiplicand.

[0029] The group of multiplier bits can be divided and then decoded according to the coding scheme. For example, the Booth base 8 encoding commonly understood can be summarized in Table 1 below. The first two columns of Table 1 (that is, "three bytes" and "tail bit") can relate to the bit group considered from the multiplier in the multiplication operation. The third column "code" of Table 1 can include the operation performed on the multiplicand in the multiplication operation. The code and subsequent operations can correspond to the bit group in the first two columns of the corresponding row of the code. For example, if a group of multiplier bits includes three bytes "101" and the "tail bit" of the group is '1', then '-2' can be the encoding corresponding to the group of bits. In this case, the operation performed on the multiplicand can include shifting the bit of the multiplicand to the left by one bit, and taking the complement of the result (that is, multiplying the multiplicand by negative 2). In the case of '+3' or '-3' code, addition can also be used because the bit shift of the multiplicand may involve multiplying by a factor of 2 or dividing by a factor of 2. In some embodiments, the addition operation may involve a multiplicand*2+multiplicand operation (ie, a '2' code added to a '1' code).

[0030] In addition, Booth radix 8 can operate on groups of four bits. The four-bit group can be composed of three bits and a tail bit, where the tail bit can include the most significant bit (MSB) of the first three bits. For the least significant three bits, '0' can be regarded as the tail bit. For example, a 12-bit multiplier can use the group {[3:1], '0'}, [6:3], [9:6] and [12:9]. Therefore, the multiplier can be decomposed into overlapping groups of four bits, and the code corresponding to each group of four bits can be determined according to Table 1.

[0031] Table 1: Known Booth radix 8 encodings

[0032] Three tail position Code "000” ‘0’ 0 "000” ‘1’ +1 "001” ‘0’ +1 "001” ‘1’ +2 "010” ‘0’ +2 "010” ‘1’ +3 "011” ‘0’ +3 "011” ‘1’ +4 "100” ‘0’ -4 "100” ‘1’ -3 "101” ‘0’ -3 "101” ‘1’ -2 "110” ‘0’ -2 "110” ‘1’ -1 "111” ‘0’ -1 "111” ‘1’ 0

[0033] Booth radix 8 encoding can be modified into high radix Booth subset encoding by removing one or more codes (i.e., taking a subset of the codes) to improve implementation efficiency. The removed codes can reduce the range of the multiplier, but the remaining support range can be continuous. For example, in some embodiments, the '-4' code can be ignored in order to create a more efficient soft multiplier architecture. In some embodiments, the '+4' code can also be ignored because it does not occur. For example, in the case of a 3-bit multiplier, the tail bit can always be 0, and therefore, the sequence '0111' will not occur for the '+4' code. Therefore, the remaining support range can be continuous (e.g., +7 to -7 for a 3-bit multiplier), and the multiplier operation can be symmetrical about 0. Due to the reduced multiplier range, the resulting multiplier can be efficiently suitable for FPGA devices.

[0034] therefore, Figure 3 An embodiment of Booth's modified radix-8 encoding mapped to a 3-bit signed multiplier 100 that can be implemented on an FPGA is shown. The FPGA can have a certain amount of soft logic, implemented using lookup tables (LUTs) (i.e., 110-113, 116, 118, 120, 122, 124, and 126) followed by dedicated ripple-carry adders (i.e., 114, 115, 128, 130, and 132). In some embodiments, an optional register stage can follow the adder. Furthermore, in some embodiments, a set of four 3-input LUTs (and two ripple-carry bits) can be combined into an adaptive logic module (ALM) (e.g., ALM 101 consisting of components 110-115). In this embodiment, ALMs 101, 102, and 103 can form the first three ALMs of the 3-bit signed multiplier 100. Additional ALMs can be added to the left of ALM 103 to implement the multiplicand. In some embodiments, the size of the multiplicand can be determined by the number of ALMs used to the left of ALM 103. Thus, the multiplicand can have any suitable size (i.e., N bits) achievable with an appropriate number of ALMs. Thus, a 3-bit signed multiplier 100 can be implemented, Nx3, and in this embodiment, a five-bit multiplicand is shown, a 5-bit x 3-bit multiplication can be performed.

[0035] The lookup tables can be arranged in several ways. In some arrangements, two 3-input lookup tables can each feed into a separate input of a ripple-carry adder. Furthermore, the LUTs feeding the same ripple-carry adder can be considered to be paired (e.g., 110 and 111). Thus, each pair of LUTs can have 6 independent inputs (i.e., 3 inputs per LUT).

[0036] In some embodiments, each LUT may receive an input signal, which may include, for example, USE_X1, USE_X2, NEG, AA(x), AA(x+1), and / or AA(x-1). USE_X1 and USE_X2 may represent the cases of "x1" and "x2," respectively. That is, the LUT may receive an input of USE_X1 to convey that a '+ / -1' code may be used for a multiplication operation, while a USE_X2 signal may convey that a '+ / -2' code may be used for a multiplication operation. In this embodiment, the NEG signal may indicate that the multiplication operation is negative. AA(x), AA(x+1), and AA(x-1) may each represent a multiplicand bit, where 'x' represents the index of a bit in the multiplicand. For example, where the value of 'x' is 3, AA(x) may correspond to the third bit of the multiplicand, while AA(x+1) may correspond to the fourth bit, and AA(x-1) may correspond to the second bit in the multiplicand.

[0037] The USE_X1, USE_X2, and NEG inputs on each LUT can receive signals from the decoder. That is, the decoder can receive three multiplier bits with a tail bit of '0', and the decoder can output the appropriate code or operation associated with the received bit sequence according to the high Booth radix 8 subset encoding (i.e., Table 1 without the '+ / -4' code). Therefore, for the 3-bit multiplier sequence "111" with a tail bit of '0', the decoder can output '-1' to be used as a multiplier operation. To convey this output, the USE_X1 and NEG signals can be set by the output of the decoder. In the case of '-4' (i.e., '100' with a tail bit of '0'), the decoder may not recognize a valid input code because '-4' is ignored. Therefore, the decoder may not set USE_X1 or USE_X2, and the result of the multiplier may be zero.

[0038] In some embodiments, each LUT can receive a USE_X1 or USE_X2 signal as a first input, a NEG signal as a second input, and AA(x), AA(x-1), and AA(x+1) as a third input. Each LUT can use a combination of each of its inputs to look up and output the corresponding multiplication result from its table. In this embodiment, the right LUT of each LUT pair (i.e., 110, 112, 116, 120, and 124) can be used for the "x1" case. That is, the right LUT can receive the USE_X1 signal as an input. The left LUT (i.e., 111, 113, 118, 122, and 126) can be used for the "x2" case (i.e., the USE_X2 signal is an input). For the "x3" case, two LUTs can be used. That is, the USE_X1 signal input of the right LUT (ie, 110, 112, 116, 120, and 124) and the USE_X2 signal input of the left LUT (ie, 111, 113, 118, 122, and 126) may both be asserted to cause both operations to be performed on the multiplicand.

[0039] Furthermore, in some embodiments, the inputs associated with the LUTs may not be independent of one another. Instead, in some embodiments, a subset of shared inputs may be used on a pair of LUTs (e.g., 110 and 111) and / or on unpaired adjacent LUTs (e.g., 112 and 118). For example, in this embodiment, each left LUT of each LUT pair may share a multiplicand bit (i.e., AA(x), AA(x-1), or AA(x+1)) to the right with the right LUT of the LUT pair. For example, the right LUT 112 may receive AA(2) as a data input, and the right LUT 112 may share AA(2) with the left LUT 118 from a different LUT pair.

[0040] Additionally, the NEG signal can be shared among all LUTs (i.e., 110-113, 116, 118, 120, 122, 124, and 126) within and among each ALM 101, 102, and 103, as shown in this embodiment. As a result, the NEG signal can invert (i.e., complement of 1) the multiplicand vector. The multiplicand vector can be represented by the multiplicand bits (i.e., AA[5:1]) received in the right LUT 110, 112, 116, 120, 124 (i.e., multiplicand vector 1) and the left LUT 113, 118, 122, 126 (i.e., multiplicand vector 2), respectively. In some cases, it may be desirable not to invert both vectors. For example, in the case of a '-2' code, USE_X1 is not set. Therefore, the multiplicand vector 1 value can be "0000...000". However, a common NEG signal may negate the value, which may then be represented in 1's complement as "1111...111". In this case, it may not be desirable to invert the multiplicand vector 1. However, external adjustments may be used, for example, to correct the vector value. In this embodiment, the left LUT 111 of the least significant bit (LSB) of the multiplier may lack a data input (i.e., AA(x), AA(x-1), or AA(x+1)). Thus, the NEG bit may be routed through this data input to convert the 1's complement value of the multiplicand vector 1 into a 2's complement value. When the NEG value is added to the least significant bit, '1' may be added to the negated multiplicand vector 1 (i.e., "1111...111"), converting it into a 2's complement value, which may be represented as "0000...000" as originally desired.

[0041] In the case of 2's complement, the adjustment of the NEG signal may not be performed at the same level of logic as described above for the case of 1's complement. Because the case of the 2's complement value may be the result of a dot product, the correction can be uniformly encoded into a single number for the entire dot product. In some embodiments, the correction used may include the addition of the value "000...010", which can be implemented by a single bit addition, although with the effect of a carry on the entire number. To add this correction, the incomplete triple in the adder tree of the dot product can be located, and the correction can be added to the end of the incomplete triple, as further described below.

[0042] As described, the current embodiment implements Nx3 multiplication, balanced around 0, where the contribution of the multiplication is contained in a single stage of logic. However, the method can also be extended to implement very efficient Nx6 multiplication, such as Figure 4 That is, a 6-bit signed multiplier 200 may be used instead of a 3-bit signed multiplier 100.

[0043] In the case of Nx6 multiplication, the multiplier can be decomposed into two groups of bits (i.e., {[3:1], '0'} and [6:3]). Each group of bits can be evaluated according to the subset of Booth radix 8 encoding used or Table 1 to determine the code for the appropriate multiplication operation corresponding to the multiplier bit group. As a result, two codes or multiplication operations will be used. That is, the 6-bit signed multiplier 200 can be evaluated similarly to two 3-bit signed multipliers 100. Therefore, if Figure 3 As shown, for Nx6 multiplication, the structure for implementing Nx3 multiplication can be implemented twice (e.g., as high block 202 and low block 201). High block 202 can handle the multiplication using the "high" bits of the multiplier (i.e., bb[6:3]). In some embodiments, low block 201 can handle the multiplication using the "low" bits of the multiplier with a tail bit of '0' (i.e., bb[3:1]), as previously described. High block 202 and low block 201 receive all bits from the multiplicand. In the illustrated embodiment, for example, an 8-bit multiplicand is depicted, and the entire multiplicand can be multiplied according to the appropriate operation corresponding to the low bits of the multiplier in low block 201 (i.e., from Table 1), and the entire multiplicand can be multiplied simultaneously according to the appropriate operation corresponding to the high bits of the multiplier in high block 202 (i.e., from Table 1). Additional logic may be involved before the results of high block 202 and low block 201 are summed, as described in further detail below.

[0044] Although the high block 202 and the low block 201 match Figure 3 The Nx3 bit multiplication shown in FIG. 1 is an Nx3 bit multiplication, but in some cases, the '-4' code is no longer ignored in the 6-bit signed multiplier. That is, when the three low bits of the multiplier (i.e., bb[3:1]) are "100" and the tail bit is automatically assumed to be '0', then '-4' can be obtained according to Table 1. Although '-4' may occur in the 3-bit signed multiplier 100, but is selectively ignored, as previously described, '-4' can be a valid code in the 6-bit signed multiplier 200 to support a continuous range of -27 to +27 centered around 0. Although, since the low block 201 can be equivalent to Figure 3 3-bit signed multiplier 100, but additional structure can be used to facilitate the '-4' code. Therefore, block 204 can be added to the multiplier architecture to detect whether the '-4' condition occurs. In some embodiments, the output of block 204 can be used as a select input of multiplexer 207. When the '-4' condition is detected by block 204, multiplexer 207 can select the complement output of block 203 as its output. Block 203 can shift the multiplicand left by two bits. Therefore, the complement of the output of block 203 can represent the multiplicand multiplied by -4. When '-4' is not detected by block 204, multiplexer 207 can select the partial product (i.e., pp_low[]) obtained by the output of low block 201.

[0045] In some embodiments, high block 202 may lack connectivity to additional structures (such as blocks 203, 204 and multiplexer 207) to handle a '+ / -4' code condition that may occur due to the input of bits bb[6:3]. As a result, the '+ / -4' code may be ignored during the multiplication of multiplicand aa[8:1] and the code resulting from the Booth radix-8 encoding of multiplier bits bb[6:3]. However, in some embodiments, high block 202 may be connected to structures to detect and handle the '+ / -4' code (e.g., such as described above), but such embodiments may minimize the optimization effect obtained by removing the code because the additional structure may require more area and / or resources.

[0046] Furthermore, since the structure may be based on a modified Booth radix 8 algorithm, the result of the high block 202 may be left shifted by 3 bits at block 205. That is, the first three bits of the partial product obtained by the high block 202 (i.e., pp_high[]) may be "000". Signal 206, including the bits from pp_high[], may be added to the output of multiplexer 207 to obtain the result of the multiplication operation (i.e., cc[14:1]). In some embodiments, signal 206 may assert '0' as its first bit (i.e., bit[1]), as shown in FIG. Figure 4 As shown. In addition, the second bit of signal 206 can be determined by the output of low block 201. If pp_low[] is negative, it can be output from low block 201 in a 1's complement format, which can be desirably converted to a 2's complement format by setting bit[2] of signal 206 to a correction factor. In some embodiments, the logical AND of the adjust_low signal (which can be set by low block 201 to correct its output (i.e., pp_low[])) and the complement of the output of block 204 (i.e., the NOT gate output) can determine the value of bit[2]. Therefore, if block 204 does not detect a '-4' condition, only bit[2] can be set to correct pp_low[]. In addition, in some embodiments, if a '-4' condition exists, a '1' can be inserted at bit[3] of signal 206 instead of bit[2]. In other words, following the same logic in the 3-bit signed multiplier 100 (where the NEG signal may be routed into the LUT 111 to counteract the inverse error), a set of correction factors may be set in the signal 206 (i.e., bit [2] and / or bit [3]) to account for any errors that may exist due to negation and / or errors associated with the desired 1's complement relative to 2's complement output.

[0047] exist Figure 4In the illustrated embodiment, each of the radix-8 multipliers (i.e., high block 202 and low block 201) can be considered a single stage of logic. In addition, block 210, which may include multiplexer 207 and adder 208, can involve a single stage of logic. Furthermore, control block 204 can be calculated in parallel with low block 201, and the shift operations of blocks 203 and 205 can be considered free operations because there may not be any actual logic involved. Thus, in some embodiments, Nx6 multiplication can utilize only two stages of logic.

[0048] In some embodiments, the method can also be extended to larger multipliers. Figure 5 An example embodiment of Nx9 multiplication using a 9-bit signed multiplier 250 is shown. In the embodiment shown, the Nx9 multiplier may include an Nx3 multiplier (i.e., high block 220), an Nx6 multiplier (i.e., 242), and additional logic coupled together. Thus, blocks 220, 202, and 201 may be constructed in Figure 3 Above is an example of the structure shown. The bits of the multiplier (i.e., bb[9:1]) can be grouped into three sets of 4 (i.e., {bb[3:1],'0'}, bb[6:3], and bb[9:6]), which can be regarded as the low bit, middle bit (i.e., middle bit), and high bit of the multiplier, respectively. As in the case of the Nx6 multiplier, the low block 201 can receive the low bit of the multiplier (i.e., {bb[3:1],'0'}), and the middle block 202 can receive the middle bit of the multiplier (i.e., bb[6:3]). The high block 220 can receive the remaining high bits of the multiplier (i.e., bb[9:6]). Additional logic can be included before summing the result of the high block 220 with the sum of the middle block 202 and the low block 201, as described in further detail below.

[0049] In the case of the 9-bit signed multiplier 250, the condition where the low bits {bb[3:1], '0'} would result in a '-4' condition would still occur and could be handled by the same logic blocks (i.e., 204, 207, 203) shown in the Nx6 multiplier. However, compared to the 6-bit signed multiplier 200, a new condition would occur due to the additional multiplier bits. In the case where the tail bits bb[6:3] of the middle of the multiplier coincide with the MSB of the low bits {bb[3:1], '0'} of the multiplier, a '+ / -4' code condition would occur. That is, '0011' and '1000' would occur as valid values ​​of bb[6:3], which could be interpreted as '+4' and '-4', respectively, by Booth's radix 8 encoding. Furthermore, in order to generate the appropriate '+4' or '-4' state based on the value of the middle multiplier bits bb[6:3], in some embodiments, block 230 may be used. Thus, at block 221, the multiplicand bits aa[8:1] can be left-shifted two bits, or multiplied by '+4', regardless of the value of the middle bits bb[6:3]. Block 222 can determine the value of bits bb[6:3] to determine whether the '+ / -4' condition is satisfied. The output of block 222 can be routed to XOR gate 223 and adder 224 to complement the value of the output of block 221, if necessary, to generate a '-4' condition. Thus, the output of adder 224 can contain either -4*multiplicand or +4*multiplicand. This output can be fed to multiplexer 225 along with the partial product of the output of middle block 202 (i.e., pp_mid[]). Furthermore, the output of block 222 can be routed to a select bit of multiplexer 225 to select between the result of the '+ / -4' condition or the output of block 202 (i.e., pp_mid[]). The output of 230 may then be left shifted three bits by block 205 to properly align the multiplier result. In other embodiments, generation of the '+ / -4' case may be accomplished using other methods that may incorporate these values ​​into the multiplier structure, which may have different suitable characteristics depending on the device.

[0050] In addition, the partial product output by high block 220 (i.e., pp_high[]) can be left-shifted by 6 bits before summing the high block 220 result with the sum of mid block 202 and low block 210, as the pp_mid[] bits can be left-shifted by three bits. The output of block 226 can be summed along signal 228. Signal 228 can have a correction factor set in bit[5] or bit[6] depending on the sign of the pp_mid[] result and the presence / absence of the '+ / -4' condition, as the Nx6 multiplier has for the '-4' condition and negative pp_high[]. Therefore, mid block 202 can output a correction factor, adjust_mid, to appropriately correct signal 228. In some embodiments, signal 228 can be added at adder 240 to the sum of the lower multiplier components added together at adder 208. Additionally, the adjust_high signal 227 can be added to the result of the adder 240 (i.e., cc[17:1]) or to another architectural stage that can use the result of the adder 240. That is, the adjust_high signal 227 can represent a correction factor for the high block 220 multiplier, but unlike adjust_mid and adjust_low, there is no location within the multiplier architecture where the correction factor is added to the product or partial product. Therefore, the adjust_high signal 227 can be routed outside the multiplier architecture and added to the result of the multiplier in another stage.

[0051] exist Figure 5 In the illustrated embodiment, similar to the embodiment of the Nx6 multiplier, each of the multipliers (i.e., 220, 202, and 201) can be viewed as a single stage of logic. Furthermore, although the XOR gate 223, adder 224, and multiplexer 225 appear to be spread over two stages of logic because the adder can be constructed as the output stage of the logic stage, the multiplexer 225 can be logically pushed back to before the adder 224 using synthesis techniques.

[0052] In addition, although Figure 3-Figure 5 The illustrated embodiments demonstrate Nx3, Nx6, and Nx9 bit signed multipliers, respectively, but in some embodiments, additional multipliers of appropriate sizes may be created using the techniques described herein.

[0053] As previously mentioned, in some embodiments, the correction value can be added to the output of one or more multipliers. If the correction is implemented separately, for example, as a single multiplier, it will take up an entire adder stage, which may be wasteful. Alternatively, in some embodiments, where a triple adder structure is available, a triple adder can be used to add the correction. However, triple adders cannot be well packaged on a large scale in an FPGA due to wiring density. However, in some embodiments, multiple multipliers can be added together for many applications, such as in the case of dot products. Therefore, it may be beneficial to use an adder tree to apply the correction factor to multiple multipliers rather than to a single multiplier.

[0054] therefore, Figure 6 An embodiment of an adder tree 450 implemented on five multipliers (e.g., 401-405) for applying correction factors is shown. The multipliers 401-405 can have any suitable size, such as Nx3, Nx6, or Nx9. In addition, in some embodiments, each multiplier 401-405 can output a unit correction factor 426 (e.g., adjust_low, adjust_mid, adjust_high), as well as an uncorrected result 428 of the multiplier operation. However, in some embodiments, the multiplier architecture can enable each multiplier to output multiple bits or encoded values ​​(such as multiple bits that have been combined into an integer correction value) as the correction value. Block 410 can receive each of the correction bits 426 from the multipliers 401-405 as input. In some embodiments, block 410 can then sum the correction bits 426 into a single correction integer 430. The single correction integer 430 output by block 410 can be added to the adder tree at adder 423. In the illustrated embodiment, adder 423 can represent an incomplete triple in adder tree 450. That is, because there is an odd number of multipliers, adders 420 and 421 receive two inputs from multipliers (i.e., 401 and 402, and 403 and 404, respectively). However, no paired multipliers are used as inputs at adder 423, resulting in an incomplete triple to which correction integer 430 can be added. By adding correction integer 430 to adder tree 450 at 423, its correction effect is propagated to adder 424 and its final output. Therefore, the corrections for each multiplier 401-405 can be summed and applied simultaneously, so that all corrections are present in the final output of adder 424. However, in some embodiments, adder tree 450 may not include an incomplete triple for correction integer 430 to add, and in such cases, adder tree 450 may include additional adders to incorporate correction integer 420 into the final sum.

[0055] While the embodiments set forth in this disclosure are susceptible to various modifications and alternative forms, specific embodiments are shown by way of example in the drawings and are described in detail herein. However, it should be understood that the disclosure is not intended to be limited to the particular forms disclosed. The disclosure is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the disclosure as defined in the appended claims.

Claims

1. A programmable logic device, comprising: a multiplier code comprising one or more encoded multiplier values; as well as A multiplier is configured to perform a multiplication operation based on the multiplier encoding, wherein the multiplier skips implementation for a subset of the encoded multiplier values, wherein the multiplier includes two lookup tables for each bit of a multiplicand to be multiplied by the encoded multiplier value.

2. The programmable logic device according to claim 1, wherein: One or more of the highest encoded multiplier values ​​in the multiplier encodings comprise a subset of the encoded multiplier values.

3. The programmable logic device according to claim 1 , wherein: The multiplier encoding is Booth radix 8 encoding.

4. The programmable logic device according to claim 3, wherein: The subset of encoded multiplier values ​​includes multiplier encodings for +4, -4, or a combination thereof.

5. The programmable logic device according to any one of claims 1 or 2, wherein: The multiplication operation includes an addition operation, a shift operation, or a combination thereof.

6. The programmable logic device according to any one of claims 1 or 2, wherein: The multiplier encoding is signed and symmetric about the value zero.

7. The programmable logic device of any one of claims 1 or 2, comprising a plurality of multipliers and comprising circuitry for processing the multiplication operation based on a set of encoded multiplier values, wherein Results from the circuits are selectively multiplexed into a final summation of a set of results from the plurality of multipliers.

8. A method for implementing a multiplication operation, comprising: generating a multiplier code comprising one or more encoded multiplier values; generating a multiplier of a programmable integrated circuit, the multiplier of the programmable integrated circuit configured to perform the multiplication operation based on the multiplier encoding, wherein the multiplier skips implementation for a subset of multiplier values ​​of the encoding; and performing said multiplication operation on the multiplicand, Therein, the multiplier comprises two lookup tables for each bit of the multiplicand to be multiplied by the encoded multiplier value.

9. The method of claim 8, wherein: The multiplier includes a plurality of additional multipliers.

10. The method of claim 9, wherein: A set of adders is configured to sum a set of results from the plurality of additional multipliers to provide a result to the multiplication operation.

11. The method according to claim 10, wherein: One of the plurality of additional multipliers further outputs an independent signal in addition to one of the results from the set of results, wherein the independent signal is added to the result of the multiplication operation.

12. The method of claim 11, wherein: The independent signal comprises one bit.

13. The method of claim 11, comprising an additional adder for adding the independent signal to the result of the multiplication operation.

14. A tangible, non-transitory machine-readable medium comprising machine-readable instructions that, when executed by one or more processors, cause the processors to perform the method of any one of claims 8-13.

15. A method for implementing a multiplication operation, comprising: decoding a set of multiplier values ​​based on the multiplier encoding; performing the multiplication operation via a multiplier circuit, wherein the multiplier circuit performs the multiplication operation based on the set of multiplier values, wherein the multiplier skips implementation of a subset of the multiplier values, Therein, the multiplier includes two lookup tables for each bit of the multiplicand to be multiplied by the multiplier value.

16. The method of claim 15, wherein: One or more of the highest ones of the multiplier values ​​comprise a subset of the multiplier values.

17. The method according to any one of claims 15 or 16, wherein The multiplication operation includes an addition operation, a shift operation, or a combination thereof.

18. The method according to any one of claims 15 or 16, wherein The multiplier includes a plurality of additional multipliers.

19. A computer program product having a computer program stored thereon, which, when executed by a processor, causes the processor to perform the method according to any one of claims 8 to 13.

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