Nanopore LED array chip with anti-reflection passivation layer and preparation method thereof

Abstract

The present invention discloses a nanohole LED array chip with an anti-reflection passivation layer and a preparation method thereof. The LED array chip of the present invention is composed of N×N light-emitting units, the anode of each light-emitting unit is independently led out, and all light-emitting units share a cathode; the active area of ​​the light-emitting unit has a relatively deep nanohole, and the depth of the nanohole exceeds the quantum well layer; the dielectric film layer on the surface of the GaN material is also distributed with relatively shallow nanoholes, and there is a dielectric film at the bottom of the nanohole. The present invention grooves the dielectric passivation layer on the active area, and combines the soft film nanoimprinting technology, so that the deep nanoholes in the active area and the shallow nanoholes in the passivation layer can be prepared at the same time. The deep nanoholes in the active area increase the radiation recombination rate, and the shallow nanoholes in the passivation layer constitute an anti-reflection passivation layer, which are beneficial to improving the escape of the photon mode, improving the light extraction efficiency and the modulation bandwidth. In addition, the preparation method of the present invention avoids the deep etching process, and has the advantages of simple process and high yield.

Description

Technical Field

[0001] The present invention relates to the field of LED chips, and in particular to a micro-sized LED array chip with a nano-hole structure for visible light communication and a preparation method thereof. Background Art

[0002] Visible light communication is an important breakthrough point for LED (light-emitting diode) in the field beyond lighting. In order to improve the modulation bandwidth of the visible light communication system, the feedback circuit of the signal receiver can be optimized, or the frequency point with excessive loss can be raised by using the equalization circuit. This technology is low-cost and effective, but because the frequency point that needs to be processed is closely related not only to the equivalent resistance and equivalent capacitance of the LED device, but also to the parasitic resistance and parasitic capacitance of the entire system, the circuit adjustment is often only applicable to specific LED devices and system components, not to mass production. In addition, high-order modulation technologies can also be used, such as quadrature amplitude modulation (QAM), discrete multi-tone technology (DMT), orthogonal frequency division multiplexing (OFDM) and wavelength division multiplexing (WDM). However, these modulation technologies all rely on complex modulation circuits.

[0003] In order to increase the modulation bandwidth of visible light communication light sources, micro-sized LED chips can be used, and technologies such as photonic crystals, resonant cavities, and surface plasmons can be used to increase the carrier recombination rate. However, the formation of photonic crystals requires a strictly periodically distributed nanostructure, and GaN-based resonant cavities require complex technologies such as laser stripping of sapphire substrates or epitaxial layer distributed Bragg reflectors. Surface plasmons are limited by the contradiction between the local field enhancement characteristics and the large thickness of the hole / electron injection layer. The process difficulty of these technologies is relatively high. In addition, due to the large difference in refractive index between GaN materials and air, when light is emitted from the inside of the LED chip, the light escape cone is small, the light extraction efficiency is low, and it is not conducive to high signal-to-noise ratio and high-speed visible light communication. Summary of the invention

[0004] The purpose of the present invention is to address the deficiencies of the prior art and provide a nanopore LED array chip with an anti-transmission passivation layer. The chip is composed of N × N light-emitting units, where N ≥ 2, the anode of each light-emitting unit is independently led out, and all light-emitting units share a cathode; the active area of ​​the light-emitting unit has a deeper nanopore, the depth of the nanopore exceeds the quantum well layer, and the radiation recombination rate is increased; the passivation layer on the surface of the chip is distributed with shallower nanopores, forming an anti-transmission passivation layer.

[0005] The present invention also aims to provide a method for preparing a nanopore LED array chip with a transmittance-enhancing passivation layer. The method adopts a process flow of "preparing a dielectric insulating layer à preparing an electrode à preparing a dielectric passivation layer à grooving the dielectric passivation layer on the active area à soft film nanoimprinting à etching nanopores", and the deep nanopores in the active area of ​​the light-emitting unit and the shallow nanopores in the passivation layer in other areas of the chip surface can be prepared simultaneously.

[0006] The purpose of the present invention is achieved through the following technical solutions.

[0007] The nanopore LED array chip with an anti-reflection passivation layer provided by the present invention is composed of N×N light-emitting units, N×N anode pads and two cathode pads, wherein N ≥ 2, and the electrode pads and the metal connecting wires are isolated from the semiconductor material by a dielectric insulating layer; the diameter of the active area of ​​the light-emitting unit is between 100μm and 200μm; the active area of ​​the light-emitting unit has deeper nanopores, the depth of the nanopores exceeds the quantum well layer, and the diameter of the nanopores is between 300nm and 1000nm; the dielectric film layer on the surface of the GaN material is also distributed with shallower nanopores to form an anti-reflection passivation layer, the depth of the nanopores is between 200nm and 500nm, and there is a dielectric film at the bottom of the nanopores.

[0008] Furthermore, from the substrate to the light emitting direction, the active area of ​​the light emitting unit includes a sapphire substrate, a GaN buffer layer, an unintentionally doped GaN layer, an N-type doped GaN layer, a quantum well layer, a P-type doped AlGaN layer, a P-type doped GaN layer, a transparent current spreading layer, and a dielectric passivation layer in sequence.

[0009] Furthermore, from the substrate to the light emitting direction, the electrode pad region includes a sapphire substrate, a GaN buffer layer, an unintentionally doped GaN layer, an N-type doped GaN layer, a dielectric insulating layer, and a metal electrode in sequence.

[0010] Furthermore, the light-emitting unit is in the form of a truncated cone structure, and the anode of the light-emitting unit is in the shape of a disk and is distributed at the center of the upper surface of the cone; the cathode of the light-emitting unit is in the shape of a ring and is distributed around the cone; there is a notch in the cathode ring, and the metal connecting wire between the anode and the anode pad passes through the notch to achieve connection, the width of the metal connecting wire is more than 20μm, and the width of the notch is more than 20μm larger than the width of the metal connecting wire; the anode of each light-emitting unit is separately led out to the anode pad, all light-emitting units share a common cathode and have a cathode pad in the first row and the Nth row respectively.

[0011] Furthermore, the dielectric insulating layer is distributed on the upper surface of the semiconductor material of the entire chip, forming electrical insulation between the electrode pads and the metal connecting wires and the semiconductor material, but grooves are opened in the anode and cathode regions of the light-emitting unit; the dielectric insulating layer is one or more of SiO2, SiN, and SiON, and has a thickness of more than 300nm; the semiconductor material includes a transparent current spreading layer, a P-type doped GaN layer, a P-type doped AlGaN layer, a quantum well layer, and an N-type doped GaN layer.

[0012] The method for preparing a nanopore LED array chip with an anti-reflection passivation layer provided by the present invention comprises the following steps:

[0013] (1) A GaN-based LED epitaxial wafer is prepared using a metal oxide vapor deposition method. The structure of the GaN-based LED epitaxial wafer includes a sapphire substrate, a GaN buffer layer, an unintentionally doped GaN layer, an N-type doped GaN layer, a quantum well layer, a P-type doped AlGaN layer, and a P-type doped GaN layer.

[0014] (2) Using electron beam evaporation to deposit a transparent current spreading layer on a GaN-based LED epitaxial wafer, forming an ohmic contact through rapid annealing, and then using ultraviolet lithography and wet etching to form a transparent current spreading layer disk distributed only in the active area of ​​the light-emitting unit. The annealing temperature of the rapid annealing process is 500-650°C, the heating rate is 5-15°C / sec, the atmosphere is a mixture of nitrogen and oxygen, and the annealing time is 60-300sec.

[0015] (3) Using inductively coupled plasma etching, the N-type doped GaN layer is exposed to form a truncated cone structure of the light-emitting unit.

[0016] (4) Use plasma enhanced chemical vapor deposition to prepare the dielectric insulating layer, and then use ultraviolet lithography and inductively coupled plasma etching to create grooves in the anode and cathode regions of the light-emitting unit.

[0017] (5) Using negative resist stripping and electron beam evaporation, a disc-shaped anode is prepared in the anode slot area on the truncated cone of the light-emitting unit, a ring-shaped cathode is prepared in the cathode slot area, and an anode pad, a cathode pad, and a metal connecting wire are prepared on the electrode insulating layer.

[0018] (6) A dielectric passivation layer is prepared by plasma enhanced chemical vapor deposition, and then a groove is formed in the dielectric passivation layer on the active area by ultraviolet lithography and inductively coupled plasma etching for nanoimprinting; the groove area is within the frustum of the light-emitting unit, outside the anode groove area of ​​the light-emitting unit, and outside the metal connection line area of ​​the light-emitting unit.

[0019] (7) Spin coating a tackifier and nanoimprint glue on the dielectric passivation layer, and then use soft film nanoimprinting to imprint a nanopore pattern on the entire upper surface of the chip; then use inductively coupled plasma etching to remove the nanoimprint glue remaining at the bottom of the air hole.

[0020] (8) The nanopore pattern on the nanoimprint glue is transferred to the dielectric passivation layer using inductively coupled plasma etching.

[0021] (9) Then use an inductively coupled plasma etcher to perform etching. In the active area, the nanohole pattern is transferred from the thinner dielectric passivation layer to the transparent current spreading layer and the GaN semiconductor material layer in sequence, and the etching depth of the GaN semiconductor material exceeds the depth of the quantum well by more than 50nm; in other areas, the nanohole pattern continues to extend deeper into the thicker dielectric passivation layer.

[0022] (10) Use UV lithography and wet etching to expose metal electrodes in the anode, cathode, electrode pad and metal connecting line areas.

[0023] Furthermore, in step (4), the plasma enhanced chemical vapor deposition of the dielectric insulating layer is prepared in four steps. In the first step, the LED epitaxial wafer is placed in a sample carrier of the plasma enhanced chemical vapor deposition equipment, and the dielectric film is deposited to 1 / 4 of the target thickness; in the second step, the LED epitaxial wafer is rotated 90° on the carrier, and the dielectric film is deposited to 1 / 2 of the target thickness; in the third step, the LED epitaxial wafer is rotated 90° on the carrier again, and the dielectric film is deposited to 3 / 4 of the target thickness; in the fourth step, the LED epitaxial wafer is rotated 90° on the carrier again, and the dielectric film is deposited to the target thickness.

[0024] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0025] (1) The nanopore LED array chip with an anti-reflection passivation layer prepared by the present invention adopts independently controllable N × N micro-sized light-emitting units. On the basis of maintaining the modulation bandwidth, the communication capacity can be improved by combining the multiple-input multiple-output (MIMO) technology and the simple on-off keying (OOK) encoding technology; the anode pads and metal connecting wires of the light-emitting units are distributed on the dielectric insulating layer, and all the light-emitting units share a common cathode, so that the semiconductor epitaxial layer of each light-emitting unit can be independently controlled without isolation, avoiding the deep etching process when the semiconductor epitaxial layers of adjacent light-emitting units are isolated from each other, so the integration method of the array chip has the advantages of simple process and high yield.

[0026] (2) The nanopore LED array chip with a transmittance-enhancing passivation layer prepared by the present invention adopts the process flow of "preparing a dielectric insulating layer à preparing an electrode à preparing a dielectric passivation layer à grooving the dielectric passivation layer on the active area à soft film nanoimprinting à etching nanopores". On the one hand, in order to form a good isolation between the metal wire and the semiconductor material, a thicker dielectric isolation layer is required; in order to protect the metal electrode from damage during the nanopore etching process, a thicker dielectric passivation layer is required; both the dielectric isolation layer and the dielectric passivation layer cover the active area of ​​the light-emitting unit; when etching the nanopore in the active area, both layers need to be etched away, so the nanoimprint glue is required to be thick enough or the etching selectivity of the imprint glue / dielectric layer is required to be large enough, which causes great difficulties for the nanoimprint process or the nanopore etching process; by grooving the dielectric passivation layer on the active area, the thickness of the passivation layer in the active area can be appropriately thinned; when the nanopore etching of the active area is completed, although the passivation layer in other areas is also etched to obtain a nanopore, there is a dielectric film of sufficient thickness at the bottom of the nanopore to avoid damaging the metal electrode or the GaN material. On the other hand, by using soft film nanoimprinting, nanohole patterns can be imprinted on the entire uneven chip surface. The deep nanoholes in the active area of ​​the light-emitting unit and the shallow nanoholes in the passivation layer on the GaN surface can be prepared at the same time. The deep nanoholes in the active area increase the radiation recombination rate, and the shallow nanoholes in the passivation layer constitute a transmittance-enhancing passivation layer, which are beneficial to improving the escape of photon modes, improving the light output efficiency and modulation bandwidth.

[0027] (3) The method for preparing a nanopore LED array chip with an anti-reflection passivation layer proposed in the present invention adopts a four-step process flow of "depositing 1 / 4 thickness à rotating 90° and then depositing 1 / 4 thickness à rotating 90° and then depositing 1 / 4 thickness à rotating 90° and then depositing 1 / 4 thickness" when preparing the dielectric insulating layer. This is beneficial to reducing pinholes in SiO2 and reducing leakage, so that a thinner SiO2 dielectric layer can be used to meet the isolation effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1a It is a schematic top view of a nanohole LED array chip with an anti-reflection passivation layer in a specific embodiment;

[0029] Figure 1b is a schematic cross-sectional view of a nanohole LED array chip with an anti-reflection passivation layer at section line AA' in a specific embodiment;

[0030] Figure 2a It is a schematic top view of the nanohole LED array chip with an anti-reflection passivation layer in Example 1 after preparing the ohmic contact layer and the frustum of the light-emitting unit;

[0031] Figure 2bIt is a schematic top view of the process of preparing the nanohole LED array chip with an anti-reflection passivation layer in Example 1 after preparing the dielectric insulating layer and opening the electrode groove;

[0032] Figure 2c It is a schematic top view of the nanohole LED array chip with an anti-reflection passivation layer in Example 1 after the metal electrode is prepared;

[0033] Figure 2d It is a schematic top view of the process of preparing the nanohole LED array chip with an anti-reflection passivation layer in Example 1 after preparing the dielectric mask layer and opening the nanoimprint groove;

[0034] Figure 2e It is a schematic top view of the nanohole LED array chip with an anti-reflection passivation layer after nanoimprinting and dry etching in the preparation process of Example 1;

[0035] Figure 2f It is a schematic top view of the nanohole LED array chip with an anti-reflection passivation layer in Example 1 after the metal electrodes and electrode pads are exposed by grooving during the preparation process;

[0036] Figure 3a This is a schematic cross-sectional view of the process of preparing the nanohole LED array chip with an anti-reflection passivation layer in Example 1 after preparing the ohmic contact layer and the frustum of the light-emitting unit;

[0037] Figure 3b This is a cross-sectional schematic diagram of the process of preparing the nanopore LED array chip with an anti-reflection passivation layer in Example 1 after preparing the dielectric insulating layer and opening the electrode groove;

[0038] Figure 3c This is a schematic cross-sectional view of the process of preparing the nanohole LED array chip with an anti-reflection passivation layer in Example 1 after the metal electrode is prepared;

[0039] Figure 3d It is a cross-sectional schematic diagram of the process of preparing the nanohole LED array chip with an anti-reflection passivation layer in Example 1 after preparing the dielectric mask layer and opening the nanoimprint groove;

[0040] Figure 3e It is a schematic cross-sectional view of the nanohole LED array chip with an anti-reflection passivation layer after nanoimprinting and dry etching in the preparation process of Example 1;

[0041] Figure 3f This is a schematic cross-sectional view of the nanohole LED array chip with an anti-reflection passivation layer after the metal electrode and the electrode pad are exposed by grooving during the preparation process of Example 1;

[0042] In the figure, 1 is a sapphire substrate; 2 is a GaN buffer layer; 3 is an unintentionally doped GaN layer; 4 is an N-type doped GaN layer; 5 is a quantum well layer; 6 is a P-type doped AlGaN layer; 7 is a P-type doped GaN layer; 8 is a transparent current spreading layer; 100 is a dielectric insulating layer; 101 is a dielectric passivation layer on the GaN surface; 102 is a dielectric passivation layer on the metal electrode; 103 is a dielectric passivation layer in the active area; 200 is an anode; 201 is a cathode; 202 is a metal connecting line; 203 is a cathode pad; 204 is an anode pad; 300 is a groove of the anode on the dielectric insulating layer; 3 01—grooving of the cathode on the dielectric insulating layer; 302—grooving of the active area on the dielectric passivation layer; 303—grooving of the anode on the passivation layer; 304—grooving of the cathode on the passivation layer; 305—grooving of the anode pad on the passivation layer; 306—grooving of the cathode pad on the passivation layer; 401—passivation layer on the GaN surface after nanopore etching; 402—nanopores in the passivation layer on the GaN surface; 403—passivation layer on the metal electrode after nanopore etching; 404—nanopores in the passivation layer on the metal electrode; 405—passivation layer in the active area after nanopore etching; 406—nanopores in the active area; 81—truncated cone of the light-emitting unit. DETAILED DESCRIPTION

[0043] The specific implementation of the present invention is further described below in conjunction with the accompanying drawings, but the implementation and protection scope of the present invention are not limited thereto.

[0044] like Figure 1a and Figure 1b The figure shows a nanohole LED array chip with an anti-reflection passivation layer in a specific embodiment of the present invention. The GaN-based LED chip is composed of 2×2 light-emitting units, 2×2 anode pads and two cathode pads. The anode pad 204, the cathode pad 203 and the metal connecting wire 202 are isolated from the semiconductor material by a dielectric insulating layer 100. The dielectric passivation layer 103 on the active area of ​​the light-emitting unit has a grooved area 302. The grooved area 302 has a nanohole 406. The diameter of the nanohole is 450nm, the depth of the nanohole is 900nm, and the groove The thickness of the dielectric passivation layer 405 in the region 302 is 70nm; the SiO2 dielectric thin film layer on the surface of the GaN material is also distributed with nanopores 402, the diameter of the nanopores is 450nm, the depth of the nanopores is 280nm, the thickness of the dielectric film at the bottom of the nanopores is 70nm, and the thickness of the dielectric thin film layer 401 is 750nm; there are grooves 303 in the dielectric passivation layer on the anode of the light-emitting unit, grooves 304 in the dielectric passivation layer on the cathode, grooves 305 in the dielectric passivation layer on the anode pad, and grooves 306 in the dielectric passivation layer on the cathode pad.

[0045] From the substrate to the light emitting direction, the active area of ​​the light emitting unit includes a sapphire substrate 1, a GaN buffer layer 2, an unintentionally doped GaN layer 3, an N-type doped GaN layer 4, a quantum well layer 5, a P-type doped AlGaN layer 6, a P-type doped GaN layer 7, a transparent current spreading layer 8, and a dielectric passivation layer 405 in sequence.

[0046] From the substrate to the light emitting direction, the electrode pad region includes the sapphire substrate 1, the GaN buffer layer 2, the unintentionally doped GaN layer 3, the N-type doped GaN layer 4, the dielectric insulating layer 100, the anode pad 204 or the cathode pad 203 in sequence.

[0047] The light-emitting unit is in the form of a truncated cone structure, the diameter of the cone 81 is 120μm, the anode 200 of the light-emitting unit is in the shape of a disk, the diameter is 40μm, and it is distributed at the center of the upper surface of the cone 81; the cathode 201 of the light-emitting unit is in the shape of a ring, the width is 10μm, and it is distributed around the cone 81; the cathode ring 201 has a gap, the gap width is 40μm, and the metal connection line 202 between the anode 200 and the anode pad 204 passes through the gap to achieve connection, and the width of the metal connection line 202 is 20μm. The anode 200 of each light-emitting unit is individually led out to the anode pad 204, all light-emitting units share a cathode and there is a cathode pad 203 in the first row and the second row respectively.

[0048] The SiO2 dielectric insulating layer 100 is distributed on the upper surface of the semiconductor material of the entire chip, with a thickness of 400nm, and forms electrical insulation between the anode pad 204, the cathode pad 203 and the metal connecting wire 202 and the semiconductor material. The SiO2 dielectric thin film layer 401 on the surface of the GaN material is composed of the SiO2 dielectric insulating layer 100 and the SiO2 dielectric passivation layer 101. The thickness of the SiO2 dielectric insulating layer 100 is 400nm, and the thickness of the SiO2 dielectric passivation layer 101 after deposition is 480nm. After the nanopore etching process, the thickness of the SiO2 dielectric passivation layer 101 is 350nm. The passivation layer contains nanopores 402, and the thickness of SiO2 at the bottom of the nanopores is 70nm, so the thickness of the SiO2 dielectric thin film layer 401 is 750nm. There is a grooved area 300 in the anode area 200 of the light-emitting unit, and there is a grooved area 301 in the cathode area 201 of the light-emitting unit.

[0049] In Example 1, the steps for preparing the nanohole LED array chip with an anti-reflection passivation layer are as follows.

[0050] (1) A GaN-based LED epitaxial wafer is prepared by metal oxide vapor deposition method. The structure of the GaN-based LED epitaxial wafer includes a sapphire substrate 1, a GaN buffer layer 2, an unintentionally doped GaN layer 3, an N-type doped GaN layer 4, a quantum well layer 5, a P-type doped AlGaN layer 6 and a P-type doped GaN layer 7. Figure 3a shown.

[0051] (2) Using electron beam evaporation, a transparent current spreading layer ITO 8 with a thickness of 100 nm is deposited on the GaN-based LED epitaxial wafer. It is rapidly annealed for 3 min in a mixed atmosphere of N2200sccm and O235sccm to form an ohmic contact. Then, ultraviolet lithography and wet etching are used. The ITO etching solution is used to immerse the wafer in the active area of ​​the light-emitting unit for 15 min to form an ITO disk with a diameter of 116 μm. Figure 3a shown.

[0052] (3) Inductively coupled plasma etching was used with an etching time of 7 min and an etching depth of 1.2 μm to expose the N-type doped GaN layer and form a truncated cone MESA structure 81 of the light-emitting unit. The MESA diameter is 120 μm. Figure 2a and 3a shown.

[0053] (4) Use plasma enhanced chemical vapor deposition to prepare SiO2 dielectric insulating layer 100 at 350°C in four steps: the first step is to deposit for 7 minutes; the second step is to rotate the LED epitaxial wafer on the carrier by 90° and deposit for 7 minutes; the third step is to rotate the LED epitaxial wafer on the carrier by another 90° and deposit for 7 minutes; the fourth step is to rotate the LED epitaxial wafer on the carrier by another 90° and deposit for 7 minutes; the total thickness of the four steps is 400nm. Then use ultraviolet lithography and inductively coupled plasma etching to form a grooved area 300 in the anode area of ​​the light-emitting unit and a grooved area 301 in the cathode area. Figure 2b and Figure 3b shown.

[0054] (5) Using negative photoresist stripping and electron beam evaporation of Cr / Al / Ti / Au, the thickness of the four metal films are 50 / 8000 / 200 / 100nm respectively, and a disc-shaped anode 200 is prepared in the anode slot area 300 of the light-emitting unit, and the electrode diameter is 40μm; a ring-shaped cathode 201 is prepared in the cathode slot area 301 of the light-emitting unit, and the width is 10μm; a square cathode pad 203 is prepared in the electrode pad area, and the side length of the pad is 100μm, and a circular anode pad 204 is prepared, and the pad diameter is 90μm; and a metal connecting wire 202 between cathodes or between electrodes and pads is prepared, and the width is 20μm; the anode pad 204, the cathode pad 203 and the metal connecting wire 202 are distributed on the SiO2 dielectric insulating layer 100. Figure 2c and 3c shown.

[0055] (6) Using plasma enhanced chemical vapor deposition to prepare SiO2 dielectric passivation layer 101, 480nm is deposited at 350℃; then, using ultraviolet lithography and inductively coupled plasma etching, grooves are formed in the dielectric passivation layer on the active area of ​​the light-emitting unit, and the groove depth is 280nm. The range of the groove area 302 is: within the frustum MESA 81 of the light-emitting unit, outside the anode groove area 300 of the light-emitting unit, and outside the metal connection line area 202 of the light-emitting unit. Figure 2d and 3d As shown. At this time, the SiO2 dielectric film on the surface of the LED chip has three thicknesses. The thickness of the SiO2 dielectric film 103 on the slotted area 302 on the active area of ​​the light-emitting unit is 200nm, the thickness of the SiO2 dielectric film 102 on the metal anode 200, the metal cathode 201, the metal anode pad 203, the metal cathode pad 204, and the metal connecting line 202 is 480nm, and the SiO2 dielectric film on the surface of the GaN material is the sum of the SiO2 dielectric insulating layer 100 and the SiO2 dielectric passivation layer 101, and the thickness is 880nm.

[0056] (7) Spin-coat the adhesion promoter and nanoimprint glue on the dielectric passivation layer, with a glue thickness of 305 nm; then use soft film nanoimprinting to imprint the nanopore pattern on the upper surface of the entire chip, with an imprinting time of 5 minutes and a UV exposure of 4000 mJ / cm 2 , the imprint depth is 280nm;

[0057] Then, inductively coupled plasma etching was used in a mixed atmosphere of CHF3 and Ar, with a CHF3 flow rate of 15 sccm, an Ar flow rate of 50 sccm, a lower electrode RF power of 500 W, a plasma RF power of 200 W, and a processing time of 60 seconds to remove the nanoimprint glue remaining at the bottom of the air hole. At this point, the depth of the nanopores in the nanoimprint glue has penetrated the imprint glue layer, the imprint glue thickness is 280 nm, and the nanopore depth is 280 nm.

[0058] (8) Then, the nanopore pattern on the nanoimprint glue is transferred to the dielectric passivation layer by inductively coupled plasma etching, with the lower electrode RF power of 100W, plasma RF power of 400W, CHF3 50sccm, Ar 100sccm, and time of 4min30sec. At this time, the depth of the nanopores on the grooved area 302 of the light-emitting unit has penetrated the SiO2 dielectric film 103, and the depth of the nanopores on the SiO2 dielectric passivation layer in other areas extends to 200nm.

[0059] (9) Then, the nanopore pattern is transferred from the dielectric passivation layer to the transparent current spreading layer ITO 8 by inductively coupled plasma etching, with the lower electrode RF power of 150 W, the plasma RF power of 500 W, BCl3 30 sccm, Ar 60 sccm, and the time of 1 min. At this time, the depth of the nanopores on the slotted area 302 of the light-emitting unit has penetrated the transparent current spreading layer ITO 8, and the depth of the nanopores on the SiO2 dielectric passivation layer in other areas extends to 260 nm.

[0060] Inductively coupled plasma etching continued, transferring the nanohole pattern to the GaN semiconductor material layer, with the lower electrode RF power of 500W, plasma RF power of 365W, Cl2 90sccm, BCl3 10 sccm, and time of 4min. At this time, the depth of the nanoholes on the slotted area 302 of the light-emitting unit has reached 900nm deep in the GaN material, and the depth of the nanoholes on the SiO2 dielectric passivation layer in other areas extends to 410nm, and the thickness of the SiO2 dielectric passivation layer is reduced by 130nm. Figure 2e and 3e shown.

[0061] (10) Using ultraviolet lithography and wet etching, grooves 303, 304, 305, and 306 are formed in the anode region, cathode region, anode pad region, and cathode pad region to expose the metal electrodes. Figure 2f and 3f shown.

Claims

1. A nanopore LED array chip with an anti-reflection passivation layer, characterized in that: It comprises N × N light-emitting units, N × N anode pads and two cathode pads, wherein N ≥ 2, which are arranged in a square array, the anode electrode pads are connected by metal connecting wires, and the cathode pads are connected by metal connecting wires; the metal connecting wires are isolated from the semiconductor material by a dielectric insulating layer; From the substrate to the light emitting direction, the active area of ​​the light emitting unit includes a sapphire substrate, a GaN buffer layer, an unintentionally doped GaN layer, an N-type doped GaN layer, a quantum well layer, a P-type doped AlGaN layer, a P-type doped GaN layer, a transparent current spreading layer and a dielectric passivation layer in sequence; the diameter of the active area of ​​the light emitting unit is 100 to 200 μm; nanopores are distributed on the active area of ​​the light emitting unit, the depth of the nanopores in the active area exceeds the quantum well layer, and the diameter is 300 to 1000 nm; nanopores are distributed on the dielectric passivation layer at the same time to form an anti-transmittance passivation layer, and the depth of the nanopores on the surface of the GaN material is 200 to 500 nm; from the substrate to the light emitting direction, the electrode pad area includes a sapphire substrate, a GaN buffer layer, an unintentionally doped GaN layer, an N-type doped GaN layer, a dielectric insulating layer and a metal electrode in sequence; the light emitting unit is in the form of a truncated cone structure, and ... The anode of the light unit is in the shape of a disk and is distributed at the center of the upper surface of the truncated cone; the cathode is in the shape of a ring and is distributed around the truncated cone; a notch is provided on the ring of the cathode, and the metal connecting wire between the anode and the anode pad passes through the notch for connection, the width of the metal connecting wire is greater than 20 μm, and the width of the notch is greater than 20 μm; the anode of each light-emitting unit is individually connected to the anode pad, all light-emitting units share a cathode and have a cathode pad in the first row and the Nth row respectively; the dielectric insulating layer covers the upper surface of the semiconductor material of the entire chip, and forms electrical insulation between the electrode pad and the metal connecting wire and the semiconductor material; the dielectric insulating layer is SiO2, SiN or SiON, and the thickness is greater than or equal to 300 nm; the semiconductor material includes a transparent current spreading layer, a P-type doped GaN layer, a P-type doped AlGaN layer, a quantum well layer, and an N-type doped GaN layer; The preparation of the nanopore LED array chip with an anti-reflection passivation layer comprises the following steps: Step 1, using a metal oxide vapor deposition method to prepare a GaN-based LED epitaxial wafer, the structure of the GaN-based LED epitaxial wafer sequentially includes a sapphire substrate, a GaN buffer layer, an unintentionally doped GaN layer, an N-type doped GaN layer, a quantum well layer, a P-type doped AlGaN layer and a P-type doped GaN layer; Step 2: Deposit a transparent current spreading layer on a GaN-based LED epitaxial wafer using electron beam evaporation, form an ohmic contact through rapid annealing, and then use ultraviolet lithography and wet etching to form a transparent current spreading layer disk distributed only in the active area of ​​the light-emitting unit; the annealing temperature of the rapid annealing process is 500-650°C, the heating rate is 5-15°C / sec, the atmosphere is a mixture of nitrogen and oxygen, and the annealing time is 60-300sec; Step 3: using inductively coupled plasma etching to expose the N-type doped GaN layer to form a truncated cone structure of the light-emitting unit; Step 4: using plasma enhanced chemical vapor deposition to prepare a dielectric insulating layer, and then using ultraviolet lithography and inductively coupled plasma etching to open grooves in the anode and cathode regions of the light-emitting unit; comprising the following steps: Step 41, placing the LED epitaxial wafer into a sample carrier of a plasma enhanced chemical vapor deposition device, and depositing a dielectric film to 1 / 4 of the target thickness; Step 42, rotating the LED epitaxial wafer on the carrier by 90 degrees, and depositing a dielectric film to 1 / 2 of the target thickness; Step 43, rotating the LED epitaxial wafer on the carrier plate by another 90°, and depositing a dielectric film to 3 / 4 of the target thickness; Step 44, rotating the LED epitaxial wafer on the carrier plate by another 90°, and depositing a dielectric film to a target thickness; Step 5: using negative resist stripping and electron beam evaporation, a disc-shaped anode is prepared in the anode slot area on the truncated table of the light-emitting unit, a ring-shaped cathode is prepared in the cathode slot area, and an anode pad, a cathode pad and a metal connecting wire are prepared on the electrode insulating layer; Step 6: Prepare a dielectric passivation layer by plasma enhanced chemical vapor deposition, and then use ultraviolet lithography and inductively coupled plasma to etch the dielectric passivation layer on the active area to form grooves for nanoimprinting; the range of the grooved area includes within the truncated cone of the light-emitting unit, outside the anode groove area of ​​the light-emitting unit, and outside the metal connection line area of ​​the light-emitting unit; Step 7: Spin-coat a tackifier and nanoimprint glue on the dielectric passivation layer, and then use soft film nanoimprinting to imprint a nanopore pattern on the upper surface of the entire chip; then use inductively coupled plasma etching to remove the nanoimprint glue remaining at the bottom of the air hole; Step 8: Using inductively coupled plasma etching to transfer the nanopore pattern on the nanoimprint glue to the dielectric passivation layer; Step 9, etching is performed again using an inductively coupled plasma etcher; in the active area, the nanohole pattern is transferred from the thinner dielectric passivation layer to the transparent current spreading layer and the GaN semiconductor material layer in sequence, and the etching depth of the GaN semiconductor material exceeds the depth of the quantum well by more than 50nm; in other areas, the nanohole pattern continues to extend deeper into the thicker dielectric passivation layer; Step 10: Use UV lithography and wet etching to expose metal electrodes in the anode, cathode, electrode pad and metal connecting line areas.

2. A method for preparing a nanopore LED array chip with an anti-reflection passivation layer, characterized in that: The steps include: Step 1, using a metal oxide vapor deposition method to prepare a GaN-based LED epitaxial wafer, the structure of the GaN-based LED epitaxial wafer sequentially includes a sapphire substrate, a GaN buffer layer, an unintentionally doped GaN layer, an N-type doped GaN layer, a quantum well layer, a P-type doped AlGaN layer and a P-type doped GaN layer; Step 2: Deposit a transparent current spreading layer on a GaN-based LED epitaxial wafer using electron beam evaporation, form an ohmic contact through rapid annealing, and then use ultraviolet lithography and wet etching to form a transparent current spreading layer disk distributed only in the active area of ​​the light-emitting unit; the annealing temperature of the rapid annealing process is 500-650°C, the heating rate is 5-15°C / sec, the atmosphere is a mixture of nitrogen and oxygen, and the annealing time is 60-300sec; Step 3: using inductively coupled plasma etching to expose the N-type doped GaN layer to form a truncated cone structure of the light-emitting unit; Step 4: using plasma enhanced chemical vapor deposition to prepare a dielectric insulating layer, and then using ultraviolet lithography and inductively coupled plasma etching to open grooves in the anode and cathode regions of the light-emitting unit; comprising the following steps: Step 41, placing the LED epitaxial wafer into a sample carrier of a plasma enhanced chemical vapor deposition device, and depositing a dielectric film to 1 / 4 of the target thickness; Step 42, rotating the LED epitaxial wafer on the carrier by 90 degrees, and depositing a dielectric film to 1 / 2 of the target thickness; Step 43, rotating the LED epitaxial wafer on the carrier plate by another 90°, and depositing a dielectric film to 3 / 4 of the target thickness; Step 44, rotating the LED epitaxial wafer on the carrier plate by another 90°, and depositing a dielectric film to a target thickness; Step 5: using negative resist stripping and electron beam evaporation, a disc-shaped anode is prepared in the anode slot area on the truncated table of the light-emitting unit, a ring-shaped cathode is prepared in the cathode slot area, and an anode pad, a cathode pad and a metal connecting wire are prepared on the electrode insulating layer; Step 6: Prepare a dielectric passivation layer by plasma enhanced chemical vapor deposition, and then use ultraviolet lithography and inductively coupled plasma to etch the dielectric passivation layer on the active area to form grooves for nanoimprinting; the range of the grooved area includes within the truncated cone of the light-emitting unit, outside the anode groove area of ​​the light-emitting unit, and outside the metal connection line area of ​​the light-emitting unit; Step 7: Spin-coat a tackifier and nanoimprint glue on the dielectric passivation layer, and then use soft film nanoimprinting to imprint a nanopore pattern on the upper surface of the entire chip; then use inductively coupled plasma etching to remove the nanoimprint glue remaining at the bottom of the air hole; Step 8: Using inductively coupled plasma etching to transfer the nanopore pattern on the nanoimprint glue to the dielectric passivation layer; Step 9, etching is performed again using an inductively coupled plasma etcher; in the active area, the nanohole pattern is transferred from the thinner dielectric passivation layer to the transparent current spreading layer and the GaN semiconductor material layer in sequence, and the etching depth of the GaN semiconductor material exceeds the depth of the quantum well by more than 50nm; in other areas, the nanohole pattern continues to extend deeper into the thicker dielectric passivation layer; Step 10: Use UV lithography and wet etching to expose metal electrodes in the anode, cathode, electrode pad and metal connecting line areas.

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