Instruction for vector operation with constant value

Abstract

Disclosed embodiments relate to instructions for vector operations with immediate values. In one embodiment, a system includes a memory and a processor including an extraction circuit to extract an instruction from a code storage, the instruction including an opcode, a destination identifier to specify a destination vector register, a first immediate number, and a write mask identifier to specify a write mask register, the write mask register including at least one bit corresponding to each destination vector register element, the at least one bit to specify whether a destination vector register element is masked or unmasked; a decode circuit to decode the extracted instruction; and an execution circuit to execute the decoded instruction to use the write mask register to determine unmasked elements in the destination vector register, and to broadcast the first immediate number to one or more unmasked vector elements in the destination vector register when the opcode specifies to broadcast.

Description

TECHNICAL FIELD

[0001] The field of the invention relates generally to computer processor architecture, and more specifically to instructions for vector operations with constant values. BACKGROUND

[0002] For applications that use vector operations for computations at run-time, the compiler or assembly programmer must attempt to assign the required vector registers for the vector operations in the loop. Failure to assign registers for all vector operations can result in vector register overflow, which can cause performance degradation and inefficient power consumption.

[0003] For example, in graphics applications, a translation transform is used to move a graphics object to a new location by adding a constant value to each coordinate point. The more graphics objects that exist in an image, the more vector registers will be used to move them. And if different graphics objects are to be translated by different amounts, more registers will be used to store the different constants. BRIEF DESCRIPTION OF DRAWINGS

[0004] The invention is illustrated in the drawings, which are in example and not limitation, in which like reference numerals indicate like elements and in which:

[0005] Figure 1 is a block diagram illustrating a processing component for executing instructions for vector operations with constant values, in accordance with some embodiments;

[0006] Figure 2 is a flow diagram of a process to be carried out by a processor to execute instructions for vector operations with constant values, in accordance with some embodiments;

[0007] Figure 3 is a block diagram illustrating a format for instructions for vector operations with constant values, in accordance with some embodiments;

[0008] Figure 4A illustrating execution of an instruction to broadcast an immediate number;

[0009] Figure 4B illustrating execution of an instruction to broadcast an immediate number;

[0010] Figure 4C illustrating execution of an instruction to broadcast an immediate number with a stride;

[0011] Figure 4D illustrating execution of an instruction to broadcast an immediate number with a stride;

[0012] Figure 4E illustrating execution of an instruction to broadcast an immediate number with a stride;

[0013] Figure 4F The diagram illustrates the execution of the instruction used to broadcast an immediate value to the mask register;

[0014] Figure 4G The diagram illustrates the execution of the instruction used to set the destination mask register to the result of an immediate operation;

[0015] Figure 4H The diagram illustrates the execution of instructions used to broadcast the results of operations on immediate values;

[0016] Figure 5 The diagram illustrates an exemplary execution of an instruction with immediate operands;

[0017] Figure 6 The figure illustrates an embodiment of hardware for processing instructions with immediate operands;

[0018] Figure 7 The figure illustrates an embodiment of a method by which a processor executes instructions to process instructions having immediate operands;

[0019] Figure 8 The diagram illustrates an exemplary execution of an instruction with immediate operands;

[0020] Figure 9 The figure illustrates an embodiment of hardware for processing instructions with immediate operands;

[0021] Figure 10 The figure illustrates an embodiment of a method by which a processor executes instructions to process instructions having immediate operands;

[0022] Figure 11 The diagram illustrates an exemplary execution of an instruction with immediate operands;

[0023] Figure 12 The figure illustrates an embodiment of hardware for processing instructions with immediate operands;

[0024] Figure 13 The figure illustrates an embodiment of a method by which a processor executes instructions to process instructions having immediate operands;

[0025] Figure 14 The diagram illustrates an exemplary execution of an instruction with immediate operands;

[0026] Figure 15 The figure illustrates an embodiment of hardware for processing instructions with immediate operands;

[0027] Figure 16 The figure illustrates an embodiment of a method by which a processor executes instructions to process instructions having immediate operands;

[0028] Figure 17 The diagram illustrates an exemplary execution of an instruction with immediate operands;

[0029] Figure 18 The figure illustrates an embodiment of hardware for processing instructions with immediate operands;

[0030] Figure 19 The figure illustrates an embodiment of a method by which a processor executes instructions to process instructions having immediate operands;

[0031] Figure 20 The diagram illustrates an exemplary execution of an instruction with immediate operands;

[0032] Figure 21 The figure illustrates an embodiment of hardware for processing instructions with immediate operands;

[0033] Figure 22 The figure illustrates an embodiment of a method by which a processor executes instructions to process instructions having immediate operands;

[0034] Figure 23 The diagram illustrates an exemplary execution of an instruction with immediate operands;

[0035] Figure 24 The figure illustrates an embodiment of hardware for processing instructions with immediate operands;

[0036] Figure 25 The figure illustrates an embodiment of a method by which a processor executes instructions to process instructions having immediate operands;

[0037] Figure 26 The diagram illustrates an exemplary execution of an instruction with immediate operands;

[0038] Figure 27 The figure illustrates an embodiment of hardware for processing instructions with immediate operands;

[0039] Figure 28 The figure illustrates an embodiment of a method by which a processor executes instructions to process instructions having immediate operands;

[0040] Figures 29A-29C This is a block diagram illustrating a general vector-friendly instruction format and its instruction template according to an embodiment of the present invention;

[0041] Figure 29A This is a block diagram illustrating a general vector-friendly instruction format and its Class A instruction template according to an embodiment of the present invention;

[0042] Figure 29B This is a block diagram illustrating a general vector-friendly instruction format and its Class B instruction template according to an embodiment of the present invention;

[0043] Figure 29C This is a block diagram illustrating a general vector-friendly instruction format and its Class B instruction template according to an embodiment of the present invention;

[0044] Figure 30 This is a block diagram of a register architecture according to an embodiment of the present invention;

[0045] Figure 31A This is a block diagram illustrating both an exemplary ordered pipeline and an exemplary register renaming and unordered release / execution pipeline according to an embodiment of the present invention;

[0046] Figure 31B This is a block diagram illustrating an exemplary embodiment of an ordered architecture core to be included in a processor, and an exemplary register renaming and out-of-order release / execution architecture core, according to embodiments of the present invention.

[0047] Figure 32A -B diagram illustrates a more specific example of an ordered core architecture, which may be one of several logical blocks in a chip (including other cores of the same type and / or different types);

[0048] Figure 32A This is a block diagram of a single processor core according to an embodiment of the present invention, its connection to the on-die interconnect network, and a local subset of its Level 2 (L2) cache;

[0049] Figure 32B According to an embodiment of the present invention Figure 32A An expanded diagram of the processor core.

[0050] Figure 33 This is a block diagram of a processor according to an embodiment of the present invention, which may have more than one core, may have an integrated memory controller, and may have an integrated graphics device;

[0051] Figure 34 A block diagram of a system according to an embodiment of the present invention is shown;

[0052] Figure 35 This is a block diagram of a first, more specific, exemplary system according to an embodiment of the present invention;

[0053] Figure 36 This is a block diagram of a second, more specific, exemplary system according to an embodiment of the present invention;

[0054] Figure 37 This is a block diagram of a system-on-a-chip (SoC) according to an embodiment of the present invention; and

[0055] Figure 38This is a block diagram illustrating the use of a software instruction converter to convert binary instructions in a source instruction set into binary instructions in a target instruction set, according to an embodiment of the present invention. Detailed Implementation

[0056] Numerous specific details are set forth in the following description. However, it is to be understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known circuits, structures, and techniques have not been shown in detail so as not to obscure the understanding of this description.

[0057] References to "an embodiment," "an embodiment," "an example embodiment," etc., in the specification indicate that the described embodiment may include a particular feature, structure, or characteristic, but not every embodiment may necessarily include that particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is claimed that incorporating other embodiments (whether explicitly described or not) to affect such a feature, structure, or characteristic is within the knowledge of those skilled in the art.

[0058] To reduce the pressure on vector registers, it is possible to extend the instruction set of the architecture hardware, as implemented in the embodiments disclosed herein, to enable vector operations using immediate (constant) values.

[0059] For example, in many video and image processing algorithms, there is a need for an architecture that supports instructions that operate on the entire vector using the same value in order to improve performance.

[0060] For example, moving to the next row of pixels (Y coordinates) requires incrementing the vector register containing the Y coordinates of the current row by 1.

[0061] As another example, moving to the next 8 pixels in that row requires adding 8 to the vector register containing the current X coordinate.

[0062] As another example, some approaches in other instruction set architectures (ISAs) require additional registers to hold constant values ​​and / or to read these constant values ​​directly from memory, which leads to cumbersome code that also consumes registers.

[0063] The embodiments disclosed herein provide an efficient way to (re)materialize (rematerialize) constant values, thereby freeing up such registers for other uses elsewhere (e.g., in hot cycles, as used herein, hot cycles refer to cycles that are executed frequently).

[0064] Currently, constant values ​​in a vector can be assigned / filled from memory either by using, for example, the VBROADCAST instruction, which uses constant values ​​stored in a memory location to fill each unmasked element of the vector register. This is useful for simple, repetitive cases, such as {m32, m32, ...,m32}. Alternatively, constant values ​​in a vector can be assigned / filled from memory by overflowing into (constant) memory (which occurs whenever the register dispatcher runs out of registers, and therefore must be "overflowed" by saving and restoring those values ​​from memory). In some embodiments, the VBROADCAST instruction is an instruction for broadcasting floating-point data to a vector location.

[0065] The embodiments disclosed herein modify the processor instruction set architecture to extend the capabilities of the VBROADCAST instructions. Using the embodiments herein offers the advantage of allowing the use of immediate values ​​in instructions without requiring that value to be stored in a register.

[0066] The disclosed vector operation embodiments allow for more sources than the current VBROADCAST instruction.

[0067] The disclosed embodiments of vector operations also allow immediate (constant) operands.

[0068] The disclosed embodiments of vector operations can also handle non-repetitive, frequently occurring vector constants involving constant values ​​(immediate values).

[0069] The disclosed embodiments extend the ability to set each partition or element of a multi-element destination register in at least two directions:

[0070] • More sources to broadcast from: immediate values, any vector element; and

[0071] • Handling non-repetitive, frequently occurring vector constants involving constant values ​​(immediate values).

[0072] In some embodiments, extended versions of "VBROADCAST" and other instructions allow multiple sources, multiple destinations, and immediate values.

[0073] Figure 1This is a block diagram illustrating a processing component according to some embodiments, the processing component being used to execute instructions for vector operations utilizing constant values ​​(immediate values). As shown, the computing system 100 includes a code storage device 102, a fetch circuit 104, a decode circuit 106, an execution circuit 108, a register 110, a memory 112, and a deprecation or commit circuit 114. In operation, instructions are fetched from the code storage device 102 by the fetch circuit 104, the code storage device 102 may include a cache memory, on-chip memory, memory on the same die as the processor, an instruction register, a general-purpose register, or system memory, without limitation. In one embodiment, the instructions have similar characteristics to... Figure 3 and Figures 29A-29C That format. After retrieving instructions from the code storage device 102, the decoding circuit 106 decodes the retrieved instructions, including by parsing various fields of the instructions. After decoding the retrieved instructions, the execution circuit 108 executes the decoded instructions. Regarding Figures 4A-4H Several exemplary embodiments of execution using execution circuitry 108 are illustrated and described. During instruction execution, execution circuitry 108 can read data from register 110 and memory 112 and write data to register 110 and memory 112, without limitation. Register 110 may include, but is not limited to, data registers, instruction registers, vector registers, mask registers, general-purpose registers, on-chip memory, memory on the same die as the processor, or memory in the same package as the processor. Memory 112 may include, but is not limited to, on-chip memory, memory on the same die as the processor, memory in the same package as the processor, cache memory, or system memory. After execution circuitry executes an instruction, deprecation or commit circuitry 114 can deprecate the instruction, thereby ensuring that the execution result is written to or has been written to the destination of the execution result, and freeing up or releasing resources for later use.

[0074] Figure 2 This is a method by which the processor executes instructions for performing operations using constant values ​​(immediate values). After the process begins, at 202, the fetch circuitry retrieves instructions from the code storage device. These instructions include an operand code, a destination identifier for specifying a destination vector register, a first immediate value, a second immediate value, and a write mask identifier for specifying a write mask register. The write mask register includes at least one bit corresponding to each element of the destination vector register, indicating whether the element is masked or not. The destination vector register is sometimes called a packed destination register.

[0075] At position 204, the extracted instructions are decoded by the decoding circuit.

[0076] At position 206, the execution circuit uses the first immediate value to set the data value.

[0077] At position 208, the execution circuit uses the second immediate value to set the step value.

[0078] At 210, the execution circuitry uses a write mask register to identify the unmasked elements of the destination vector register.

[0079] At 212, the execution circuitry determines whether the opcode specifies a step. If not, the process ends. However, if it does, at 214, the execution circuitry stores the data value into the first unmasked destination vector register element, and for each subsequent unmasked destination vector register element, generates a step-over value by adding the step value to the immediately preceding unmasked destination vector register, and stores the step-over value into the unmasked destination vector register element. In some embodiments, the execution circuitry zeroes out the masked elements of the destination vector register. In some embodiments, the masked elements of the destination vector register retain their previous values. The process then ends.

[0080] Figure 3 This is a block diagram illustrating the format of instructions for operations using constant values ​​(immediate values) according to some embodiments. As shown, instruction 300 includes an operand code 302, a destination identifier 304, an immediate value 306, an optional source identifier 308 (optional instruction fields are shown in boxes with dashed outlines), an optional second immediate value 310, an optional element size identifier 312, and an optional write mask 314.

[0081] In some embodiments, the operation code 302 is VBROADCAST * As shown, the operation code 302 includes an asterisk (" * The asterisk (*) is a suffix or prefix that can be added to the operand to control the operation of the instruction. In some embodiments, operand 302 is an arithmetic operation, such as ADD, SUB, DIV, MUL, MOD, etc., in which case the corresponding suffix will replace the asterisk. In some embodiments, for example, operand 302 includes an “IM” or “STR” control suffix to specify whether the immediate operand is broadcast to each fixed-size partition of the destination register (as stated below). Figure 4A (in the middle), or whether to add the step value to a consecutive fixed-size partition of the destination register (as described below, in Figure 4C , 4D (and 4E). In the following text about Figures 4A-4H The diagrams illustrate and discuss some examples of different operand codes.

[0082] In the following text, the following is about Figures 29A-29C Examples describing vector-friendly instruction formats. Comparison Figure 3 and Figures 29A-29C In some embodiments, the operation code 302 is mapped to the basic operation field 542 ( Figure 5 The destination identifier 304, immediate value 306, and optional source identifier 308 are mapped to register index field 2944. Figures 29A-29C The register index field 2944 is described below as containing enough bits N to identify three source registers and one destination register. Further references Figures 29A-29C In some embodiments, the optional second immediate value 310, the optional element size identifier 312, and the optional write mask 314 are respectively mapped to the immediate number field 2972, the data element width field 2964, and the write mask field 2970.

[0083] In some embodiments, destination identifier 304 specifies a vector register, such as one of the vector registers provided in the processor's register file. In some embodiments, destination identifier 304 specifies a mask register, such as one of the mask registers provided in the processor's register file. (The following refers to...) Figure 30 An exemplary processor register file is illustrated and described.

[0084] In some embodiments, the optional source identifier 308 specifies a source vector register, such as a vector register included in the processor's register file (see, for example, below). Figure 4C (Discussion and illustrations of embodiments). In some embodiments, the optional source identifier 308 identifies a general-purpose register included in the processor's register file, for example, as discussed below regarding... Figure 4C The embodiments discussed and illustrated herein. Further details are as follows. Figure 30 The associated description describes an embodiment of the processor's register file. In some embodiments, an optional source identifier 308 identifies a memory location.

[0085] Some embodiments of vector operations utilizing immediate values ​​include an optional second immediate value 310, for example, as described below regarding Figure 4D and Figure 4E The embodiments discussed and illustrated herein.

[0086] In some embodiments, the operand code includes optional element size identifiers 312, such as prefixes or suffixes "B", "W", "D", and "Q", which correspond to the size of each destination vector element—1 byte, 2 bytes, 4 bytes, or 8 bytes, respectively. In some embodiments, the operand code includes optional element size identifiers 312, such as prefixes or suffixes "H", "S", "D", "Q", and "E", which correspond to the precision level of each destination vector element—half-precision (2 bytes), single-precision (4 bytes), double-precision (8 bytes), and quad-precision (16 bytes), respectively. In other embodiments, the optional element size identifiers 312 are instruction parameters or operands specifying the size and / or precision level of the destination vector element.

[0087] In some embodiments, the optional write mask 314 is a multi-bit operand, where each bit controls whether a corresponding element of the destination vector is masked. In some embodiments, the optional write mask 314 identifies a write mask register in the processor's register file. In some embodiments, if an element of the destination vector is masked, the element retains its value prior to instruction execution; in other embodiments, if an element of the destination vector is masked, the element is set to zero during instruction execution. In some embodiments, whether a value in an element of the destination vector retains its value or is zeroed is specified by a mask element control field, which is to be included in instructions used for vector operations utilizing immediate values. If an element of the destination vector is not masked, the element is set to the value obtained by the execution of the instruction.

[0088] In some embodiments, the behavior of an optional write mask 314 is specified by using a specific selection of the operand 302, or by a suffix or prefix to the operand 302. For example, the suffix or prefix "SZ" can be added to the operand to indicate that the masked vector elements are to be "set to zero". Alternatively, the suffix or prefix "ODD" can be added to the operand to indicate that the odd elements of the destination vector are to be unmasked.

[0089] Figures 4A-4H The figures illustrate various embodiments of instructions for performing vector operations using constant values.

[0090] Figure 4A The diagram illustrates the execution of an instruction used to broadcast an immediate value. This instruction includes an operand code (e.g., the mnemonic "VBROADCASTIMM"). *The instruction `<imm>` is used to specify the destination identifier (zmm / ymm / xmm) of the packing destination register and the immediate value. Execution of this instruction broadcasts the immediate value (imm) to all vector (packed data) elements of the packing destination register (zmm / ymm / xmm). This example has register zmm2 as the destination and 0xF as the immediate value. 0xF is broadcast to every element of zmm2.

[0091] Operation code mnemonic VBROADCASTIMM * Including the asterisk " * The asterisk (*) indicates various controls that can be added to control the operation of instructions. (As used herein, the term "mnemonic" refers to an abbreviation of an operation, instruction, or operation code.) For example, here, the asterisk can be replaced by one or more suffixes such as "B" or "W" or "D" or "Q" to specify the size of the vector elements of zmm2 as bytes, words, double words, or quad words.

[0092] The elements of the destination vector 402 before execution are illustrated as "x", signifying any value (don't care value). They are not relevant to the discussion of the operation of this instruction. The immediate value 404 is shown as having the value 0xF. In response to the decoded instruction 401 broadcasting the immediate value, the execution circuit 406 uses the broadcast circuit 407 to broadcast the immediate value 404 to each element of the destination vector register. In this illustration, the destination vector register after execution is shown as 408. In some embodiments, the broadcast circuit 407 is a crossbar switch.

[0093] Figure 4B The diagram illustrates the execution of an instruction used to broadcast an immediate value. Instruction 411 includes an arithmetic code (e.g., the mnemonic "VBROADCASTVREG"). * The instruction selects an element from the source vector register (zmm1 / ymm1 / xmm1), the destination vector (SIMD, packed data) register (zmm2 / ymm2 / xmm2), and an immediate value (imm1). The execution of this instruction uses the immediate value (imm1) to select an element from the source vector register (zmm2 / ymm2 / xmm2) and broadcasts the selected value to all vector (packed data) elements in the destination register (zmm1 / ymm1 / xmm1).

[0094] Operation code mnemonic VBROADCASTVREG * Including the asterisk " *The asterisk (*) indicates various controls that can be added to control the operation of instructions. For example, here, the asterisk can be replaced by one or more suffixes such as "B" or "W" or "D" or "Q" to specify the size of the vector elements of zmm2 as bytes, words, double words, or quad words.

[0095] The elements of the destination vector 412 before execution are illustrated as "x", signifying arbitrary values. They are not relevant to the discussion of the operation of this instruction.

[0096] This example shows register ymm1 as the destination, imm1 414 having the value 2, and source vector register xmm2 having the value 3 in its third element. In response to the decoded instruction 411 to broadcast an immediate value, execution circuitry 416 uses immediate value 414 to control multiplexer 415 to select the third element (xmm2[2]) of source vector register xmm2 413, and uses broadcast circuitry 417 to broadcast the selected value to each element in destination vector register ymm1 418. In some embodiments, broadcast circuitry 417 is a crossbar switch.

[0097] Figure 4C The diagram illustrates the execution of an instruction used to broadcast immediate values ​​using a step. This instruction includes an operand code (e.g., the mnemonic "VBROADCASTSTRIMM"). * The instruction sets the first element of the destination vector register (zmm1 / ymm1 / xmm1), the source general-purpose register (m / reg), and the immediate value imm1. The execution of this instruction sets the first element of the destination vector register (zmm1 / ymm1 / xmm1) to the value of the source general-purpose register (m / reg 423), and uses adders 427A-427G to add the step value specified by the immediate value imm1 424 to subsequent elements of the destination vector register 428.

[0098] Operation code mnemonic VBROADCASTSTRIMM * Including the asterisk " * The asterisk (*) indicates various controls that can be added to control the operation of instructions. For example, here, the asterisk can be replaced by one or more suffixes such as "B" or "W" or "D" or "Q" to specify the size of the vector elements of zmm2 as bytes, words, double words, or quad words.

[0099] The elements of the destination vector register ymm1 422 before execution are illustrated as "x", signifying any value. They are not relevant to the discussion of the instruction's operation. This example uses register ymm1 422 as the destination, sets the first element of the destination vector (shown as ymm1 428 after execution) to 0x333 (the value stored in the general-purpose register m / reg), and successively adds a step value of 2 (as specified by imm1) to each subsequent element of ymm1 428. In response to the decoded instruction 421 broadcasting an immediate value using a step, execution circuitry 426 sets the first element of the destination vector register ymm1 428 to the value stored in general-purpose register 423 (which is 333), and uses adders 427A-427G to successively add the step value (which is 2) stored in imm1 424 to each of the second and subsequent elements.

[0100] As illustrated, ymm1 428 is sorted according to little-endian, with the least significant element shown on the right. In some embodiments, ymm1 428 is sorted according to big-endian.

[0101] Figure 4D The diagram illustrates the execution of an instruction used to broadcast immediate values ​​using a step. This instruction includes an operand code (e.g., the mnemonic "VBROADCASTSTRVREG"). * The instruction executes the following parameters: destination vector (SIMD, packed data) register (zmm1 / ymm1 / xmm1), source vector (SIMD, packed data) register (zmm2 / ymm2 / xmm2), first immediate value (imm1), and second immediate value (imm2). The first immediate value (imm1) is used to select an element of the source vector (SIMD, packed data) register (zmm2 / ymm2 / xmm2), the first data element of the destination vector (SIMD, packed data) register (zmm1 / ymm1 / xmm1) is set to the value of the selected element, and the step value specified by the second immediate value is successively added to the second and subsequent elements of the destination vector (zmm1 / ymm1 / xmm1) register.

[0102] Operation code mnemonic VBROADCASTSTRVREG * Including the asterisk " * The asterisk (*) indicates various controls that can be added to control the operation of instructions. For example, here, the asterisk can be replaced by one or more suffixes such as "B" or "W" or "D" or "Q" to specify the size of the vector elements of zmm2 as bytes, words, double words, or quad words.

[0103] This example has register ymm1 as the destination, imm1 434 as the first immediate value, source vector xmm2 433, and a second immediate value imm2 435. The elements of ymm1 432 before execution and all elements of xmm2 433 except element [1] are illustrated as “x”, meaning any value. They are not relevant to the discussion of the operation of this instruction. In response to the decoded instruction 431 broadcasting the immediate value using a step, the execution circuit 437 uses a multiplexer 436 controlled by imm1 434 (with a value of 1) to select the first (index=1) element (with a value of 33) of the source vector register xmm2 433 and sets the first element of the destination vector register ymm1 439 to the selected element. The execution circuit 437 further uses adders 438A-438G to successively add the step value “2” specified by imm2 435 to the second and subsequent elements of ymm1 439.

[0104] Figure 4E The diagram illustrates the execution of an instruction used to broadcast immediate values ​​using a step. Instruction 441 includes an arithmetic code (e.g., the mnemonic "VBROADCASTSTRIMMMSKED"). * The instruction specifies the destination vector (SIMD, packetized data) register (zmm1 / ymm1 / xmm1), write mask (k1), mask element control field (z), first immediate value (imm1), and second immediate value (imm2). The execution of this instruction uses the first immediate value (imm1) to set the first unmasked element of the destination vector register (zmm1 / ymm1 / xmm1), and then successively adds the step value specified by the second immediate value (imm2) to the second and subsequent unmasked elements of the destination vector register (zmm1 / ymm1 / xmm1). In an embodiment, the mask element control field z, when equal to zero, causes the execution of this instruction to zero out the masked destination vector element, and when equal to 1, causes the execution of this instruction to allow the masked destination vector element to retain its previous value.

[0105] Operation code mnemonic VBROADCASTSTRIMMMSKED * Including the asterisk " * The asterisk (*) indicates various controls that can be added to control the operation of instructions. For example, here, the asterisk can be replaced by one or more suffixes such as "B" or "W" or "D" or "Q" to specify the size of the vector elements of ymm1 as bytes, words, double words, or quad words.

[0106] This example has ymm1 as the destination, where the elements of ymm1 442 before execution are illustrated as "x", meaning any value. These are not relevant to the discussion of the operation of this instruction. In response to the decoded instruction 441 broadcasting an immediate value using a step, the execution circuit 446 uses the broadcast circuit 448 under the write mask k1 445 to set the first unmasked element of ymm1 449 to 55 as specified by imm1 443, and uses adders 447A to 447D to successively add the step value 3 specified by imm2 444 to the second and subsequent unmasked elements of ymm1 449. In some embodiments, the broadcast circuit 448 is a crossbar switch. This example has a masked element control field z 450, which is equal to zero, causing the execution circuit to zero out the masked elements of ymm1 449.

[0107] Figure 4F The diagram illustrates the execution of an instruction used to broadcast an immediate value to a write mask. Instruction 451 includes an arithmetic code (e.g., the mnemonic "KBROADCASTIMM2MSK"). * The instruction sets up a destination write mask k1, a write mask k2, and an immediate value imm1. Execution of this instruction logically partitions the write mask k1 into equal-sized logical partitions with the same size as imm1, uses the write mask k2 to identify the unmasked partitions of the destination write mask k1, and broadcasts imm1 to the unmasked logical partitions.

[0108] The mnemonic for the operation code is KBROADCASTIMM2MSK. * Including the asterisk " * The asterisk (*) indicates various controls that can be added to control the operation of instructions. For example, here, the asterisk can be replaced by one or more suffixes such as "B" or "W" or "D" or "Q" to specify the number of least significant bits of the destination write mask k1 to be written, and the size is a byte, word, double word, or quad word.

[0109] This example has a write mask k1 as the destination, where the elements of the write mask k1 452 before execution are illustrated as "x", meaning any value. These are not relevant to the discussion of the operation of this instruction. In response to the decoded instruction 451 to broadcast an immediate value to the write mask, the execution circuit 455 logically partitions the destination write mask k1 into equal-sized logical partitions of the same size as the 8-bit imm1 454, and uses the write mask k2 453 and multiplexer 456 to select the value of each element to be written into k1 458. When masked (e.g., when k2[i] equals 0), the old value of the corresponding k1 element is selected, and when unmasked (e.g., when k2[i] equals 1), the immediate value imm1 454 is selected and written to the corresponding logical partition of k1; as shown, imm1 454 is written to the first, sixth, seventh, and eighth logical partitions of k1. It should be noted that the write mask k2 is optional, and when the write mask k2 is not provided, each logical partition of k1 is set to an immediate value.

[0110] In the following text, regarding Figures 29A-29C Examples describing vector-friendly instruction formats. Comparison Figure 4F and Figures 29A-29C In some embodiments, the operation code KBROADCASTIMM2MSK * Mapped to basic operation field 2942 ( Figure 29B In some embodiments, the destination write mask identifier k1, the source write mask identifier k2, and the immediate value imm1 are mapped to register index field 2944 (). Figure 29A The register index field 2944 is described below as containing enough bits N to identify three source registers and one destination register.

[0111] Figure 4G The diagram illustrates the execution of an instruction used to set the destination mask register to write the result of an operation on an immediate value. Instruction 461 includes the arithmetic code (e.g., the mnemonic "KXORKREGIMM"). * The instruction executes an operation using the immediate value imm1 and the source mask register k2, and writes the result to the destination mask register k1.

[0112] Operation code mnemonic KXORKREGIMM * Including the asterisk " *The asterisk (*) indicates various controls that can be added to control the operation of instructions. For example, here, the asterisk can be replaced by one or more suffixes such as "B" or "W" or "D" or "Q" to specify the number of least significant bits of the destination mask register k1 to be written, and the size is a byte, word, double word, or quad word.

[0113] This example illustrates a write mask k1 as the destination, where the elements of the pre-execution write mask k1 462 are illustrated as "x", signifying any value. These are not relevant to the discussion of the instruction's operation. In response to the decoded instruction 461 setting the write mask to the result of an operation, the execution circuit 465 uses an XOR gate 466 to perform a bitwise XOR operation between the source write mask k2 463 (with a value of 0x00) and the 8-bit immediate value imm1 464 (with an initial value of 0x035), and writes the result 0x35 to the destination write mask register k1 468.

[0114] Figure 4G The illustrated embodiments demonstrate the following benefits of this embodiment: using register file locations to store immediate values ​​avoids the use of general-purpose registers and vector registers in the register file. In some embodiments, the immediate value imm1, such as that stored in k1 468, is used directly by the execution hardware. In other embodiments, instructions (e.g., KMOV) are used to move the contents of k1 to general-purpose register 469 for use during execution.

[0115] Figure 4H The diagram illustrates the execution of an instruction used to broadcast the result of an operation on an immediate number. Instruction 470 includes an arithmetic code (e.g., the mnemonic "VPADD3OPR"). * The instruction executes the following: destination vector (SIMD, packed data) registers (zmm1 / ymm1 / xmm1), write mask (k1), mask element control field (z), source vector (SIMD, packed data) registers (zmm2 / ymm2 / xmm2), and immediate value (imm1). The instruction uses the write mask k1 to identify unmasked elements in the destination vector registers (zmm1 / ymm1 / xmm1), generates a sum of each element in the destination vector (SIMD, packed data) registers (zmm1 / ymm1 / xmm1) plus the corresponding element in the source vector registers (zmm2 / ymm2 / xmm2) plus the immediate value imm1, and broadcasts this sum to each unmasked element in the destination vector registers (zmm1 / ymm1 / xmm1).

[0116] The arithmetic code mnemonic is VPADD3OPR. * Including the asterisk " *The asterisk (*) indicates various controls that can be added to control the operation of instructions. For example, here, the asterisk can be replaced by one or more suffixes such as "B" or "W" or "D" or "Q" to specify the size of the vector elements of zmm2 as bytes, words, double words, or quad words.

[0117] This example shows xmm1 471 as the destination, each element of xmm1 471 having an initial value of 0x33; xmm2 472 as the source, each element of xmm2 472 having a value of 0x22; an immediate value imm1 with a value of 0x11; and a write mask k1 with a value of 0x55. In response to the decoded instruction, the operation on the immediate value (VPADD3OPR) is broadcast. * As a result, execution circuitry 476 generates a sum of xmm1[i] plus xmm2[i] plus an immediate value for each element in xmm1, and uses a multiplexer 477 controlled by write mask k1 to broadcast this sum to the unmasked elements in the destination vector xmm1. The masked element control field z 474 controls how the masked elements in the destination vector are processed. The masked element control field z has a value of zero, which specifies that the masked elements in the destination vector register xmm1 478 should be zeroed. In some embodiments, when z=1, the masked elements in the destination vector retain their previous values.

[0118] VBROADCASTIMM instruction

[0119] Exemplary execution

[0120] This article details an embodiment of the VBROADCASTIMM instruction used to improve the computer itself. In particular, execution of the VBROADCASTIMM instruction causes an immediate value to be broadcast to all elements in the destination packing register.

[0121] Figure 5 The diagram illustrates an exemplary execution of the VBROADCASTIMM instruction. The VBROADCASTIMM instruction formats 500 and 502 include fields for the operand code 504 (e.g., the mnemonic "VBROADCASTIMM"), a destination identifier 506 to specify the packing destination register 506, and an immediate value (imm1 508).

[0122] In response to an instruction having an operand code 504 equal to VBROADCASTIMM, execution circuitry 510 uses broadcast circuitry 512 to broadcast imm1 508 to all vector (packed data) elements in packing destination register 514. This example has 0xF as imm1 508. 0xF is broadcast to all vector (packed data) elements in packing destination register 514.

[0123] Exemplary hardware for executing VBROADCASTIMM instructions

[0124] Figure 6 The figure illustrates an embodiment of hardware for processing instructions such as the VBROADCASTIMM instruction. As illustrated, storage device 603 stores the VBROADCASTIMM instruction 601 to be executed.

[0125] Decoding circuit 605 receives the instruction. For example, decoding circuit 605 receives the instruction from extraction logic / circuit. Instruction 601 includes fields for the arithmetic code (e.g., the mnemonic "VBROADCASTIMM"), a destination identifier for specifying the packing destination register, and an immediate value. A more detailed embodiment of at least one instruction format will be described later. Decoding circuit 605 decodes the instruction into one or more operations. In some embodiments, the decoding includes generating multiple micro-operations to be performed by execution circuitry (such as execution circuitry 609 or 510). Decoding circuit 605 also decodes the instruction prefix (if used).

[0126] In some embodiments, register renaming, register dispatching, and / or scheduling circuitry 607 provides functionality for one or more of the following: 1) renaming logical operand values ​​to physical operand values ​​(e.g., in a register alias table in some embodiments), 2) dispatching status bits and flags to decoded instructions, and 3) (e.g., using a reserved station in some embodiments) scheduling decoded instructions from an instruction pool for execution on execution circuitry.

[0127] Registers (register file) and / or memory 608 store data as operands of instructions to be processed by the execution circuitry. Exemplary register types include packed data registers, general-purpose registers, and floating-point registers.

[0128] Execution circuit 609 executes the decoded VBROADCASTIMM instruction. Figure 5 An embodiment of the execution circuit 510 is shown. The write-back (retirement) circuit 611 submits the result of the execution of the decoded VBROADCASTIMM instruction.

[0129] Example format of the VBROADCASTIMM instruction

[0130] In some embodiments, the write-back / write-back circuitry architecturally commits the destination register to a register or memory and writes the instruction back.

[0131] An embodiment of the format used for the VBROADCASTIMM instruction is OPCODE DSTREG, IMM1. In some embodiments, VBROADCASTIMM{B / W / D / Q} is the mnemonic for the instruction's operand code. DSTREG is the field used to pack the destination register operand. IMM1 is the field used to pack the immediate value to the destination register.

[0132] In some embodiments, the OPCODE field is a full operand field (such as 2974) or a real operand field (such as 2930), the DSTREG field is a Reg field (such as 2944), and the IMM1 field is an IMM8 field (such as 2972).

[0133] In some embodiments, the VBROADCASTIMM instruction includes a field (k) for a write mask register operand (e.g., VBROADCASTIMM{k} DSTREG, SRC1, SRC2). A write mask is used to conditionally control the operation on each element and the update of the result. Depending on the implementation, the write mask uses either a merge or zero-based mask. Instructions encoded with assertion (write mask, write mask, or k register) operands use these operands to conditionally control the computation on each element and the update of the result to the destination operand. The assertion operand is called the opmask (write mask) register. In some embodiments, the opmask is a set of 64-bit architecture registers. It should be noted that only k1 through k7 can be addressed as assertion operands from this set of architecture registers. k0 can be used as a regular source or destination, but cannot be encoded as an assertion operand. It should also be noted that assertion operands can be used to enable memory fault tolerance for some instructions with memory operands (sources or destinations). As an assertion operand, the arithmetic mask register contains one bit to manage the operation / update of each data element in the vector register. Generally, the arithmetic mask register can support instructions with the following element sizes: single-precision floating-point (float32), integer double-word (int32), double-precision floating-point (float64), and integer quad-word (int64). The length MAX_KL of the arithmetic mask register is sufficient to handle up to 64 elements, with one bit per element, i.e., 64 bits. For a given vector length, each instruction accesses only the least significant mask bits required based on its data type.

[0134] The arithmetic mask register affects instructions at the granularity of each element. Therefore, the corresponding bits in the arithmetic mask register assert any numerical or non-numerical operations on each data element, as well as updates to each element of the destination operand from intermediate results. In most embodiments, the arithmetic mask acting as the assertion operand obeys the following properties: 1) If the corresponding arithmetic mask bit is not set (which implies that operations on masked elements cannot cause an exception or violation, and therefore, the exception flag will not be updated as a result of the masked operation), then the instruction is not performed on that element; 2) If the corresponding write mask bit is not set, then the destination element is not updated with the result of the operation; instead, the destination element value must be preserved (merge masking) or it must be zeroed (zero masking); and 3) For some instructions with memory operands, memory faults are suppressed for elements with a mask bit of 0. It should be noted that this feature provides a universal construct for implementing control flow assertions, since the mask effectively provides merge behavior for the vector register destination. As an alternative, this masking can be used for zeroing instead of merging, so that the masked elements are updated with 0 instead of retaining the old value. Zeroing behavior is provided to remove implicit dependencies on the old value when it is no longer needed.

[0135] In one embodiment, the instruction encoding includes a Scale-Index-Radius (SIB) type memory addressing operand, which indirectly identifies multiple indexed destination locations in memory. In one embodiment, the SIB type memory operand may include encoding identifying a radius address register. The contents of this radius address register may represent a radius address in memory, used to calculate the address of a specific destination location in memory. For example, the radius address may be the address of a first location in a potential destination location block for extended vector instructions. In one embodiment, the SIB type memory operand may include encoding identifying an index register. Each element of the index register may specify an index or offset value that can be used to calculate the address of the corresponding destination location within the potential destination location block based on the radius address. In one embodiment, the SIB type memory operand may include encoding specifying a scaling factor to be applied to each index value when calculating the corresponding destination address. For example, if a scaling factor of 4 is encoded in the SIB type memory operand, each index value obtained from an element in the index register can be multiplied by 4 and then added to the radius address to calculate the destination address.

[0136] In one embodiment, SIB memory operands of the form vm32{x, y, z} can identify a vector array of memory operands specified using SIB memory addressing. In this example, an array of memory addresses is specified using a common base register, a constant scaling factor, and a vector index register containing individual elements (each of which is a 32-bit index value). The vector index register can be a 128-bit register (e.g., XMM) register (vm32x), a 256-bit register (e.g., YMM) register (vm32y), or a 512-bit register (e.g., ZMM) register (vm32z). In another embodiment, SIB memory operands of the form vm64{x, y, z} can identify a vector array of memory operands specified using SIB memory addressing. In this example, an array of memory addresses is specified using a common base register, a constant scaling factor, and a vector index register containing individual elements (each of which is a 64-bit index value). The vector index register can be a 128-bit register (e.g., XMM) register (vm64x), a 256-bit register (e.g., YMM) register (vm64y), or a 512-bit register (e.g., ZMM) register (vm64z).

[0137] Exemplary execution method of the VBROADCASTIMM instruction

[0138] Figure 7 The diagram illustrates an embodiment of a method implemented by a processor to process the VBROADCASTIMM instruction. For example, Figure 6 The method is implemented using processor components, pipelines, etc., as detailed below.

[0139] At 701, an instruction is fetched. For example, the VBROADCASTIMM instruction is fetched. The VBROADCASTIMM instruction includes fields for the operand, immediate value, and destination operand. In some embodiments, the instruction further includes a field for a write mask. In some embodiments, the instruction is fetched from the instruction cache. The destination operand specifies the packed data vector register. The operand of the VBROADCASTIMM instruction indicates that the immediate value is broadcast.

[0140] At 703, the extracted instruction is decoded. For example, the extracted VBROADCASTIMM instruction is decoded by a decoding circuit such as that detailed herein.

[0141] At 705, the decoded instructions are scheduled (on demand).

[0142] At 707, the scheduled instruction is executed by execution circuitry (hardware), such as execution circuitry 510. For the VBROADCASTIMM instruction, this execution will cause execution circuitry 510 to use broadcast circuitry (such as 512) to broadcast imm1 (such as 508) to all vector (packed data) elements in the pack destination register 514.

[0143] In some embodiments, at 709, the instruction is submitted or withdrawn.

[0144] VBROADCASTVREG instruction

[0145] Exemplary execution

[0146] This article details an embodiment of the VBROADCASTVREG instruction used to improve the computer itself. In particular, execution of the VBROADCASTVREG instruction causes an immediate value stored in the packing source register to be selected and the selected element to be broadcast to all elements in the packing destination register.

[0147] Figure 8 The diagram illustrates an exemplary execution of the VBROADCASTVREG instruction. The VBROADCASTVREG instruction format 800, 802 includes fields for the operand 804 (e.g., the mnemonic "VBROADCASTVREG"), a destination identifier 806 to specify the packing destination register 806, a source vector (SIMD, packing data) register 808, and an immediate value (imm1 810).

[0148] In response to the instruction having an arithmetic code 804 equal to VBROADCASTVREG, the execution circuit 814 uses a multiplexer 816 controlled by imm1 810 to select an element in the packing source register 812 and uses a broadcast circuit 818 to broadcast the selected element to all vector (packed data) elements in the packing destination register 820. This example has 2 as imm1 810 and 0x0F as the third element in the packing source 812; 0x0F is selected from the source packing data register and broadcast to all vector (packed data) elements in the packing destination register 820.

[0149] Figure 8 Some vector elements are illustrated as "x", signifying arbitrary values. They are not relevant to the discussion of the operation of this instruction.

[0150] Exemplary hardware for executing VBROADCASTVREG instructions

[0151] Figure 9The figure illustrates an embodiment of hardware for processing instructions such as arithmetic recursive instructions. As illustrated, storage device 903 stores the VBROADCASTVREG instruction 901 to be executed.

[0152] Decoding circuit 905 receives the instruction. For example, decoding circuit 905 receives the instruction from extraction logic / circuit. Decoding circuit 905 decodes the instruction into one or more operations. In some embodiments, the decoding includes generating multiple micro-operations to be performed by execution circuitry (such as execution circuitry 909 or 814). Decoding circuit 905 also decodes instruction prefixes (if used).

[0153] In some embodiments, register renaming, register dispatching, and / or scheduling circuitry 907 provides functionality for one or more of the following: 1) renaming logical operand values ​​to physical operand values ​​(e.g., in a register alias table in some embodiments), 2) dispatching status bits and flags to decoded instructions, and 3) (e.g., using a reserved station in some embodiments) scheduling decoded instructions from an instruction pool for execution on execution circuitry.

[0154] Registers (register file) and / or memory 908 store data as operands of instructions to be processed by the execution circuitry. Exemplary register types include packed data registers, general-purpose registers, and floating-point registers.

[0155] Execution circuit 909 executes the decoded VBROADCASTVREG instruction. Figure 8 An embodiment of the execution circuit 814 is shown. The write-back (retreat) circuit 911 submits the execution result of the decoded VBROADCASTVREG instruction.

[0156] Example format of the VBROADCASTVREG instruction

[0157] In some embodiments, the write-back / write-back circuitry architecturally commits the destination register to a register or memory and writes the instruction back.

[0158] An embodiment of the format used for the VBROADCASTVREG instruction is OPCODE DSTREG, DSRCREG, IMM1. In some embodiments, VBROADCASTVREG{B / W / D / Q} is the arithmetic code mnemonic for this instruction. SRCREG is a field used to identify the source register operands. DSTREG is a field used to identify the destination register operands. IMM1 is a field used to select the immediate value to be used in the source vector register.

[0159] In some embodiments, the OPCODE field is a full operand field (such as 2974) or a real operand field (such as 2930), the SRCREG field is a Reg field (such as 2944), the DSTREG field is an R / M field (such as 2946), and the IMM1 field is an IMM8 field (such as...). Figure 29A (2972 in the middle).

[0160] In some embodiments, the VBROADCASTVREG instruction includes a field (k) for a write mask register operand (e.g., VBROADCASTVREG{k} DSTREG, SRC1, SRC2). A write mask is used to conditionally control the operation on each element and the update of the result. Depending on the implementation, the write mask uses a merge or zero-based mask. Instructions encoded with assertion (write mask, write mask, or k register) operands use these operands to conditionally control the computation on each element and the update of the result to the destination operand. The assertion operand is known as an operand mask (write mask) register. In some embodiments, the operand mask is a set of 64-bit architecture registers. It should be noted that only k1 through k7 can be addressed as assertion operands from this set of architecture registers. k0 can be used as a regular source or destination, but cannot be encoded as an assertion operand. It should also be noted that assertion operands can be used to enable memory fault suppression for some instructions that have memory operands (sources or destinations). As an assertion operand, the arithmetic mask register contains one bit to manage the operation / update of each data element in the vector register. Generally, the arithmetic mask register can support instructions with the following element sizes: single-precision floating-point (float32), integer double-word (int32), double-precision floating-point (float64), and integer quad-word (int64). The length MAX_KL of the arithmetic mask register is sufficient to handle up to 64 elements, with one bit per element, i.e., 64 bits. For a given vector length, each instruction accesses only the least significant mask bits required based on its data type.

[0161] The arithmetic mask register affects instructions at the granularity of each element. Therefore, the corresponding bits in the arithmetic mask register assert any numerical or non-numerical operations on each data element, as well as updates to each element of the destination operand from intermediate results. In most embodiments, the arithmetic mask acting as the assertion operand obeys the following properties: 1) If the corresponding arithmetic mask bit is not set (which implies that operations on masked elements cannot cause an exception or violation, and therefore, the exception flag will not be updated as a result of the masked operation), then the instruction is not performed on that element; 2) If the corresponding write mask bit is not set, then the destination element is not updated with the result of the operation; instead, the destination element value must be preserved (merge masking) or it must be zeroed (zero masking); and 3) For some instructions with memory operands, memory faults are suppressed for elements with a mask bit of 0. It should be noted that this feature provides a universal construct for implementing control flow assertions, since the mask effectively provides merge behavior for the vector register destination. As an alternative, this masking can be used for zeroing instead of merging, so that the masked elements are updated with 0 instead of retaining the old value. Zeroing behavior is provided to remove implicit dependencies on the old value when it is no longer needed.

[0162] In one embodiment, the instruction encoding includes a Scale-Index-Radius (SIB) type memory addressing operand, which indirectly identifies multiple indexed destination locations in memory. In one embodiment, the SIB type memory operand may include encoding identifying a radius address register. The contents of this radius address register may represent a radius address in memory, used to calculate the address of a specific destination location in memory. For example, the radius address may be the address of a first location in a potential destination location block for extended vector instructions. In one embodiment, the SIB type memory operand may include encoding identifying an index register. Each element of the index register may specify an index or offset value that can be used to calculate the address of the corresponding destination location within the potential destination location block based on the radius address. In one embodiment, the SIB type memory operand may include encoding specifying a scaling factor to be applied to each index value when calculating the corresponding destination address. For example, if a scaling factor of 4 is encoded in the SIB type memory operand, each index value obtained from an element in the index register can be multiplied by 4 and then added to the radius address to calculate the destination address.

[0163] In one embodiment, SIB memory operands of the form vm32{x, y, z} can identify a vector array of memory operands specified using SIB memory addressing. In this example, an array of memory addresses is specified using a common base register, a constant scaling factor, and a vector index register containing individual elements (each of which is a 32-bit index value). The vector index register can be a 128-bit register (e.g., XMM) register (vm32x), a 256-bit register (e.g., YMM) register (vm32y), or a 512-bit register (e.g., ZMM) register (vm32z). In another embodiment, SIB memory operands of the form vm64{x, y, z} can identify a vector array of memory operands specified using SIB memory addressing. In this example, an array of memory addresses is specified using a common base register, a constant scaling factor, and a vector index register containing individual elements (each of which is a 64-bit index value). The vector index register can be a 128-bit register (e.g., XMM) register (vm64x), a 256-bit register (e.g., YMM) register (vm64y), or a 512-bit register (e.g., ZMM) register (vm64z).

[0164] Exemplary execution method of the VBROADCASTVREG instruction

[0165] Figure 10 The diagram illustrates an embodiment of a method implemented by a processor to process the VBROADCASTVREG instruction. For example, Figure 9 The method is implemented using processor components, pipelines, etc., as detailed below.

[0166] At position 1001, fetch the instruction. For example, fetch the VBROADCASTVREG instruction. The VBROADCASTVREG instruction includes fields for the operand, destination operand, source operand, and immediate value. In some embodiments, the instruction further includes a field for the write mask. In some embodiments, the instruction is fetched from the instruction cache. The destination operand specifies the packed data vector register. The operand of the VBROADCASTVREG instruction indicates that the vector register element is broadcast.

[0167] At position 1003, the extracted instruction is decoded. For example, the extracted VBROADCASTVREG instruction is decoded by a decoding circuit such as that detailed herein.

[0168] At position 1005, the decoded instructions are scheduled (on demand).

[0169] At 1007, the scheduled instruction is executed by execution circuitry (hardware) such as 810. For the VBROADCASTVREG instruction, this execution will cause the execution circuitry (such as 814) to use a multiplexer (such as 816) controlled by imm1 (such as imm1 810) to select an element in the packing source register (such as 812), and use broadcast circuitry (such as 818) to broadcast the selected element to all vector (packed data) elements in the packing destination register (such as 820).

[0170] In some embodiments, at 1009, the instruction is submitted or withdrawn.

[0171] VBROADCASTSTRIMM instruction

[0172] Exemplary execution

[0173] This article details an embodiment of the VBROADCASTSTRIMM instruction used to improve the computer itself. Specifically, execution of the VBROADCASTSTRIMM instruction sets the first element in the pack destination register to the value stored in the register, and adds a stride value specified by an immediate value to the second and subsequent elements of the pack destination vector.

[0174] Figure 11 The figure illustrates an exemplary execution of the VBROADCASTSTRIMM instruction. The VBROADCASTSTRIMM instruction 1102 format includes fields for the operand 1104 (e.g., the mnemonic "VBROADCASTSTRIMM"), a destination identifier 1106 for specifying the packing destination register, a source register identifier 1108, and an immediate value (imm1 1110).

[0175] In response to the instruction having an arithmetic code 1104 equal to VBROADCASTSTRIMM, execution circuitry 1114 uses the contents of source register 1112, identified by source register identifier 1108, as first data 1116 to write to the first element 1118 of the vector, and uses an immediate value (imm1) 1110 as a step 1120 to be successively added to the second and subsequent elements of the vector. In this example, 0x33 is stored in source register 1112; and execution circuitry 1114 writes 0x33 as first data 1116 to the first element 1118 of the vector. Execution circuitry 1114 further adds a step 1120 of 2, specified by imm1 1110, to the second and subsequent elements of the vector. Execution circuitry 1114 further uses broadcast circuitry 1122 to broadcast the result of the operation to the packing destination register 1124.

[0176] Exemplary hardware for executing VBROADCASTSTRIMM instructions

[0177] Figure 12 The figure illustrates an embodiment of hardware for processing instructions such as arithmetic recursive instructions. As illustrated, storage device 1203 stores the VBROADCASTSTRIMM instruction 1201 to be executed.

[0178] Decoding circuit 1205 receives the instruction. For example, decoding circuit 1205 receives the instruction from extraction logic / circuit. As described above, the instruction includes fields for an arithmetic code (e.g., the mnemonic "VBROADCASTSTRIMM"), a destination identifier for specifying the destination register, a source operand for specifying the source register, and an immediate value. In some embodiments, the source[s] and destination are registers, while in other embodiments, one or more of them are memory locations. More detailed embodiments of at least one instruction format will be described later. Decoding circuit 1205 decodes the instruction into one or more operations. In some embodiments, the decoding includes generating multiple micro-operations to be performed by execution circuitry (such as execution circuitry 1209). Decoding circuit 1205 also decodes instruction prefixes (if used).

[0179] In some embodiments, register renaming, register dispatching, and / or scheduling circuitry 1207 provides functionality for one or more of the following: 1) renaming logical operand values ​​to physical operand values ​​(e.g., in a register alias table in some embodiments), 2) dispatching status bits and flags to decoded instructions, and 3) (e.g., using a reserved station in some embodiments) scheduling decoded instructions from an instruction pool for execution on execution circuitry.

[0180] Registers (register file) and / or memory 1208 store data as operands of instructions to be processed by the execution circuitry. Exemplary register types include packed data registers, general-purpose registers, and floating-point registers.

[0181] Execution circuit 1209 executes the decoded VBROADCASTSTRIMM instruction. Figure 11 An embodiment of execution circuit 1114 is shown, which is similar to 1209. Write-back (retirement) circuit 1211 submits the execution result of the decoded VBROADCASTSTRIMM instruction.

[0182] Example format of the VBROADCASTSTRIMM instruction

[0183] In some embodiments, the write-back / write-back circuitry architecturally commits the destination register to a register or memory and writes the instruction back.

[0184] An embodiment of the format used for the VBROADCASTSTRIMM instruction is OPCODE DSTREG, SRCREG, IMM1. In some embodiments, VBROADCASTSTRIMM{B / W / D / Q} is the mnemonic for the instruction's operand code. SRCREG is the field used to identify the source register. In some embodiments, the source register is an element in a packed data vector register. DSTREG is the field used to identify the operand in the packed destination register. IMM1 is the field used for the immediate value to be used as a step value.

[0185] In some embodiments, the OPCODE field is a full operand field (such as 2974) or a real operand field (such as 2930), the SRCREG field is a Reg field (such as 2944), the DSTREG field is an R / M field (such as 2946), and the IMM1 field is an IMM8 field (such as...). Figure 29A (2972 in the middle).

[0186] In some embodiments, the VBROADCASTSTRIMM instruction includes a field (k) for a write mask register operand (e.g., VBROADCASTSTRIMM{k} DSTREG, SRC1, SRC2). A write mask is used to conditionally control the operation on each element and the update of the result. Depending on the implementation, the write mask uses either a merge or zero-based mask. Instructions encoded with assertion (write mask, write mask, or k register) operands use these operands to conditionally control the computation on each element and the update of the result to the destination operand. Assertion operands are known as operand mask (write mask) registers. In some embodiments, the operand mask is a set of 64-bit architecture registers. It should be noted that only k1 through k7 can be addressed as assertion operands from this set of architecture registers. k0 can be used as a regular source or destination, but cannot be encoded as an assertion operand. It should also be noted that assertion operands can be used to enable memory fault tolerance for some instructions with memory operands (sources or destinations). As an assertion operand, the arithmetic mask register contains one bit to manage the operation / update of each data element in the vector register. Generally, the arithmetic mask register can support instructions with the following element sizes: single-precision floating-point (float32), integer double-word (int32), double-precision floating-point (float64), and integer quad-word (int64). The length MAX_KL of the arithmetic mask register is sufficient to handle up to 64 elements, with one bit per element, i.e., 64 bits. For a given vector length, each instruction accesses only the least significant mask bits required based on its data type.

[0187] The arithmetic mask register affects instructions at the granularity of each element. Therefore, the corresponding bits in the arithmetic mask register assert any numerical or non-numerical operations on each data element, as well as updates to each element of the destination operand from intermediate results. In most embodiments, the arithmetic mask acting as the assertion operand obeys the following properties: 1) If the corresponding arithmetic mask bit is not set (which implies that operations on masked elements cannot cause an exception or violation, and therefore, the exception flag will not be updated as a result of the masked operation), then the instruction is not performed on that element; 2) If the corresponding write mask bit is not set, then the destination element is not updated with the result of the operation; instead, the destination element value must be preserved (merge masking) or it must be zeroed (zero masking); and 3) For some instructions with memory operands, memory faults are suppressed for elements with a mask bit of 0. It should be noted that this feature provides a universal construct for implementing control flow assertions, since the mask effectively provides merge behavior for the vector register destination. As an alternative, this masking can be used for zeroing instead of merging, so that the masked elements are updated with 0 instead of retaining the old value. Zeroing behavior is provided to remove implicit dependencies on the old value when it is no longer needed.

[0188] In one embodiment, the instruction encoding includes a Scale-Index-Radius (SIB) type memory addressing operand, which indirectly identifies multiple indexed destination locations in memory. In one embodiment, the SIB type memory operand may include encoding identifying a radius address register. The contents of this radius address register may represent a radius address in memory, used to calculate the address of a specific destination location in memory. For example, the radius address may be the address of a first location in a potential destination location block for extended vector instructions. In one embodiment, the SIB type memory operand may include encoding identifying an index register. Each element of the index register may specify an index or offset value that can be used to calculate the address of the corresponding destination location within the potential destination location block based on the radius address. In one embodiment, the SIB type memory operand may include encoding specifying a scaling factor to be applied to each index value when calculating the corresponding destination address. For example, if a scaling factor of 4 is encoded in the SIB type memory operand, each index value obtained from an element in the index register can be multiplied by 4 and then added to the radius address to calculate the destination address.

[0189] In one embodiment, SIB memory operands of the form vm32{x, y, z} can identify a vector array of memory operands specified using SIB memory addressing. In this example, an array of memory addresses is specified using a common base register, a constant scaling factor, and a vector index register containing individual elements (each of which is a 32-bit index value). The vector index register can be a 128-bit register (e.g., XMM) register (vm32x), a 256-bit register (e.g., YMM) register (vm32y), or a 512-bit register (e.g., ZMM) register (vm32z). In another embodiment, SIB memory operands of the form vm64{x, y, z} can identify a vector array of memory operands specified using SIB memory addressing. In this example, an array of memory addresses is specified using a common base register, a constant scaling factor, and a vector index register containing individual elements (each of which is a 64-bit index value). The vector index register can be a 128-bit register (e.g., XMM) register (vm64x), a 256-bit register (e.g., YMM) register (vm64y), or a 512-bit register (e.g., ZMM) register (vm64z).

[0190] Exemplary execution method of the VBROADCASTSTRIMM instruction

[0191] Figure 13 The diagram illustrates an embodiment of a method implemented by a processor to process the VBROADCASTSTRIMM instruction. For example, Figure 12 The method is implemented using processor components, pipelines, etc., as detailed below.

[0192] At 1301, an instruction is fetched. For example, the VBROADCASTSTRIMM instruction is fetched. The VBROADCASTSTRIMM instruction includes fields for the operand, destination operand, source operand, and immediate value. In some embodiments, the instruction further includes a field for a write mask. In some embodiments, the instruction is fetched from the instruction cache. The destination operand specifies the packed data vector register. The operand of the VBROADCASTSTRIMM instruction indicates that an immediate value is used as the stride value to broadcast the stride to the vector register.

[0193] At 1303, the extracted instruction is decoded. For example, the extracted VBROADCASTSTRIMM instruction is decoded by a decoding circuit such as that detailed herein.

[0194] At 1305, the decoded instructions are scheduled (on demand).

[0195] At 1307, the scheduled instruction is executed by execution circuitry (hardware) such as 1114. For the VBROADCASTSTRIMM instruction, this execution will cause the execution circuitry (such as 1114) to write the contents of source register 1112 as the first data 1116 to the first element 1118 of the vector, and to use an immediate value (imm11110) as a step 1120 to be successively added to the second and subsequent elements of the vector.

[0196] In some embodiments, at 1309, the instruction is submitted or withdrawn.

[0197] VBROADCASTSTRVREG instruction

[0198] Exemplary execution

[0199] This document details an embodiment of the VBROADCASTSTRVREG instruction used to improve the computer itself. Specifically, execution of the VBROADCASTSTRVREG instruction causes the execution circuitry, in response to receiving the instruction, to use a first immediate value to select an element in the packing source register, set the first element in the packing destination register to the selected value, and successively add a step value specified by a second immediate value to the second and subsequent elements of the packing destination register.

[0200] Figure 14 The diagram illustrates an exemplary execution of the VBROADCASTSTRVREG instruction. The VBROADCASTSTRVREG instruction 1402 format includes fields for the operand 1404 (e.g., the mnemonic "VBROADCASTSTRVREG"), a destination identifier 1406 for specifying the packing destination register 1424, a source identifier 1408 for specifying the packing source register 1414, a first immediate value (imm1 1410), and a second immediate value (imm2 1412).

[0201] In response to the instruction having an arithmetic code 1404 equal to VBROADCASTSTRVREG, execution circuitry 1416 uses imm11410 to control multiplexer 1418 to select an element from packing source register 1414. Execution circuitry 1416 sets the first element of the vector to the value stored in the selected element. Execution circuitry 1416 further adds a step 1420 of 2, specified by imm2 1412, to the second and subsequent elements of the vector. Execution circuitry 1416 further uses broadcast circuitry 1422 to broadcast the result of the operation to packing destination register 1424.

[0202] Figure 14Some vector elements in the code are illustrated as "x", signifying arbitrary values. They are not relevant to the discussion of the operation of this instruction.

[0203] Exemplary hardware for executing VBROADCASTSTRVREG instructions

[0204] Figure 15 The figure illustrates an embodiment of hardware for processing instructions such as arithmetic recursive instructions. As illustrated, storage device 1503 stores the VBROADCASTSTRVREG instruction 1501 to be executed.

[0205] Decoding circuit 1505 receives the instruction. For example, decoding circuit 1505 receives the instruction from extraction logic / circuit. Instruction 1501 includes fields for arithmetic codes (e.g., the mnemonic "VBROADCASTSTRVREG"), a destination identifier 1106 to specify the packing destination register, and an immediate value. More detailed embodiments of at least one instruction format will be described later. Decoding circuit 1505 decodes the instruction into one or more operations. In some embodiments, the decoding includes generating multiple micro-operations to be performed by execution circuitry (such as execution circuitry 1416 or execution circuitry 1509). Decoding circuit 1505 also decodes instruction prefixes (if used).

[0206] In some embodiments, register renaming, register dispatching, and / or scheduling circuitry 1507 provides functionality for one or more of the following: 1) renaming logical operand values ​​to physical operand values ​​(e.g., in a register alias table in some embodiments), 2) dispatching status bits and flags to decoded instructions, and 3) (e.g., using a reserved station in some embodiments) scheduling decoded instructions from an instruction pool for execution on execution circuitry.

[0207] Registers (register file) and / or memory 1508 store data as operands of instructions to be processed by the execution circuitry. Exemplary register types include packed data registers, general-purpose registers, and floating-point registers.

[0208] Execution circuit 1509 executes the decoded VBROADCASTSTRVREG instruction. Figure 14 The diagram shows execution circuit 1416, which in some embodiments is similar to execution circuit 1509. Write-back (retirement) circuit 1511 submits the execution result of the decoded VBROADCASTSTRVREG instruction.

[0209] Example format of the VBROADCASTSTRVREG instruction

[0210] In some embodiments, the write-back / write-back circuitry architecturally commits the destination register to a register or memory and writes the instruction back.

[0211] An embodiment of the format used for the VBROADCASTSTRVREG instruction is OPCODE DSTREG, SRCREG, IMM1, IMM2. In some embodiments, VBROADCASTSTRVREG{B / W / D / Q} is the mnemonic for the instruction's operand code. SRCREG is a field used to identify the source register. In some embodiments, the source register is a general-purpose register. In some embodiments, the source register is an element of a packed data vector register. DSTREG is a field used to identify the operand of the packed destination register. IMM1 is a field used to select an immediate value from among multiple elements in the packed source register 1414.

[0212] In some embodiments, the OPCODE field is a full operand field (such as 2974) or a real operand field (such as 2930), the SRCREG field is a Reg field (such as 2944), the DSTREG field is an R / M field (such as 2946), and the IMM1 field is an IMM8 field (such as...). Figure 29A (2972 in the middle).

[0213] In some embodiments, the VBROADCASTSTRVREG instruction includes a field (k) for a write mask register operand (e.g., VBROADCASTSTRVREG{k} DSTREG, SRC1, SRC2). A write mask is used to conditionally control the operation on each element and the update of the result. Depending on the implementation, the write mask uses a merge or zero-mapping mask. Instructions encoded with assertion (write mask, write mask, or k register) operands use these operands to conditionally control the computation on each element and the update of the result to the destination operand. The assertion operand is known as an operand mask (write mask) register. In some embodiments, the operand mask is a set of 64-bit architecture registers. It should be noted that only k1 through k7 can be addressed as assertion operands from this set of architecture registers. k0 can be used as a regular source or destination, but cannot be encoded as an assertion operand. It should also be noted that assertion operands can be used to enable memory fault tolerance for some instructions with memory operands (sources or destinations). As an assertion operand, the arithmetic mask register contains one bit to manage the operation / update of each data element in the vector register. Generally, the arithmetic mask register can support instructions with the following element sizes: single-precision floating-point (float32), integer double-word (int32), double-precision floating-point (float64), and integer quad-word (int64). The length MAX_KL of the arithmetic mask register is sufficient to handle up to 64 elements, with one bit per element, i.e., 64 bits. For a given vector length, each instruction accesses only the least significant mask bits required based on its data type.

[0214] The arithmetic mask register affects instructions at the granularity of each element. Therefore, the corresponding bits in the arithmetic mask register assert any numerical or non-numerical operations on each data element, as well as updates to each element of the destination operand from intermediate results. In most embodiments, the arithmetic mask acting as the assertion operand obeys the following properties: 1) If the corresponding arithmetic mask bit is not set (which implies that operations on masked elements cannot cause an exception or violation, and therefore, the exception flag will not be updated as a result of the masked operation), then the instruction is not performed on that element; 2) If the corresponding write mask bit is not set, then the destination element is not updated with the result of the operation; instead, the destination element value must be preserved (merge masking) or it must be zeroed (zero masking); and 3) For some instructions with memory operands, memory faults are suppressed for elements with a mask bit of 0. It should be noted that this feature provides a universal construct for implementing control flow assertions, since the mask effectively provides merge behavior for the vector register destination. As an alternative, this masking can be used for zeroing instead of merging, so that the masked elements are updated with 0 instead of retaining the old value. Zeroing behavior is provided to remove implicit dependencies on the old value when it is no longer needed.

[0215] In one embodiment, the instruction encoding includes a Scale-Index-Radius (SIB) type memory addressing operand, which indirectly identifies multiple indexed destination locations in memory. In one embodiment, the SIB type memory operand may include encoding identifying a radius address register. The contents of this radius address register may represent a radius address in memory, used to calculate the address of a specific destination location in memory. For example, the radius address may be the address of a first location in a potential destination location block for extended vector instructions. In one embodiment, the SIB type memory operand may include encoding identifying an index register. Each element of the index register may specify an index or offset value that can be used to calculate the address of the corresponding destination location within the potential destination location block based on the radius address. In one embodiment, the SIB type memory operand may include encoding specifying a scaling factor to be applied to each index value when calculating the corresponding destination address. For example, if a scaling factor of 4 is encoded in the SIB type memory operand, each index value obtained from an element in the index register can be multiplied by 4 and then added to the radius address to calculate the destination address.

[0216] In one embodiment, SIB memory operands of the form vm32{x, y, z} can identify a vector array of memory operands specified using SIB memory addressing. In this example, an array of memory addresses is specified using a common base register, a constant scaling factor, and a vector index register containing individual elements (each of which is a 32-bit index value). The vector index register can be a 128-bit register (e.g., XMM) register (vm32x), a 256-bit register (e.g., YMM) register (vm32y), or a 512-bit register (e.g., ZMM) register (vm32z). In another embodiment, SIB memory operands of the form vm64{x, y, z} can identify a vector array of memory operands specified using SIB memory addressing. In this example, an array of memory addresses is specified using a common base register, a constant scaling factor, and a vector index register containing individual elements (each of which is a 64-bit index value). The vector index register can be a 128-bit register (e.g., XMM) register (vm64x), a 256-bit register (e.g., YMM) register (vm64y), or a 512-bit register (e.g., ZMM) register (vm64z).

[0217] Exemplary execution method of the VBROADCASTSTRVREG instruction

[0218] Figure 16 The diagram illustrates an embodiment of a method implemented by a processor to process the VBROADCASTSTRVREG instruction. For example, Figure 15 The method is implemented using processor components, pipelines, etc., as detailed below.

[0219] At 1601, an instruction is fetched. For example, the VBROADCASTSTRVREG instruction is fetched. The VBROADCASTSTRVREG instruction includes fields for the opcode, destination operand, source operand, immediate value, and second immediate value. In some embodiments, the instruction further includes a field for a write mask. In some embodiments, the instruction is fetched from the instruction cache. The destination operand specifies the packed data vector register. The opcode of the VBROADCASTSTRVREG instruction indicates that an immediate value is used as the stride value to broadcast the stride to the vector register.

[0220] At 1603, the extracted instruction is decoded. For example, the extracted VBROADCASTSTRVREG instruction is decoded by a decoding circuit such as that detailed herein.

[0221] At 1605, the decoded instructions are scheduled (on demand).

[0222] At 1607, the scheduled instruction is executed by execution circuitry (hardware), such as execution circuitry 1416. For the VBROADCASTSTRVREG instruction, this execution causes the execution circuitry to write the contents of a packing source register (such as 1414) as the first data to the first element of the vector, and to use a second immediate value (imm2) as a step 1420 to be successively added to the second and subsequent elements of the vector.

[0223] In some embodiments, at 1609, the instruction is submitted or withdrawn.

[0224] VBROADCASTSTRIMMMSKED instruction

[0225] Exemplary execution

[0226] This document details an embodiment of the VBROADCASTSTRIMMMSKED instruction used to improve the computer itself. Specifically, execution of the VBROADCASTSTRIMMMSKED instruction causes the execution circuitry to use a first immediate value to set the first unmasked element in the packing destination register, and to successively add the step value specified by the second immediate value to the second and subsequent elements in the packing destination register.

[0227] Figure 17 The diagram illustrates an exemplary execution of the VBROADCASTSTRIMMMSKED instruction. The VBROADCASTSTRIMMMSKED instruction includes fields containing OPCODE {k1} {Z}, DST, IMM1, and IMM2. k1 is a write mask used to specify whether elements in the packing destination register are masked or unmasked. The masking element control field z specifies whether to zero out masked data elements or allow them to retain their previous values. In some embodiments, VBROADCASTSTRIMMMSKED{B / W / D / Q} is the instruction's operand mnemonic, where DST is the field used to identify the operand in the packing destination register, and k1 identifies the k1 mask register 1720. The instruction further includes the masking element control field z 1710, a first immediate value (imm1) 1712, and a second immediate value (imm2) 1714. IMM1 is the field used as the first unmasked data element in the immediate value vector. IMM2 is a field used to define the immediate value of the stride, which is added successively to the second and subsequent elements of the intermediate vector.

[0228] In response to the instruction having an operand code 1704 equal to VBROADCASTSTRIMMMSKED, execution circuitry 1716 uses the k1 write mask identifier 1708 to identify the k1 mask register 1720, uses the k1 mask register 1720 to identify the unmasked elements in the packing destination register 1726 and the unmasked elements of the intermediate vector formed by execution circuitry 1716, uses the masked element control field z 1710 to set the z register 1722, sets the first unmasked element 1718 of the intermediate vector to the value imm1 1712, and adds the value imm2 1714 as a step value to the second and subsequent unmasked data elements of the intermediate vector. Execution circuitry 1716 uses broadcast circuitry 1724 to write the intermediate vector to the packing destination register 1726.

[0229] This example has 33 as imm1 1712, which is written to the first unmasked element 1718 of the intermediate vector. Execution circuitry 1716 further adds the step value 2, specified by imm2 1714, to the second and subsequent elements. Execution circuitry 1716 further uses broadcast circuitry 1724 to broadcast the intermediate vector to the packing destination register 1726.

[0230] Exemplary hardware for executing the VBROADCASTSTRIMMMSKED instruction

[0231] Figure 18 The figure illustrates an embodiment of hardware for processing instructions such as arithmetic recursive instructions. As illustrated, storage device 1803 stores the VBROADCASTSTRIMMMSKED instruction 1801 to be executed.

[0232] Decoding circuit 1805 receives the instruction. For example, decoding circuit 1805 receives the instruction from extraction logic / circuit. Instruction 1801 includes fields for arithmetic codes (e.g., the mnemonic "VBROADCASTSTRIMMMSKED"), a destination identifier 1106 for specifying the packing destination register, a write mask, a mask element control field, a first immediate value, and a second immediate value. In some embodiments, the source[s] and destination are registers, while in other embodiments, one or more of them are memory locations. More detailed embodiments of at least one instruction format will be described later. Decoding circuit 1805 decodes the instruction into one or more operations. In some embodiments, the decoding includes generating multiple micro-operations to be performed by execution circuitry (such as execution circuitry 1809 or 1716). Decoding circuit 1805 also decodes instruction prefixes (if used).

[0233] In some embodiments, register renaming, register dispatching, and / or scheduling circuitry 1807 provides functionality for one or more of the following: 1) renaming logical operand values ​​to physical operand values ​​(e.g., in a register alias table in some embodiments), 2) dispatching status bits and flags to decoded instructions, and 3) (e.g., using a reserved station in some embodiments) scheduling decoded instructions from an instruction pool for execution on execution circuitry.

[0234] Registers (register files) and / or memory 1808 store data as operands of instructions to be processed by the execution circuitry. Exemplary register types include packed data registers, general-purpose registers, and floating-point registers.

[0235] Execution circuit 1809 executes the decoded VBROADCASTSTRIMMMSKED instruction. Figure 17 The execution circuit 1716 is shown. The execution of the decoded VBROADCASTSTRIMMMSKED instruction uses a first immediate value (imm1) to set the first unmasked element in the packing destination register, and then successively adds a step value specified by a second immediate value (imm2) to the second and subsequent unmasked elements in the packing destination register. In this embodiment, the masking element control field z, when equal to zero (as here), causes the execution of the instruction to zero out the masked destination vector element, and when equal to 1, causes the execution of the instruction to allow the masked destination vector element to retain its previous value. The write-back (retreat) circuit 1811 submits the execution result of the decoded VBROADCASTSTRIMMMSKED instruction.

[0236] Exemplary format of the VBROADCASTSTRIMMMSKED instruction

[0237] In some embodiments, the write-back / write-back circuitry architecturally commits the destination register to a register or memory and writes the instruction back.

[0238] An embodiment of the format for the VBROADCASTSTRIMMMSKED instruction is OPCODE {k1} {Z}, DST, IMM1, IMM2. k1 is a write mask used to specify whether elements in the destination register are masked or unmasked. The masking element control field z specifies whether masked data elements should be zeroed out or allowed to retain their previous values. In some embodiments, VBROADCASTSTRIMMMSKED{B / W / D / Q} is the operand mnemonic for this instruction, where DST is the field used to identify the operands in the destination write mask register, and k1 is the k1 write mask identifier 1708. The instruction further includes the masking element control field z 1710, a first immediate value (imm1 1712), and a second immediate value (imm2) 1714. IMM1 is the field used as the first unmasked element 1718 in the immediate value vector. IMM2 is a field used to define an immediate value (here, 2) that is successively added to the second and subsequent elements of the intermediate vector. In some embodiments, execution circuitry 1716 uses broadcast circuitry 1724 to broadcast the intermediate vector to packing destination register 1726.

[0239] In some embodiments, the OPCODE field is a full operand field (such as 2974) or a real operand field (such as 2930), the DSTREG field is an R / M field (such as 2946), and the IMM1 field is an IMM8 field (such as...). Figure 29A (2972 in the text), and the IMM2 field is a vvvv field (such as...). Figure 29A (2920 in the middle).

[0240] In some embodiments, the VBROADCASTSTRIMMMSKED instruction includes a field (k) for a write mask register operand (e.g., VBROADCASTSTRIMMMSKED{k} DSTREG, SRC1, SRC2). A write mask is used to conditionally control the operation on each element and the update of the result. Depending on the implementation, the write mask uses either a merge or zero-based mask. Instructions encoded with assertion (write mask, write mask, or k register) operands use these operands to conditionally control the computation on each element and the update of the result to the destination operand. The assertion operand is known as an operand mask (write mask) register. In some embodiments, the operand mask is a set of 64-bit architecture registers. It should be noted that only k1 through k7 can be addressed as assertion operands from this set of architecture registers. k0 can be used as a regular source or destination, but cannot be encoded as an assertion operand. It should also be noted that assertion operands can be used to enable memory fault tolerance for some instructions with memory operands (sources or destinations). As an assertion operand, the arithmetic mask register contains one bit to manage the operation / update of each data element in the vector register. Generally, the arithmetic mask register can support instructions with the following element sizes: single-precision floating-point (float32), integer double-word (int32), double-precision floating-point (float64), and integer quad-word (int64). The length MAX_KL of the arithmetic mask register is sufficient to handle up to 64 elements, with one bit per element, i.e., 64 bits. For a given vector length, each instruction accesses only the least significant mask bits required based on its data type.

[0241] The arithmetic mask register affects instructions at the granularity of each element. Therefore, the corresponding bits in the arithmetic mask register assert any numerical or non-numerical operations on each data element, as well as updates to each element of the destination operand from intermediate results. In most embodiments, the arithmetic mask acting as the assertion operand obeys the following properties: 1) If the corresponding arithmetic mask bit is not set (which implies that operations on masked elements cannot cause an exception or violation, and therefore, the exception flag will not be updated as a result of the masked operation), then the instruction is not performed on that element; 2) If the corresponding write mask bit is not set, then the destination element is not updated with the result of the operation; instead, the destination element value must be preserved (merge masking) or it must be zeroed (zero masking); and 3) For some instructions with memory operands, memory faults are suppressed for elements with a mask bit of 0. It should be noted that this feature provides a universal construct for implementing control flow assertions, since the mask effectively provides merge behavior for the vector register destination. As an alternative, this masking can be used for zeroing instead of merging, so that the masked elements are updated with 0 instead of retaining the old value. Zeroing behavior is provided to remove implicit dependencies on the old value when it is no longer needed.

[0242] In one embodiment, the instruction encoding includes a Scale-Index-Radius (SIB) type memory addressing operand, which indirectly identifies multiple indexed destination locations in memory. In one embodiment, the SIB type memory operand may include encoding identifying a radius address register. The contents of this radius address register may represent a radius address in memory, used to calculate the address of a specific destination location in memory. For example, the radius address may be the address of a first location in a potential destination location block for extended vector instructions. In one embodiment, the SIB type memory operand may include encoding identifying an index register. Each element of the index register may specify an index or offset value that can be used to calculate the address of the corresponding destination location within the potential destination location block based on the radius address. In one embodiment, the SIB type memory operand may include encoding specifying a scaling factor to be applied to each index value when calculating the corresponding destination address. For example, if a scaling factor of 4 is encoded in the SIB type memory operand, each index value obtained from an element in the index register can be multiplied by 4 and then added to the radius address to calculate the destination address.

[0243] In one embodiment, SIB memory operands of the form vm32{x, y, z} can identify a vector array of memory operands specified using SIB memory addressing. In this example, an array of memory addresses is specified using a common base register, a constant scaling factor, and a vector index register containing individual elements (each of which is a 32-bit index value). The vector index register can be a 128-bit register (e.g., XMM) register (vm32x), a 256-bit register (e.g., YMM) register (vm32y), or a 512-bit register (e.g., ZMM) register (vm32z). In another embodiment, SIB memory operands of the form vm64{x, y, z} can identify a vector array of memory operands specified using SIB memory addressing. In this example, an array of memory addresses is specified using a common base register, a constant scaling factor, and a vector index register containing individual elements (each of which is a 64-bit index value). The vector index register can be a 128-bit register (e.g., XMM) register (vm64x), a 256-bit register (e.g., YMM) register (vm64y), or a 512-bit register (e.g., ZMM) register (vm64z).

[0244] Exemplary execution method of the VBROADCASTSTRIMMMSKED instruction

[0245] Figure 19 The diagram illustrates an embodiment of a method implemented by a processor to process the VBROADCASTSTRIMMMSKED instruction. For example, Figure 18 The method is implemented using processor components, pipelines, etc., as detailed below.

[0246] At 1901, an instruction is fetched. For example, the VBROADCASTSTRIMMMSKED instruction is fetched. The VBROADCASTSTRIMMMSKED instruction includes a field for the operand, a DST field to identify the packed destination register operand, a source write mask operand to identify the unmasked elements in the packed destination register, a mask element control field to specify whether to zero out the masked elements or allow them to retain their previous values, a first immediate value, and a second immediate value. In some embodiments, the instruction is fetched from the instruction cache. The destination operand specifies the packed data vector register. The operand of the VBROADCASTSTRIMMMSKED instruction indicates that vector register elements are broadcast under the write mask using the immediate value as the step value.

[0247] In some embodiments, the instruction is retrieved from the instruction cache.

[0248] At 1903, the extracted instruction is decoded. For example, the extracted VBROADCASTSTRIMMMSKED instruction is decoded by a decoding circuit such as that detailed herein.

[0249] At 1905, the instructions scheduled are dispatched (on demand).

[0250] At 1907, the decoded instruction is executed by an execution circuit (hardware) such as 1716. For the VBROADCASTSTRIMMMSKED instruction, execution uses the k1 write mask identifier 1708 to identify the k1 mask register 1720, and the k1 mask register 1720 to identify the unmasked elements in the packing destination register 1726 and the unmasked elements of the intermediate vector formed by the execution circuit 1716. The execution circuit 1716 sets the first unmasked element of the intermediate vector to the value imm1 1712, and adds the value imm2 1712 (which is 2) as a step value to the second and subsequent data elements of the intermediate vector. The execution circuit 1716 uses the broadcast circuit 1724 to write the intermediate vector into the packing destination register 1726.

[0251] In some embodiments, at 1909, the instruction is submitted or withdrawn.

[0252] KBROADCASTIMM2MSK instruction

[0253] Exemplary execution

[0254] This article details an implementation of the KBROADCASTIMM2MSK instruction used to improve the computer itself. Specifically, execution of the KBROADCASTIMM2MSK instruction causes the execution circuitry to logically partition the destination mask register into equal-sized partitions with the same size as the immediate value, use a write mask register to identify the unmasked logical partitions of the destination write mask register, and broadcast the immediate value to the unmasked logical partitions.

[0255] Figure 20 The diagram illustrates an exemplary execution of the KBROADCASTIMM2MSK instruction. The KBROADCASTIMM2MSK instruction 2002 format includes fields for the operand 2004 (e.g., the mnemonic "KBROADCASTIMM2MSK"), the destination write mask register (k1) 2006, the source write mask register (k2) 2010, and the immediate value (imm1 2008).

[0256] In response to the instruction having an arithmetic code 2004 equal to KBROADCASTIMM2MSK, execution circuitry 2016 logically partitions the destination mask register (k1) into equal-sized partitions of the same size as the immediate value. A source write mask register (k2) is used to identify the unmasked logical partitions of the destination write mask register (k1). This source write mask register controls multiplexer 2018 to select between the immediate value (for the unmasked element) and a previous value (for the masked element). Execution circuitry 2016 further feeds the output of multiplexer 2018 to broadcast circuitry 2020, which then writes it into destination mask register k1.

[0257] Figure 20 Some vector elements in the code are illustrated as "x", signifying arbitrary values. They are not relevant to the discussion of the operation of this instruction.

[0258] Exemplary hardware for executing KBROADCASTIMM2MSK instructions

[0259] Figure 21 The figure illustrates an embodiment of hardware for processing instructions such as arithmetic recursive instructions. As illustrated, storage device 2103 stores the KBROADCASTIMM2MSK instruction 2101 to be executed.

[0260] Decoding circuit 2105 receives the instruction. For example, decoding circuit 2105 receives the instruction from extraction logic / circuit. Instruction 2101 includes fields for arithmetic codes (e.g., the mnemonic "KBROADCASTIMM2MSK"), a destination identifier 1106 for specifying the packaged destination register, and an immediate value. In some embodiments, the source[s] and destination are registers, while in other embodiments, one or more of them are memory locations. More detailed embodiments of at least one instruction format will be described later. Decoding circuit 2105 decodes the instruction into one or more operations. In some embodiments, the decoding includes generating multiple micro-operations to be performed by execution circuitry (such as execution circuitry 2109 or 2016). Decoding circuit 2105 also decodes instruction prefixes (if used).

[0261] In some embodiments, register renaming, register dispatching, and / or scheduling circuitry 2107 provides functionality for one or more of the following: 1) renaming logical operand values ​​to physical operand values ​​(e.g., in a register alias table in some embodiments), 2) dispatching status bits and flags to decoded instructions, and 3) (e.g., using a reserved station in some embodiments) scheduling decoded instructions from an instruction pool for execution on execution circuitry.

[0262] Registers (register files) and / or memory 2108 store data as operands of instructions to be processed by the execution circuitry. Exemplary register types include packed data registers, general-purpose registers, and floating-point registers.

[0263] The execution circuit 2109 executes the decoded KBROADCASTIMM2MSK instruction. Figure 20 An embodiment of execution circuit 2016 is shown, which is similar to execution circuit 2109. Write-back (retirement) circuit 2111 submits the execution result of the decoded KBROADCASTIMM2MSK instruction.

[0264] Example format of the KBROADCASTIMM2MSK instruction

[0265] In some embodiments, the write-back / write-back circuitry architecturally commits the destination register to a register or memory and writes the instruction back.

[0266] An embodiment of the format used for the KBROADCASTIMM2MSK instruction is OPCODE DSTMASKREG,SRCMASKREG, IMM1. In some embodiments, KBROADCASTIMM2MSK{B / W / D / Q} is the arithmetic code mnemonic for the instruction, where the size parameter {B / W / D / Q} specifies the size of the immediate value. SRCREG is a field used to identify the write mask (such as k2) to select which of the immediate value and the previous value to broadcast to the destination mask register 2022.

[0267] In some embodiments, the OPCODE field is a full operand field (such as 2974) or a real operand field (such as 2930), the SRCREG field is a Reg field (such as 2944), the DSTREG field is an R / M field (such as 2946), and the IMM1 field is an IMM8 field (such as...). Figure 29A (2972 in the middle).

[0268] In some embodiments, the KBROADCASTIMM2MSK instruction includes a field (k) for a write mask register operand (e.g., KBROADCASTIMM2MSK{k} DSTREG, SRC1, SRC2). A write mask is used to conditionally control the operation on each element and the update of the result. Depending on the implementation, the write mask uses a merge or zero-based mask. Instructions encoded with assertion (write mask, write mask, or k register) operands use these operands to conditionally control the computation on each element and the update of the result to the destination operand. The assertion operand is known as an operand mask (write mask) register. In some embodiments, the operand mask is a set of 64-bit architecture registers. It should be noted that only k1 through k7 can be addressed as assertion operands from this set of architecture registers. k0 can be used as a regular source or destination, but cannot be encoded as an assertion operand. It should also be noted that assertion operands can be used to enable memory fault tolerance for some instructions with memory operands (sources or destinations). As an assertion operand, the arithmetic mask register contains one bit to manage the operation / update of each data element in the vector register. Generally, the arithmetic mask register can support instructions with the following element sizes: single-precision floating-point (float32), integer double-word (int32), double-precision floating-point (float64), and integer quad-word (int64). The length MAX_KL of the arithmetic mask register is sufficient to handle up to 64 elements, with one bit per element, i.e., 64 bits. For a given vector length, each instruction accesses only the least significant mask bits required based on its data type.

[0269] The arithmetic mask register affects instructions at the granularity of each element. Therefore, the corresponding bits in the arithmetic mask register assert any numerical or non-numerical operations on each data element, as well as updates to each element of the destination operand from intermediate results. In most embodiments, the arithmetic mask acting as the assertion operand obeys the following properties: 1) If the corresponding arithmetic mask bit is not set (which implies that operations on masked elements cannot cause an exception or violation, and therefore, the exception flag will not be updated as a result of the masked operation), then the instruction is not performed on that element; 2) If the corresponding write mask bit is not set, then the destination element is not updated with the result of the operation; instead, the destination element value must be preserved (merge masking) or it must be zeroed (zero masking); and 3) For some instructions with memory operands, memory faults are suppressed for elements with a mask bit of 0. It should be noted that this feature provides a universal construct for implementing control flow assertions, since the mask effectively provides merge behavior for the vector register destination. As an alternative, this masking can be used for zeroing instead of merging, so that the masked elements are updated with 0 instead of retaining the old value. Zeroing behavior is provided to remove implicit dependencies on the old value when it is no longer needed.

[0270] In one embodiment, the instruction encoding includes a Scale-Index-Radius (SIB) type memory addressing operand, which indirectly identifies multiple indexed destination locations in memory. In one embodiment, the SIB type memory operand may include encoding identifying a radius address register. The contents of this radius address register may represent a radius address in memory, used to calculate the address of a specific destination location in memory. For example, the radius address may be the address of a first location in a potential destination location block for extended vector instructions. In one embodiment, the SIB type memory operand may include encoding identifying an index register. Each element of the index register may specify an index or offset value that can be used to calculate the address of the corresponding destination location within the potential destination location block based on the radius address. In one embodiment, the SIB type memory operand may include encoding specifying a scaling factor to be applied to each index value when calculating the corresponding destination address. For example, if a scaling factor of 4 is encoded in the SIB type memory operand, each index value obtained from an element in the index register can be multiplied by 4 and then added to the radius address to calculate the destination address.

[0271] In one embodiment, SIB memory operands of the form vm32{x, y, z} can identify a vector array of memory operands specified using SIB memory addressing. In this example, an array of memory addresses is specified using a common base register, a constant scaling factor, and a vector index register containing individual elements (each of which is a 32-bit index value). The vector index register can be a 128-bit register (e.g., XMM) register (vm32x), a 256-bit register (e.g., YMM) register (vm32y), or a 512-bit register (e.g., ZMM) register (vm32z). In another embodiment, SIB memory operands of the form vm64{x, y, z} can identify a vector array of memory operands specified using SIB memory addressing. In this example, an array of memory addresses is specified using a common base register, a constant scaling factor, and a vector index register containing individual elements (each of which is a 64-bit index value). The vector index register can be a 128-bit register (e.g., XMM) register (vm64x), a 256-bit register (e.g., YMM) register (vm64y), or a 512-bit register (e.g., ZMM) register (vm64z).

[0272] Exemplary execution method of the KBROADCASTIMM2MSK instruction

[0273] Figure 22 The diagram illustrates an embodiment of a method implemented by a processor to process the KBROADCASTIMM2MSK instruction. For example, Figure 21 The method is implemented using processor components, pipelines, etc., as detailed below.

[0274] At 2201, fetch the instruction. For example, fetch the KBROADCASTIMM2MSK instruction. The KBROADCASTIMM2MSK instruction includes fields for the operand, destination write mask operand, source operand, and immediate value. In some embodiments, the instruction further includes a field for the write mask. In some embodiments, the instruction is fetched from the instruction cache. The destination operand specifies the write mask register. The operand of the KBROADCASTIMM2MSK instruction indicates that the immediate value is to be broadcast to the mask register.

[0275] At 2203, the extracted instruction is decoded. For example, the extracted KBROADCASTIMM2MSK instruction is decoded by a decoding circuit such as that detailed herein.

[0276] At 2205, the decoded instructions are scheduled (on demand).

[0277] At 2207, the scheduled instruction is executed by an execution circuit (hardware) such as 2016. For the KBROADCASTIMM2MSK instruction, this execution will cause the execution circuit (such as 2016) to logically partition the write mask register k1 into logical partitions of the same size as imm1, use the write mask register k2 to identify the unmasked partition of the destination write mask register k1, and broadcast imm1 to the unmasked partition.

[0278] In some embodiments, at 2209, the instruction is submitted or withdrawn.

[0279] KXORKREGIMM command

[0280] Exemplary execution

[0281] This article details an implementation of the KXORKREGIMM instruction for improving the computer itself. In particular, the execution of the KXORKREGIMM instruction provides the advantage of allowing the use of immediate values ​​within the instruction without requiring that value to be stored in a register.

[0282] Figure 23 The diagram illustrates an exemplary execution of the KXORKREGIMM instruction. The KXORKREGIMM instruction 2302 format includes fields for the operand 2304 (e.g., the mnemonic "KXORKREGIMM"), the destination write mask register (k12306), the source write mask register (k2) 2308, the second source write mask register (k3) 2310, the mask element control field (z 2312), and the immediate value (imm12314).

[0283] In response to the instruction having an arithmetic code 2304 equal to KXORKREGIMM, the execution circuit 2318 logically partitions the destination write mask register (k1 2328) into equal-sized partitions with the same size as the immediate value (imm1 2314). The source write mask register (k2) is used to identify the unmasked logical partitions of the destination write mask register (k1 2328). An XOR gate 2320 performs a bitwise XOR operation on the source write mask register (k3 2326) and the immediate value (imm1 2314). The execution circuit 2318 further feeds the output of the XOR gate 2320 to the broadcast circuit 2322, which in turn broadcasts the result of the XOR operation to the unmasked logical partitions of the destination mask register k1. For masked logical partitions, the execution circuit 2318 sets the logical partitions in the destination write mask register 2328 to zero when the masking element control field indicates that the masked element should be zeroed.

[0284] Exemplary hardware for executing KXORKREGIMM instructions

[0285] Figure 24 The figure illustrates an embodiment of hardware for processing instructions such as arithmetic recursive instructions. As illustrated, storage device 2403 stores KXORKREGIMM instructions 2401 to be executed.

[0286] Decoding circuit 2405 receives the instruction. For example, decoding circuit 2405 receives the instruction from extraction logic / circuit. Instruction 2401 includes fields for arithmetic codes (e.g., the mnemonic "KXORKREGIMM"), a destination identifier 1106 for specifying the packing destination register, and an immediate value. In some embodiments, the source[s] and destination are registers, while in other embodiments, one or more of them are memory locations. More detailed embodiments of at least one instruction format will be described later. Decoding circuit 2405 decodes the instruction into one or more operations. In some embodiments, the decoding includes generating multiple micro-operations to be performed by execution circuitry (such as execution circuitry 2409 or 2318). Decoding circuit 2405 also decodes instruction prefixes (if used).

[0287] In some embodiments, register renaming, register dispatching, and / or scheduling circuitry 2407 provides functionality for one or more of the following: 1) renaming logical operand values ​​to physical operand values ​​(e.g., in a register alias table in some embodiments), 2) dispatching status bits and flags to decoded instructions, and 3) (e.g., using a reserved station in some embodiments) scheduling decoded instructions from an instruction pool for execution on execution circuitry.

[0288] Registers (register files) and / or memory 2408 store data as operands of instructions to be processed by the execution circuitry. Exemplary register types include packed data registers, general-purpose registers, and floating-point registers.

[0289] Execution circuit 2409 executes the decoded KXORKREGIMM instruction. Figure 23 The execution circuit 2318 is shown. The execution of the decoded KXORKREGIMM instruction logically partitions the destination write mask register into equal-sized partitions with the same size as the immediate value 2314, and uses source write mask registers k2 2308, 2326 to identify the unmasked partitions. The execution circuit further performs a bitwise XOR operation between the immediate value and the second source write mask register k3 2310. The execution circuit further forwards the result of the XOR gate 2320 to the broadcast circuit 2322k, which then writes the result to the unmasked partition of the destination register k3. The write-back (retirement) circuit 2411 submits the execution result of the decoded KXORKREGIMM instruction.

[0290] Example format of KXORKREGIMM instructions

[0291] In some embodiments, the write-back / write-back circuitry architecturally commits the destination register to a register or memory and writes the instruction back.

[0292] An example of the format used for KXORKREGIMM instruction 2302 ( Figure 23 The parameters are OPCODE (such as opcode 2304), DSTMASKREG (such as k1 2306), WRITEMASK (such as k2 2308), mask element control fields (such as Z-CTRL 2310), SRCMASKREG (such as k3 2312), and IMM1 (such as IMM1 2314). In some embodiments, KXORKREGIMM{B / W / D / Q} is the opcode mnemonic for the instruction, where the size parameter {B / W / D / Q} specifies the size of the immediate value. k2 2308 identifies a write mask register (such as k2 mask register 2326) to select which of the immediate value and the previous value to broadcast to the destination write mask register 2328.

[0293] In some embodiments, the OPCODE field is a full operand field (such as 2974) or a real operand field (such as 2930), the SRCMASKREG field is a Reg field (such as 2944), the DSMMASKREG field is an R / M field (such as 2946), and the IMM1 field is an IMM8 field (such as...). Figure 29A (2972 in the middle).

[0294] In some embodiments, the KXORKREGIMM instruction includes a field (k) for a write mask register operand (e.g., KXORKREGIMM{k} DSTREG, SRC1, SRC2). A write mask is used to conditionally control the operation on each element and the update of the result. Depending on the implementation, the write mask uses either a merge or zero-mapping mask. Instructions encoded with assertion (write mask, write mask, or k register) operands use these operands to conditionally control the computation on each element and the update of the result to the destination operand. Assertion operands are known as operand mask (write mask) registers. In some embodiments, the operand mask is a set of 64-bit architecture registers. It should be noted that only k1 through k7 can be addressed as assertion operands from this set of architecture registers. k0 can be used as a regular source or destination, but cannot be encoded as an assertion operand. It should also be noted that assertion operands can be used to enable memory fault tolerance for some instructions with memory operands (sources or destinations). As an assertion operand, the arithmetic mask register contains one bit to manage the operation / update of each data element in the vector register. Generally, the arithmetic mask register can support instructions with the following element sizes: single-precision floating-point (float32), integer double-word (int32), double-precision floating-point (float64), and integer quad-word (int64). The length MAX_KL of the arithmetic mask register is sufficient to handle up to 64 elements, with one bit per element, i.e., 64 bits. For a given vector length, each instruction accesses only the least significant mask bits required based on its data type.

[0295] The arithmetic mask register affects instructions at the granularity of each element. Therefore, the corresponding bits in the arithmetic mask register assert any numerical or non-numerical operations on each data element, as well as updates to each element of the destination operand from intermediate results. In most embodiments, the arithmetic mask acting as the assertion operand obeys the following properties: 1) If the corresponding arithmetic mask bit is not set (which implies that operations on masked elements cannot cause an exception or violation, and therefore, the exception flag will not be updated as a result of the masked operation), then the instruction is not performed on that element; 2) If the corresponding write mask bit is not set, then the destination element is not updated with the result of the operation; instead, the destination element value must be preserved (merge masking) or it must be zeroed (zero masking); and 3) For some instructions with memory operands, memory faults are suppressed for elements with a mask bit of 0. It should be noted that this feature provides a universal construct for implementing control flow assertions, since the mask effectively provides merge behavior for the vector register destination. As an alternative, this masking can be used for zeroing instead of merging, so that the masked elements are updated with 0 instead of retaining the old value. Zeroing behavior is provided to remove implicit dependencies on the old value when it is no longer needed.

[0296] In one embodiment, the instruction encoding includes a Scale-Index-Radius (SIB) type memory addressing operand, which indirectly identifies multiple indexed destination locations in memory. In one embodiment, the SIB type memory operand may include encoding identifying a radius address register. The contents of this radius address register may represent a radius address in memory, used to calculate the address of a specific destination location in memory. For example, the radius address may be the address of a first location in a potential destination location block for extended vector instructions. In one embodiment, the SIB type memory operand may include encoding identifying an index register. Each element of the index register may specify an index or offset value that can be used to calculate the address of the corresponding destination location within the potential destination location block based on the radius address. In one embodiment, the SIB type memory operand may include encoding specifying a scaling factor to be applied to each index value when calculating the corresponding destination address. For example, if a scaling factor of 4 is encoded in the SIB type memory operand, each index value obtained from an element in the index register can be multiplied by 4 and then added to the radius address to calculate the destination address.

[0297] In one embodiment, SIB memory operands of the form vm32{x, y, z} can identify a vector array of memory operands specified using SIB memory addressing. In this example, an array of memory addresses is specified using a common base register, a constant scaling factor, and a vector index register containing individual elements (each of which is a 32-bit index value). The vector index register can be a 128-bit register (e.g., XMM) register (vm32x), a 256-bit register (e.g., YMM) register (vm32y), or a 512-bit register (e.g., ZMM) register (vm32z). In another embodiment, SIB memory operands of the form vm64{x, y, z} can identify a vector array of memory operands specified using SIB memory addressing. In this example, an array of memory addresses is specified using a common base register, a constant scaling factor, and a vector index register containing individual elements (each of which is a 64-bit index value). The vector index register can be a 128-bit register (e.g., XMM) register (vm64x), a 256-bit register (e.g., YMM) register (vm64y), or a 512-bit register (e.g., ZMM) register (vm64z).

[0298] Exemplary Execution Method of KXORKREGIMM Instructions

[0299] Figure 25 The diagram illustrates an embodiment of a method implemented by a processor to process KXORKREGIMM instructions. For example, Figure 24 The method is implemented using processor components, pipelines, etc., as detailed below.

[0300] At 2501, an instruction is fetched. For example, the KXORKREGIMM instruction is fetched. The KXORKREGIMM instruction includes fields for the operand, destination operand, write mask identifier, mask element control field, source operand, and immediate value. In some embodiments, the instruction is fetched from the instruction cache. The destination operand specifies the write mask register. The operand of the KXORKREGIMM instruction indicates that the result of an XOR operation involving the immediate value (imm1 2314) and the source mask register (k3 register 2326) is broadcast to the write mask register (k1 2328) using the broadcast circuit 2322.

[0301] As shown, the broadcast circuit 2322 uses the write mask register (k2 2326) and the mask element control field (Z-CTRL 2324) to broadcast the result of the XOR operation to each of the unmasked elements of k1 2328 and to zero out the masked elements of k1 2328.

[0302] At position 2503, the extracted instruction is decoded. For example, the extracted KXORKREGIMM instruction is decoded by a decoding circuit such as that detailed herein.

[0303] At 2505, the decoded instructions are scheduled (on demand).

[0304] At 2507, the decoded instruction is executed by an execution circuit (hardware) such as 2318. For the KXORKREGIMM instruction, this execution causes the execution circuit (such as 2318) (e.g., by using an XOR gate 2320) to perform an XOR operation between an immediate value (such as imm1 2314) and a source mask register (such as k3 mask register 2326), and uses a broadcast circuit (such as k2 mask register 2326) and a mask element control field (such as Z-CTRL 2324) to broadcast the result of the XOR operation to the unmasked element in the destination write mask register (such as k1 2328) and to zero out the masked element in the destination register.

[0305] In some embodiments, at 2509, the instruction is submitted or withdrawn.

[0306] VPADD3OPR command

[0307] Exemplary execution

[0308] This article details an embodiment of the VPADD3OPR instruction used to improve the computer itself. In particular, the execution of the VPADD3OPR instruction has the advantage of allowing the use of immediate values ​​in instructions involving three operands without requiring multiple instructions to achieve the same result.

[0309] Figure 26 The diagram illustrates an exemplary execution of the VPADD3OPR instruction. The VPADD3OPR instruction 2602 format includes an arithmetic code 2604 (e.g., the mnemonic "VPADD3OPR"), a packing dst register 2622 to specify the result of the operation to be stored, a packing source / destination identifier (dst / src1 2612 before execution, dst / src1 2622 after execution) to specify the packing dst / src1 register (used as both source and destination for the operation), a second packing source identifier (src2 2608) to specify the packing src2 register 2614, and an immediate value (imm1 2610).

[0310] In response to an instruction having an arithmetic code 2604 equal to VPADD3OPR, execution circuitry 2616 uses adder 2618 to add packed dst / src1 2612 to packed src2 2614 plus the immediate value imm1 2610, and passes the resulting sum to broadcast circuitry 2620, which broadcasts the sum to packed dst register 2622. In an embodiment, adder 2618 includes multiple adders to add all destination vector elements in parallel.

[0311] Exemplary hardware for executing VPADD3OPR instructions

[0312] Figure 27 The figure illustrates an embodiment of hardware for processing instructions such as arithmetic recursive instructions. As illustrated, storage device 2703 stores the VPADD3OPR instruction 2701 to be executed.

[0313] Decoding circuit 2705 receives the instruction. For example, decoding circuit 2705 receives the instruction from extraction logic / circuit. Instruction 2701 includes fields for an arithmetic code (e.g., the mnemonic "VPADD3OPR"), a destination identifier 1106 for specifying the packaged destination register, and an immediate value. In some embodiments, the source[s] and destination are registers, while in other embodiments, one or more of them are memory locations. More detailed embodiments of at least one instruction format will be described later. Decoding circuit 2705 decodes the instruction into one or more operations. In some embodiments, the decoding includes generating multiple micro-operations to be performed by execution circuitry (such as execution circuitry 2709 or 2616). Decoding circuit 2705 also decodes instruction prefixes (if used).

[0314] In some embodiments, register renaming, register dispatching, and / or scheduling circuitry 2707 provides functionality for one or more of the following: 1) renaming logical operand values ​​to physical operand values ​​(e.g., in a register alias table in some embodiments), 2) dispatching status bits and flags to decoded instructions, and 3) (e.g., using a reserved station in some embodiments) scheduling decoded instructions from an instruction pool for execution on execution circuitry.

[0315] Registers (register files) and / or memory 2708 store data as operands of instructions to be processed by the execution circuitry. Exemplary register types include packed data registers, general-purpose registers, and floating-point registers.

[0316] Execution circuit 2709 executes the decoded VPADD3OPR instruction. Figure 26The execution circuit 2616 is shown in the figure. The write-back (retirement) circuit 2711 submits the execution result of the decoded VPADD3OPR instruction.

[0317] Example format of the VPADD3OPR instruction

[0318] In some embodiments, the write-back / write-back circuitry architecturally commits the destination register to a register or memory and writes the instruction back.

[0319] An example of the format used for VPADD3OPR instruction 2602 ( Figure 26 The OPCODE (such as operation code 2604), the DST.SRC1 identifier (such as dst / src1 2606), the second source identifier SRC2 2608, and the immediate value (such as IMM12614) are all present. In some embodiments, VPADD3OPR{B / W / D / Q} is the operation code mnemonic for this instruction, where the size parameter {B / W / D / Q} specifies the size of the immediate value.

[0320] In some embodiments, the OPCODE field is a full operand field (such as 2974) or a real operand field (such as 2930), the DST / SRC1 field is a Reg field (such as 2944), the SRC2 field is an R / M field (such as 2946), and the IMM1 field is an IMM8 field (such as...). Figure 29A (2972 in the middle).

[0321] In some embodiments, the VPADD3OPR instruction includes a field (k) for a write mask register operand (e.g., VPADD3OPR{k} DST / SRC1, SRC2, IMM1). A write mask is used to conditionally control the operation on each element and the update of the result. Depending on the implementation, the write mask uses either a merge or zero-based mask. Instructions encoded with assertion (write mask, write mask, or k register) operands use these operands to conditionally control the computation on each element and the update of the result to the destination operand. Assertion operands are known as operand mask (write mask) registers. In some embodiments, the operand mask is a set of 64-bit architecture registers. It should be noted that only k1 through k7 can be addressed as assertion operands from this set of architecture registers. k0 can be used as a regular source or destination, but cannot be encoded as an assertion operand. It should also be noted that assertion operands can be used to enable memory fault tolerance for some instructions with memory operands (sources or destinations). As an assertion operand, the arithmetic mask register contains one bit to manage the operation / update of each data element in the vector register. Generally, the arithmetic mask register can support instructions with the following element sizes: single-precision floating-point (float32), integer double-word (int32), double-precision floating-point (float64), and integer quad-word (int64). The length MAX_KL of the arithmetic mask register is sufficient to handle up to 64 elements, with one bit per element, i.e., 64 bits. For a given vector length, each instruction accesses only the least significant mask bits required based on its data type.

[0322] The arithmetic mask register affects instructions at the granularity of each element. Therefore, the corresponding bits in the arithmetic mask register assert any numerical or non-numerical operations on each data element, as well as updates to each element of the destination operand from intermediate results. In most embodiments, the arithmetic mask acting as the assertion operand obeys the following properties: 1) If the corresponding arithmetic mask bit is not set (which implies that operations on masked elements cannot cause an exception or violation, and therefore, the exception flag will not be updated as a result of a masked operation), then the instruction is not performed on that element; 2) If the corresponding write mask bit is not set, then the destination element is not updated with the result of the operation. Alternatively, the destination element value must be preserved (merge masking) or it must be zeroed (zero masking); and 3) For some instructions with memory operands, memory faults are suppressed for elements with a mask bit of 0. It should be noted that this feature provides a universal construct for implementing control flow assertions, since the mask effectively provides merge behavior for the vector register destination. As an alternative, this masking can be used for zeroing instead of merging, so that the masked elements are updated with 0 instead of retaining the old value. Zeroing behavior is provided to remove implicit dependencies on the old value when it is no longer needed.

[0323] In one embodiment, the instruction encoding includes a Scale-Index-Radius (SIB) type memory addressing operand, which indirectly identifies multiple indexed destination locations in memory. In one embodiment, the SIB type memory operand may include encoding identifying a radius address register. The contents of this radius address register may represent a radius address in memory, used to calculate the address of a specific destination location in memory. For example, the radius address may be the address of a first location in a potential destination location block for extended vector instructions. In one embodiment, the SIB type memory operand may include encoding identifying an index register. Each element of the index register may specify an index or offset value that can be used to calculate the address of the corresponding destination location within the potential destination location block based on the radius address. In one embodiment, the SIB type memory operand may include encoding specifying a scaling factor to be applied to each index value when calculating the corresponding destination address. For example, if a scaling factor of 4 is encoded in the SIB type memory operand, each index value obtained from an element in the index register can be multiplied by 4 and then added to the radius address to calculate the destination address.

[0324] In one embodiment, SIB memory operands of the form vm32{x, y, z} can identify a vector array of memory operands specified using SIB memory addressing. In this example, an array of memory addresses is specified using a common base register, a constant scaling factor, and a vector index register containing individual elements (each of which is a 32-bit index value). The vector index register can be a 128-bit register (e.g., XMM) register (vm32x), a 256-bit register (e.g., YMM) register (vm32y), or a 512-bit register (e.g., ZMM) register (vm32z). In another embodiment, SIB memory operands of the form vm64{x, y, z} can identify a vector array of memory operands specified using SIB memory addressing. In this example, an array of memory addresses is specified using a common base register, a constant scaling factor, and a vector index register containing individual elements (each of which is a 64-bit index value). The vector index register can be a 128-bit register (e.g., XMM) register (vm64x), a 256-bit register (e.g., YMM) register (vm64y), or a 512-bit register (e.g., ZMM) register (vm64z).

[0325] Exemplary Execution Method of VPADD3OPR Instruction

[0326] Figure 28 The diagram illustrates an embodiment of a method implemented by a processor to process the VPADD3OPR instruction. For example, Figure 27 The method is implemented using processor components, pipelines, etc., as detailed below.

[0327] At 2801, an instruction is fetched. For example, the VPADD3OPR instruction is fetched. The VPADD3OPR instruction includes fields for an operand, a first source / destination operand (the packed data register storing the first source is also used to store the result of this operation), a second source operand, and an immediate value. In some embodiments, this instruction is fetched from the instruction cache. The source / destination operand specifies the packed data vector register, sometimes referred to herein as the packed destination register. The operand of the VPADD3OPR instruction indicates an addition (ADD) operation with three addends: the first source, the second source, and the immediate value. In embodiments, this addition operation is detrimental in terms of the extent to which the resulting sum is written into the first source register, thereby corrupting the previous contents of the source register. Broadcast circuitry.

[0328] At 2803, the extracted instruction is decoded. For example, the extracted VPADD3OPR instruction is decoded by a decoding circuit such as that detailed herein.

[0329] At 2805, the decoded instructions are scheduled (on demand).

[0330] At 2807, the scheduled instruction is executed by execution circuitry (hardware) such as 2616. For the VPADD3OPR instruction, this execution causes the execution circuitry (such as 2616) to perform an addition operation (e.g., using adder 2618) on an immediate value (such as imm1 2610), a first packing source (such as packing dst / src 2612), and a second packing source register (such as packing src2 2614). The resulting sum is routed to broadcast circuitry 2620, which broadcasts the result to packing destination register 2622, which in some embodiments is the same packing destination register used by packing dst / src1 2612.

[0331] In some embodiments, at 2809, the instruction is submitted or withdrawn.

[0332] Instruction set

[0333] An instruction set comprises one or more instruction formats. A given instruction format defines various fields (number of bits, bit positions) to specify, among other things, the operation to be performed (operation code) and the operand(s) to be operated on. Some instruction formats are further decomposed by defining instruction templates (or subformats). For example, an instruction template for a given instruction format can be defined as having different subsets of the fields of the instruction format (the included fields are typically in the same order, but at least some have different bit positions because fewer fields are included) and / or can be defined as having given fields interpreted in different ways. Thus, each instruction of the ISA is expressed using a given instruction format (and, if defined, a given instruction template from the instruction templates of that instruction format), and each instruction includes fields for specifying the operation and operands. For example, an exemplary addition instruction has a specific operation code and instruction format, which includes an operation code field for specifying the operation code and an operand field for selecting operands (source 1 / destination and source 2); and the appearance of this addition instruction in the instruction stream will have specific content in the operand field for selecting specific operands.

[0334] Exemplary instruction format

[0335] Examples of the instructions(s) described herein may be embodied in different formats. Additionally, exemplary systems, architectures, and pipelines are detailed below. Examples of instructions(s)(s) can be executed on such systems, architectures, and pipelines, but are not limited to those detailed herein.

[0336] VEX command format

[0337] VEX encoding allows instructions to have more than two operands and allows SIMD vector registers to be longer than 298 bits. The use of the VEX prefix provides syntax for three (or more) operands. For example, previous two-operand instructions performed operations such as A = A + B, which overwrote the source operands. The use of the VEX prefix allows operands to perform non-destructive operations, such as A = B + C.

[0338] Figure 29A The diagram illustrates an exemplary AVX instruction format, which includes a VEX prefix 2902, a real operand field 2930, a ModR / M byte 2940, a SIB byte 2950, ​​a shift field 2962, and an IMM8 2972. Figure 29B The diagram shows the source Figure 29A Which fields in the table constitute the full operand field 2974 and the basic operand field 2942? Figure 29C The diagram shows the source Figure 29A Which fields in the register index field 2944 constitute the register index field?

[0339] The VEX prefix (bytes 0-2) 2902 is encoded in three-byte form. The first byte is the format field 2940 (VEX byte 0, bits [7:0]), which contains the explicit C4 byte value (a unique value used to distinguish the C4 instruction format). The second and third bytes (VEX bytes 1-2) include several bit fields that provide specific capabilities. Specifically, the REX field 2905 (VEX byte 1, bits [7-5]) includes the VEX.R bit field (VEX byte 1, bits [7]-R), the VEX.X bit field (VEX byte 1, bits [6]-X), and the VEX.B bit field (VEX byte 1, bits [5]-B). The other fields of the instruction encode the three lower bits (rrr, xxx, and bbb) of the register index as is known in the art, so that Rrrr, Xxxx, and Bbbb can be formed by adding VEX.R, VEX.X, and VEX.B. The operand mapping field 2932 (VEX byte 1, bits [4:0]-mmmmmm) includes the contents used to encode the implicit preamble operand byte. The W field 2964 (VEX byte 2, bits [7]-W) is indicated by the tag VEX.W and provides different functions depending on the instruction. The function of VEX.vvvv 2920 (VEX byte 2, bits [6:3]-vvvv) can include the following: 1) VEX.vvvv encodes the first source register operand, which is specified in reverse (1s complement) form and is valid for instructions with two or more source operands; 2) VEX.vvvv encodes the destination register operand, which is specified in 1s complement form for certain vector shifts; or 3) VEX.vvvv does not encode any operand, and this field is reserved and should contain 1111b. If the VEX.L 2968 size field (VEX byte 2, bits [2]-L) = 0, it indicates a 298-bit vector; if VEX.L = 1, it indicates a 256-bit vector. The prefix encoding field 2925 (VEX byte 2, bits [1:0]-pp) provides additional bits for the basic operation field.

[0340] The actual operand field 2930 (byte 3) is also known to be the operand byte. The operand is specified in this field.

[0341] The MOD R / M field 2940 (byte 4) includes the MOD field 2942 (bits [7-6]), the Reg field 2944 (bits [5-3]), and the R / M field 2946 (bits [2-0]). The Reg field 2944 can encode either a destination register operand or a source register operand (rrr in Rrrr), or it can be treated as an operand extension and not used to encode any instruction operand. The R / M field 2946 can encode either an instruction operand referencing a memory address, or it can encode either a destination register operand or a source register operand.

[0342] The proportion, index, and base (SIB) field 2950 (byte 5) contains SS2952 (bits [7-6]), which is used for memory address generation. The contents of SIB.xxx 2954 (bits [5-3]) and SIB.bbb2956 (bits [2-0]) have been previously cited regarding register indices Xxxx and Bbbb.

[0343] The displacement field 2962 and the immediate numeric field (IMM8) 2972 ​​contain data.

[0344] Exemplary Register Architecture

[0345] Figure 30 This is a block diagram of a register architecture 3000 according to an embodiment of the present invention. In the illustrated embodiment, there are 32 vector registers 3010 with a width of 512 bits; these registers are referenced as zmm0 to zmm31. The lower-order 256 bits of the lower 33 zmm registers cover registers ymm0-15. The lower-order 128 bits of the lower 33 zmm registers (the lower-order 128 bits of the ymm registers) cover registers xmm0-15.

[0346] General Purpose Register 3025 – In the illustrated embodiment, there are 16 64-bit general purpose registers that, together with the existing x86 addressing modes, are used to address memory operands. These registers are referred to by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R32.

[0347] Scalar floating-point stack register file (x87 stack) 3045 (also known as MMX packed integer flat register file 3050) — In the illustrated embodiment, the x87 stack is an 8-element stack used for performing scalar floating-point operations on 32 / 64 / 80-bit floating-point data extended with the x87 instruction set; the MMX register is used to perform operations on 64-bit packed integer data and to store operands for some operations performed between the MMX and XMM registers.

[0348] Alternative embodiments of the invention may use wider or narrower registers. Additionally, alternative embodiments of the invention may use more, fewer, or different register files and registers.

[0349] Exemplary core architecture, processor, and computer architecture

[0350] Processor cores can be implemented in different ways, for different purposes, and implemented in different processors. For example, such core implementations can include: 1) general-purpose ordered cores intended for general-purpose computing; 2) high-performance general-purpose unordered cores intended for general-purpose computing; and 3) dedicated cores primarily intended for graphics and / or scientific (throughput) computing. Different processor implementations can include: 1) a CPU comprising one or more general-purpose ordered cores intended for general-purpose computing and / or one or more general-purpose unordered cores intended for general-purpose computing; and 2) a coprocessor comprising one or more dedicated cores primarily intended for graphics and / or scientific (throughput) computing. Such different processors result in different computer system architectures, which can include: 1) a coprocessor on a separate chip from the CPU; 2) a coprocessor on a separate die in the same package as the CPU; 3) a coprocessor on the same die as the CPU (in which case, such a coprocessor is sometimes also referred to as dedicated logic, such as integrated graphics and / or scientific (throughput) logic, or a dedicated core); and 4) a system-on-a-chip (sometimes also referred to as one or more application cores or one or more application processors) that can be included on the same die as the CPU, along with the aforementioned coprocessors and additional functionality. The exemplary core architecture is described next, followed by a description of the exemplary processor and computer architecture. Circuits (units) including the exemplary core, processor, etc., are described in detail herein.

[0351] Exemplary core architecture

[0352] Block diagram of ordered and disordered cores

[0353] Figure 31A This is a block diagram illustrating both an exemplary ordered pipeline and an exemplary register renaming and unordered release / execution pipeline according to an embodiment of the present invention. Figure 31B This is a block diagram illustrating an exemplary embodiment of an ordered architecture core and an exemplary register renaming and out-of-order release / execution architecture core to be included in the processor, according to embodiments of the present invention. Figure 31A The solid-line diagram in -B illustrates ordered pipelines and ordered kernels, while the optional dashed-line diagrams illustrate register renaming, out-of-order release / execution pipelines, and kernels. Assuming that ordered aspects are a subset of out-of-order aspects, the out-of-order aspects will be described.

[0354] existFigure 31A In the processor pipeline 3100, there are fetch stage 3102, length decoding stage 3104, decoding stage 3106, dispatch stage 3108, rename stage 3110, scheduling (also known as dispatch or issue) stage 3112, register read / memory read stage 3114, execution stage 3116, write back / memory write stage 3118, exception handling stage 3122, and commit stage 3124.

[0355] Figure 31B The processor core 3190 is shown, which includes a front-end unit 3130 coupled to an execution engine unit 3150, and both units are coupled to a memory unit 3170. The core 3190 can be a Reduced Instruction Set Computing (RISC) core, a Complex Instruction Set Computing (CISC) core, a Very Long Instruction Word (VLIW) core, or a hybrid or alternative core type. Alternatively, the core 3190 can be a dedicated core, such as, for example, a network or communication core, a compression engine, a coprocessor core, a general-purpose computing graphics processing unit (GPGPU) core, a graphics core, etc.

[0356] Front-end unit 3130 includes branch prediction unit 3132 coupled to instruction cache unit 3134, instruction cache unit 3134 coupled to instruction translation lookup buffer (TLB) 3136, instruction translation lookup buffer (TLB) 3136 coupled to instruction fetch unit 3138, and instruction fetch unit 3138 coupled to decoding unit 3140. Decoding unit 3140 (or decoder) can decode instructions and generate one or more micro-operations, microcode entry points, microinstructions, other instructions, or other control signals as output, which are decoded from, or otherwise reflect, or derived from, the original instructions. Decoding unit 3140 can be implemented using various mechanisms. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLAs), microcode read-only memory (ROM), etc. In one embodiment, core 3190 includes microcode ROM or other medium storing microcode for certain macro instructions (e.g., in decoding unit 3140 or otherwise within front-end unit 3130). The decoding unit 3140 is coupled to the rename / dispatch unit 3152 in the execution engine unit 3150.

[0357] Execution engine unit 3150 includes a rename / dispatch unit 3152, which is coupled to retirement unit 3154 and a set of one or more scheduler units 3156. The scheduler units 3156 represent any number of different schedulers, including reservation stations, central instruction windows, etc. The scheduler units 3156 are coupled to one or more physical register file units 3158. Each of the physical register file units 3158 represents one or more physical register files, where different physical register files store one or more different data types, such as scalar integers, scalar floating-point numbers, packed integers, packed floating-point numbers, vector integers, vector floating-point numbers, status (e.g., an instruction pointer as the address of the next instruction to be executed), etc. In one embodiment, the physical register file units 3158 include vector register units, write mask register units, and scalar register units. These register units can provide architectural vector registers, vector mask registers, and general-purpose registers. One or more physical register file units 3158 are overlapped by retirement units 3154 to illustrate various ways in which register renaming and out-of-order execution can be implemented (e.g., using one or more reorder buffers and one or more retirement register files; using one or more future files, one or more history buffers, and one or more retirement register files; using register mappings and register pools, etc.). Retirement units 3154 and one or more physical register file units 3158 are coupled to one or more execution clusters 3160. Execution clusters 3160 include a set of one or more execution units 3162 and a set of one or more memory access units 3164. Execution units 3162 can perform various operations (e.g., shift, addition, subtraction, multiplication) and various data types (e.g., scalar floating-point, packed integer, packed floating-point, vector integer, vector floating-point). While some embodiments may include several execution units dedicated to a particular function or set of functions, other embodiments may include only one or more execution units that perform all functions. One or more scheduler units 3156, one or more physical register file units 3158, and one or more execution clusters 3160 are shown as possibly multiple, because some embodiments create separate pipelines for certain data / operation types (e.g., scalar integer pipelines, scalar floating-point / packed integer / packed floating-point / vector integer / vector floating-point pipelines, and / or memory access pipelines, each having its own scheduler unit, one or more physical register file units, and / or execution clusters—and in the case of separate memory access pipelines, implement certain embodiments in which only the execution cluster of that pipeline has one or more memory access units 3164).It should also be understood that, in the case of using separate pipelines, one or more of these pipelines may be unordered releases / executions while the rest are ordered.

[0358] The memory access unit 3164 is coupled to memory unit 3170, which includes a data TLB unit 3172. The data TLB unit 3172 is coupled to data cache unit 3174, which is coupled to level 2 (L2) cache unit 3176. In one exemplary embodiment, memory access unit 3164 may include a load unit, a memory address unit, and a memory data unit, each of which is coupled to the data TLB unit 3172 in memory unit 3170. Instruction cache unit 3134 is further coupled to level 2 (L2) cache unit 3176 in memory unit 3170. L2 cache unit 3176 is coupled to one or more other levels of cache and ultimately coupled to main memory.

[0359] By way of example, the exemplary register renaming, out-of-order release / execution core architecture can implement pipeline 3100 as follows: 1) Instruction fetch 3138 performs fetch and length decoding stages 3102 and 3104; 2) Decoding unit 3140 performs decoding stage 3106; 3) Rename / dispatcher unit 3152 performs dispatch stage 3108 and rename stage 3110; 4) (one or more) scheduler unit 3156 performs scheduling stage 3112; 5) (one or more) physical register file unit 3158 and memory unit 3170 perform register read / memory read stage 3114; execution cluster 3160 performs execution stage 3116; 6) memory unit 3170 and (one or more) physical register file unit 3158 perform write-back / memory write stage 3118; 7) Various units may be involved in exception handling stage 3122; and 8) retirement unit 3154 and (one or more) physical register file unit 3158 perform commit stage 3124.

[0360] Core 3190 may support one or more instruction sets (e.g., the x86 instruction set (and some extensions with newer versions added); the MIPS instruction set of MIPS Technologies, Sunnyvale, California; the ARM instruction set of ARM Holdings, Sunnyvale, California (and optional additional extensions such as NEON)), including one or more instructions described herein. In one embodiment, core 3190 includes logic for supporting packaged data instruction set extensions (e.g., AVX1, AVX2), thereby allowing the use of packaged data to perform operations used by many multimedia applications.

[0361] It should be understood that the core can support multithreading (execute two or more parallel sets of operations or sets of threads) and can do so in a variety of ways, including time-slice multithreading, simultaneous multithreading (where a single physical core provides a logical core for each of the threads that the physical core is performing multithreading on simultaneously), or a combination thereof (e.g., time-slice extraction and decoding followed by simultaneous multithreading, as in Intel® Hyper-Threading Technology).

[0362] Although register renaming is described in an out-of-order execution scenario, it should be understood that register renaming can be used in ordered architectures. While the illustrated processor embodiment also includes separate instruction and data cache units 3134 / 3174 and a shared L2 cache unit 476, alternative embodiments may have a single internal cache for both instructions and data, such as, for example, a Level 1 (L1) internal cache or a multi-level internal cache. In some embodiments, the system may include a combination of internal caches and external caches located outside the core and / or processor. Alternatively, all caches may be located outside the core and / or processor.

[0363] Specific Exemplary Ordered Core Architecture

[0364] Figure 32A -B diagram illustrates a more specific exemplary ordered core architecture, where the core will be one of several logic blocks in the chip (including other cores of the same and / or different types). The logic blocks communicate through a high-bandwidth interconnect network (e.g., a ring network) with certain fixed-function logic, memory I / O interfaces, and other necessary I / O logic (depending on the application).

[0365] Figure 32A This is a block diagram of a single processor core according to an embodiment of the invention, its connection to a ring network 3202 (e.g., an on-die interconnect network), and a local subset of its Level 2 (L2) cache 3204. In one embodiment, the instruction decoder 3200 supports the x86 instruction set with Packed Data Instruction Set Extensions. The L1 cache 3206 allows low-latency access to cache memory in scalar and vector units. Although (for design simplification) in one embodiment scalar unit 3208 and vector unit 3210 use separate register sets (scalar register 3212 and vector register 3214, respectively) and data transferred between them is written to memory and then read back from the Level 1 (L1) cache 3206, alternative embodiments of the invention may use different methods (e.g., using a single register set or including a communication path that allows data transfer between two register files without write-and-read-back).

[0366] The local subset 3204 of the L2 cache is part of the global L2 cache, which is divided into separate local subsets for each processor core. Each processor core has a direct access path to its own local subset 3204 of the L2 cache. Data read by a processor core is stored in its L2 cache subset 3204 and can be accessed quickly, in parallel with other processor cores accessing their own local L2 cache subsets. Data written by a processor core is stored in its own L2 cache subset 3204 and is evicted from other subsets if necessary. The ring network 3202 ensures the consistency of shared data. This ring network 3202 is bidirectional to allow agents such as processor cores, L2 caches, and other logical blocks to communicate with each other within the chip. Each ring data path is 1012 bits wide in each direction.

[0367] Figure 32B This is an embodiment of the present invention. Figure 32A An expanded diagram of the processor core. Figure 32B This includes L1 data cache 3206A (part of L1 cache 3204) and further details regarding vector unit 3210 and vector register 3214. Specifically, vector unit 3210 is a 33-width vector processing unit (VPU) (see 16-width ALU 3228) that executes one or more of integer instructions, single-precision float instructions, and double-precision float instructions. The VPU supports mixing register inputs using mixing unit 3220, performing value conversions using value conversion units 3222A-B, and copying memory inputs using copy unit 3224.

[0368] Processor with integrated memory controller and graphics device

[0369] Figure 33 This is a block diagram of a processor 3300 according to an embodiment of the present invention, which may have more than one core, may have an integrated memory controller, and may have an integrated graphics device. Figure 33 The solid-line block diagram shows a processor 3300 having a single core 3302A, a system agent 3310, and a group of one or more bus controller units 3316, while the dashed-line block optional additional diagram shows an alternative processor 3300 having multiple cores 3302A-N, a group of one or more integrated memory controller units 3331 among the system agent units 3310, and dedicated logic 3308.

[0370] Therefore, different implementations of processor 3300 may include: 1) a CPU with dedicated logic 3308 integrating graphics and / or scientific (throughput) logic (which may include one or more cores), and cores 3302A-N being one or more general-purpose cores (e.g., general-purpose ordered cores, general-purpose unordered cores, or a combination of both); 2) a coprocessor with cores 3302A-N, which are a large number of dedicated cores primarily used for graphics and / or scientific (throughput); and 3) a coprocessor with cores 3302A-N, which are a large number of general-purpose ordered cores. Thus, processor 3300 can be a general-purpose processor, a coprocessor, or a dedicated processor, such as, for example, a network or communication processor, a compression engine, a graphics processor, a GPGPU (General-Purpose Graphics Processing Unit), a high-throughput multi-core (MIC) coprocessor (including 30 or more cores), an embedded processor, etc. The processor can be implemented on one or more chips. The processor 3300 may be part of one or more substrates, or the processor 3300 may be implemented on one or more substrates using any of a variety of process technologies, such as, for example, BiCMOS, CMOS or NMOS.

[0371] The memory hierarchy includes one or more cache levels within cores 3304A-N, a set of one or more shared cache units 3306, and external memory (not shown) coupled to the set of integrated memory controller units 3331. The set of shared cache units 3306 may include one or more intermediate-level caches, such as Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache, last-level cache (LLC), and / or combinations thereof. While in one embodiment the integrated graphics logic 3308, the set of shared cache units 3306, and the system proxy units 3310 / (one or more) integrated memory controller units 3331 are interconnected based on a ring interconnect unit 3312, alternative embodiments may use any number of known techniques to interconnect such units. In one embodiment, consistency is maintained between one or more cache units 3306 and cores 3302-AN.

[0372] In some embodiments, one or more of the cores 3302A-N are capable of multithreading. System agent 3310 includes those components that coordinate and operate the cores 3302A-N. System agent unit 3310 may include, for example, a power control unit (PCU) and a display unit. The PCU may be, or include, the logic and components required to regulate the power states of the cores 3302A-N and the integrated graphics logic 3308. The display unit is used to drive one or more externally connected displays.

[0373] In terms of the instruction set of the architecture, the cores 3302A-N can be homogeneous or heterogeneous; that is, two or more cores of 3302A-N can be able to execute the same instruction set, while other cores can be able to execute only a subset of the instruction set or execute different instruction sets.

[0374] Exemplary computer architecture

[0375] Figures 34-37 This is a block diagram of an exemplary computer architecture. Other system designs and configurations known in the field of laptops, desktop computers, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, cellular phones, portable media players, handheld devices, and various other electronic devices are also suitable. In general, a wide variety of systems or electronic devices capable of incorporating processors and / or other execution logic as disclosed herein are generally suitable.

[0376] Now for reference Figure 34 A block diagram of a system 3400 according to an embodiment of the present invention is shown. System 3400 may include one or more processors 3410, 3415 coupled to a controller hub 3420. In one embodiment, the controller hub 3420 includes a graphics memory controller hub (GMCH) 3490 and an input / output hub (IOH) 3450 (which may be on a separate chip); the GMCH 3490 includes memory and a graphics controller, to which a memory 3440 and a coprocessor 3445 are coupled; the IOH 3450 couples an input / output (I / O) device 3460 to the GMCH 3490. Alternatively, one or both of the memory and the graphics controller are integrated within the processor (as described herein), with the memory 3440 and the coprocessor 3445 directly coupled to the processor 3410 and the controller hub 3420 on a single chip with the IOH 3450.

[0377] exist Figure 34 The optional nature of the additional processor 3415 is indicated by a dashed line. Each processor 3410, 3415 may include one or more of the processing cores described herein and may be a version of processor 3300.

[0378] The memory 3440 may be, for example, dynamic random access memory (DRAM), phase-change memory (PCM), or a combination of both. For at least one embodiment, the controller hub 3437 communicates with one or more processors 3410, 3415 via a multipoint bus 3495, such as a front-side bus (FSB), a point-to-point interface, or a similar connection.

[0379] In one embodiment, the coprocessor 3445 is a dedicated processor, such as, for example, a high-throughput MIC processor, a network or communications processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, and so on. In one embodiment, the controller hub 3420 may include an integrated graphics accelerator.

[0380] In terms of the metric spectrum of advantages including architecture, microarchitecture, thermal properties, power consumption characteristics, etc., there can be various differences between physical resources 3410 and 34155.

[0381] In one embodiment, processor 3410 executes instructions that control general-type data processing operations. Embedded within these instructions may be coprocessor instructions. Processor 3410 identifies these coprocessor instructions as types that should be executed by an attached coprocessor 3445. Therefore, processor 3410 sends these coprocessor instructions (or control signals representing coprocessor instructions) to coprocessor 3445 on a coprocessor bus or other interconnect. One or more coprocessors 3445 receive and execute the received coprocessor instructions.

[0382] Now for reference Figure 35 A block diagram of a first, more specific, exemplary system 3500 according to an embodiment of the present invention is shown. Figure 35 As shown, the multiprocessor system 3500 is a point-to-point interconnect system and includes a first processor 3570 and a second processor 3580 coupled via a point-to-point interconnect 3550. Each of processors 3570 and 3580 may be a version of processor 3300. In one embodiment of the invention, processors 3570 and 3580 are processors 3410 and 3432, respectively, and coprocessor 3538 is coprocessor 3445. In another embodiment, processors 3570 and 3580 are processor 3410 and coprocessor 3445, respectively.

[0383] Processors 3570 and 3580 are shown as including integrated memory controller (IMC) units 3572 and 3582, respectively. Processor 3570 also includes point-to-point (PP) interfaces 3576 and 3578 as part of its bus controller unit; similarly, the second processor 3580 includes PP interfaces 3586 and 3588. Processors 3570 and 3580 can exchange information via point-to-point (PP) interface 3550 using PP interface circuits 3578 and 3588. Figure 35 As shown, IMC3572 and 3582 couple the processor to the corresponding memory, namely memory 3532 and memory 3534, which may be portions of the main memory locally attached to the corresponding processor.

[0384] Processors 3570 and 3580 can exchange information with chipset 3590 via point-to-point interface circuits 3576, 3594, 3586, and 3598 through separate PP interfaces 3552 and 3554. Chipset 3590 can optionally exchange information with coprocessor 3538 via high-performance interface 3592. In one embodiment, coprocessor 3538 is a dedicated processor, such as, for example, a high-throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, etc.

[0385] A shared cache (not shown) may be included in either processor or outside of both processors, or connected to the processors via a PP interconnect, such that if the processors are put into a low-power mode, the local cache information of either or both processors may be stored in the shared cache.

[0386] Chipset 3590 can be coupled to first bus 3516 via interface 3596. In one embodiment, first bus 3516 may be a peripheral component interconnect (PCI) bus, or a bus such as PCI fast bus or another I / O interconnect bus, but the scope of the invention is not limited thereto.

[0387] like Figure 35As shown, various I / O devices 3514 can be coupled to a first bus 3516 and a bus bridge 3518, which couples the first bus 3516 to a second bus 3520. In one embodiment, one or more additional processors 3515, such as a coprocessor, a high-throughput MIC processor, a GPGPU, an accelerator (such as, for example, a graphics accelerator or digital signal processing (DSP) unit), a field-programmable gate array, or any other processor, are coupled to the first bus 3533. In one embodiment, the second bus 3520 may be a low pin count (LPC) bus. Various devices can be coupled to the second bus 3520, including, for example, a keyboard and / or mouse 3522, a communication device 3527, and a storage unit 3528, such as a disk drive or other mass storage device, which in one embodiment may include instruction / code and / or data 3530. Furthermore, audio I / O 3524 can be coupled to the second bus 3516. Note that other architectures are also possible. For example, as Figure 35 As a replacement for point-to-point architecture, the system can implement multi-point bus or other similar architectures.

[0388] Now for reference Figure 36 The diagram shows a block diagram of a second, more specific, exemplary system 3600 according to an embodiment of the present invention. Figure 35 and 36 Similar elements in the figures have similar reference numerals, and from Figure 36 The middle part is omitted Figure 35 certain aspects in order to avoid ambiguity Figure 36 Other aspects.

[0389] Figure 36 The diagram shows that processors 3570 and 3580 may include integrated memory and I / O control logic (“CL”) 3672 and 3682, respectively. Therefore, CL 3672 and 3682 include an integrated memory controller unit and I / O control logic. Figure 36 The diagram shows that not only are memories 3532 and 3534 coupled to CL3572 and 3582, but I / O device 3614 is also coupled to control logic 3572 and 3582. Legacy I / O device 3615 is coupled to chipset 3590.

[0390] Now for reference Figure 37 A block diagram of a SoC 3700 according to an embodiment of the present invention is shown. Figure 33 Similar components in the diagram have similar reference numerals. Furthermore, the dashed box is an optional feature on more advanced SoCs. Figure 37In this embodiment, one or more interconnect units 3702 are coupled to: an application processor 3710, which includes a set of one or more cores 372A-N, cache units 3304A-N, and one or more shared cache units 3306; a system proxy unit 3310; one or more bus controller units 3316; one or more integrated memory controller units 3314; a set of one or more coprocessors 3720, which may include integrated graphics logic, an image processor, an audio processor, and a video processor; a static random access memory (SRAM) unit 3730; a direct memory access (DMA) unit 3732; and a display unit 3740 for coupling to one or more external displays. In one embodiment, the one or more coprocessors 3720 are dedicated processors, such as, for example, network or communication processors, compression engines, GPGPUs, high-throughput MIC processors, embedded processors, and so on.

[0391] Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementations. Embodiments of the invention may be implemented as computer programs or program code that execute on a programmable system comprising at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0392] Applications such as Figure 35 The program code, such as code 3530 shown in the figure, is used to input instructions to perform the functions described herein and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, the processing system includes any system having a processor, such as, for example, a digital signal processor (DSP), a microcontroller, an application-specific integrated circuit (ASIC), or a microprocessor.

[0393] The program code can be implemented in a high-level programming language or an object-oriented programming language to communicate with the processing system. If desired, it can also be implemented in assembly language or machine language. In fact, the mechanisms described in this paper are not limited to any particular programming language. In any case, the language can be a compiled language or an interpreted language.

[0394] One or more aspects of at least one embodiment can be implemented by representative instructions representing various logics within a processor, stored on a machine-readable medium, which, when read by a machine, cause the machine to manufacture logic to implement the techniques described herein. Such a representation, known as an "IP core," can be stored on a tangible machine-readable medium and supplied to various customers or manufacturing facilities for loading into manufacturing machines that actually manufacture the logic or processor.

[0395] Such machine-readable storage media may include, without limitation, arrangements of non-transitory tangible articles made or formed by a machine or device, including storage media such as hard disks, any other type of disk (including floppy disks, optical disks, compact disk read-only memory (CD-ROM), compact disk rewritable device (CD-RW), and magneto-optical disks), semiconductor devices (such as read-only memory (ROM), random access memory (RAM) (such as dynamic random access memory (DRAM), static random access memory (SRAM)), erasable programmable read-only memory (EPROM), flash memory, electrically erasable programmable read-only memory (EEPROM), phase-change memory (PCM)), magnetic cards or optical cards, or any other type of media suitable for storing electronic instructions.

[0396] Accordingly, embodiments of the invention also include a non-transitory tangible machine-readable medium containing instructions or design data (such as a hardware description language (HDL)) that defines the architectures, circuits, devices, processors, and / or system features described herein. Such embodiments may also be referred to as program products.

[0397] Simulation (including binary translation, code transformation, etc.)

[0398] In some cases, an instruction translator can be used to translate instructions from a source instruction set into a target instruction set. For example, an instruction translator can translate (e.g., using static binary translation, including dynamic binary translation with dynamic compilation), transform, emulate, or otherwise translate instructions into one or more other instructions to be processed by the kernel. Instruction translators can be implemented in software, hardware, firmware, or a combination thereof. Instruction translators can be on-processor, off-processor, or partially on-processor and partially off-processor.

[0399] Figure 38 This is a block diagram illustrating the use of a software instruction converter to convert binary instructions in a source instruction set into binary instructions in a target instruction set, according to an embodiment of the present invention. In the illustrated embodiment, the instruction converter is a software instruction converter; however, alternatively, the instruction converter may be implemented in software, firmware, hardware, and various combinations thereof. Figure 38A program in the form of a high-level language 3802 can be compiled using a first compiler 3804 to generate first binary code (e.g., x86) 3806, which can be natively executed by a processor 3816 having at least one first instruction set core. In some embodiments, a processor 3816 having at least one first instruction set core represents any processor that can substantially perform the same function as an Intel processor having at least one x86 instruction set core by mutually compatiblely executing or otherwise processing the following: (1) a substantial portion of the instruction set of an Intel x86 instruction set core or (2) a version of object code for an application or other software targeted to run on an Intel processor having at least one x86 instruction set core in order to substantially achieve the same result as an Intel processor having at least one x86 instruction set core. The first compiler 3804 represents a compiler operable to generate binary code 3806 (e.g., object code) of the first instruction set, which can be executed on a processor 3816 having at least one first instruction set core with or without additional linking processing. Similarly, Figure 38 A program in the form of a high-level language 3802 is shown to be compiled using a substitution instruction set compiler 3808 to generate substitution instruction set binary code 3810, which can be natively executed by a processor that does not have at least one first instruction set core 3814 (e.g., a processor with a core that executes the MIPS instruction set of MIPS Technologies, Sunnyvale, California, and / or the ARM instruction set of ARM Holdings, Sunnyvale, California). An instruction converter 3812 is used to translate the first binary code 3806 into code that can be natively executed by a processor 3814 that does not have a first instruction set core. This translated code is likely not identical to the substitution instruction set binary code 3810, as instruction converters capable of doing so are difficult to manufacture; however, the translated code will perform general operations and consist of instructions from the substitution instruction set. Therefore, the instruction converter 3812 represents software, firmware, hardware, or a combination thereof that allows a processor or other electronic device without a first instruction set processor or core to execute the first binary code 3806 through emulation, simulation, or any other process.

[0400] Other examples

[0401] Example 1 provides a method for executing vector instructions, the method comprising: extracting the vector instructions from a code storage device by an extraction circuit, the vector instructions including an opcode, a destination identifier for specifying a packing destination register, a first immediate value and a second immediate value; decoding the extracted vector instructions by a decoding circuit; and executing the decoded vector instructions by an execution circuit to: broadcast the first immediate value to each vector element in the packing destination register when the opcode specifies broadcasting, and storing the first immediate value in the first vector element in the packing destination register when the opcode specifies stepping, and successively generating and storing the value of the immediately preceding vector element plus the second immediate value for each subsequent vector element in the packing destination register.

[0402] Example 2 includes the substance of the exemplary method described in Example 1, wherein, when the operand specifies to step, the values ​​written by the execution circuit to successive vector elements differ by a second immediate value.

[0403] Example 3 includes the substance of the exemplary method described in Example 2, wherein the vector instruction further includes a write mask identifier to select a vector write mask register comprising a plurality of one-bit vector write mask elements, each of the plurality of one-bit vector write mask elements controlling whether to write the execution result to a corresponding vector element in the packing destination register, the corresponding vector element occupying the same relative position in the packing destination register as the relative position occupied by the vector write mask element in the write mask register, wherein the execution result is to be written only to the unmasked vector elements in the packing destination register.

[0404] Example 4 includes the substance of the exemplary method described in Example 3, wherein executing the vector instruction further includes zeroing the masked vector elements in the packing destination register.

[0405] Example 5 includes the substance of the exemplary method described in Example 3, wherein executing the vector instruction further includes not writing the new value to the masked vector element in the packing destination register.

[0406] Example 6 includes the substance of the exemplary method described in Example 3, wherein the vector instruction further includes a masking element control field to specify whether the masked vector element in the packing destination register should retain its value or be zeroed out.

[0407] Example 7 includes the substance of the exemplary method described in Example 6, wherein the masking element control field is to be derived from the operation code.

[0408] Example 8 includes the substance of the exemplary method described in any of Examples 1-7, wherein the vector instruction further includes an element size identifier to specify the size of the vector element in the packing destination register.

[0409] Example 9 includes the substance of the exemplary method described in Example 8, wherein the element size identifier is included in the operation code.

[0410] Example 10 includes the substance of the exemplary method described in Example 1, wherein the packing destination register includes one of the following: a 128-bit vector register, a 256-bit vector register, and a 512-bit vector register, and the packing destination register includes a plurality of fixed-size vector elements.

[0411] Example 11 provides a processor for executing vector instructions, the processor comprising: extraction circuitry for extracting the vector instructions from a code storage device, the vector instructions including an opcode, a destination identifier for specifying a pack destination register, a first immediate value, and a second immediate value; decoding circuitry for decoding the extracted vector instructions; and execution circuitry for executing the decoded vector instructions to: broadcast the first immediate value to each vector element in the pack destination register when the opcode specifies broadcasting, and store the first immediate value in the first vector element in the pack destination register when the opcode specifies stepping, and successively generate and store the value of the immediately preceding vector element plus the second immediate value for each subsequent vector element in the pack destination register.

[0412] Example 12 includes the substance of the exemplary processor described in Example 11, wherein, when the operand specifies a step, the values ​​of successive vector elements written by the execution circuitry into the packing destination register differ from the value of a second immediate value.

[0413] Example 13 includes the substance of the exemplary processor described in Example 12, wherein the vector instruction further includes a write mask identifier to select a vector write mask register comprising a plurality of one-bit vector write mask elements, each of the plurality of one-bit vector write mask elements controlling whether to write the execution result to a corresponding vector element in the packing destination register, the corresponding vector element occupying the same relative position in the packing destination register as the relative position occupied by the vector write mask element in the write mask register, wherein the execution result is to be written only to the unmasked vector elements in the packing destination register.

[0414] Example 14 includes the substance of the exemplary processor described in Example 13, wherein executing the vector instruction further includes zeroing the masked vector elements in the packing destination register.

[0415] Example 15 includes the substance of the exemplary processor described in Example 13, wherein executing the vector instruction further includes not writing new values ​​to the masked vector elements in the packing destination register.

[0416] Example 16 includes the substance of the exemplary processor described in Example 13, wherein the vector instruction further includes a masking element control field to specify whether to retain the value of the masked vector element in the packing destination register or to zero it out.

[0417] Example 17 includes the substance of the exemplary processor described in Example 16, wherein the masking element control field is to be derived from the operation code.

[0418] Example 18 includes the substance of the exemplary processor described in any of Examples 11-17, wherein the vector instruction further includes an element size identifier to specify the size of the vector element in the packing destination register.

[0419] Example 19 includes the substance of the exemplary processor described in Example 18, wherein the element size identifier is one of the prefix and suffix of the operand code.

[0420] Example 20 includes the substance of the exemplary processor described in Example 11, wherein the packing destination register includes one of the following: a 128-bit vector register, a 256-bit vector register, and a 512-bit vector register, the packing destination register including a plurality of fixed-size vector elements.

[0421] Example 21 provides a system for executing vector instructions, the system comprising: a memory, and a processor, the processor comprising: fetching circuitry for fetching the vector instructions from a code storage device, the vector instructions including an opcode, a destination identifier for specifying a pack destination register, a first immediate value, and a second immediate value; decoding circuitry for decoding the fetched vector instructions; and execution circuitry for executing the decoded vector instructions to: broadcast the first immediate value to each vector element in the pack destination register when the opcode specifies broadcasting, and store the first immediate value in the first vector element in the pack destination register when the opcode specifies stepping, and for each subsequent vector element in the pack destination register, successively generate and store the value of the immediately preceding vector element plus the second immediate value.

[0422] Example 22 includes the substance of the exemplary system described in Example 21, wherein, when the operand specifies to step, after the execution, the values ​​of successive vector elements written by the execution circuit differ by a second immediate value.

[0423] Example 23 includes the substance of the exemplary system described in Example 22, wherein the vector instruction further includes a write mask identifier to select a vector write mask register comprising a plurality of one-bit vector write mask elements, each of the plurality of one-bit vector write mask elements controlling whether to write the execution result to a corresponding vector element in the packing destination register, the corresponding vector element occupying the same relative position in the packing destination register as the relative position occupied by the vector write mask element in the write mask register, wherein the execution result is to be written only to the unmasked vector elements in the packing destination register.

[0424] Example 24 includes the substance of the exemplary system described in Example 23, wherein executing the vector instruction further includes zeroing the masked vector element in the packing destination register.

[0425] Example 25 includes the substance of the exemplary system described in Example 23, wherein executing the vector instruction further includes not writing new values ​​to the masked vector elements in the packing destination register.

[0426] Example 26 includes the substance of the exemplary system described in Example 23, wherein the vector instruction further includes a masking element control field to specify whether the masked vector element in the packing destination register should retain its value or be zeroed out.

[0427] Example 27 includes the substance of the exemplary system described in Example 26, wherein the masking element control field is to be derived from the operation code.

[0428] Example 28 includes the substance of the exemplary system described in any of Examples 21-27, wherein the vector instruction further includes an element size identifier to specify the size of the vector element in the packing destination register.

[0429] Example 29 includes the substance of the exemplary system described in Example 28, wherein the element size identifier is one of the prefix and suffix of the operand.

[0430] Example 30 includes the substance of the exemplary system described in Example 21, wherein the packing destination register includes one of the following: a 128-bit vector register, a 256-bit vector register, and a 512-bit vector register, and the packing destination register includes a plurality of fixed-size vector elements.

[0431] Example 31 provides a method for executing vector instructions, the method comprising: extracting the vector instructions from a code storage device by an extraction circuit, the vector instructions including an operand, a destination identifier for specifying a pack destination register, a write mask identifier for specifying a write mask register, and first and second immediate values; decoding the extracted vector instructions by a decoding circuit; and executing the decoded vector instructions by an execution circuit to: derive a data value using the first immediate value; derive a stride value using the second immediate value; identify unmasked pack destination register elements using the write mask register; broadcast the data value to each unmasked pack destination register element when the operand specifies broadcasting; store the data value in the first unmasked pack destination register element when the operand specifies stride; and for each subsequent unmasked pack destination register element, sequentially generating and storing the value of the immediately preceding unmasked pack destination register element plus the stride value.

[0432] Example 32 includes the substance of the exemplary method described in Example 31, wherein the vector instruction further includes a source identifier to specify a source vector register, and wherein deriving the broadcast data value includes one of: using a first immediate value as the broadcast data value, and using the first immediate value to select a vector element within the source vector register and using the selected source vector register element as the broadcast data value.

[0433] Example 33 includes the substance of the exemplary method described in Example 31, wherein the vector instruction further includes a source identifier to specify a source vector register, and wherein deriving the straddle data value includes one of: using a second immediate value as the straddle data value, and using the second immediate value to select a vector element within the source vector register and using the selected source vector register element as the straddle data value.

[0434] Example 34 includes the substance of the exemplary method described in Example 31, wherein the write mask register includes a plurality of one-bit vector write mask elements, each of the plurality of one-bit vector write mask elements controlling whether to write the execution result to a corresponding vector element in the packing destination register, the corresponding vector element occupying the same relative position in the packing destination register as the relative position occupied by the vector write mask element in the write mask register, wherein the execution result is written only to the unmasked vector elements in the packing destination register.

[0435] Example 35 includes the substance of the exemplary method described in Example 34, wherein executing the vector instruction further includes zeroing the masked vector elements in the packing destination register.

[0436] Example 36 includes the substance of the exemplary method described in Example 34, wherein executing the vector instruction further includes not writing the new value to the masked vector element in the packing destination register.

[0437] Example 37 includes the substance of the exemplary method described in Example 33, wherein the vector instruction further includes a masking element control field to specify whether the masked vector element in the packing destination register should retain its value or be zeroed out.

[0438] Example 38 includes the substance of the exemplary method described in Example 37, wherein the masking element control field is to be derived from the operation code.

[0439] Example 39 includes the substance of the exemplary method described in Example 38, wherein the masking element control field is one of the suffix and prefix of the operation code.

[0440] Example 40 includes the substance of the exemplary method described in any of Examples 31-39, wherein the vector instruction further includes an element size identifier to specify the size of the vector element in the packing destination register.

[0441] Example 41 provides a processor for executing vector instructions, the processor comprising: extraction circuitry for extracting the vector instructions from a code storage device, the vector instructions including an opcode, a destination identifier for specifying a packing destination register, a write mask identifier for specifying a write mask register, and first and second immediate values; decoding circuitry for decoding the extracted vector instructions; and execution circuitry for executing the decoded vector instructions to: derive a data value using the first immediate value, derive a step value using the second immediate value, and identify an unmasked destination vector register using the write mask register.

[0442] Example 42 includes the substance of the exemplary processor described in Example 41, wherein the vector instruction further includes a source identifier to specify a source vector register, and wherein deriving the broadcast data value includes one of: using a first immediate value as the broadcast data value, and using the first immediate value to select a vector element within the source vector register and using the selected source vector register element as the broadcast data value.

[0443] Example 43 includes the substance of the exemplary processor described in Example 41, wherein the vector instruction further includes a source identifier to specify a source vector register, and wherein deriving the straddle data value includes one of: using a second immediate value as the straddle data value, and using the second immediate value to select a vector element within the source vector register and using the selected source vector register element as the straddle data value.

[0444] Example 44 includes the substance of the exemplary processor described in Example 41, wherein the write mask register includes a plurality of one-bit vector write mask elements, each of the plurality of one-bit vector write mask elements controlling whether to write the execution result to a corresponding vector element in the destination vector register, the corresponding vector element occupying the same relative position in the destination vector register as the relative position occupied by the vector write mask element in the write mask register, wherein the execution result is written only to the unmasked vector element in the destination vector register.

[0445] Example 45 includes the substance of the exemplary processor described in Example 44, wherein executing the vector instruction further includes zeroing the masked vector elements in the destination vector register.

[0446] Example 46 includes the substance of the exemplary processor described in Example 44, wherein executing the vector instruction further includes masking the vector element without writing a new value to the destination vector register.

[0447] Example 47 includes the substance of the exemplary processor described in Example 43, wherein the vector instruction further includes a masking element control field to specify whether to retain the value of the masked vector element in the destination vector register or to zero it.

[0448] Example 48 includes the substance of the exemplary processor described in Example 47, wherein the masking element control field is to be derived from the operation code.

[0449] Example 49 includes the substance of the exemplary processor described in Example 48, wherein the masking element control field is one of the prefix and suffix of the operation code.

[0450] Example 50 includes the substance of the exemplary processor described in any of Examples 41-49, wherein the vector instruction further includes an element size identifier to specify the size of the vector element in the destination vector register.

[0451] Example 51 provides a system for executing vector instructions, the system including: a memory, and a processor including: fetching circuitry for fetching the vector instructions from a code storage device, the vector instructions including an opcode, a destination identifier for specifying a destination vector register, a write mask identifier for specifying a write mask register, and first and second immediate values; decoding circuitry for decoding the fetched vector instructions; and execution circuitry for executing the decoded vector instructions to: derive a broadcast data value using the first immediate value, derive a stride value using the second immediate value, identify unmasked destination vector register elements using the write mask register, broadcast the broadcast data value to each unmasked destination vector register element when the opcode specifies broadcasting, store the broadcast data value in the first unmasked destination vector register element when the opcode specifies stride, and for each subsequent unmasked destination vector register element, successively generate and store the value of the immediately preceding unmasked destination vector register element plus the stride value.

[0452] Example 52 includes the substance of the exemplary system described in Example 51, wherein the vector instruction further includes a source identifier to specify a source vector register, and wherein deriving the broadcast data value includes one of: using a first immediate value as the broadcast data value, and using the first immediate value to select a vector element within the source vector register and using the selected source vector register element as the broadcast data value.

[0453] Example 53 includes the substance of the exemplary system described in Example 51, wherein the vector instruction further includes a source identifier to specify a source vector register, and wherein deriving the straddle data value includes one of: using a second immediate value as the straddle data value, and using the second immediate value to select a vector element within the source vector register and using the selected source vector register element as the straddle data value.

[0454] Example 54 includes the substance of the exemplary system described in Example 51, wherein the write mask register includes a plurality of one-bit vector write mask elements, each of which controls whether to write the execution result to a corresponding vector element in the destination vector register, the corresponding vector element occupying the same relative position in the destination vector register as the relative position occupied by the vector write mask element in the write mask register, wherein the execution result is written only to the unmasked vector elements in the destination vector register.

[0455] Example 55 includes the substance of the exemplary system described in Example 54, wherein executing the vector instruction further includes zeroing the masked vector element in the destination vector register.

[0456] Example 56 includes the substance of the exemplary system described in Example 54, wherein executing the vector instruction further includes not writing the new value to the masked vector element in the destination vector register.

[0457] Example 57 includes the substance of the exemplary system described in Example 53, wherein the vector instruction further includes a masking element control field to specify whether the masked vector element in the destination vector register should retain its value or be zeroed out.

[0458] Example 58 includes the substance of the exemplary system described in Example 57, wherein the masking element control field is to be derived from the operation code.

[0459] Example 59 includes the substance of the exemplary system described in Example 58, wherein the masking element control field is one of the prefix and suffix of the operation code.

[0460] Example 60 includes the substance of the exemplary system described in any of Examples 51-59, wherein the vector instruction further includes an element size identifier to specify the size of the vector element in the destination vector register.

[0461] Example 61 provides a processor for executing vector instructions, the processor comprising: extraction circuitry for extracting the vector instructions from a code storage device, the vector instructions including an operand code, a source identifier for specifying a source write mask register, a destination identifier for specifying a destination write mask register, a write mask identifier for specifying a write mask register, an element size identifier for specifying a destination vector element size, and an immediate value; decoding circuitry for decoding the extracted vector instructions; and execution circuitry for executing the decoded vector instructions to: identify one or more equal partitions of the destination write mask register using the element size identifier, perform an operation on the source write mask register and the immediate value to generate a result, determine which of the equal partitions is unmasked using the write mask register, and write the result to each of the unmasked equal partitions.

[0462] Example 62 includes the substance of the exemplary processor described in Example 61, wherein the source identifier and the destination identifier identify the same write mask register.

[0463] Example 63 includes the substance of the exemplary processor described in any of Examples 61 and 62, wherein the vector instruction further includes a second source identifier to specify a second source write mask register, and wherein the execution circuitry performs operations on the source write mask register, the second source write mask generator, and the immediate value to generate the result.

[0464] Example 64 includes the substance of the exemplary processor described in Example 61, wherein the write mask register includes a plurality of one-bit vector write mask elements, each of the plurality of one-bit vector write mask elements controlling whether to write the execution result to a corresponding one of the one or more partitions in the destination write mask register, wherein each of the plurality of one-bit vector write mask elements occupies the same relative position in the write mask register as the relative position occupied by the one partition in the destination vector register.

[0465] Example 65 includes the substance of the exemplary processor described in Example 64, wherein executing the vector instruction further includes zeroing the masked vector elements in the destination write mask register.

[0466] Example 66 includes the substance of the exemplary processor described in Example 64, wherein executing the vector instruction further includes not writing the new value to the masked vector element in the destination write mask register.

[0467] Example 67 includes the substance of the exemplary processor described in Example 64, wherein the vector instruction further includes a masking element control field to specify whether to retain the value of the masked vector element in the destination vector register or to zero it.

[0468] Example 68 includes the substance of the exemplary processor described in Example 61, wherein the element size identifier is included in the operation code.

[0469] Example 69 includes the substance of the exemplary processor described in Example 61, wherein the operation that generates the result using the source write mask register and the immediate value is a bitwise binary operation, which is one of AND, OR, XOR, left shift, and right shift.

[0470] Example 70 includes the substance of the exemplary processor described in any one of Examples 61, 62 and 64-49, wherein the vector instruction further includes a second destination identifier to specify a general-purpose register, and wherein the execution circuitry further intends to copy the result from one of the unmasked equal partitions in the destination write mask register to the general-purpose register.

[0471] Example 71 provides a method for executing vector instructions, the method comprising: extracting the vector instructions from a code storage device by extraction circuitry, the vector instructions including an operand code, a source identifier for specifying a source write mask register, a destination identifier for specifying a destination write mask register, a write mask identifier for specifying a write mask register, an element size identifier for specifying a destination vector element size, and an immediate value; decoding the extracted vector instructions by decoding circuitry; and executing the decoded vector instructions by execution circuitry to: identify one or more equal partitions of the destination write mask register using the element size identifier; perform operations on the source write mask register and the immediate value to generate a result; determine which of the equal partitions is unmasked using the write mask register; and write the result to each of the unmasked equal partitions.

[0472] Example 72 includes the substance of the exemplary method described in Example 71, wherein the source identifier and the destination identifier identify the same write mask register.

[0473] Example 73 includes the substance of the exemplary method described in any of Examples 71 and 72, wherein the vector instruction further includes a second source identifier to specify a second source write mask register, and wherein the execution circuitry performs operations on the source write mask register, the second source write mask generator, and the immediate value to generate the result.

[0474] Example 74 includes the substance of the exemplary method described in Example 71, wherein the write mask register includes a plurality of one-bit vector write mask elements, each of the plurality of one-bit vector write mask elements controlling whether to write the execution result to a corresponding one of the one or more partitions in the destination write mask register, wherein each of the plurality of one-bit vector write mask elements occupies the same relative position in the write mask register as the relative position occupied by the one partition in the destination vector register.

[0475] Example 75 includes the substance of the exemplary method described in Example 74, wherein executing the vector instruction further includes zeroing the masked vector elements in the destination write mask register.

[0476] Example 76 includes the substance of the exemplary method described in Example 74, wherein executing the vector instruction further includes not writing the new value to the masked vector element in the destination write mask register.

[0477] Example 77 includes the substance of the exemplary method described in Example 74, wherein the vector instruction further includes a masking element control field to specify whether to retain the value of the masked vector element in the destination vector register or to zero it.

[0478] Example 78 includes the substance of the exemplary method described in Example 71, wherein the element size identifier is included in the operation code.

[0479] Example 79 includes the substance of the exemplary method described in Example 71, wherein the operation of generating the result using the source write mask register and the immediate value is a bitwise binary operation, which is one of AND, OR, XOR, left shift, and right shift.

[0480] Example 80 includes the substance of the exemplary method described in any one of Examples 71, 72 and 74-79, wherein the vector instruction further includes a second destination identifier to specify a general-purpose register, and wherein the execution circuitry further intends to copy the result from one of the unmasked equal partitions in the destination write mask register to the general-purpose register.

[0481] Example 81 provides a system for executing vector instructions, the system including: a memory, and a processor, the processor including: fetching circuitry for fetching the vector instructions from a code storage device, the vector instructions including an opcode, a source identifier for specifying a source write mask register, a destination identifier for specifying a destination write mask register, a write mask identifier for specifying a write mask register, an element size identifier for specifying a destination vector element size, and an immediate value; decoding circuitry for decoding the fetched vector instructions; and execution circuitry for executing the decoded vector instructions to: identify one or more equal partitions of the destination write mask register using the element size identifier, perform an operation on the source write mask register and the immediate value to generate a result, use the write mask register to determine which of the equal partitions is unmasked, and write the result to each of the unmasked equal partitions.

[0482] Example 82 includes the substance of the exemplary system described in Example 81, wherein the source identifier and the destination identifier identify the same write mask register.

[0483] Example 83 includes the substance of the exemplary system described in any of Examples 81 and 82, wherein the vector instruction further includes a second source identifier to specify a second source write mask register, and wherein the execution circuitry performs operations on the source write mask register, the second source write mask generator, and the immediate value to generate the result.

[0484] Example 84 includes the substance of the exemplary system described in Example 81, wherein the write mask register includes a plurality of one-bit vector write mask elements, each of the plurality of one-bit vector write mask elements controlling whether to write the execution result to a corresponding one of the one or more partitions in the destination write mask register, wherein each of the plurality of one-bit vector write mask elements occupies the same relative position in the write mask register as the relative position occupied by the one partition in the destination vector register.

[0485] Example 85 includes the substance of the exemplary system described in Example 84, wherein executing the vector instruction further includes zeroing the masked vector element in the destination write mask register.

[0486] Example 86 includes the substance of the exemplary system described in Example 84, wherein executing the vector instruction further includes not writing the new value to the masked vector element in the destination write mask register.

[0487] Example 87 includes the substance of the exemplary system described in Example 84, wherein the vector instruction further includes a masking element control field to specify whether to retain the value of the masked vector element in the destination vector register or to zero it.

[0488] Example 88 includes the substance of the exemplary system described in Example 81, wherein the element size identifier is included in the operation code.

[0489] Example 89 includes the substance of the exemplary system described in Example 81, wherein the operation that generates the result using the source write mask register and the immediate value is a bitwise binary operation, which is one of AND, OR, XOR, left shift, and right shift.

[0490] Example 90 includes the substance of the exemplary system described in Example 81, wherein the vector instruction further includes a second destination identifier to specify a general-purpose register, and wherein the execution circuitry further intends to copy the result from one of the unmasked equal partitions in the destination write mask register to the general-purpose register.

[0491] Example 91 provides a processor for executing vector instructions, the processor comprising: extraction circuitry for extracting the vector instructions from a code storage device, the vector instructions including an operand code, a destination identifier, and an immediate value; decoding circuitry for decoding the extracted vector instructions; and execution circuitry for executing the decoded vector instructions, wherein, in response to the decoded vector instructions, the execution circuitry generates a result to be written to each element of a stored destination vector specified by the destination identifier, the result being based on the immediate value.

[0492] Example 92 includes the substance of the exemplary processor described in Example 91, wherein the stored destination vector includes a destination vector register, wherein the vector instruction further includes a source identifier to identify the source vector register, and wherein, in response to the decoded vector instruction, the execution circuitry uses the immediate value to select an element in the source vector register and broadcast the selected element to a plurality of elements in the destination vector register.

[0493] Example 93 includes the substance of the exemplary processor described in Example 91, wherein the stored destination vector includes a destination vector register, and wherein, in response to a decoded vector instruction, the execution circuitry broadcasts the immediate value to each vector element in the destination vector register.

[0494] Example 94 includes the substance of the exemplary processor described in Example 91, wherein the stored destination vector includes a destination vector register, wherein the vector instruction further includes a source identifier to identify the source register, wherein the immediate value represents a stride value, and wherein, in response to the decoded vector instruction, the execution circuitry sets the first element in the destination vector register to the value stored in the source register, and sets each subsequent element in the destination vector register to the value of the immediately preceding element in the destination vector register plus the stride value.

[0495] Example 95 includes the substance of the exemplary processor described in Example 91, wherein the stored destination vector includes a destination vector register, wherein the vector instruction further includes a second immediate value and a source identifier for identifying the source vector register, wherein the second immediate value represents a stride value, and wherein, in response to the decoded vector instruction, the execution circuitry uses the immediate value to select an element in the source vector register, sets the first element in the destination vector register to the value stored in the selected source vector register element, and sets each subsequent element in the destination vector register to the value of the immediately preceding element in the destination vector register plus the stride value.

[0496] Example 96 includes the substance of the exemplary processor described in Example 91, wherein the stored destination vector includes a destination vector register, wherein the vector instruction further includes a second immediate value, wherein the second immediate value represents a stride value, and wherein, in response to the decoded vector instruction, the execution circuitry sets the first element in the destination vector register to the value of the immediate value, and sets each subsequent element in the destination vector register to the value of the immediately preceding element in the destination vector register plus the stride value.

[0497] Example 97 includes the substance of the exemplary processor described in Example 91, wherein the stored destination vector includes a destination vector register, wherein the vector instruction further includes a first source identifier for identifying a first source vector register and a second source identifier for identifying a second source vector register, and wherein, in response to the decoded vector instruction, the execution circuitry sets each element in the destination vector register to the value of the corresponding element in the first source vector register plus the value of the corresponding element in the second source vector register plus the immediate value.

[0498] Example 98 includes the substance of the exemplary processor described in Example 91, wherein the stored destination vector includes a destination vector register, wherein the vector instruction further includes a write mask identifier to identify the write mask register, wherein the immediate value is a short immediate value, and wherein, in response to the decoded vector instruction, the execution circuitry uses the write mask register to set each unmasked element in the destination vector register to the immediate value.

[0499] Example 99 includes the substance of the exemplary processor described in Example 92, wherein the vector instruction further includes a size identifier to specify the element size of each element in the destination vector register, and wherein, in response to the decoded vector instruction, the execution circuitry uses the element size identifier to determine how many elements in the destination vector register to be set.

[0500] Example 100 includes the substance of the exemplary processor described in Example 91, wherein the stored destination vector includes a destination mask register, wherein the vector instruction further includes a write mask identifier to specify the write mask register, and wherein, in response to the decoded vector instruction, the execution circuitry uses the write mask register to set the unmasked elements in the destination mask register to one and to set the masked elements in the destination mask register to zero, without using the immediate value.

[0501] Example 101 provides a non-transitory computer-readable medium containing instructions that, when executed by a processor, cause the processor to, in response to vector instructions,: extract vector instructions from a code storage device by extraction circuitry, the vector instructions including an operand, a destination identifier, and an immediate value; decode the extracted vector instructions by decoding circuitry; and execute the decoded vector instructions by execution circuitry, wherein, in response to the decoded vector instructions, the execution circuitry generates a result to be written to each element of a stored destination vector specified by the destination identifier, the result being based on the immediate value.

[0502] Example 102 includes the substantive content of the exemplary non-transitory computer-readable medium described in Example 101, wherein the stored destination vector includes a destination vector register, wherein the vector instruction further includes a source identifier to identify the source vector register, and wherein the execution by the execution circuitry in response to the decoded vector instruction includes using the immediate value to select an element in the source vector register and broadcasting the selected element to a plurality of elements in the destination vector register.

[0503] Example 103 includes the substantive content of the exemplary non-transitory computer-readable medium described in Example 101, wherein the stored destination vector includes a destination vector register, and wherein the execution by the execution circuitry in response to the decoded vector instruction includes broadcasting the immediate value to each vector element in the destination vector register.

[0504] Example 104 includes the substantive content of the exemplary non-transitory computer-readable medium of Example 101, wherein the stored destination vector includes a destination vector register, wherein the vector instruction further includes a source identifier to identify the source register, wherein the immediate value represents a stride value, and wherein the execution by the execution circuitry in response to the decoded vector instruction includes setting the first element in the destination vector register to the value stored in the source register, and setting each subsequent element in the destination vector register to the value of the immediately preceding element in the destination vector register plus the stride value.

[0505] Example 105 includes the substantive content of the exemplary non-transitory computer-readable medium described in Example 101, wherein the stored destination vector includes a destination vector register, wherein the vector instruction further includes a second immediate value and a source identifier for identifying a source vector register, wherein the second immediate value represents a stride value, and wherein the execution by the execution circuitry in response to the decoded vector instruction includes using the immediate value to select an element in the source vector register, setting a first element in the destination vector register to the value of the selected source vector register element, and setting each subsequent element in the destination vector register to the value of the immediately preceding element in the destination vector register plus the stride value.

[0506] Example 106 provides an apparatus for executing vector instructions, the apparatus comprising: components for retrieving the vector instructions from a code storage device, the vector instructions including an operand, a destination identifier, and an immediate value; components for decoding the retrieved vector instructions; and components for executing the decoded vector instructions, wherein, in response to the decoded vector instructions, the execution components generate results to be written to each element of a stored destination vector specified by the destination identifier, the results being based on the immediate value.

[0507] Example 107 includes the substance of the exemplary apparatus described in Example 106, wherein the stored destination vector includes a destination vector register, wherein the vector instruction further includes a source identifier to identify the source vector register, and wherein the execution by the component for execution in response to the decoded vector instruction includes using the immediate value to select an element in the source vector register and broadcasting the selected element to a plurality of elements in the destination vector register.

[0508] Example 108 includes the substance of the exemplary apparatus described in Example 106, wherein the stored destination vector includes a destination vector register, and wherein the execution by the component for execution in response to the decoded vector instruction includes broadcasting the immediate value to each vector element in the destination vector register.

[0509] Example 109 includes the substance of the exemplary apparatus described in Example 106, wherein the stored destination vector includes a destination vector register, wherein the vector instruction further includes a source identifier to identify the source register, wherein the immediate value represents a stride value, and wherein the execution by the component for execution in response to the decoded vector instruction includes setting the first element in the destination vector register to the value stored in the source register, and setting each subsequent element in the destination vector register to the value of the immediately preceding element in the destination vector register plus the stride value.

[0510] Example 110 includes the substance of the exemplary apparatus described in Example 106, wherein the vector instruction further includes a second immediate value and a source identifier for identifying the source vector register, wherein the stored destination vector includes a destination vector register, wherein the second immediate value represents a stride value, and wherein the execution by the component for execution in response to the decoded vector instruction includes using the immediate value to select an element in the source vector register, setting a first element in the destination vector register to the value of the selected source vector register element, and setting each subsequent element in the destination vector register to the value of the immediately preceding element in the destination vector register plus the stride value.

[0511] Example 111 provides a system for executing vector instructions, the system comprising: a memory, and a processor, the processor comprising: fetching circuitry for fetching the vector instructions from a code storage device, the vector instructions including an operand code, a destination identifier, and an immediate value; decoding circuitry for decoding the fetched vector instructions; and execution circuitry for executing the decoded vector instructions, wherein, in response to the decoded vector instructions, the execution circuitry generates a result to be written to each element of a stored destination vector specified by the destination identifier, the result being based on the immediate value.

[0512] Example 112 includes the substance of the exemplary system described in Example 111, wherein the stored destination vector includes a destination vector register, wherein the vector instruction further includes a source identifier to identify the source vector register, and wherein, in response to the decoded vector instruction, the execution circuitry uses the immediate value to select an element in the source vector register and broadcast the selected element to a plurality of elements in the destination vector register.

[0513] Example 113 includes the substance of the exemplary system described in Example 111, wherein the vector instruction further includes a source identifier to identify a source register, wherein the immediate value represents a stride value, and wherein, in response to the decoded vector instruction, the execution circuitry sets the first element in the destination vector register to the value stored in the source register, and sets each subsequent element in the destination vector register to the value of the immediately preceding element in the destination vector register plus the stride value.

[0514] Example 114 includes the substance of the exemplary system described in Example 111, wherein the vector instruction further includes a second immediate value and a source identifier for identifying the source vector register, wherein the second immediate value represents a stride value, and wherein, in response to the decoded vector instruction, the execution circuitry uses the immediate value to select an element in the source vector register, sets a first element in the destination vector register to the value stored in the selected source vector register element, and sets each subsequent element in the destination vector register to the value of the immediately preceding element in the destination vector register plus the stride value.

[0515] Example 115 includes the substance of the exemplary system described in Example 111, wherein the vector instruction further includes a second immediate value, wherein the second immediate value represents a stride value, and wherein, in response to the decoded vector instruction, the execution circuitry sets the first element in the destination vector register to the value of the immediate value, and sets each subsequent element in the destination vector register to the value of the immediately preceding element in the destination vector register plus the stride value.

[0516] Example 116 includes the substance of the exemplary system described in Example 111, wherein the vector instruction further includes a first source identifier for identifying a first source vector register and a second source identifier for identifying a second source vector register, and wherein, in response to the decoded vector instruction, the execution circuitry sets each element in the destination vector register to the value of the corresponding element in the first source vector register plus the value of the corresponding element in the second source vector register plus the immediate value.

[0517] Example 117 includes the substance of the exemplary system described in Example 111, wherein the stored destination vector includes a destination vector register, wherein the vector instruction further includes a write mask identifier to identify the write mask register, wherein the immediate value is a short immediate value, and wherein, in response to the decoded vector instruction, the execution circuitry uses the write mask register to set each unmasked element in the destination vector register to the immediate value.

[0518] Example 118 includes the substance of the exemplary system described in Example 112, wherein the vector instruction further includes an element size identifier, and wherein, in response to the decoded vector instruction, the execution circuitry further uses the element size identifier to determine how many elements to set in the destination vector register.

[0519] Example 119 includes the substance of the exemplary system described in Example 111, wherein the stored destination vector includes a destination mask register, wherein the vector instruction further includes a write mask identifier to specify the write mask register, and wherein, in response to the decoded vector instruction, the execution circuitry uses the write mask register to set only the unmasked elements in the destination mask register, without using the immediate value.

[0520] Example 120 includes the substance of the exemplary system described in Example 119, wherein the execution by the execution circuit in response to the decoded vector instruction further includes setting the masked element in the destination mask register to zero.

[0521] Example 121 provides a non-transitory machine-readable medium containing instructions that, when executed by a processor, cause the processor to: extract vector instructions from a code storage device by extraction circuitry, the vector instructions including an opcode, a destination identifier for specifying a destination vector register, a write mask identifier for specifying a write mask register, and first and second immediate values; decode the extracted vector instructions by decoding circuitry; and execute the decoded vector instructions by execution circuitry to: derive a data value using the first immediate value; derive a stride value using the second immediate value; identify unmasked destination vector register elements using the write mask register; broadcast the data value to each unmasked destination vector register element when the opcode specifies broadcasting; store the data value in the first unmasked destination vector register element when the opcode specifies stride; and for each subsequent unmasked destination vector register element, successively generate and store the value of the immediately preceding unmasked destination vector register element plus the stride value.

[0522] Example 122 includes the substantive content of the exemplary non-transitory machine-readable medium described in Example 121, wherein the vector instructions further include a source identifier to specify a source vector register, and wherein deriving the broadcast data value includes one of: using a first immediate value as the broadcast data value, and using the first immediate value to select a vector element within the source vector register and using the selected source vector register element as the broadcast data value.

[0523] Example 123 includes the substantive content of the exemplary non-transitory machine-readable medium described in Example 121, wherein the vector instruction further includes a source identifier to specify a source vector register, and wherein deriving the straddle data value includes one of: using a second immediate value as the straddle data value, and using the second immediate value to select a vector element within the source vector register and using the selected source vector register element as the straddle data value.

[0524] Example 124 includes the substantive content of the exemplary non-transitory machine-readable medium described in Example 121, wherein the write mask register includes a plurality of one-bit vector write mask elements, each of the plurality of one-bit vector write mask elements controlling whether to write an execution result to a corresponding vector element in the destination vector register, the corresponding vector element occupying the same relative position in the destination vector register as the relative position occupied by the vector write mask element in the write mask register, wherein the execution result is to be written only to the unmasked vector element in the destination vector register.

[0525] Example 125 includes the substantive content of the exemplary non-transitory machine-readable medium described in Example 124, wherein executing the vector instructions further includes zeroing the masked vector elements in the destination vector register.

[0526] Example 126 includes the substantive content of the exemplary non-transitory machine-readable medium described in Example 124, wherein executing the vector instructions further includes masking vector elements that do not write new values ​​to the destination vector register.

[0527] Example 127 includes the substantive content of the exemplary non-transitory machine-readable medium described in Example 123, wherein the vector instructions further include a masking element control field to specify whether to retain the value of the masked vector element in the destination vector register or to zero it.

[0528] Example 128 includes the substantive content of the exemplary non-transitory machine-readable medium described in Example 127, wherein the masking element control field is to be derived from the operational code.

[0529] Example 129 includes the substantive content of the exemplary non-transitory machine-readable medium described in Example 127, wherein the masking element control field is one of the prefix and suffix of the operation code.

[0530] Example 130 includes the substantive content of an exemplary non-transitory machine-readable medium as described in any of Examples 121-129, wherein the vector instructions further include an element size identifier to specify the size of the vector element in the destination vector register.

[0531] Example 131 provides a processor for executing vector instructions, the processor comprising: components for retrieving the vector instructions from a code storage device, the vector instructions including an opcode, a destination identifier for specifying a destination vector register, a write mask identifier for specifying a write mask register, and first and second immediate values; components for decoding the retrieved vector instructions; and components for executing the decoded vector instructions to perform the following: deriving a data value using the first immediate value, deriving a stride value using the second immediate value, identifying unmasked destination vector register elements using the write mask register, broadcasting the data value to each unmasked destination vector register element when the opcode specifies broadcasting, storing the data value in the first unmasked destination vector register element when the opcode specifies stride, and for each subsequent unmasked destination vector register element, successively generating and storing the value of the immediately preceding unmasked destination vector register element plus the stride value.

[0532] Example 132 includes the substance of the exemplary processor described in Example 131, wherein the vector instruction further includes a source identifier to specify a source vector register, and wherein deriving the broadcast data value includes one of: using a first immediate value as the broadcast data value, and using the first immediate value to select a vector element within the source vector register and using the selected source vector register element as the broadcast data value.

[0533] Example 133 includes the substance of the exemplary processor described in Example 131, wherein the vector instruction further includes a source identifier to specify a source vector register, and wherein deriving the straddle data value includes one of: using a second immediate value as the straddle data value, and using the second immediate value to select a vector element within the source vector register and using the selected source vector register element as the straddle data value.

[0534] Example 134 includes the substance of the exemplary processor described in Example 131, wherein the write mask register includes a plurality of one-bit vector write mask elements, each of the plurality of one-bit vector write mask elements controlling whether to write the execution result to a corresponding vector element in the destination vector register, the corresponding vector element occupying the same relative position in the destination vector register as the relative position occupied by the vector write mask element in the write mask register, wherein the execution result is written only to the unmasked vector element in the destination vector register.

[0535] Example 135 includes the substance of the exemplary processor described in Example 134, wherein executing the vector instruction further includes zeroing the masked vector elements in the destination vector register.

[0536] Example 136 includes the substance of the exemplary processor described in Example 134, wherein executing the vector instruction further includes masking the vector element without writing the new value to the destination vector register.

[0537] Example 137 includes the substance of the exemplary processor described in Example 133, wherein the vector instruction further includes a masking element control field to specify whether to retain the value of the masked vector element in the destination vector register or to zero it.

[0538] Example 138 includes the substance of the exemplary processor described in Example 137, wherein the masking element control field is to be derived from the operation code.

[0539] Example 139 includes the substance of the exemplary processor described in Example 137, wherein the masking element control field is a suffix or prefix of the operation code.

[0540] Example 140 includes the substance of the exemplary processor described in any of Examples 131-139, wherein the vector instruction further includes an element size identifier to specify the size of the vector element in the destination vector register.

[0541] Example 141 provides a system for executing instructions, the system comprising: a memory; and a processor, the processor comprising: fetching circuitry for fetching the instructions from a code storage device, the instructions including an opcode, a destination identifier for specifying a destination vector register, a first immediate value, and a write mask identifier for specifying a write mask register, the write mask register including at least one bit corresponding to each destination vector register element, the at least one bit for specifying whether the destination vector register element is masked or unmasked; decoding circuitry for decoding the fetched instructions; and execution circuitry for executing the decoded instructions to use the write mask register to determine unmasked elements in the destination vector register, and broadcasting the first immediate value to one or more unmasked vector elements in the destination vector register when the opcode specifies broadcasting.

[0542] Example 142 includes the substance of the exemplary system described in Example 141, wherein the execution circuitry further aims to zero out the masked vector elements in the destination vector register.

[0543] Example 143 includes the substance of the exemplary system described in Example 142, wherein the execution circuitry further allows the masked vector elements to retain their previous values.

[0544] Example 144 includes the substance of the exemplary system described in Example 141, wherein the instructions further include a masking element control field to specify whether to retain the value of a masked vector element in the destination vector register or to zero it, and wherein the execution circuitry further uses the masking element control field for each masked element in the destination vector register to determine whether to zero out the masked element or to allow the masked element to retain its value.

[0545] Example 145 includes the substance of the exemplary system described in Example 144, wherein the masking element control field is derived from the operation code.

[0546] Example 146 includes the substance of the exemplary system described in Example 141, wherein the operand further includes an element size identifier to specify the element size of the destination vector register element, wherein the element size identifier is one of the prefix and suffix of the operand.

[0547] Example 147 includes the substance of the exemplary system described in Example 141, wherein the destination vector register includes one of the following: a 128-bit vector register, a 256-bit vector register, and a 512-bit vector register, the destination vector register including a plurality of fixed-size vector elements.

[0548] Example 148 provides a method for executing instructions, the method comprising: retrieving the instructions from a code storage device by an extraction circuit, the instructions including an operand, a destination identifier for specifying a destination vector register, a first immediate value and a second immediate value, and a write mask identifier for specifying a write mask register, the write mask register including at least one bit corresponding to each destination vector register element, the at least one bit being used to specify whether the destination vector register element is masked or unmasked; decoding the extracted instructions by a decoding circuit; and executing the decoded instructions by an execution circuit to: derive a data value using the first immediate value; derive a stride value using the second immediate value; identify unmasked destination vector register elements using the write mask register; and when the operand specifies stride, storing the data value in the first unmasked destination vector register element, and for each subsequent unmasked destination vector register element, generating a strided value by adding the strid value to the immediately preceding unmasked destination vector register, and storing the strided value in the unmasked destination vector register element.

[0549] Example 149 includes the substance of the exemplary method described in Example 148, wherein the instructions further include a source identifier to specify a source vector register, and wherein deriving the data value includes one of: using a first immediate value as the data value and using the first immediate value to select an element within the source vector register.

[0550] Example 150 includes the substance of the exemplary method described in Example 148, wherein the instructions further include a source identifier to specify a source vector register, and wherein deriving the stride value includes one of: using a second immediate value as the stride value and using the second immediate value to select an element within the source vector register to be used as the stride value.

[0551] Example 151 includes the substance of the exemplary method described in Example 148, wherein executing the instructions further includes zeroing the masked vector elements in the destination vector register.

[0552] Example 152 includes the substance of the exemplary method described in Example 148, wherein executing the instructions further includes allowing the masked vector elements in the destination vector register to retain their values.

[0553] Example 153 includes the substance of the exemplary method described in Example 148, wherein the instructions further include a masking element control field to specify whether to retain the value of the masked vector element in the destination vector register or to zero it.

[0554] Example 154 provides a processor for executing instructions, the processor comprising: means for retrieving the instructions from a code storage device, the instructions including an opcode, a destination identifier for specifying a destination vector register, a first immediate value and a second immediate value, and a write mask identifier for specifying a write mask register, the write mask register including at least one bit corresponding to each destination vector register element, the at least one bit being used to specify whether the destination vector register element is masked or unmasked; means for decoding the retrieved instructions; and means for executing the decoded instructions to perform the following: deriving a data value using the first immediate value; deriving a stride value using the second immediate value; identifying unmasked destination vector register elements using the write mask register; and when the opcode specifies stride, storing the data value in the first unmasked destination vector register element, and for each subsequent unmasked destination vector register element, generating a stride value by adding the stride value to the immediately preceding unmasked destination vector register, and storing the stride value in the unmasked destination vector register element.

[0555] Example 155 includes the substance of the exemplary processor described in Example 154, wherein the instructions further include a source identifier to specify a source vector register, and wherein the execution component derives the data value by one of: using a first immediate value as the data value and using the first immediate value to select an element within the source vector register.

[0556] Example 156 includes the substance of the exemplary processor described in Example 154, wherein the instructions further include a source identifier to specify a source vector register, and wherein the component for execution derives the stride value by one of: using a second immediate value as the stride value and using the second immediate value to select an element within the source vector register to be used as the stride value.

[0557] Example 157 includes the substance of the exemplary processor described in Example 154, wherein the execution component further zeroes the masked vector elements in the destination vector register.

[0558] Example 158 includes the substance of the exemplary processor described in Example 154, wherein the execution component further allows the masked vector elements in the destination vector register to retain their previous values.

[0559] Example 159 includes the substance of the exemplary processor described in Example 154, wherein the instructions further include a masking element control field to specify whether to retain the value of a masked vector element in the destination vector register or to zero it, and wherein the execution component further zeroes the masked element in the destination vector register or allows the masked element in the destination vector register to retain its previous value based on the masking element control field.

[0560] Example 160 includes the substance of the exemplary processor described in Example 154, wherein the instructions further include a source identifier to specify a source vector register, and wherein the component for execution is to derive the data value by adding a first immediate value to an element identified by a second immediate value in the source vector register.

Claims

1. A system for executing instructions, the system comprising: Memory; as well as Processor, comprising: An extraction circuit extracts the instructions from a code storage device. The instructions include an operation code, a destination identifier for specifying a destination vector register, a first immediate value, a second immediate value, and a write mask identifier for specifying a write mask register, the write mask register including at least one bit corresponding to each destination vector register element, the at least one bit being used to specify whether the destination vector register element is masked or unmasked. Decoding circuitry, which decodes the extracted instructions; and The execution circuit executes the decoded instructions to determine the unmasked elements in the destination vector register using the write mask register, and broadcasts a first immediate value to one or more unmasked vector elements in the destination vector register when the operand specifies broadcasting, and stores the first immediate value in the first unmasked vector element in the destination vector register when the operand specifies stepping, and for each subsequent unmasked vector element in the destination vector register, successively generates and stores the value of the immediately preceding unmasked vector element plus the second immediate value.

2. The system according to claim 1, wherein, The execution circuit further needs to zero out the masked vector elements in the destination vector register.

3. The system according to claim 1, wherein, The execution circuitry must further allow the masked vector elements to retain their previous values.

4. The system according to any one of claims 1-3, wherein, The instruction further includes a masking element control field to specify whether to retain the value of the masked vector element in the destination vector register or to zero it, and wherein the execution circuitry further uses the masking element control field for each masked element in the destination vector register to determine whether to zero out the masked element or to allow the masked element to retain its value.

5. The system according to claim 4, wherein, The masking element control field is derived from the operation code.

6. The system according to any one of claims 1-3, wherein, The operand code further includes an element size identifier to specify the element size of the destination vector register element, wherein the element size identifier is one of the prefix and suffix of the operand code.

7. The system according to claim 6, wherein, The element size is one of one byte, two bytes, four bytes, and eight bytes.

8. The system according to any one of claims 1-3, wherein, The destination vector register includes one of the following: a 128-bit vector register, a 256-bit vector register, and a 512-bit vector register, and the destination vector register includes multiple fixed-size vector elements.

9. The system according to any one of claims 1-3, wherein after executing the decoded instruction, the execution circuit further moves the contents of the destination vector register to a general-purpose register.

10. The system according to any one of claims 1-3, wherein, The instructions are formatted according to the Advanced Vector Extension Format.

11. A method for executing instructions, the method comprising: The instruction is extracted from the code storage device by the extraction circuit. The instruction includes an operation code, a destination identifier for specifying a destination vector register, a first immediate value and a second immediate value, and a write mask identifier for specifying a write mask register. The write mask register includes at least one bit corresponding to each destination vector register element, and the at least one bit is used to specify whether the destination vector register element is masked or not. The instructions extracted by the decoding circuit; as well as The decoded instructions are executed by the execution circuit to: Use the first immediate value to derive the data value; Use the second immediate value to derive the step value; Use the write mask register to identify unmasked destination vector register elements; as well as When the operation code specifies a step, the data value is stored in the first unmasked destination vector register element, and for each subsequent unmasked destination vector register element, a step value is generated by adding the step value to the immediately preceding unmasked destination vector register, and the step value is stored in the unmasked destination vector register element.

12. The method according to claim 11, wherein, The instruction further includes a source identifier to specify a source vector register, and wherein deriving the data value includes one of: using a first immediate value as the data value and using the first immediate value to select an element within the source vector register.

13. The method according to claim 11, wherein, The instruction further includes a source identifier to specify a source vector register, and wherein deriving the stride value includes one of: using a second immediate value as the stride value and using the second immediate value to select an element within the source vector register to be used as the stride value.

14. The method according to any one of claims 11-13, wherein, Executing the instruction further includes zeroing the masked vector element in the destination vector register after storing the step-after value into each subsequent unmasked destination vector register element.

15. The method according to any one of claims 11-13, wherein, Executing the instructions further includes allowing the masked vector elements in the destination vector register to retain their values ​​after storing the value after the step into each subsequent unmasked destination vector register element.

16. The method according to any one of claims 11-13, wherein, The instruction further includes a masking element control field to specify whether to retain the value of the masked vector element in the destination vector register or to zero it.

17. The method according to any one of claims 11-13, wherein, The operand code further includes an element size identifier to specify the element size of the destination vector register element, wherein the element size identifier is one of the prefix and suffix of the operand code.

18. A machine-readable medium comprising code, which, when executed, causes a machine to perform the method according to any one of claims 11-17.

19. A processor for executing instructions, the processor comprising: Components for retrieving the instructions from a code storage device, the instructions including an operation code, a destination identifier for specifying a destination vector register, a first immediate value and a second immediate value, and a write mask identifier for specifying a write mask register, the write mask register including at least one bit corresponding to each destination vector register element, the at least one bit being used to specify whether the destination vector register element is masked or unmasked. A component used to decode the extracted instructions; as well as The component used to execute the decoded instructions to perform the following: Use the first immediate value to derive the data value; Use the second immediate value to derive the step value; Use the write mask register to identify unmasked destination vector register elements; as well as When the operation code specifies a step, the data value is stored in the first unmasked destination vector register element, and for each subsequent unmasked destination vector register element, a step value is generated by adding the step value to the immediately preceding unmasked destination vector register, and the step value is stored in the unmasked destination vector register element.

20. The processor of claim 19, wherein, The instruction further includes a source identifier to specify a source vector register, and wherein the component for execution derives the data value by one of: using a first immediate value as the data value and using the first immediate value to select an element within the source vector register.

21. The processor according to claim 19, wherein, The instruction further includes a source identifier to specify a source vector register, and wherein the component for execution derives the stride value by one of: using a second immediate value as the stride value and using the second immediate value to select an element within the source vector register as the stride value.

22. The processor according to any one of claims 19-21, wherein, The execution component further zeroes out the masked vector elements in the destination vector register after storing the data into each subsequent unmasked destination vector register element.

23. The processor according to any one of claims 19-21, wherein, The execution component further allows the masked vector elements in the destination vector register to retain their previous values ​​after storing the data into each subsequent unmasked destination vector register element.

24. The processor according to any one of claims 19-21, wherein, The instruction further includes a masking element control field to specify whether to retain the value of the masked vector element in the destination vector register or to zero it, and wherein the component for execution further zeroes the masked element in the destination vector register or allows the masked element in the destination vector register to retain its previous value based on the masking element control field.

25. The processor according to any one of claims 19-21, wherein, The instruction further includes a source identifier to specify a source vector register, and wherein the component for execution derives the data value by adding a first immediate value to the element identified by a second immediate value in the source vector register.

Images