Coarse and fine pass multi-level nvm programming

Abstract

Embodiments of a memory programmer apparatus can include a first level programmer to program a first level cell portion of a multi-level memory in a first pass, a coarse programmer to coarsely program a second level cell portion of the multi-level memory in the first pass, where the second level cell portion includes more levels than the first level cell portion, and a fine programmer to finely program the second level cell portion of the multi-level memory in a second pass according to data programmed in the first level cell portion in the first pass.

Description

Technical Field

[0001] The embodiments generally relate to memory systems. More specifically, the embodiments relate to coarse-pass and fine-pass multi-level NVM programming. Background Technology

[0002] Multilevel nonvolatile memory stores more than one bit per cell. A multilevel NAND memory with four (4) possible voltage levels per cell can represent two (2) bits of data per cell. A NAND memory with eight (8) voltage levels per cell can be called a three-level cell (TLC) memory and can represent three (3) bits of data per cell. A NAND memory with sixteen (16) voltage levels per cell can be called a four-level cell (QLC) memory and can represent four (4) bits of data per cell. For some NAND flash memory devices, erasing a block can set all bit values ​​to 1. Programming can refer to the process of changing the erased bit from a bit value of 1 to a bit value of 0. Attached Figure Description

[0003] By reading the following specification and appended claims, and by referring to the accompanying drawings, various advantages of the embodiments will become apparent to those skilled in the art, wherein:

[0004] Figure 1 This is a block diagram of an example electronic processing system according to an embodiment;

[0005] Figure 2 This is a block diagram of an example memory programmer device according to an embodiment;

[0006] Figures 3A to 3C This is a flowchart illustrating an example of a method for programming a memory according to an embodiment;

[0007] Figure 4 This is a flowchart of another example of a method for programming a memory according to an embodiment;

[0008] Figure 5 This is an illustrative diagram of the threshold voltage distribution according to an embodiment;

[0009] Figure 6 This is an explanatory diagram of the programming pulses according to an embodiment;

[0010] Figure 7 This is another illustrative diagram of the programming pulse according to an embodiment;

[0011] Figure 8 This is a flowchart of another example of a method for programming a memory according to an embodiment;

[0012] Figure 9 This is a flowchart of another example of a method for programming a memory according to an embodiment;

[0013] Figure 10 This is a block diagram of another example of an electronic processing system according to an embodiment; and

[0014] Figure 11 This is a block diagram of another example of an electronic processing system according to an embodiment. Detailed Implementation

[0015] The various embodiments described herein may include memory components and / or interfaces to memory components. Such memory components may include volatile and / or non-volatile memory. Non-volatile memory may be a storage medium that does not require power to maintain the state of data stored by the medium. In one embodiment, the memory device may include block-addressable memory devices, such as those based on NAND or NOR technologies. The memory device may also include future-generation non-volatile devices, such as three-dimensional cross-point memory devices, or other byte-addressable in-situ write non-volatile memory devices. In one embodiment, a memory device may be or may include a memory device using chalcogenide glass, a multi-threshold NAND flash memory, a NOR flash memory, a single-level or multi-level phase-change memory (PCM), a resistive memory, a nanowire memory, a ferroelectric transistor random access memory (FeTRAM), an antiferroelectric memory, a magnetoresistive random access memory (MRAM) incorporating memristor technology, a resistive memory including a metal oxide substrate, an oxygen vacancy substrate, and a bridged random access memory (CB-RAM) or spin-transfer torque (STT)-MRAM, a device based on a spintronic magnetic junction memory, a device based on a magnetic tunneling junction (MTJ), a device based on domain walls (DW) and spin-orbit transfer (SOT), a thyristor-based memory device, or any combination of the above or other memories. A memory device may refer to the die itself and / or a packaged memory product. In certain embodiments, memory components having non-volatile memory may conform to one or more standards issued by the Joint Electron Device Engineering Council (JEDEC), such as JESD218, JESD219, JESD220-1, JESD223B, JESD223-1, or other suitable standards (the JEDEC standards cited herein are available at jedec.org).

[0016] Volatile memory can be a storage medium that requires power to maintain the state of data stored by the medium. Non-limiting examples of volatile memory can include various types of RAM, such as dynamic random access memory (DRAM) or static random access memory (SRAM). One particular type of DRAM that can be used in a memory module is synchronous dynamic random access memory (SDRAM). In certain embodiments, the DRAM of the memory component can conform to standards promulgated by JEDEC, such as JESD79F for DDR SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, JESD79-4A for DDR4 SDRAM, JESD209 for low-power DDR (LPDDR), JESD209-2 for LPDDR2, JESD209-3 for LPDDR3, and JESD209-4 for LPDDR4 (these standards are available at www.jedec.org). Such a standard (and similar standards) can be called a DDR-based standard, and the communication interface of a storage device that implements such a standard can be called a DDR-based interface.

[0017] Turn now Figure 1 Embodiments of the electronic processing system 10 may include a processor 11, a multi-level NAND memory 12 communicatively coupled to the processor 11, and a memory programmer 13 communicatively coupled to the multi-level NAND memory 12 for programming the multi-level NAND memory 12. In some embodiments, the multi-level NAND memory 12 may include a single-level cell (SLC) portion 14 and a quad-level cell (QLC) portion 15. The memory programmer 13 may advantageously be configured to program the SLC portion 14 in a first round, coarsely program the QLC portion 15 in a first round, and finely program the QLC portion 15 in a second round based on data programmed into the SLC portion 14 in the first round. For example, the data programmed into the QLC portion 15 in the first round may be unverified. In some embodiments, the memory programmer 13 may also be configured to finely program the QLC portion 15 based on data stored in the SLC portion 14 after a power outage. As described in more detail below, some embodiments may work with other multi-level portions (e.g., TLC, etc.). In some embodiments, the memory programmer 13 may include or incorporate a memory controller.

[0018] Some embodiments of system 10 may also include a page mapping translator 16 communicatively coupled to the multi-level NAND memory 12 to translate addresses between the SLC portion 14 and the QLC portion 15. In some embodiments, for example, the page mapping translator 16 may be integrated on the same die as the multi-level NAND memory 12. System 10 may also include a page buffer 17 communicatively coupled to a memory programmer 13 to store data pages, wherein the memory programmer 13 may be configured to program the SLC portion 14 based on a first data page stored in the page buffer 17 simultaneously with a second data page being transferred to the page buffer 17.

[0019] Embodiments of each of the processor 11, multi-level NAND memory 12, memory programmer 13, SLC section 14, QLC section 15, page mapping translator 16, page buffer 17, and other system components described above can be implemented in hardware, software, or any suitable combination thereof. For example, hardware implementations may include configurable logic, such as, for example, a programmable logic array (PLA), a field-programmable gate array (FPGA), a complex programmable logic device (CPLD), or fixed-function logic hardware using circuitry such as, for example, application-specific integrated circuit (ASIC), complementary metal-oxide-semiconductor (CMOS), or transistor-transistor (TTL) logic technology, or any combination thereof.

[0020] Alternatively or additionally, all or part of these components may be implemented in one or more modules as a set of logical instructions to be executed by a processor or computing device, stored in a machine or computer-readable storage medium such as RAM, read-only memory (ROM), programmable ROM (PROM), firmware, flash memory, etc. For example, computer program code implementing the operation of the components may be written in any combination of programming languages ​​applicable / suitable for one or more operating systems (OS), including object-oriented programming languages ​​such as PYTHON, PERL, JAVA, SMALLTALK, C++, C#, etc., and conventional procedural programming languages ​​such as the "C" programming language or similar programming languages. For example, multi-level NAND memory 12, other persistent storage media, or other system memory may store a set of instructions that, when executed by processor 11, cause system 10 to implement one or more components, features, or aspects of system 10 (e.g., memory programmer 13, etc.).

[0021] Turn now Figure 2Embodiments of the memory programmer device 20 may include a first-level programmer 21 that programs a first-level cell portion of a multi-level memory in a first round, a coarse programmer 22 that coarsely programs a second-level cell portion of the multi-level memory in the first round, wherein the second-level cell portion includes more voltage levels than the first-level cell portion, and a fine programmer 23 that finely programs the second-level cell portion of the multi-level memory in a second round based on data programmed into the first-level cell portion in the first round. For example, the data programmed into the second-level cell portion in the first round may be unverified. In some embodiments, the fine programmer 23 may also be configured to finely program the second-level cell portion based on data stored in the first-level cell portion after a power outage.

[0022] Some embodiments of device 20 may also include a page mapping translator 24 communicatively coupled to one or more of the first-level programmer 21, coarse programmer 22, and / or fine programmer 23 to translate addresses between the first-level cell portion and the second-level cell portion. In some embodiments, for example, the page mapping translator 24 may be integrated on the same die as the multi-level non-volatile memory. Some embodiments may also include a page buffer 25 communicatively coupled to the first-level programmer 21 to store data pages, wherein the first-level programmer 21 may be configured to program the first-level cell portion based on the first data page stored in the page buffer 25 simultaneously with the transfer of a second data page to the page buffer 25.

[0023] Embodiments of each of the first-level programmer 21, coarse programmer 22, fine programmer 23, page mapping translator 24, page buffer 25, and other components of device 20 described above can be implemented in hardware, software, or any combination thereof. For example, a hardware implementation may include configurable logic such as, for example, PLA, FPGA, CPLD, or fixed-function logic hardware using circuitry such as, for example, ASIC, CMOS, or TTL technology, or any combination thereof. Alternatively or additionally, these components may be implemented in one or more modules as a set of logical instructions to be executed by a processor or computing device, stored in a machine- or computer-readable storage medium such as RAM, ROM, PROM, firmware, flash memory, etc. For example, computer program code implementing the operation of the components may be written in any combination of one or more OS-suitable / appropriate programming languages, including object-oriented programming languages ​​such as PYTHON, PERL, JAVA, SMALLTALK, C++, C#, etc., and conventional procedural programming languages ​​such as the "C" programming language or similar programming languages.

[0024] Turn now Figures 3A to 3CAn embodiment of method 30 for programming multi-level non-volatile memory may include programming a first-level cell portion of the multi-level memory in a first round at block 31, coarsely programming a second-level cell portion of the multi-level memory in a first round at block 32, wherein the second-level cell portion includes more levels than the first-level cell portion, and finely programming the second-level cell portion of the multi-level memory in a second round at block 33 based on data programmed into the first-level cell portion in the first round. For example, at block 34, the data programmed into the second-level cell portion in the first round may be unverified. Method 30 may also include finely programming the second-level cell portion based on data stored in the first-level cell portion after a power outage at block 35.

[0025] Some embodiments of method 30 may further include translating addresses between the first-level cell portion and the second-level cell portion at block 36, and / or integrating address translation on the same die as the multilevel memory at block 37. In some embodiments, method 30 may further include programming the first-level cell portion according to the first data page at block 38 while the second data page is transferred to the multilevel memory.

[0026] Embodiments of method 30 can be implemented in systems, apparatuses, computers, devices, etc., such as those described herein. More specifically, hardware implementations of method 30 may include configurable logic, such as, for example, PLA, FPGA, CPLD, or fixed-function logic hardware using circuitry such as, for example, ASIC, CMOS, or TTL technology, or any combination thereof. Alternatively or additionally, method 30 may be implemented in one or more modules as a set of logical instructions to be executed by a processor or computing device, stored in a machine- or computer-readable storage medium, such as RAM, ROM, PROM, firmware, flash memory, etc. For example, computer program code implementing the operation of the components may be written in any combination of one or more OS-suitable / appropriate programming languages, including object-oriented programming languages ​​such as PYTHON, PERL, JAVA, SMALLTALK, C++, C#, etc., and conventional procedural programming languages ​​such as the "C" programming language or similar programming languages. For example, method 30 may be implemented on a computer-readable medium as described in conjunction with the following Examples 19 to 24. For example, embodiments or portions of method 30 may be implemented in driver software or applications running on an operating system (OS), such as via an application programming interface (API).

[0027] Some embodiments may provide methods for programming NAND memories such as QLC NAND products. Some embodiments may advantageously improve the programming speed of multi-bit-per-cell NAND memories, and particularly, the programming speed of 4-bit-per-cell QLC NAND memories, by improving the speed of the first round of programming in a two-round programming scheme. For example, some embodiments may provide two rounds of programming, wherein the first round is performed significantly faster than some other two-round programming techniques.

[0028] Without being limited to operational theory, in some other QLC NAND memories, starting from the erased state, word line WLn is programmed to 8 voltage levels (states) per cell (first round for WLn) based on user data provided for 3 pages. Then, the next adjacent word line WLn+1 is programmed to 8 levels per cell state (first round for WLn+1). Due to the coupling between WLn+1 and WLn cells, the 8-level placement of WLn cells is affected at this stage. However, since this is not the final 16-level placement, there is more tolerance for infringement from the WLn+1 placement. WLn is then programmed to its final 16-level per cell state (second round for WLn) based on its current content (3 data pages written in the first round) and an additional data page provided by the user. By doing so, once WLn is in its 16-level per-cell state, its threshold voltage (Vt) arrangement is only affected by programming WLn+1 from the 8-level to the 16-level per-cell state, which is significantly less intrusive than programming WLn+1 from the erased state to the 8-level per-cell state. In some implementations, this alternative programming technique may be referred to as the 8-16 programming technique.

[0029] In the aforementioned 8-16 programming technique (which may be part of a write operation), the first round of placement encodes data from three user data pages. Correctly placing the cell to its final 16-level per-cell (QLC) state requires correctly reading the data from the first round. Any errors made during the reading of the first round data result in a misplacement of the final QLC state. The ability to correctly read data from the 8-level per-cell (TLC) state requires a relatively fine placement of that state. To do this, the first round of the 8-16 programming technique requires relatively small gate control steps and many verification steps. Therefore, the first round of the aforementioned two-round programming will also be relatively slow. Furthermore, depending on the expected raw error rate (RBER) of the read operation, the reading of the three TLC data pages in the preparation of the second round of programming may require error correction on one or more pages, which further slows down the overall programming. A fourth data page is also provided and used in combination with the three data pages read from the TLC state to program the cell to the final 16-level QLC state. For example, level 16 can correspond to a 4-bit binary value (0 to 15), where the first 3 pages provide the initial 3 bits of the value, and the fourth page provides the last fourth bit of the 4-bit value.

[0030] In another two-round programming technique, faster two-round programming can be achieved by programming to a level 4 per cell (MLC) state based on two user data pages in the first round and then programming to a final level 16 per cell (QLC) state based on another two user data pages in the second round. However, this 4-16 programming technique comes at the cost of more intrusion from adjacent word lines and exhibits RWB loss compared to the 8-16 programming technique.

[0031] Another drawback of some other programming techniques is that an interruption or power loss during the second round (which can be a few milliseconds) can result in the loss of data previously stored in the MLC / TLC state. Since this data is written significantly earlier (sometimes days earlier) than the fourth page provided for the second round of programming, provisions are needed to provide immunity to or recovery from data loss in such interruption / power loss events. This problem adds further complexity to the system and / or the technology.

[0032] In a QLC implementation according to some embodiments, during the first round of programming the word line WLn, four (4) data pages may be provided by the system (e.g., as opposed to three data pages in some other 8-16 programming techniques). The page data may be temporarily written to the SLC block and may also be used to arrange the corresponding cells in the QLC block into a coarse 16-level per-cell state. The coarse arrangement may reduce or minimize Vt movement as a result of the second round of programming and thus reduce or minimize infringement on adjacent word lines WLn+1 (adjacent word lines WLn+1 may have already been programmed into the final 16-level per-cell state before WLn is programmed from the coarse 16-level per-cell state to the final 16-level per-cell state in the second round of programming of WLn). After programming the next adjacent word line WLn+1 into the coarse 16-level per-cell state, the second round of programming WLn may be performed by first reading the corresponding SLC block internally and using the data from the SLC block to move the cells in WLn into their fine 16-level per-cell states.

[0033] Advantageously, in some embodiments, the overall programming speed of QLC NAND can be significantly improved (e.g., by more than 20%) compared to some other 8-16 two-round programming techniques, while providing a comparable read window budget (RWB). Furthermore, or alternatively, some embodiments may also be advantageously inherently immune to or resilient to power loss during the second round of programming, since data is available in the SLC block prior to the final QLC arrangement (e.g., the QLC block can be resumed or programmed from the SLC block after an interruption in programming between the first and second rounds due to, for example, a power outage or loss).

[0034] Turn now Figure 4 An embodiment of the method 40 for programming the memory may include a first round 41 and a second round 42. In the first round 41 of programming the word line WLn, four data pages P1, P2, P3, and P4 may be provided to the multilevel memory at block 43. At block 44, this data may be immediately written to the designated single-level per-cell (SLC) location corresponding to WLn. At block 45, the data may also be used to arrange WLn into a coarse 16-level state (e.g., as described in more detail below). The coarse programming at block 45 may move the Vt of each cell close to its final arrangement so that the second round 42 of programming on WLn does not cause significant encroachment on adjacent word lines WLn-1. In the second round 42 of programming WLn, four data pages P1, P2, P3, and P4 may be read from the corresponding SLC location at block 46, and are used at block 47 to arrange WLn into a fine 16-level state.

[0035] Turn now Figure 5The illustrative Vt distribution can represent a first QLC programming round 52 based on a coarse arrangement and a second QLC programming round 54 based on a fine arrangement. Starting at the erased state (L0), during the first round 52 of programming WLn, four data pages are provided, and the cells are programmed in a coarse 16-level state. (As...) Figure 5 As shown, the data in the coarse 16-level state is not readable, as illustrated by the wide-level schematic diagrams that overlap each other. After performing a similar first round of coarse programming on WLn+1, WLn will no longer be significantly compromised, and a second round of 54 programming can be performed on WLn. To perform the second round of 54, the corresponding four data pages can first be read from the specified SLC location, and then the cells of WLn can be arranged in its final 16-level state (e.g., as illustrated by the narrower-level schematic diagrams that do not overlap each other).

[0036] Since a copy of the data is stored in the corresponding SLC location before programming the QLC cell to its final 16-level state, according to some embodiments, the coarse 16-level arrangement in the first round 52 advantageously does not need to be readable and therefore does not need to be tightly arranged. Advantageously, some embodiments can use a very fast programming process without verifying the data. In terms of coarseness, in some embodiments, the first round arrangement can ensure that the Vt distribution of each level does not exceed the expected maximum value Vt of the final 16-level arrangement plus a margin to account for the worst-case conditions of programming speed and the impact from the first round arrangement of WLn+1.

[0037] Turn now Figure 6The diagram illustrates a sequence of program pulses during the first round of programming a QLC cell. In some other programming techniques, a sequence of programming pulses with increasing amplitude is applied to a selected bit line (WL). Each programming pulse is then followed by a staircase sequence to determine whether each bit line (BL) has reached its desired programming state (e.g., the cell's Vt is above a predetermined verification voltage). At each programming pulse, BLs that have reached their desired programming state are connected to a voltage typically in the 2-3V range, preventing further programming. BLs that have not yet reached their desired programming state are connected to a low voltage, such as a ground signal, allowing them to be programmed. Additionally, a verification step may include special steps to identify those BLs that have not yet reached their desired programming state but are close to it. Typically, these BLs are connected to a signal between the programming voltage and the inhibit voltage, allowing them to be programmed at a reduced rate using, for example, selective slow program convergence (SSPC). In conventional 8-16 programming techniques, for example, programming the first round (TLC state) may require up to 20 or more programming pulses, each followed by several verification steps (e.g., three verification steps). As a result, in some other programming techniques, the first round can be required to complete in as little as 3ms.

[0038] In some embodiments, the first round of programming the QLC unit can advantageously be performed by applying a sequence of programming pulses to the selected WL without having each program pulse followed by a series of verification stair sequences. Figure 6 As shown, for example, the first program pulse can program all cells except those belonging to L0 (e.g., it can disable L0 BL, and all other BLs can receive the program signal). The second program pulse can program all cells except L0 and L1, and so on, as... Figure 6 As illustrated in the figure. Advantageously, some embodiments can utilize only 15 program pulses and have no verification step, and can be executed much faster than other first-round programming techniques (e.g., less than 1 ms).

[0039] Turn now Figure 7 In some embodiments, two sets of units can be programmed at each program pulse. For example... Figure 7 As illustrated, the first program pulse can program L2 and above at full programming speed and L1 at a slower speed (e.g., L0 BL can be disabled; L2 and above BLs can be connected to the program voltage (e.g., ground); and L1 BL can be connected to an intermediate voltage). The second pulse can program L4 and above at full speed and L3 at a slower speed, and so on. Advantageously, some embodiments can utilize a total of 8 program pulses (and no verification step), which can reduce the programming time of the first round (e.g., to less than 500 μs).

[0040] In some embodiments, the first round may also include programming the data in a specified SLC location. Since the SLC utilizes a single-level arrangement, programming can be accomplished by applying a single pulse to the selected WL without a verification step. Such SLC programming is very fast (e.g., performed in 250 μs or less). Similarly, reading four SLC data pages in preparation for the second round of programming can be done much faster than reading three TLC data pages, and advantageously, external error correction is not required. In some embodiments, the size of the available SLC memory can be pre-configured or can be dynamically configured.

[0041] Turn now Figure 8 An embodiment of method 60 for programming the memory may include transferring a first data page P1 to the NAND at block 61, and programming the P1 data at the corresponding SLC location at block 62. Method 60 may then include transferring a second data page P2 to the NAND at block 63, and programming the P2 data at the corresponding SLC location at block 64. Method 60 may then include transferring a third data page P3 to the NAND at block 65, and programming the P3 data at the corresponding SLC location at block 66. Method 60 may then include transferring a fourth data page P4 to the NAND at block 67, and programming the P4 data at the corresponding SLC location at block 68. Method 60 may then include programming the QLC WLn to a coarse-grained state at block 69 based on the four pages P1, P2, P3, and P4. Subsequently, method 60 may include reading four pages P1, P2, P3, and P4 from the SLC location corresponding to QLCWLn at block 70, and programming QLC WLn to the 16-level final state at block 71 based on the internally read pages P1, P2, P3, and P4.

[0042] In the first round of programming, for example, four data pages can be transferred to the NAND and stored in a designated SLC location. The same data can be held inside the NAND die's page buffer and used to program the corresponding QLC WL to 16 coarse states. In the second round of programming, four data pages can be read from inside the SLC location without transferring data outside the NAND die and used to program the corresponding QLC WL to the final 16-level state. In some embodiments, programming the QLC WL to the coarse state can be performed immediately after programming the four data pages to the SLC location. The second round of programming the QLC WLn can be performed after the second round of coarse programming of the data corresponding to WLn+1 is completed. To further increase the speed of programming data into the SLC pages, it is advantageous to program each data page to a designated SLC location while the next data page is transferred to the NAND.

[0043] Turn now Figure 9 An embodiment of method 80 for programming memory may include transferring a first data page P1 to the NAND at block 81, and programming the P1 data in the corresponding SLC location at block 82. Method 80 may then include transferring a second data page P2 to the NAND at block 83, and programming the P2 data in the corresponding SLC location at block 84. Method 80 may then include transferring a third data page P3 to the NAND at block 85, and programming the P3 data in the corresponding SLC location at block 86. Method 80 may then include transferring a fourth data page P4 to the NAND at block 87, and programming the P4 data in the corresponding SLC location at block 88. Method 80 may then include reading four pages P1, P2, P3, and P4 from within the SLC location corresponding to QLC WLn at block 89, and programming QLCWLn to a coarse state of level 16 based on the internally read four pages P1, P2, P3, and P4 at block 90. Subsequently, method 80 may include reading four pages P1, P2, P3, and P4 from the SLC location corresponding to QLC WLn at block 91, and programming QLC WLn to the 16-level final state at block 92 based on the internally read pages P1, P2, P3, and P4.

[0044] In some embodiments of method 80, the data may not be used directly to program the corresponding QLC WL to a level 16 state during the write operation. Instead (e.g., if initiated by a copy-back command), four data pages that may be needed to program the QLC WLn can be read from within the corresponding SLC location. The data can then be used to program the QLC WLn to a coarse level 16 state. Method 80 can then read four data pages that may be needed to program WLn+1 from within the corresponding SLC location and program the QLC WLn+1 to a coarse level 16 state. Subsequently, method 80 can again read the four pages needed to program the QLC WLn from within the specified SLC location and use the data to program the QLC WLn to the final level 16 state.

[0045] Although illustrative examples have been described in conjunction with a first-level cell portion corresponding to an SLC memory and a second-level cell portion corresponding to a QLC memory, other numbers of levels are possible within the scope of some embodiments. For example, some embodiments may include a first-level cell portion corresponding to an MLC memory. Similarly, some embodiments may benefit from a second-level cell portion corresponding to a TLC memory and / or more than 16 levels.

[0046] Turn now Figure 10 An embodiment of the electronic processing system 100 may include a computing system 101 coupled to a multi-level NAND device 102. The NAND device 102 may include a command and address state machine 103 coupled to a QLC block 104. The state machine 103 may also be coupled to a page mapping translator 105, which may be coupled to four SLC stripes A, B, C, and D. The number and / or size of the SLC stripes may be pre-configured or dynamically configured. The page mapping translator 105 may translate between QLC addresses and their corresponding SLC addresses. For example, the system 100 may determine and manage the SLC address corresponding to a specific QLC address. A storage device such as a solid-state drive (SSD) may include a controller chip and one or more NAND dies. In the system 100, the translation between QLC addresses and their corresponding SLC addresses may be performed within each NAND die.

[0047] Turn now Figure 11Embodiments of the electronic processing system 110 may include a computing system 111 coupled to a multi-level NAND device 112. The NAND device 112 may include a command and address state machine 113 coupled to a QLC block 114 and four SLC strips A, B, C, and D. The number and / or size of the SLC strips may be pre-configured or dynamically configured. The computing system 111 may include a page mapping translator 115. The page mapping translator 115 can translate between QLC addresses and corresponding SLC addresses. For example, the system 110 may determine and manage the SLC address corresponding to a specific QLC address. A storage device such as an SSD may include a controller chip and one or more NAND dies. In the system 110, the translation between QLC addresses and corresponding SLC addresses may be performed by the NAND controller in the computing system 111.

[0048] Additional notes and examples:

[0049] Example 1 may include an electronic processing system comprising: a processor; a multi-level NAND memory communicatively coupled to the processor, the multi-level NAND memory including a single-cell (SLC) portion and a quad-cell (QLC) portion; and a memory programmer communicatively coupled to the multi-level NAND memory for programming the multi-level NAND memory, wherein the memory programmer also programs the SLC portion in a first round, coarsely programs the QLC portion in a first round, and finely programs the QLC portion in a second round based on data programmed into the SLC portion in the first round.

[0050] Example 2 may include the system of Example 1, and also includes a page mapping translator whose communication is coupled to a multi-level NAND memory to translate addresses between the SLC section and the QLC section.

[0051] Example 3 may include the system of Example 2, wherein the page mapping translator is integrated on the same die as the multi-level NAND memory.

[0052] Example 4 may include a system that can be any of Examples 1 to 3, wherein the memory programmer also fine-programs the QLC section based on data stored in the SLC section after a power outage.

[0053] Example 5 may include a system of any of Examples 1 to 3, wherein the data programmed into the QLC section in the first round is unvalidated.

[0054] Example 6 may include a system that can include any of Examples 1 to 3, and also includes a page buffer that is communicatively coupled to a memory programmer to store data pages, wherein the memory programmer also programs the SLC portion based on the first data page stored in the page buffer while the second data page is being transferred to the page buffer.

[0055] Example 7 may include a memory programmer apparatus comprising: a first-level programmer for programming a first-level cell portion of a multi-level non-volatile memory in a first round; a coarse programmer for coarsely programming a second-level cell portion of the multi-level memory in the first round, wherein the second-level cell portion includes more voltage levels than the first-level cell portion; and a fine programmer for finely programming the second-level cell portion of the multi-level memory in a second round based on data programmed into the first-level cell portion in the first round.

[0056] Example 8 may include the apparatus of Example 7, and also includes a page mapping translator that is communicatively coupled to a first-level programmer, a coarse programmer, and a fine programmer to translate addresses between the first-level cell portion and the second-level cell portion.

[0057] Example 9 may include the apparatus of Example 8, wherein the page mapping translator is integrated on the same die as the multilevel memory.

[0058] Example 10 may include the apparatus of any of Examples 7 to 9, wherein the fine programmer also fine programs the second-level unit portion based on data stored in the first-level unit portion after a power outage.

[0059] Example 11 may include the apparatus of any of Examples 7 to 9, wherein the data programmed in the second-level unit section during the first round is unverified.

[0060] Example 12 may include the apparatus of any of Examples 7 to 9, and also includes a page buffer communicatively coupled to a first-level programmer to store data pages, wherein the first-level programmer also programs a portion of the first-level cell based on the first data page stored in the page buffer while a second data page is being transferred to the page buffer.

[0061] Example 13 may include a method for programming a memory, comprising: programming a first-level cell portion of a multi-level non-volatile memory in a first round; coarsely programming a second-level cell portion of the multi-level memory in the first round, wherein the second-level cell portion includes more levels than the first-level cell portion; and finely programming the second-level cell portion of the multi-level memory in a second round based on data programmed into the first-level cell portion in the first round.

[0062] Example 14 may include the method of Example 13, and may also include translating addresses between the first-level unit section and the second-level unit section.

[0063] Example 15 may include the method of Example 14, and may also include integrating address translation on the same die as the multilevel memory.

[0064] Example 16 may include the method of any of Examples 13 to 15, and may also include fine programming of the second-level unit section based on data stored in the first-level unit section after a power outage.

[0065] Example 17 may include the method of any of Examples 13 to 15, wherein the data programmed in the first round in the second-level unit section is unvalidated.

[0066] Example 18 may include the method of any of Examples 13 to 15, and may also include programming the first-level cell portion based on the first data page while the second data page is being transferred to the multi-level memory.

[0067] Example 19 may include at least one computer-readable medium comprising an instruction set that, when executed by a computing device, causes the computing device to: program a first-level cell portion of a multi-level memory in a first round; coarsely program a second-level cell portion of the multi-level memory in the first round, wherein the second-level cell portion includes more levels than the first-level cell portion; and finely program the second-level cell portion of the multi-level memory in a second round based on data programmed into the first-level cell portion in the first round.

[0068] Example 20 may include at least one computer-readable medium as described in Example 19, including an additional set of instructions that, when executed by a computing device, cause the computing device to translate addresses between a first-level unit portion and a second-level unit portion.

[0069] Example 21 may include at least one computer-readable medium as described in Example 20, including an additional instruction set that, when executed by a computing device, causes the computing device to integrate address translation on the same die as the multilevel memory.

[0070] Example 22 may include at least one computer-readable medium as described in any of Examples 19 to 21, including an additional set of instructions that, when executed by a computing device, cause the computing device to finely program a second-level unit portion based on data stored in the first-level unit portion after a power outage.

[0071] Example 23 may include at least one computer-readable medium as described in any of Examples 19 to 21, wherein the data programmed into the second-level unit portion in the first round is unverified.

[0072] Example 24 may include at least one computer-readable medium as described in any of Examples 19 to 21, including an additional set of instructions that, when executed by a computing device, cause the computing device to program a first-level cell portion based on the first data page while the second data page is transferred to a multi-level memory.

[0073] Example 25 may include a memory programmer apparatus comprising: means for programming a first-level cell portion of a multi-level memory in a first round; means for coarsely programming a second-level cell portion of the multi-level memory in the first round, wherein the second-level cell portion includes more levels than the first-level cell portion; and means for finely programming the second-level cell portion of the multi-level memory in a second round based on data programmed in the first-level cell portion in the first round.

[0074] Example 26 may include the means of Example 25, and also includes components for translating addresses between the first-level unit portion and the second-level unit portion.

[0075] Example 27 may include the apparatus of Example 26, and also includes components for integrating address translation on the same die as the multilevel memory.

[0076] Example 28 may include the means of any of Examples 25 to 27, and also includes components for finely programming the second-level unit portion based on data stored in the first-level unit portion after a power outage.

[0077] Example 29 may include the apparatus of any of Examples 25 to 27, wherein the data programmed in the second-level unit section during the first round is unverified.

[0078] Example 30 may include means of any of Examples 25 to 27, and further include components for programming a first-level cell portion based on the first data page while the second data page is being transferred to the multi-level memory.

[0079] The embodiments are applicable to all types of semiconductor integrated circuit (“IC”) chips. Examples of such IC chips include, but are not limited to, processors, controllers, chip assembly assemblies, programmable logic arrays (PLAs), memory chips, network chips, system-on-a-chip (SoC), SSD / NAND controller ASICs, etc. Furthermore, in some figures, lines are used to represent signal conductor lines. Some may differ to indicate more constituting signal paths, have numerical labels to indicate several constituting signal paths, and / or have arrows at one or more ends to indicate the primary direction of information flow. However, this should not be interpreted in a limiting manner. Rather, such added details may be used in conjunction with one or more exemplary embodiments to facilitate easier understanding of the circuit. Any signal line represented, whether or not it has additional information, may practically include one or more signals that can propagate in multiple directions and can be implemented using any suitable type of signaling scheme, such as digital or analog lines implemented using differential pairs, fiber optic lines, and / or single-ended lines.

[0080] Example dimensions / models / values / ranges may have been given, although the embodiments are not limited thereto. As manufacturing technologies (e.g., photolithography) mature over time, it is anticipated that smaller devices can be manufactured. Furthermore, known power / ground connections to the IC chip and other components may or may not be shown in the figures for the sake of simplicity in illustration and discussion, and to avoid obscuring certain aspects of the embodiments. Additionally, arrangements may be shown in block diagram form to avoid obscuring the embodiments, also given that details regarding the implementation of such block diagram arrangements are highly dependent on the platform in which the embodiments are to be implemented, i.e., such details should be well within the scope of those skilled in the art. In the context of setting forth specific details (e.g., circuitry) to describe exemplary embodiments, it will be apparent to those skilled in the art that the embodiments can be practiced without these specific details or using variations of these specific details. Therefore, the description is to be regarded as illustrative rather than restrictive.

[0081] The term “coupling” may be used herein to refer to any type of relationship (direct or indirect) between the components under discussion, and may apply to electrical, mechanical, fluid, optical, electromagnetic, electromechanical, or other connections. Furthermore, the terms “first,” “second,” etc., may be used herein for convenience only and do not imply a specific time or sequence unless otherwise indicated.

[0082] As used in this application and in the claims, a list of items linked by the term "one or more" can mean any combination of the listed items. For example, the phrase "one or more of A, B, and C" and the phrase "one or more of A, B, or C" can both mean A; B; C; A and B; A and C; B and C; or A, B, and C.

[0083] Those skilled in the art will appreciate from the foregoing description that a wide range of techniques can be implemented in various forms. Therefore, although embodiments have been described in conjunction with specific examples, the true scope of the embodiments should not be so limited, as other modifications will become apparent to those skilled in the art upon examination of the drawings, specification, and appended claims.

Claims

1. An electronic processing system comprising: a processor; a multi-level NAND memory communicatively coupled to the processor, the multi-level NAND memory comprising: a single-level cell (SLC) portion, and a quad-level cell (QLC) portion; and a memory programmer communicatively coupled to the multi-level NAND memory to program the multi-level NAND memory, wherein the memory programmer is further to: program data into the SLC portion in a first pass, coarsely program data into the QLC portion in the first pass, wherein the QLC portion comprises more voltage levels than the SLC portion and a sequence of program pulses is applied to a word line of the QLC portion without each program pulse being followed by a sequence of verify ladder sequences, wherein a first pulse of the sequence programs all cells in the word line except cells belonging to a L0 level, a second pulse of the sequence programs all cells in the word line except cells belonging to L0 and L1 levels, and a third pulse of the sequence programs all cells in the word line except cells belonging to L0, L1 and L2 levels, and fine program data into the QLC portion in a second pass from data programmed in the SLC portion in the first pass.

2. The system of claim 1, further comprising: a page map translator communicatively coupled to the multi-level NAND memory to translate addresses between the SLC portion and the QLC portion.

3. The system of claim 2, wherein the page map translator is integrated on the same die as the multi-level NAND memory.

4. The system of any one of claims 1 to 3, wherein the memory programmer is further to fine program the QLC portion from data stored in the SLC portion after a power interruption.

5. The system of any one of claims 1 to 3, wherein data programmed in the QLC portion in the first pass is unverified.

6. The system of any one of claims 1 to 3, further comprising: a page buffer communicatively coupled to the memory programmer to store a page of data, wherein the memory programmer is further to program the SLC portion from a first page of data stored in the page buffer at the same time a second page of data is transferred to the page buffer.

7. A memory programmer apparatus comprising: a first level programmer to program data into a first level cell portion of a multi-level non-volatile memory in a first pass; a coarse programmer to coarsely program data in a second level cell portion of a multi-level memory in a first pass, wherein the second level cell portion includes more voltage levels than a first level cell portion, and wherein the coarse programmer is configured to apply a sequence of program pulses to a word line of the second level cell portion without each program pulse being followed by a series of verify staircase sequences, wherein a first pulse of the sequence programs all cells in the word line except cells belonging to an L0 level, a second pulse of the sequence programs all cells in the word line except cells belonging to L0 and L1 levels, and a third pulse of the sequence programs all cells in the word line except cells belonging to L0, L1 and L2 levels; and a fine programmer to finely program data in the second level cell portion of the multi-level memory in a second pass according to data programmed in the first level cell portion in the first pass.

8. The apparatus of claim 7, further comprising: a page map translator communicatively coupled to the first level programmer, the coarse programmer and the fine programmer to translate addresses between the first level cell portion and the second level cell portion.

9. The apparatus of claim 8, wherein the page map translator is integrated on the same die as the multi-level memory.

10. The apparatus of any one of claims 7 to 9, wherein the fine programmer is further to finely program the second level cell portion according to data stored in the first level cell portion after a power interruption.

11. The apparatus of any one of claims 7 to 9, wherein the coarse programmer is to program unverified data in the second level cell portion in the first pass.

12. The apparatus of any one of claims 7 to 9, further comprising: a page buffer communicatively coupled to the first level programmer to store a page of data, wherein the first level programmer is further to program the first level cell portion according to a first page of data stored in the page buffer at the same time a second page of data is transferred to the page buffer.

13. A method of programming a memory, comprising: programming data in a first level cell portion of a multi-level memory in a first pass; coarsely programming data in a second level cell portion of the multi-level memory in the first pass, wherein the second level cell portion includes more levels than the first level cell portion, and wherein the coarse programming applies a sequence of program pulses to a word line of the second level cell portion without each program pulse being followed by a series of verify staircase sequences, wherein a first pulse of the sequence programs all cells in the word line except cells belonging to an L0 level, a second pulse of the sequence programs all cells in the word line except cells belonging to L0 and L1 levels, and a third pulse of the sequence programs all cells in the word line except cells belonging to L0, L1 and L2 levels; and finely programming data in the second level cell portion of the multi-level memory in a second pass according to data programmed in the first level cell portion in the first pass.

14. The method of claim 13, further comprising: translate addresses between the first level cell portion and the second level cell portion.

15. The method of claim 14, further comprising: integrating the address translation on the same die as the multi-level memory.

16. The method of any one of claims 13 to 15, further comprising: fine programming the second level cell portion after a power interruption according to data stored in the first level cell portion.

17. The method of any one of claims 13 to 15, wherein the coarse programming comprises programming unverified data into the second level cell portion in the first pass.

18. The method of any one of claims 13 to 15, further comprising: programming the first level cell portion according to a first data page at the same time as a second data page is transferred to the multi-level memory.

19. A memory programmer apparatus, comprising: means for programming data into a first level cell portion of a multi-level memory in a first pass; means for coarse programming data into a second level cell portion of the multi-level memory in the first pass, wherein the second level cell portion comprises more levels than the first level cell portion, and wherein the coarse programming applies a sequence of programming pulses to a word line of the second level cell portion without following each program pulse with a sequence of verify staircase sequences, wherein a first pulse of the sequence programs all cells in the word line except cells belonging to an L0 level, a second pulse of the sequence programs all cells in the word line except cells belonging to L0 and LI levels, and a third pulse of the sequence programs all cells in the word line except cells belonging to L0, LI and L2 levels; and means for fine programming data into the second level cell portion of the multi-level memory according to data programmed in the first level cell portion in the first pass in a second pass.

20. The apparatus of claim 19, further comprising: means for translating addresses between the first level cell portion and the second level cell portion.

21. The apparatus of claim 20, further comprising: means for integrating the address translation on the same die as the multi-level memory.

22. The apparatus of any one of claims 19 to 21, further comprising: means for fine programming the second level cell portion after a power interruption according to data stored in the first level cell portion.

23. The apparatus of any one of claims 19 to 21, wherein unverified data is programmed into the second level cell portion in the first pass.

24. The apparatus of any one of claims 19 to 21, further comprising: means for programming the first level cell portion according to a first data page at the same time as a second data page is transferred to the multi-level memory.

25. A computer readable medium having stored thereon instructions which, when executed by a computing device, cause the computing device to perform the method of any one of claims 13 to 18.

26. A computer program product comprising instructions which, when executed by a processor, cause the processor to carry out the method of any one of claims 13 to 18.

Images