Techniques for caching persistent secondary storage data

Abstract

A technique for caching persistent secondary memory (2LM) data includes a memory and a processor. The memory includes a volatile memory device and a non-volatile memory device. The processor determines a persistent memory address space for persistent 2LM data and determines one or more non-volatile memory devices to which the persistent memory address space is mapped. The processor further configures the persistent memory address space of the non-volatile memory device to operate in a persistent 2LM mode, and further configures an operating system to cache access to the persistent memory address space in the volatile memory.

Description

Technical Field

[0001] The present invention relates to techniques for caching persistent secondary storage data. Background Art

[0002] Generally, memory used to store data in a computing system can be volatile to store volatile data or non-volatile to store persistent data. Volatile data cached in volatile memory is often used as temporary data to support the functionality of a program during the program's runtime. On the other hand, persistent data structures stored in non-volatile or persistent memory are available outside of the program's runtime and can be reused across power cycles.

[0003] As computing power increases in processors, one concern is the speed at which persistent memory can be accessed by the processor. With current non-volatile memory technology, persistent memory can be directly accessible by the processor to perform write and read operations; however, because non-volatile memory is far memory, the latency of the far memory can have a direct impact on overall system performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The concepts described herein are illustrated in the accompanying drawings by way of example and not by way of limitation. For simplicity and clarity of illustration, the elements illustrated in the drawings are not necessarily drawn to scale. Where appropriate, reference numerals have been repeated in the various figures to indicate corresponding or similar elements.

[0005] Figure 1 is a simplified block diagram of at least one embodiment of a computing device for caching persistent secondary memory (2LM) data;

[0006] Figure 2 It can be done by Figure 1 A simplified block diagram of at least one embodiment of an environment for establishing a computing device;

[0007] Figure 3 It can be done by Figure 1 and 2 A simplified flowchart of at least one embodiment of a method for setting up a cache for persistent 2LM data performed by a computing device of;

[0008] Figure 4 It can be done by Figure 1 and 2 A simplified flowchart of at least one embodiment of a method for performing persistent 2LM data operations performed by a computing device of

[0009] Figure 5 It can be done by Figure 1 and 2A simplified flow chart of at least one embodiment of a method for system shutdown performed by a computing device of the present invention. DETAILED DESCRIPTION

[0010] Although the concept of the present disclosure is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and will be described in detail herein. However, it should be understood that it is not intended to limit the concept of the present disclosure to the specific form disclosed, but on the contrary, it is intended to cover all modifications, equivalents and alternatives consistent with the present disclosure and the appended claims.

[0011] References in the specification to "one embodiment," "an embodiment," "an illustrative embodiment," and the like indicate that the described embodiment may include a particular feature, structure, or characteristic, but each embodiment may or may not necessarily include the particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is considered to be within the knowledge of those skilled in the art to implement such feature, structure, or characteristic in conjunction with other embodiments, whether or not explicitly described. Additionally, it should be appreciated that an item included in a list in the form of "at least one of A, B, and C" may mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C). Similarly, an item listed in the form of "at least one of A, B, or C" may mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C).

[0012] In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried by or stored on a transient or non-transient machine-readable (e.g., computer-readable) storage medium, which may be read and executed by one or more processors. A machine-readable storage medium may be embodied as any storage device, mechanism, or other physical structure for storing or transmitting information in a form that can be read by a machine (e.g., a volatile or non-volatile memory, a media disk, or other media device).

[0013] In the drawings, some structural or method features may be shown in a specific arrangement and / or order. However, it should be appreciated that such specific arrangement and / or order may not be required. More specifically, in some embodiments, such features may be arranged in a manner and / or order different from that shown in the illustrative figures. In addition, the inclusion of structural or method features in a particular figure does not mean that such features are required in all embodiments, and such features may not be included in some embodiments or may be combined with other features.

[0014] As in Figure 1 , an illustrative computing device 100 for caching persistent secondary memory (2LM) data includes a processor 102 and a memory 104 divided into two levels. One level, referred to as "near memory", includes volatile memory 130. The second level, referred to as "far memory", is embodied as a relatively slower memory (e.g., lower bandwidth and / or higher latency) than the near memory (e.g., volatile memory 130), and includes non-volatile memory 140 in this illustrative embodiment. In other embodiments, the far memory may be volatile. The far memory is presented as main memory to an operating system executed by the processor 102, while the near memory is transparent to the operating system. In operation, and as explained in more detail herein, the near memory can act as a cache for the far memory, thereby providing the processor 102 with faster access to data than would be possible if the data existed only in the far memory. Further, and as described in more detail below, in use, the processor 102 is configured to set up a cache of persistent data associated with the application 122, which is mapped to the persistent memory address space of the non-volatile memory 140. To do so, the processor 102 configures the persistent memory address space to operate in a persistent secondary memory (2LM) mode. As further described below, the persistent 2LM mode provides direct access to the non-volatile memory 140 to store and / or load persistent 2LM data and further allows the operating system to cache access to the persistent memory address space in the volatile memory 130 without implementing any changes to the hardware components of the computing device 100.

[0015] The processor 102 may be embodied as any type of processor capable of performing the functions described herein. For example, the processor 102 may be embodied as (one or more) single-core or multi-core processors, digital signal processors, field programmable gate arrays (FPGAs), microcontrollers, or other processors or processing / control circuits. Similarly, the memory 104 may be embodied as any type of volatile and / or non-volatile memory or data storage device capable of performing the functions described herein. In some embodiments, the processor 102 and memory 104 may form part of a system on chip (SoC) and be incorporated onto a single integrated circuit chip along with other components of the computing device 100.

[0016] The memory 104 is communicatively coupled to the processor 102 via an I / O subsystem 106, which may be embodied as circuitry and / or components used to facilitate input / output operations with the processor 102, the memory 104, and other components of the computing device 100. For example, the I / O subsystem 106 may be embodied as or otherwise include a memory controller hub, an input / output control hub, a firmware device, communication links (i.e., point-to-point links, bus links, wires, cables, optical guides, printed circuit board traces, etc.), and / or other components and subsystems used to facilitate input / output operations. In some embodiments, the I / O subsystem 106 may form part of a system on a chip (SoC) and be incorporated on a single integrated circuit chip along with the processor 102, the memory 104, and other components of the computing device 100.

[0017] The internal memory controller 120 may be embodied as a collection of any type of control device, circuit system, or hardware device capable of writing data to the memory 104, reading data from the memory 104, locating data from the memory 104, and replacing data from the memory 104. In this illustrative embodiment, the internal memory controller 120 is configured to control memory accesses to the volatile memory 130 and the non-volatile memory 140. To do so, the internal memory controller 120 may control the source address decoder and the target address decoder of the processor 102 by switching between different operating modes for the memory address space. It should be appreciated that the memory address space is a set of discrete logical addresses, each of which may correspond to a different physical memory address in the volatile memory 130 and / or the non-volatile memory 140. By configuring operating modes for logical addresses, the internal memory controller 120 can control memory access to one or more volatile and non-volatile memory devices 132, 142 and implement caching of persistent 2LM data (e.g., in the volatile memory 130), which would normally only be stored in and accessed from the non-volatile memory 140.

[0018] The memory 104 may be embodied as any type of data storage device capable of storing data. In the illustrative embodiment, the memory 104 includes a volatile memory 130 controlled by a volatile memory controller 134 and a non-volatile memory 140 controlled by a non-volatile memory controller 144. It should be appreciated that the volatile memory controller 134 and the non-volatile memory controller 144 are configured to communicate with the internal memory controller 120. For example, the volatile memory controller 134 is configured to receive application data instructions for execution and cache application data in the volatile memory 130. On the other hand, the non-volatile memory controller 134 is configured to receive application data instructions for execution and store application data in the non-volatile memory 140. In some embodiments, the VM controller 134 and / or the NVM controller 144 may form part of other components of the computing device 100, such as the I / O subsystem 106.

[0019] The volatile memory 130 may be embodied as any type of data storage device capable of storing data when power is supplied to the volatile memory 130. For example, in this illustrative embodiment, the volatile memory 130 is embodied as one or more volatile memory devices 132 and is periodically referred to as volatile memory 130 below with the understanding that in other embodiments the volatile memory 130 may be embodied as other types of non-persistent data storage devices. The volatile memory devices of the volatile memory 130 may be embodied as any storage medium that requires power to maintain the state of the data stored by the medium. Non-limiting examples of volatile memory may include various types of random access memory (RAM), such as dynamic random access memory (DRAM) or static random access memory (SRAM). One specific type of DRAM that may be used in a memory module is a synchronous dynamic random access memory (SDRAM). In a particular embodiment, the DRAM of the memory component may comply with a standard promulgated by JEDEC, such as JESD79F for DDR SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, JESD79-4A for DDR4 SDRAM, JESD209 for Low Power DDR (LPDDR), JESD209-2 for LPDDR2, JESD209-3 for LPDDR3, and JESD209-4 for LPDDR4 (these standards are available at www.jedec.org). Such standards (and similar standards) may be referred to as DDR-based standards and the communication interface of a storage device implementing such standards may be referred to as a DDR-based interface.

[0020] The non-volatile memory 140 may be embodied as any type of data storage device that can store data in a persistent manner even if power to the non-volatile memory 140 is interrupted. For example, in this illustrative embodiment, the non-volatile memory 140 is embodied as one or more non-volatile memory devices 142. The non-volatile memory device 142 is illustratively embodied as a byte-addressable or block-addressable write-in-place non-volatile memory device. In some embodiments, the non-volatile memory device 142 may be arranged in levels. It should be appreciated that the non-volatile memory devices 142 in each level are connected to the same communication channel.

[0021] Each nonvolatile memory device 142 may be embodied as a block-addressable memory device, such as those based on NAND or NOR technology. Nonvolatile memory devices 142 may also include future generation nonvolatile devices, such as three-dimensional cross-point memory devices, or other byte-addressable write-in-place nonvolatile memory devices. In one embodiment, the non-volatile memory device 142 may be or may include a memory device that uses chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single-level or multi-level phase change memory (PCM), resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), antiferroelectric memory, magnetoresistive random access memory (MRAM) memory that merges memristor technology, resistive memory including metal oxide-based, oxygen vacancy-based and conductive bridge random access memory (CB-RAM), or spin transfer torque (STT)-MRAM, a device based on spin magnetic junction memory, a device based on magnetic tunneling junction (MTJ), a device based on DW (domain wall) and SOT (spin orbit transfer), a thyristor-based memory device, or any combination of the above, or other memory. The memory device may refer to the die itself and / or the packaged memory product. In some embodiments, a 3D cross point memory may include a transistor-less stackable cross point architecture in which memory cells are located at the intersections of word lines and bit lines and are individually addressable and in which bit storage is based on changes in bulk resistance.

[0022] The data storage device 108 may be embodied as one or more devices of any type configured for short-term or long-term data storage, such as, for example, memory devices and circuits, memory cards, hard disk drives, solid-state drives, or other data storage devices. The data storage device 108 may be incorporated into or form a part of one or more other components of the computing device 100. For example, the data storage device 108 may be embodied as the main memory 104, or otherwise included in the main memory 104. Additionally or alternatively, the data storage device 108 may be embodied as or otherwise included in a solid-state drive of the computing device 100. Further, in some embodiments, the data storage device 108 may be embodied as or otherwise included in a hard disk drive of the computing device 100. Of course, in other embodiments, the data storage device 108 may be included in or form a part of other components of the computing device 100.

[0023] The peripherals 110 may include any number of input / output devices, user interface devices, and / or externally connected peripherals. For example, in some embodiments, the peripherals 110 may include a display, a touch screen, a graphics circuit system, a keypad, a keyboard, a mouse, a speaker system, and / or other input / output devices, interface devices, and / or peripherals. Additionally or alternatively, the peripherals 110 may include one or more ports (such as USB ports), for example, for connecting external peripherals to the computing device 100.

[0024] Reference now Figure 2 , in use, the computing device 100 can establish an environment 200. The illustrative environment 200 includes a mode determiner 210, a memory mapper 220, an interface manager 230, and a command issuer 240. The memory mapper 220 further includes an address distributor 222 and an address decoder 224. Further, the command issuer 240 includes a data reader 242 and a data writer 244. In addition, the illustrative environment 200 includes a memory map 250, cached data 260, and persistent 2LM data 270. Each of the components of the environment 200 can be embodied as firmware, software, hardware, or a combination thereof. For example, the logic and other components of the environment 200 can form part of the computing device 100 or other hardware components of the computing device 100 or be otherwise established by the computing device 100 or other hardware components of the computing device 100. As such, in some embodiments, any one or more of the components of environment 200 may be embodied as a collection of circuits or electrical devices (eg, memory mode determiner circuit 210, memory mapper circuit 220, interface manager circuit 230, command issuer circuit 240, etc.).

[0025] The mode determiner 210, which may be embodied as hardware, firmware, software, virtualized hardware, emulation architecture, and / or combinations thereof as described above, is configured to determine different configurable operating modes for memory addresses within a memory address space. As described above, the memory address space includes a set of logical addresses corresponding to physical addresses in the volatile memory 130 and / or the non-volatile memory 140. By configuring an operating mode for each logical memory address or range thereof, the mode determiner 210 may control memory access to one or more of the volatile and non-volatile memory devices 132, 142. For example, in this illustrative embodiment, the operating modes include a cache mode, a non-cache memory mode, and a persistent 2LM mode, thereby resulting in different types of memory address spaces within the main memory address space presented to the operating system and other software, including a volatile memory address space, a non-volatile memory address space, and a persistent memory address space. Typically, the volatile memory address space is configured to operate in a cache mode, the non-volatile memory address space is configured to operate in a non-cache mode, and the persistent memory address space is typically configured to operate in a non-cache mode. However, in this illustrative embodiment, the persistent memory address space is configured to operate in a persistent 2LM mode, which is described in detail below. It should be appreciated that other embodiments may provide other modes of operation that result in other types of memory address spaces within the main memory address space.

[0026] In use, when the internal memory controller 120 receives a data instruction (e.g., write or read) from an application 122 mapped to a memory address space, the internal memory controller 120 can determine which memory (i.e., volatile memory 130 or non-volatile memory 140) to access to execute the data instruction based on the operating mode for the memory address space. For example, if the memory address of the requested data instruction is mapped to a volatile memory address space that can operate in a cache mode, the requested data instruction is directed to the volatile memory 130 for execution. However, if the memory address of the requested data instruction is mapped to a non-volatile memory address space that can operate in a non-cache memory mode, the requested data instruction bypasses the volatile memory 130 and is directed to the non-volatile memory 140 for execution. Alternatively, if the memory address of the requested data instruction is mapped to a persistent memory address space that can operate in a persistent 2LM mode, the requested data instruction is directed to the volatile memory 130 and / or the non-volatile memory 140 for execution, as described in detail below.

[0027] The memory mapper 220, which may be embodied as hardware, firmware, software, virtualized hardware, emulation architecture, and / or combinations thereof as described above, is configured to generate a memory map 250 that includes a memory address space within a main memory address space and a corresponding operating mode. As described below, in this illustrative embodiment, the memory map 250 is used to determine whether an application data instruction received from an application requires that the application data be persistent after execution. For example, the memory map 250 may indicate that the memory address to which the application data instruction is mapped is configured to operate in a cache mode, a non-cacheable memory mode, or a persistent 2LM mode. To do this, the memory mapper 220 includes an address allocator 222 and an address decoder 224.

[0028] In this illustrative embodiment, the address allocator 222 is configured to provide address interleaving that maps contiguous logical memory addresses to physical addresses allocated across multiple memory devices, such as multiple volatile memory devices 132 or multiple non-volatile memory devices 142. For example, a first logical memory address may be mapped to a first physical memory address in one of the volatile memory devices 132, and a second logical memory address may be mapped to a second physical memory address in a second of the volatile memory devices 132, and so on.

[0029] The address decoder 224 is configured to change the memory mode of the memory address space to a different memory mode so that the operating system can use the memory address space configured to operate in one memory mode in another memory mode without implementing any changes to the hardware components of the computing device 100. For example, in this illustrative embodiment, the address decoder 224 allows the processor 102 and software to use the memory address space configured to operate in the persistent 2LM mode in a cached volatile memory so that memory accesses are cached in the persistent memory address space in the volatile memory 130.

[0030] In use, when the internal memory controller 120 receives a data request from an application 122, the memory mapper 220 determines the memory address space to which the application data instruction is mapped, and further determines which memory mode corresponds to the determined memory address space. For example, if the memory mapper 220 determines that the logical address associated with the requested data instruction is mapped to a memory address space configured to operate in a cache mode, the internal memory controller 120 forwards the requested data instruction to the volatile memory controller 134 to access the corresponding physical address of the volatile memory 130 in order to execute the requested data instruction (i.e., write data to the volatile memory 130 or read data from the volatile memory 130) for execution.

[0031] However, if the memory mapper 220 determines to map the requested data instruction to a memory address space configured to operate in a non-cache memory mode, the internal memory controller 120 forwards the requested data instruction to the non-volatile memory controller 144 to access the corresponding physical memory address of the non-volatile memory 140 in order to execute the requested data instruction (i.e., write data to the non-volatile memory 140 or read data from the non-volatile memory 140).

[0032] Alternatively, if the memory mapper 220 determines to map the requested data instruction to a memory address space configured to operate in the persistent 2LM mode, the internal memory controller 120 may forward the requested data instruction to the non-volatile memory controller 144 and the volatile memory controller 134. As such, the requested data instruction may be executed in the volatile and non-volatile memories 130, 140 (i.e., persistent data may be written to or read from the volatile and non-volatile memories 130, 140), as described in detail below.

[0033] The interface manager 230 is configured to process various instructions, including but not limited to data storage instructions and data read instructions received from a host (which may be embodied as an application, service, and / or other device). In some embodiments, the interface manager 230 may be configured to also process other instructions, including self-monitoring, analysis, and reporting technology ("SMART") instructions, and other instructions defined in the non-volatile memory interface ("NVMe") specification. NVMe is a logical device interface for accessing non-volatile storage media attached via a peripheral component interconnect interface (PCIe) bus. The non-volatile storage medium may include flash memory and a solid-state drive (SSD). It should be appreciated that NVMe is designed to access low-latency storage devices in computer systems (including personal and enterprise computer systems), and is also deployed in data centers that need to scale thousands of low-latency storage devices. In order to process various instructions, the interface manager 230 is configured to identify the received instructions and any data and / or parameters associated with the instructions, and transmit those items to the mode determiner 210. For example, in response to a read command, the interface manager 230 transmits the data read by the data manager 230 to the host.

[0034] The command issuer 240, which may be embodied as hardware, firmware, software, virtualized hardware, emulation architecture, and / or a combination thereof, is configured to manage the reading of data from the volatile memory device 132 of the volatile memory 130 and / or the non-volatile memory device 142 of the non-volatile memory 140 and the writing of data to the volatile memory device 132 of the volatile memory 130 and / or the non-volatile memory device 142 of the non-volatile memory 140. To do so, the command issuer 240 includes a data reader 242 and a data writer 244.

[0035] The data reader 242 is configured to read data from the volatile memory device(s) 132 and / or the non-volatile memory device(s) 142 in response to an application read instruction. As described above, whether the volatile memory 130 or the non-volatile memory 140 is accessed depends on the memory address of the requested application read instruction.

[0036] The data writer 244 is configured to write data to the volatile memory device(s) 132 and / or the non-volatile memory device(s) 142 in response to an application write instruction. As described above, whether to access the volatile memory 130 or the non-volatile memory 140 depends on the memory address of the requested application write instruction.

[0037] In addition, the illustrative environment 200 includes memory map data 250, cache data 260, and persistent 2LM data 270. The memory map data 250 can be embodied as any data indicating one or more memory maps including (one or more) memory address spaces and (one or more) corresponding operating modes. The memory map 250 can be accessed by modules and / or sub-modules of the computing device 100.

[0038] The cache data 260 may be embodied as any cache data generated by the execution of application data instructions and stored in the volatile memory 130. For example, as described above, application data instructions, which are mapped to a memory address space operable in cache mode and / or persistent 2LM mode, are executed and cached in the volatile memory 130.

[0039] The persistent 2LM data 270 may be embodied as any data generated by the execution of persistent 2LM data instructions and stored in the non-volatile memory 140 when executed. For example, as described above, application data instructions, which are mapped to a memory address space operable in persistent 2LM mode, are executed and stored in the non-volatile memory 140.

[0040] Reference now Figure 3 In use, the processor 102 may perform a method 300 for configuring an operating system executed by the computing device 100 to cache accesses to a persistent memory address space in the volatile memory 130. The method 300 begins at block 302, where the processor 102 determines whether to set a cache for application data that will be persistent by configuring an operating mode for the corresponding memory address space. In some embodiments, the processor 102 determines whether to set a cache for persistent 2LM data based on the type of application and / or the type of application data. If the processor 102 determines not to set a cache for persistent 2LM data, the method 300 loops back to block 302 to continue determining whether to set a cache for persistent 2LM data.

[0041] However, if the processor 102 determines to set a cache for persistent 2LM data, the method 300 proceeds to block 304. In block 304, the processor 102 determines a persistent memory address space within the nonvolatile memory address space for storage of persistent data, and further determines one or more corresponding nonvolatile memory devices configured to contain the persistent memory address space. In other words, the processor 102 determines one or more nonvolatile memory devices configured to contain persistent 2LM data.

[0042] In block 306, the processor 102 configures the determined persistent memory address space of the determined non-volatile memory device(s) to operate in persistent 2LM mode. In some embodiments, the processor 102 may set address interleaving to distribute memory addresses of the memory address space across multiple non-volatile memory devices 142 in block 308. Alternatively, the processor 102 may update an existing address interleaving to further distribute memory addresses of the persistent memory address space across multiple non-volatile memory devices 142.

[0043] Additionally or alternatively, in some embodiments, in block 310, the processor 102 may generate an address map including a memory address and a corresponding operating mode for each memory address. Alternatively, the processor 102 may update an existing address map in order to update those memory addresses that are now configured to operate in persistent 2LM mode. For example, as described above, the address map may indicate whether a memory address included in an application data instruction is configured to operate in cache mode, non-cache memory mode, or persistent 2LM mode. As described above, application data instructions that include memory addresses mapped to a non-volatile memory address space are generally directed to the non-volatile memory 140 for execution and persistent storage. On the other hand, application data instructions that include memory addresses mapped to a persistent memory address space are directed both to the non-volatile memory 140 for persistent storage and to the volatile memory 130 for caching persistent 2LM data.

[0044] Additionally or alternatively, in some embodiments, the processor 102 may set at least one block window that defines at least one address range for accessing one or more blocks of persistent 2LM data that may be stored within the non-volatile memory device(s) 142 .

[0045] In block 312, the processor 102 and software are configured to cache accesses to the persistent memory address space in the volatile memory 130. In other words, the processor 102 is configured to cache the persistent 2LM data in the volatile memory 130 while processing the persistent 2LM data in accordance with the persistent 2LM mode in the non-volatile memory 140. To do so, in block 314, the processor 102 is configured to cache the persistent 2LM data in the volatile memory 130. In some embodiments, in block 316, the internal memory controller 102 of the processor 102 may configure one or more address decoders to change the operating mode of the memory address. For example, the address decoder may convert the persistent 2LM mode of the persistent memory address space to a cache memory mode.

[0046] In block 318 , the processor 102 further reports the persistent memory address space as a volatile area to the operating system so that application instructions mapped to the persistent memory address space are executed and corresponding data are cached in the volatile memory 130 .

[0047] In block 320, the processor 102 tracks the persistent memory address space and the cached volatile memory address space. The processor 102 is configured to generate a memory management map of the persistent memory address space and the volatile memory address space to track persistent 2LM data. In block 322, the processor 102 updates the memory management map.

[0048] Reference now Figure 4 In use, the processor 102 of the computing device 100 may perform a method 400 for executing persistent 2LM data instructions. The method 400 begins at block 402, where the processor 102 determines whether a data operation request has been received. If the processor 102 determines that a data operation request has not been received, the method 400 loops back to block 402 to continue monitoring application data operation requests. However, if the processor 102 determines that a data operation request has been received, the method 400 proceeds to block 404.

[0049] In block 404, the internal memory controller 120 determines whether the memory address of the received data operation request is mapped to the volatile memory address space. If the processor 102 determines to map the data operation request to the volatile memory address space, the method 400 proceeds to block 406, where the processor 102 executes the data operation request and caches the requested data in the corresponding volatile memory device 132 of the volatile memory 130 based on the address mapping.

[0050] However, if the processor 102 determines not to map the data operation request to the volatile memory address space, the method 400 proceeds to block 408. In block 408, the processor 102 determines whether the requested data is persistent 2LM data. To do so, in block 410, the processor 102 determines whether to map the memory address of the requested data to the persistent memory address space of the non-volatile memory device 142 based on the address mapping.

[0051] If the processor 102 determines in block 412 that the requested data is not persistent 2LM data (e.g., the memory address of the requested data is not mapped to the persistent memory address space), the method 400 proceeds to block 414. In block 414, the processor 102 executes the data operation request and stores the requested data in the corresponding non-volatile memory device 142 of the non-volatile memory 140.

[0052] However, if the processor 102 determines in block 412 that the requested data is persistent 2LM data, the method 400 proceeds to block 416. In block 416, the processor 102 executes the received data operation request. To do so, in block 418, the internal memory controller 120 of the processor 102 directs the data operation request to the volatile memory controller 134 to execute the data operation request and cache the persistent 2LM data in the corresponding volatile memory device 132 of the volatile memory 130.

[0053] In addition, in block 420, the internal memory controller 120 of the processor 102 directs the data operation request to the non-volatile memory controller 144 to execute the data operation request and store the persistent 2LM data in the corresponding non-volatile memory device 142 of the non-volatile memory 140. For example, in block 422, the non-volatile memory controller 144 may write the persistent 2LM data cached in the volatile memory 130 to the corresponding address of the non-volatile memory device 142 of the non-volatile memory 140 in response to receiving a write data instruction from the application.

[0054] Alternatively, in block 422 , the nonvolatile memory controller 144 may read the persistent 2LM data from the corresponding address of the nonvolatile memory device 142 of the nonvolatile memory 140 in response to receipt of a read data instruction from the application program.

[0055] In some embodiments, in the event that volatile memory 130 overflows, persistent 2LM data stored in volatile memory 130 may be written to non-volatile memory 140. In other embodiments, if persistent 2LM data is not found in volatile memory 130, the requested persistent 2LM data may be read from non-volatile memory 140.

[0056] In some embodiments, persistent 2LM data may be committed from volatile memory 130 to nonvolatile memory 140 in response to receipt of a shutdown signal. Figure 5 Additionally or alternatively, persistent 2LM data may be periodically committed from volatile memory 130 to nonvolatile memory 140 .

[0057] Reference now Figure 5In use, the processor 102 of the computing device 100 may execute a method 500 for flushing the persistent 2LM data 270 cached in the volatile memory 130 to the non-volatile memory 140. The method 500 begins at block 502, where the processor 102 determines whether a system shutdown request has been received. If the processor 102 determines that a system shutdown request has not been received, the method 500 loops back to block 502 to continue monitoring for a system shutdown request. However, if the processor 102 determines that a system shutdown request has been received, the method 500 proceeds to block 504.

[0058] In block 504, the processor 102 issues a write-back and flush operation request before shutting down the system. In block 506, in response to receiving the write-back and flush operation request, the processor 102 flushes the persistent 2LM data 270 stored in the volatile memory 130 to the non-volatile memory 140. To do so, in some embodiments, as indicated in block 508, the processor 102 may serialize and execute any and all queued data instructions received prior to the shutdown request. Once the instructions in the queue are exhausted, the processor 102 may read the volatile memory address in block 510 to flush all modified cached data of the persistent memory address space to the non-volatile memory 140. Once the persistent 2LM data 270 cached in the volatile memory 130 is stored in the non-volatile memory 140, the method 500 proceeds to block 512 to shut down the system.

[0059] References to memory devices can apply to different memory types, and in particular any memory with a bank group architecture. Memory devices generally refer to volatile memory technology. Volatile memory is memory whose state (and therefore the data stored thereon) is indeterminate if power to the device is interrupted. Non-volatile memory refers to memory whose state is determined even if power to the device is interrupted. Dynamic volatile memory requires refreshing of the data stored in the device to maintain the state. An example of dynamic volatile memory includes DRAM (dynamic random access memory), or some variants such as synchronous DRAM (SDRAM). The memory subsystem as described herein may be compatible with many memory technologies and technologies based on derivatives or extensions of such specifications, such as DDR4 (DDR version 4, an initial specification disclosed by JEDEC in September 2012), DDR4E (under development by JEDEC), LPDDR4 (Low Power Double Data Rate (LPDDR) version 4, JESD209-4, originally disclosed by JEDEC in August 2014), WIO 2 (Wide I / O 2 (WideIO2), JESD229-2, originally disclosed by JEDEC in August 2014), HBM (High Bandwidth Memory DRAM, JESD235, originally disclosed by JEDEC in October 2013), DDR5 (DDR version 5, currently under discussion by JEDEC), LPDDR5 (currently under discussion by JEDEC), HBM2 (HBM version 2, currently under discussion by JEDEC), and the like.

[0060] In addition to or as an alternative to volatile memory, in one embodiment, reference to a memory device may refer to a non-volatile memory device whose state is determined even if power to the device is interrupted.

[0061] This application provides the following technical solutions:

[0062] 1. One or more machine-readable storage media comprising a plurality of instructions stored thereon that, when executed by a computing device, cause the computing device to:

[0063] determining a persistent memory address space for persistent 2LM data and one or more non-volatile memory devices to which the persistent memory address space is mapped, wherein each non-volatile memory device contains persistent 2LM data;

[0064] configuring a persistent memory address space of the non-volatile memory device to operate in a persistent secondary memory (2LM) mode in which application data written to the persistent memory address space may be reused across power cycles; and

[0065] The operating system is configured to cache accesses to the persistent memory address space in volatile memory.

[0066] 2. One or more machine-readable storage media according to technical solution 1, wherein configuring the operating system to cache accesses to the persistent memory address space in the volatile memory includes configuring the address decoder to switch from a first operating mode for the persistent memory address space to a second operating mode for the persistent memory address space.

[0067] 3. One or more machine-readable storage media according to technical solution 2, wherein the first operating mode is a persistent 2LM mode for storing persistent 2LM data in a non-volatile memory, and the second operating mode is a cache mode for caching persistent 2LM data in one or more volatile memory devices.

[0068] 4. One or more machine-readable storage media according to technical solution 1, wherein the plurality of instructions, when executed, further cause the computing device to perform the following:

[0069] receiving a write data instruction for writing application data;

[0070] determining whether the write data instruction requires the application data to be persistent;

[0071] executing a write data instruction on a memory address of the write data instruction in response to determining that the application data is persistent;

[0072] caching the persistent 2LM data in corresponding volatile memory; and

[0073] The persistent 2LM data is stored in the corresponding non-volatile memory device.

[0074] 5. One or more machine-readable storage media according to technical solution 4, wherein determining whether application data needs to be persistent includes determining whether to map a memory address of a write data instruction to a persistent memory address space configured to operate in persistent 2LM mode.

[0075] 6. One or more machine-readable storage media according to technical solution 4, wherein storing the application data in the non-volatile memory device includes storing the modified application data cached in the volatile memory device to the non-volatile memory device.

[0076] 7. One or more machine-readable storage media according to technical solution 1, wherein the plurality of instructions, when executed, further cause the computing device to perform the following:

[0077] receiving a read data instruction for reading application data;

[0078] determining whether the read data instruction requires the application data to be persistent;

[0079] executing a read data instruction on a memory address of the read data instruction in response to determining that the application data is required to be persistent; and

[0080] Application data is cached in corresponding volatile memory devices.

[0081] 8. One or more machine-readable storage media according to technical solution 1, wherein determining one or more non-volatile memory devices to which the persistent memory address space is mapped includes determining one or more non-volatile write-in-place byte-addressable memory devices to which the persistent memory address space is mapped.

[0082] 9. One or more machine-readable storage media according to technical solution 1, wherein the multiple instructions, when executed, further cause the computing device to set address interleaving for mapping adjacent logical memory addresses across multiple non-adjacent physical addresses of one or more non-volatile memory devices.

[0083] 10. One or more machine-readable storage media according to technical solution 1, wherein the multiple instructions, when executed, further prompt the computing device to detect a system shutdown request, and write application data from one or more volatile memory devices to one or more non-volatile memory devices in response to detecting the system shutdown request.

[0084] 11. One or more machine-readable storage media according to technical solution 1, wherein the multiple instructions, when executed, further cause the computing device to serialize data instructions in the queue and execute the data instructions in response to detecting a system shutdown request.

[0085] Example.

[0086] Illustrative examples of the technology disclosed herein are provided below. Embodiments of the technology may include any one or more of the examples described below and any combination of the examples described.

[0087] Example 1 includes a computing device for caching persistent secondary memory (2LM) data, the computing device comprising: a memory comprising one or more volatile memory devices and one or more non-volatile memory devices; and a processor configured to: determine a persistent memory address space for persistent 2LM data and one or more non-volatile memory devices to which the persistent memory address space is mapped, wherein each non-volatile memory device contains persistent 2LM data; configure the persistent memory address space of the non-volatile memory device to operate in a persistent secondary memory (2LM) mode in which application data written to the persistent memory address space can be reused across power cycles; and configure an operating system to cache accesses to the persistent memory address space in volatile memory.

[0088] Example 2 includes the subject matter of Example 1, and wherein configuring the operating system to cache accesses to the persistent memory address space in the volatile memory includes configuring the address decoder to switch from a first operating mode for the persistent memory address space to a second operating mode for the persistent memory address space.

[0089] Example 3 includes the subject matter of any of Examples 1 and 2, and wherein the first operating mode is a persistent 2LM mode for storing persistent 2LM data in a non-volatile memory, and the second operating mode is a cache mode for caching the persistent 2LM data in one or more of the volatile memory devices.

[0090] Example 4 includes the subject matter of any of Examples 1-3, and wherein the processor further performs the following: receiving a write data instruction for writing application data; determining whether the write data instruction requires the application data to be persistent; executing the write data instruction on a memory address of the write data instruction in response to determining that the application data is persistent; caching the persistent 2LM data in a corresponding volatile memory; and storing the persistent 2LM data in a corresponding non-volatile memory device.

[0091] Example 5 includes the subject matter of any of Examples 1-4, and wherein determining whether the application data is required to be persistent comprises determining whether a memory address of a write data instruction is mapped to a persistent memory address space configured to operate in persistent 2LM mode.

[0092] Example 6 includes the subject matter of any of Examples 1-5, and wherein storing the application data in the non-volatile memory device comprises storing the modified application data cached in the volatile memory device to the non-volatile memory device.

[0093] Example 7 includes the subject matter of any of Examples 1-6, and wherein the processor further performs the following: receiving a read data instruction for reading application data; determining whether the read data instruction requires the application data to be persistent; executing the read data instruction on a memory address of the read data instruction in response to determining that the application data is required to be persistent; and caching the application data in a corresponding volatile memory device.

[0094] Example 8 includes the subject matter of any of Examples 1-7, and wherein determining one or more nonvolatile memory devices to which the persistent memory address space is mapped comprises determining one or more nonvolatile write-in-place byte-addressable memory devices to which the persistent memory address space is mapped.

[0095] Example 9 includes the subject matter of any of Examples 1-8, and wherein the processor further arranges for address interleaving to map contiguous logical memory addresses across a plurality of non-contiguous physical addresses of the one or more non-volatile memory devices.

[0096] Example 10 includes the subject matter of any of Examples 1-9, and wherein the processor further detects a system shutdown request, and writes the application data from the one or more volatile memory devices to the one or more non-volatile memory devices in response to detecting the system shutdown request.

[0097] Example 11 includes the subject matter of any of Examples 1-10, and wherein the processor is further to serialize the data instructions in the queue and execute the data instructions in response to detecting the system shutdown request.

[0098] Example 12 includes a method for caching persistent secondary memory (2LM) data, comprising: determining, by a computing device, a persistent memory address space for persistent 2LM data and one or more non-volatile memory devices to which the persistent memory address space is mapped, wherein each non-volatile memory device contains persistent 2LM data; configuring, by the computing device, the persistent memory address space of the non-volatile memory device to operate in a persistent secondary memory (2LM) mode, in which application data written to the persistent memory address space can be reused across power cycles; and configuring, by the computing device, an operating system to cache accesses to the persistent memory address space in volatile memory.

[0099] Example 13 includes the subject matter of Example 12, and wherein configuring the operating system to cache accesses to the persistent memory address space in the volatile memory comprises configuring the address decoder to switch from a first operating mode for the persistent memory address space to a second operating mode for the persistent memory address space.

[0100] Example 14 includes the subject matter of any of Examples 12 and 13, and wherein the first operating mode is a persistent 2LM mode for storing persistent 2LM data in a non-volatile memory, and the second operating mode is a cache mode for caching the persistent 2LM data in one or more of the volatile memory devices.

[0101] 15. The method of Example 12 further includes: receiving, by the computing device, a write data instruction for writing application data; determining, by the computing device, whether the write data instruction requires the application data to be persistent; executing, by the computing device and in response to determining that the application data is persistent, the write data instruction on a memory address of the write data instruction; caching, by the computing device, the persistent 2LM data in a corresponding volatile memory; and storing, by the computing device, the persistent 2LM data in a corresponding non-volatile memory device.

[0102] Example 16 includes the subject matter of any of Examples 12-15, and wherein determining whether the application data is required to be persistent comprises determining whether a memory address of a write data instruction is mapped to a persistent memory address space configured to operate in persistent 2LM mode.

[0103] Example 17 includes the subject matter of any of Examples 12-16, and wherein storing the application data in the non-volatile memory device comprises storing the modified application data cached in the volatile memory device to the non-volatile memory device.

[0104] Example 18 includes the subject matter of any of Examples 12-17, and further includes: receiving, by a computing device, a read data instruction for reading application data; determining, by the computing device, whether the read data instruction requires the application data to be persistent; executing, by the computing device and in response to determining that the application data is required to be persistent, the read data instruction on a memory address of the read data instruction; and caching, by the computing device, the application data in a corresponding volatile memory device.

[0105] Example 19 includes the subject matter of any of Examples 12-18, and wherein determining one or more non-volatile memory devices to which the persistent memory address space is mapped comprises determining one or more non-volatile write-in-place byte-addressable memory devices to which the persistent memory address space is mapped.

[0106] Example 20 includes the subject matter of any of Examples 12-19, and further includes arranging address interleaving to map contiguous logical memory addresses across a plurality of non-contiguous physical addresses of one or more non-volatile memory devices.

[0107] Example 21 includes the subject matter of any of Examples 12-20, and further includes detecting a system shutdown request, and writing application data from the one or more volatile memory devices to the one or more non-volatile memory devices in response to detecting the system shutdown request.

[0108] Example 22 includes the subject matter of any of Examples 12-21, and further comprises serializing the data instructions in the queue and executing the data instructions in response to detecting the system shutdown request.

[0109] Example 23 includes one or more machine-readable storage media including a plurality of instructions stored thereon that, when executed by a processor, cause the processor to perform the method of any of Examples 12-22.

[0110] Example 24 includes a computing device for caching persistent secondary memory (2LM) data, the computing device comprising one or more processors; one or more memory devices having a plurality of instructions stored therein, the plurality of instructions, when executed by the one or more processors, causing the computing device to perform the method of any one of Examples 12-22.

[0111] Example 25 includes a computing device comprising: a device for determining a persistent memory address space for persistent 2LM data and one or more non-volatile memory devices to which the persistent memory address space is mapped, wherein each non-volatile memory device contains persistent 2LM data; a device for configuring the persistent memory address space of the non-volatile memory device to operate in a persistent secondary memory (2LM) mode, in which application data written to the persistent memory address space can be reused across power cycles; and a device for configuring an operating system to cache accesses to the persistent memory address space in a volatile memory.

[0112] Example 26 includes the subject matter of Example 25, and wherein the means for configuring the operating system to cache accesses to the persistent memory address space in the volatile memory includes means for configuring the address decoder to switch from a first operating mode for the persistent memory address space to a second operating mode for the persistent memory address space.

[0113] Example 27 includes the subject matter of any of Examples 25 and 26, and wherein the first operating mode is a persistent 2LM mode for storing persistent 2LM data in a non-volatile memory, and the second operating mode is a cache mode for caching the persistent 2LM data in one or more of the volatile memory devices.

[0114] 28. The computing device of Example 25 further includes: a device for receiving a write data instruction for writing application data; a device for determining whether the write data instruction requires the application data to be persistent; a device for executing the write data instruction on a memory address of the write data instruction in response to determining that the application data is persistent; a device for caching persistent 2LM data in a corresponding volatile memory; and a device for storing the persistent 2LM data in a corresponding non-volatile memory device.

[0115] Example 29 includes the subject matter of any of Examples 25-28, and wherein the means for determining whether application data is required to be persistent comprises means for determining whether to map a memory address of a write data instruction to a persistent memory address space configured to operate in persistent 2LM mode.

[0116] Example 30 includes the subject matter of any of Examples 25-29, and wherein means for storing the application data in the non-volatile memory device comprises means for storing the modified application data cached in the volatile memory device to the non-volatile memory device.

[0117] Example 31 includes the subject matter of any of Examples 25-30, and further includes: an apparatus for receiving a read data instruction for reading application data; an apparatus for determining whether the read data instruction requires the application data to be persistent; an apparatus for executing the read data instruction on a memory address of the read data instruction in response to determining that the application data is required to be persistent; and an apparatus for caching the application data in a corresponding volatile memory device.

[0118] Example 32 includes the subject matter of any of Examples 25-31, and wherein the apparatus for determining one or more non-volatile memory devices to which the persistent memory address space is mapped includes apparatus for determining one or more non-volatile write-in-place byte-addressable memory devices to which the persistent memory address space is mapped.

[0119] Example 33 includes the subject matter of any of Examples 25-32, and further includes means for arranging address interleaving to map contiguous logical memory addresses across multiple non-contiguous physical addresses of one or more non-volatile memory devices.

[0120] Example 34 includes the subject matter of any of Examples 25-33, and further includes means for detecting a system shutdown request, and writing application data from one or more volatile memory devices to one or more non-volatile memory devices in response to detecting the system shutdown request.

[0121] Example 35 includes the subject matter of any of Examples 25-34, and further comprises means for serializing data instructions in a queue and executing the data instructions in response to detecting a system shutdown request.

Claims

1. A computing device for caching persistent secondary memory (2LM) data, comprising: a memory including one or more volatile memory devices and one or more non-volatile memory devices; as well as A processor that is used to: determining a persistent memory address space for persistent 2LM data and one or more non-volatile memory devices to which the persistent memory address space is mapped, wherein each non-volatile memory device contains persistent 2LM data; configuring a persistent memory address space of the non-volatile memory device to operate in a persistent secondary memory 2LM mode in which application data written to the persistent memory address space may be reused across power cycles; as well as The operating system is configured to cache data accessed to the persistent memory address space in volatile memory.

2. The computing device of claim 1 , wherein configuring the operating system to cache accesses to the persistent memory address space in the volatile memory comprises configuring an address decoder to switch from a first operating mode for the persistent memory address space to a second operating mode for the persistent memory address space.

3. The computing device of claim 2 , wherein the first operating mode is a persistent 2LM mode for storing persistent 2LM data in a non-volatile memory, and the second operating mode is a cache mode for caching persistent 2LM data in one or more of the volatile memory devices.

4. The computing device of claim 1 , wherein the processor further performs the following: receiving a write data instruction for writing application data; determining whether the write data instruction requires the application data to be persistent; executing a write data instruction on a memory address of the write data instruction in response to determining that the application data is persistent; caching the persistent 2LM data in the corresponding volatile memory; as well as The persistent 2LM data is stored in the corresponding non-volatile memory device. 5 . The computing device of claim 4 , wherein determining whether the application data is required to be persistent comprises determining whether a memory address of a write data instruction is mapped to a persistent memory address space configured to operate in persistent 2LM mode. 6 . The computing device of claim 4 , wherein storing the application data in the non-volatile memory device comprises storing the modified application data cached in the volatile memory device to the non-volatile memory device.

7. The computing device of claim 1 , wherein the processor further performs the following: receiving a read data instruction for reading application data; determining whether the read data instruction requires the application data to be persistent; executing a read data instruction on a memory address of the read data instruction in response to determining that the application data is required to be persistent; and Application data is cached in corresponding volatile memory devices.

8. The computing device of claim 1, wherein determining one or more non-volatile memory devices to which the persistent memory address space is mapped comprises determining one or more non-volatile write-in-place byte-addressable memory devices to which the persistent memory address space is mapped.

9. The computing device of claim 1, wherein the processor further configures address interleaving to map contiguous logical memory addresses across a plurality of non-contiguous physical addresses of one or more non-volatile memory devices.

10. The computing device of claim 1, wherein the processor further detects a system shutdown request and writes the application data from the one or more volatile memory devices to the one or more non-volatile memory devices in response to detecting the system shutdown request.

11. The computing device of claim 1, wherein the processor is further to serialize the data instructions in the queue and execute the data instructions in response to detecting the system shutdown request.

12. A computing device comprising: means for determining a persistent memory address space for persistent 2LM data and one or more non-volatile memory devices to which the persistent memory address space is mapped, wherein each non-volatile memory device contains persistent 2LM data; means for configuring a persistent memory address space of a non-volatile memory device to operate in a persistent secondary memory 2LM mode in which application data written to the persistent memory address space can be reused across power cycles; as well as Means for configuring an operating system to cache data accessed to a persistent memory address space in volatile memory.

13. A computing device according to claim 12, wherein the device for configuring the operating system to cache accesses to the persistent memory address space in the volatile memory includes a device for configuring the address decoder to switch from a first operating mode for the persistent memory address space to a second operating mode for the persistent memory address space.

14. The computing device of claim 13, wherein the first operating mode is a persistent 2LM mode for storing persistent 2LM data in non-volatile memory, and the second operating mode is a cache mode for caching persistent 2LM data in one or more of the volatile memory devices.

15. The computing device of claim 12, further comprising: means for receiving a write data instruction for writing application data; means for determining whether a write data instruction requires the application data to be persistent; means for executing a write data instruction on a memory address of the write data instruction in response to determining that the application data is persistent; means for caching the persistent 2LM data in the corresponding volatile memory; as well as Means for storing persistent 2LM data in a corresponding non-volatile memory device.

16. The computing device of claim 15, wherein the means for determining whether application data is required to be persistent comprises means for determining whether to map a memory address of a write data instruction to a persistent memory address space configured to operate in persistent 2LM mode.

17. The computing device of claim 15, wherein the means for storing the application data in the non-volatile memory device comprises means for storing the modified application data cached in the volatile memory device to the non-volatile memory device.

18. The computing device of claim 12, further comprising: means for receiving a read data instruction for reading application data; means for determining whether a read data instruction requires the application data to be persistent; means for executing a read data instruction on a memory address of the read data instruction in response to determining that the application data is required to be persistent; as well as Means for caching application data in corresponding volatile memory devices.

19. A computing device according to claim 12, wherein the device for determining one or more non-volatile memory devices to which the persistent memory address space is mapped includes a device for determining one or more non-volatile write-in-place byte-addressable memory devices to which the persistent memory address space is mapped.

20. The computing device of claim 12, further comprising means for arranging address interleaving to map contiguous logical memory addresses across a plurality of non-contiguous physical addresses of one or more non-volatile memory devices.

21. The computing device of claim 12, further comprising means for detecting a system shutdown request and writing application data from the one or more volatile memory devices to the one or more non-volatile memory devices in response to detecting the system shutdown request.

22. The computing device of claim 12, further comprising means for serializing data instructions in a queue and executing the data instructions in response to detecting a system shutdown request.

23. A method for caching persistent secondary memory (2LM) data, comprising: determining, by a computing device, a persistent memory address space for persistent 2LM data and one or more non-volatile memory devices to which the persistent memory address space is mapped, wherein each non-volatile memory device contains persistent 2LM data; configuring, by the computing device, a persistent memory address space of the non-volatile memory device to operate in a persistent secondary memory 2LM mode in which application data written to the persistent memory address space may be reused across power cycles; as well as The operating system is configured by the computing device to cache data of accesses to the persistent memory address space in the volatile memory.

24. The method of claim 23, wherein configuring the operating system to cache accesses to the persistent memory address space in the volatile memory comprises configuring an address decoder to switch from a first operating mode for the persistent memory address space to a second operating mode for the persistent memory address space.

25. The method of claim 24, wherein the first operating mode is a persistent 2LM mode for storing persistent 2LM data in non-volatile memory, and the second operating mode is a cache mode for caching persistent 2LM data in one or more of the volatile memory devices.

26. A computer readable medium having stored thereon instructions which, when executed, cause a computing device to perform the method of any one of claims 23 to 25.

27. A device for caching persistent secondary memory (2LM) data, comprising: means for determining, by a computing device, a persistent memory address space for persistent 2LM data and one or more non-volatile memory devices to which the persistent memory address space is mapped, wherein each non-volatile memory device contains the persistent 2LM data; means for configuring, by the computing device, a persistent memory address space of the non-volatile memory device to operate in a persistent secondary memory 2LM mode in which application data written to the persistent memory address space may be reused across power cycles; as well as Means for configuring an operating system, by a computing device, to cache data accessed to a persistent memory address space in volatile memory.

28. The apparatus of claim 27, wherein configuring the operating system to cache accesses to the persistent memory address space in the volatile memory comprises configuring an address decoder to switch from a first operating mode for the persistent memory address space to a second operating mode for the persistent memory address space.

29. The apparatus of claim 28, wherein the first operating mode is a persistent 2LM mode for storing persistent 2LM data in non-volatile memory, and the second operating mode is a cache mode for caching persistent 2LM data in one or more of the volatile memory devices.

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