Power electronic assembly with adhesive layer, and method for manufacturing the same

Abstract

A method and an assembly manufactured by the method are presented, the assembly being configured to have a substrate, to have a power semiconductor element, and to have an adhesive layer disposed therebetween, wherein the substrate has a first surface facing the power semiconductor element, wherein the power semiconductor element has a third surface facing the substrate, wherein the adhesive layer has a second surface which preferably contacts the third surface across an entire area and has a first uniform surface profile having a first roughness, and wherein a fourth surface of the power semiconductor element opposite the third surface has a second surface profile having a second roughness, said second surface profile following the first surface profile.

Description

TECHNICAL FIELD

[0001] The invention relates to a power electronics assembly having a substrate, having a power semiconductor element and having an adhesive layer arranged therebetween. The invention also describes a method for configuring a power electronics assembly of this type. BACKGROUND

[0002] It is currently known from the generally known prior art that the adhesive layer is arranged on the substrate by various methods, for example by screen printing or stencil printing. Thereafter, a mating component, in particular configured as a power semiconductor element, is arranged on the adhesive layer. Depending on the design embodiment of the additional layer, further industrial standard method steps are also carried out in order to finally configure a material-integrally connected connection between the substrate and the power semiconductor element. The industrial standard methods are in particular soldering, adhesive bonding and pressure sintering methods.

[0003] The insufficient durability of the material-integrally connected connection, in particular under temperature fluctuations, is a common disadvantage. SUMMARY

[0004] In view of the described situation, it is an object of the invention to provide a power electronics assembly and a method for manufacturing the latter, i.e. the power electronics assembly, wherein the durability of the material-integrally connected connection is improved.

[0005] According to the invention, this object is achieved by a power electronics assembly as described below and by a method as described below.

[0006] The power electronics assembly according to the invention is configured to have a substrate, to have a power semiconductor element and to have an adhesive layer arranged therebetween, wherein the substrate has a first surface facing the power semiconductor element, wherein the power semiconductor element has a third surface facing the substrate, wherein the adhesive layer has a second surface which preferably contacts the third surface across the entire area and which has a first uniform surface profile having a first roughness, and wherein a fourth surface of the power semiconductor element, which is opposite the third surface, has a second surface profile having a second roughness, said second surface profile following the first surface profile. The term profile is to be understood herein and hereinafter as two "profiles" having the same type of three-dimensional structure, wherein the height of the structure does not necessarily have to be identical. The term "roughness" is to be understood herein and hereinafter as the average roughness Ra according to DIN 4760. A power electronics assembly configured in this way has the significant advantage that the connection between the second and third surfaces is significantly improved. This is due to the three-dimensional character combined with the fineness of the structure and thus the roughness.

[0007] In a preferred design embodiment of the assembly, the second roughness has a value between 50% and 100%, preferably between 85% and 99%, and particularly preferably between 95% and 99% of the value of the first roughness.

[0008] Advantageously, the first roughness is configured to vary from the center of the power semiconductor element towards the outside in a uniform or non-uniform manner. Thus, the first roughness assigned to the center of the power semiconductor element can be higher or lower than the roughness on the periphery of the power semiconductor element.

[0009] Preferably, the first average thickness of the adhesion layer (2) at the center of the power semiconductor element and defined below is between 10 pm and 200 pm, preferably between 20 pm and 100 pm, and particularly preferably between 10 pm and 30 pm, or between 50 pm and 80 pm. Here, the first value range is particularly preferred for sintered metal layers, while the second value range is preferred in the case of solder layers. There is no clearly preferred defined range of values for the adhesion layer, as the specific properties of the layer jointly determine the preferred value range. The average thickness is to be understood herein and hereinafter as the average of a range which is sufficiently large for the influence of the roughness to be averaged out when determining the thickness. In other words, the average thickness value does not take into account the roughness of the assigned surface, as the thickness is measured to the center line of the determined roughness.

[0010] The first roughness preferably has a value between 5% and 50%, preferably between 10% and 30%, and particularly preferably between 15% and 20% of the first average thickness of the adhesion layer.

[0011] The second average thickness of the adhesion layer at the periphery of the power semiconductor element and defined below has a value of at most 95% of the first average thickness, preferably at most 90% of the first average thickness, and particularly preferably at most 80% of the first average thickness.

[0012] In a preferred design embodiment, the substrate is configured to be rigid, in particular with a ceramic substrate carrier having metal conductor paths arranged thereon. In another preferred design embodiment, the substrate is configured to be flexible, in particular configured to have a thin-film / foil-type electrically insulating substrate carrier having metal conductor paths arranged thereon.

[0013] The method for producing an assembly according to the application comprises the following method steps in the sequence a-b-c-d-e, wherein steps b) and c) can be carried out simultaneously, or the following method steps in the sequence a-c-b-d-e:

[0014] a) providing a substrate and a power semiconductor element;

[0015] b) providing an adhesion layer on the first surface of the substrate;

[0016] c) structuring the second surface of the adhesion layer to configure a uniform surface structure;

[0017] d) providing a power semiconductor element, wherein its third surface is located on the second surface of the adhesion layer;

[0018] e) connecting the power semiconductor element to the adhesion layer.

[0019] It can be advantageous here that the adhesion layer is provided on the first surface of the substrate by a screen printing method and that the surface structure is configured at least initially by a screen printing method, thus not in the final representation, in particular not in the final first roughness.

[0020] Alternatively, the adhesion layer can be provided on the first surface of the substrate by a stencil printing method. The surface structure here can be produced by an embossing stamp.

[0021] Another possible alternative is to provide the adhesion layer on an intermediate carrier, in particular on a carrier sheet or a carrier film / foil, and to place it from the intermediate carrier onto the first surface of the substrate by a transfer method. The surface structure here can be produced from a negative structure of a fifth surface of the intermediate carrier.

[0022] Features mentioned in singular, in particular the power semiconductor element and the adhesion layer, can of course exist in plural in each case, as long as this is not explicitly or inherently excluded or contradicts the concept of the invention, in the context of the press sintering method.

[0023] It is to be understood that the various design embodiments of the present application, whether the latter is mentioned in the context of an assembly or a method, can be realized individually or in any combination in order to achieve the improvement. In particular, the features mentioned and explained above and below can be used not only in the combinations stated, but also in other combinations or alone, without departing from the scope of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0024] Further explanations, advantageous details and features of the present application result from the following description of exemplary embodiments of the present application, which are shown schematically and not to scale in Figures 1 to 5 or are shown from their respective parts.

[0025] In the drawings:

[0026] Figure 1A first power electronics assembly according to the application is shown, which has an additional connection device;

[0027] Figure 2 A second power electronics assembly according to the application is shown;

[0028] Figure 3 A third power electronics assembly according to the application is shown, which has an additional connection device; and

[0029] Figure 4 and Figure 5 A special design embodiment of a third surface of a power electronics assembly according to the application is shown. DETAILED DESCRIPTION

[0030] Figure 1 A first power electronics assembly according to the application is shown, which has an additional connection device 5. A substantially industrially standard power electronics device substrate 1 is shown, which is configured here with a rigid substrate carrier 10, which is configured as an insulating material component, in particular made of industrial ceramic with a thickness of 300 μιη. On the insulating material component 10, a conductor path 12 is provided, which is configured as a copper laminate, which likewise has a thickness of 300 μιη. For a thin noble metal layer provided on the copper laminate, which is also industrially standard, the thin noble metal layer has a first surface 120.

[0031] For the material-integrally connected electrical and thermal conduction between the conductor path 12 and a power semiconductor element 2, which is in exemplary fashion a transistor or a diode, such a connection is configured to be industrially standard by means of a sintered connection, in particular a press-sintered connection. For this purpose, the power semiconductor element 3 has a third surface 320 facing the first surface, on which a thin noble metal, which is industrially standard, is likewise provided.

[0032] A bond layer 2, which is configured here as a sintered metal layer, is provided between the first surface 120 and the third surface 320. The industrially standard sintered metal layer is made of a sintering material, preferably consisting of a suspension of liquid and silver flakes, which is provided between two mating parts. The sintering material is transferred into the sintered metal layer by the influence of pressure on the two mating parts and in most cases also by the influence of temperature on the two mating parts.

[0033] The sintered metal layer 2 has an average thickness of approximately 20 pm across the entire range. Furthermore, according to the application, the sintered metal layer 2, more specifically its second surface 220 facing the power semiconductor element 3, has a first uniform surface profile with a first roughness. In the case of the first power electronics assembly, the surface profile of the second surface 220 is configured irregularly. Here, the first roughness of the second surface 220 has a value Ra of approximately 4 pm.

[0034] Purely for the sake of clarity, the power semiconductor elements 3 are shown spaced apart. Industrial standard power semiconductor elements such as shown here have a thickness in the range of approximately 50 pm to 120 pm, which is the reason why the power semiconductor elements are flexible within certain limits despite having a crystalline structure. The third surface 320 almost contacts the second surface 220 across the entire area.

[0035] The fourth surface 340 of the power semiconductor element 3 is located opposite the third surface 320 and, according to the application, has a second surface profile with a second roughness, wherein the second surface profile follows the first surface profile as a result of the process described above for configuring the sintered connection. The second roughness of this fourth surface 340 is approximately 98% of the value of the first roughness. In other words, the structure of the sintered layer is almost reproduced on the fourth surface 340 of the power semiconductor element 3 and can be recognized without visual aids in this design embodiment.

[0036] In order to configure the first surface profile with the first roughness, the desired first surface profile can be configured in the method step c) of the method according to the application, wherein the first surface profile is imprinted in the second surface 220 of the sintered material by means of an imprinting stamp, that is to say before the configuration of the sintered connection and before the conversion of the sintered material into sintered metal. At the point in time of the imprinting, the roughness can still have a value which is twice the value of the second surface of the later sintered metal layer.

[0037] Furthermore, another electrically conductive connection of the power semiconductor element 3, in particular of the fourth surface 340 of the latter, the power semiconductor element 3, is shown spaced apart purely for the sake of clarity. This fourth surface is connected to the connection device 5 by means of a further layer of sintered metal 4. The connection device of the industrial standard consists of a sequence of layers of electrically conductive and electrically insulating thin films / foils 50, 52, 54.

[0038] Figure 2A second power electronics assembly according to the application is shown. Shown is a flexible substrate 1, which here is configured with an insulating material film / foil 14 having a thickness of 50 pm as a substrate carrier. A metal foil 16, which constitutes a conductor path and has a thickness of 80 pm, is arranged on the insulating material film / foil 14. For the very thin noble metal layer to be arranged on the metal foil 16, it is also an industry standard that the thin noble metal layer has a first surface 160.

[0039] The pressure-sintered connection here also constitutes an electrically conductive material-integral connection between the conductor path 16 and the power semiconductor element 3. For this purpose, the power semiconductor element has a third surface 320 facing the first surface, on which a thin noble metal layer is also arranged.

[0040] The adhesion layer 2, which here is also configured as a sintered metal layer, is arranged between the first surface 120 and the third surface 320. The sintered metal layer 2 here has an average thickness of approximately 15 pm across the entire area. Furthermore, the second surface 220 according to the application has a first uniform surface profile, which has a first roughness. In the case of the first power electronics assembly, the surface profile of the second surface 220 is configured in a regular manner. Here, the first roughness of the second surface 220 has a value Ra of approximately 2 pm.

[0041] The power semiconductor element 3 is shown spaced apart purely for the sake of clarity. The power semiconductor element 3 here has a thickness of approximately 60 pm. The third surface 320 of the power semiconductor element 3 contacts the second surface 220 across the entire area.

[0042] The fourth surface 340 of the power semiconductor element 3 according to the application has a second surface profile, which has a second roughness, wherein the second surface profile also follows the first surface profile. The second roughness of the fourth surface 340 is approximately 99% of the value of the first roughness. In other words, the structure of the sintered layer 2 is almost completely reproduced on the fourth surface 340 of the power semiconductor element 3 and is also recognizable without visual aids.

[0043] In order to configure the first surface profile having the first roughness, the required first surface profile can be configured in the method step c) of the method according to the application, wherein the sintering material is applied by means of a screen printing method, whereby, by means of a suitable selection of the screen structure and the viscosity of the sintering material, the surface profile is configured automatically. At this point in time of the embossing, the roughness can still have a value which is higher than the value of the second surface of the subsequent sintered metal layer.

[0044] Figure 3 A third power electronics assembly according to the application is shown, which has an additional connection device 5, in a similar manner to the second power electronics assembly according to the application. Figure 1In this case, the essential difference is that the adhesive layer 2 (here: adhesive layer) does not have a uniform average thickness, but rather has a first average thickness of approximately 80 pm in the center of the power semiconductor element 3, while the average thickness in the peripheral region of the power semiconductor element 3 is approximately 70 pm. For the reasons already mentioned above, the curvature of this type of power semiconductor element 3 is not problematic, in particular for reasons of the smaller thickness of the power semiconductor element 3.

[0045] In principle, the second surface 220 and the fourth surface 340 have a surface profile according to the application, which has a specified first and second roughness, respectively, without being explicitly indicated here.

[0046] In the context of the specified method, a respective adhesive layer in the non-crosslinked state is applied to the first surface 120 of the conductor path 12 in step b). An adhesive having a high viscosity is used here. Thereafter, the power semiconductor element 3 is arranged on the adhesive layer 2 and fixed by means of a stamp (the stamp having a defined surface profile including a curvature) until the crosslinking of the adhesive has progressed to a sufficient extent such that the shape of the second surface 220 of the adhesive layer 2 is no longer changed or at least not substantially changed.

[0047] Figure 4 and Figure 5 Special design embodiments of the second surface 220 of a power electronics assembly according to the application are shown. In each case, an adhesive layer 2 is shown, preferably a layer composed of sintered metal, which has a first surface profile. These layers as sintered material have been applied to the conductor path 12 by means of a stencil printing method in the context of the production method and the surface, that is to say the surface structure, has subsequently been structured by means of a stamping method, that is to say with a defined roughness.

[0048] In the transition of the sintered material into the layer composed of sintered metal by means of a press sintering method, the second surface 220 according to Figure 4 has a certain roughness, which has a value corresponding to approximately half the value of the peripheral roughness, said center also corresponding to the center of the power semiconductor element 3 to be arranged, and said periphery also corresponding to the periphery of the power semiconductor element 3 to be arranged. The value of this roughness thus steadily increases from the center toward the periphery.

[0049] The roughness of the second surface 220 according to Figure 5 corresponds to the roughness according to Figure 4 Figure 5 . However, in the case of this layer being made of sintered metal, the first average thickness 224 in the center is smaller than the first average thickness on the periphery. The second average thickness 226 on the periphery is approximately 5% higher than the second average thickness in the center.

Claims

1. A power electronics assembly, characterized by: having a substrate (1), having a power semiconductor element (3) and an adhesive layer (2) arranged therebetween, wherein the substrate (1) has a first surface (120, 160) facing the power semiconductor element (3), wherein the power semiconductor element (3) has a third surface (320) facing the substrate (2), wherein the adhesive layer (2) has a second surface (220) contacting the third surface (320) and having a uniform first surface profile with a first roughness, and wherein a fourth surface (340) of the power semiconductor element (3) opposite the third surface (320) has a second surface profile with a second roughness, said second surface profile following the first surface profile to reproduce the structure of the second surface (220) on the fourth surface (340).

2. The power electronics assembly according to claim 1, characterized in that: the value of the second roughness is between 95% and 99% of the value of the first roughness.

3. The power electronics assembly according to claim 1 or 2, characterized in that: the first roughness is configured to vary from the center of the power semiconductor element (3) towards the outside in a uniform or non-uniform manner.

4. The power electronics assembly according to claim 1 or 2, characterized in that: a first average thickness (224) of the adhesive layer (2) defined at the center of the power semiconductor element (3) is between 10 pm and 200 pm.

5. The power electronics assembly according to claim 1 or 2, characterized in that: a first average thickness (224) of the adhesive layer (2) defined at the center of the power semiconductor element (3) is between 20 pm and 100 pm.

6. The power electronics assembly according to claim 1 or 2, characterized in that: a first average thickness (224) of the adhesive layer (2) defined at the center of the power semiconductor element (3) is between 10 pm and 30 pm, or between 50 pm and 80 pm.

7. The power electronics assembly according to claim 1 or 2, characterized in that: the first roughness has a value between 5% and 50% of the first average thickness (224) of the adhesive layer (2).

8. The power electronics assembly according to claim 1 or 2, characterized in that: the first roughness has a value between 10% and 30% of the first average thickness (224) of the adhesive layer (2).

9. The power electronics assembly according to claim 1 or 2, characterized in that: the first roughness has a value between 15% and 20% of the first average thickness (224) of the adhesive layer (2).

10. The power electronics assembly according to claim 1 or 2, characterized in that: the adhesive layer (2) is configured as an adhesive bonding layer or a solder layer or a sintered metal layer.

11. The power electronics assembly according to claim 1 or 2, characterized in that: a second average thickness (226) of the adhesive layer (2) defined at the periphery of the power semiconductor element (3) has a value of at most 95% of the first average thickness (224).

12. The power electronics assembly according to claim 1 or 2, characterized in that: the second average thickness (226) of the adhesive layer (2) defined at the periphery of the power semiconductor element (3) has a value of at most 90% of the first average thickness (224).

13. The power electronics assembly according to claim 1 or 2, characterized in that: the second average thickness (226) of the adhesive layer (2) defined at the periphery of the power semiconductor element (3) has a value of at most 80% of the first average thickness (224).

14. The power electronics assembly according to claim 1 or 2, characterized in that: the substrate (1) is configured to be rigid.

15. The power electronics assembly according to claim 1 or 2, characterized in that: the substrate (1) is configured to have a ceramic substrate carrier (10) with a metal conductor path (12) arranged thereon.

16. The power electronics assembly according to claim 1 or 2, characterized in that: the substrate (1) is configured to be flexible.

17. The power electronics assembly according to claim 1 or 2, characterized in that: the substrate (1) is configured to have a thin film / foil type electrically insulating substrate carrier (14) with a metal conductor path (16) arranged thereon.

18. Method for producing a power electronics assembly according to any of the preceding claims, comprising the following method steps in the order a-b-c-d-e, wherein steps b) and c) can be performed simultaneously, or comprising the following method steps in the order a-c-b-d-e: a) providing a substrate (1) and a power semiconductor element (3); b) arranging an adhesive layer (2) on a first surface (120, 160) of the substrate (1); c) structuring a second surface (220) of the adhesive layer (2) to configure a uniform surface structure; d) arranging the power semiconductor element (3) with its third surface (320) on the second surface (220) of the adhesive layer (2); e) connecting the power semiconductor element (3) to the adhesive layer (2).

19. The method according to claim 18, characterized in that: the adhesive layer (2) is arranged on the first surface (120, 160) of the substrate (1) by a screen printing method and the surface structure is configured at least initially by a screen printing method.

20. The method according to claim 18, characterized in that: the adhesive layer (2) is arranged on the first surface (120, 160) of the substrate (1) by a stencil printing method.

21. The method according to claim 20, characterized in that: the surface structure is generated by an embossing stamp.

22. The method according to claim 18, characterized in that: the adhesive layer (2) is arranged on an intermediate carrier and placed from the intermediate carrier onto the first surface (120, 160) of the substrate (1) by a transfer method.

23. The method according to claim 22, characterized in that: the intermediate carrier is a carrier sheet or a carrier thin film / foil.

24. The method according to claim 22 or 23, characterized in that: the surface structure is generated from a negative structure of a fifth surface of the intermediate carrier.

Images