Techniques for providing shared memory for accelerator boards

Abstract

Techniques for providing shared memory for accelerator boards include an accelerator board to receive a memory access request from an accelerator device to access a memory region with a memory controller. The request is to identify the memory region with a logical address. In addition, the accelerator board is to determine a physical address associated with the memory region from a mapping of logical addresses and associated physical addresses. In addition, the accelerator board is to route the memory access request to a memory device associated with the determined physical address.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefits of U.S. Provisional Patent Application No. 62 / 427,268, filed November 29, 2016, and Indian Provisional Patent Application No. 201741030632, filed August 30, 2017. Background Technology

[0003] The use of accelerator devices (such as field-programmable gate arrays (FPGAs)) in data centers is increasing to the point where more memory is needed for access to accelerator devices and to allow for more fluid operations between individual accelerator devices. Currently, computing devices with one or more accelerator devices contain memory devices that are local to the accelerator devices on the computing device and inaccessible to other accelerator devices. That is, the memory devices are used only by the individual accelerator device coupled to the memory devices within the computing device.

[0004] The way the memory devices in the aforementioned accelerator devices are implemented makes it difficult to distribute workloads (e.g., applications, processes, etc.) across multiple accelerator devices because any dataset to be operated on can only be accessed by a single accelerator device. Therefore, in a data center comprising many accelerator devices, a significant number of accelerator devices may not be in use at any given time because they cannot share workload execution with other accelerator devices. Attached Figure Description

[0005] The concepts described herein are illustrated in the accompanying drawings by way of example rather than limitation. For simplicity and clarity, the elements shown in the drawings are not necessarily drawn to scale. Where deemed appropriate, reference numerals are repeated in the drawings to indicate corresponding or similar elements.

[0006] Figure 1 This is a diagram that provides a conceptual overview of a data center that can implement one or more of the technologies described herein, according to various embodiments;

[0007] Figure 2 yes Figure 1 A diagram illustrating an exemplary embodiment of the logical configuration of a data center rack;

[0008] Figure 3 This diagram illustrates an exemplary embodiment of another data center that can implement one or more technologies described herein according to various embodiments;

[0009] Figure 4 This diagram illustrates another exemplary embodiment of a data center that can implement one or more technologies described herein according to various embodiments;

[0010] Figure 5It means that it is possible Figure 1 , Figure 3 and Figure 4 A diagram showing the connection scheme for establishing link layer connections between various boards in a data center;

[0011] Figure 6 It can be represented according to some embodiments in Figure 1-4 A diagram of the rack architecture depicting any specific one of the racks;

[0012] Figure 7 It is possible to be with Figure 6 A diagram illustrating an exemplary embodiment of the board used in a rack architecture;

[0013] Figure 8 This is a diagram of an exemplary embodiment of a rack architecture for providing support for boards characterized by scalability;

[0014] Figure 9 It is based on Figure 8 A diagram illustrating an exemplary embodiment of a rack architecture;

[0015] Figure 10 It was designed to be with Figure 9 A diagram illustrating an exemplary embodiment of a board used in conjunction with a rack;

[0016] Figure 11 These are diagrams illustrating exemplary embodiments of data centers that implement one or more of the technologies described herein, according to various implementations;

[0017] Figure 12 This is a simplified block diagram of at least one embodiment of a system for sharing virtual memory between accelerator boards;

[0018] Figure 13 yes Figure 12 A simplified block diagram of at least one embodiment of the accelerator board of the system;

[0019] Figure 14 yes Figure 12 A simplified block diagram of at least one embodiment of the computing board of the system;

[0020] Figure 15 It can be made by Figure 12 and Figure 13 A simplified block diagram of at least one embodiment of the environment established by the accelerator board;

[0021] Figures 16-17 It is by Figure 12 and 13 A simplified flowchart of at least one embodiment of a method for sharing virtual memory executed on an accelerator board;

[0022] Figure 18It is possible to be Figure 12 The system performs an example of virtual memory sharing;

[0023] Figure 19 It can be made by Figure 12 The exemplary virtual address mapping to physical addresses performed by the system; and

[0024] Figure 20 This is a simplified block diagram of another embodiment of a system for sharing virtual memory within an accelerator board. Detailed Implementation

[0025] While the concepts of this disclosure are readily adaptable to various modifications and substitutions, specific embodiments thereof have been illustrated by way of example in the accompanying drawings and will be described in detail herein. However, it should be understood that the concepts of this disclosure are not intended to be limited to the specific forms disclosed, but rather, are intended to cover all modifications, equivalents, and substitutions consistent with this disclosure and the appended claims.

[0026] References to "an embodiment," "embodiment," "illustrative embodiment," etc., in the specification indicate that the described embodiment may include a particular feature, structure, or characteristic, but each embodiment necessarily or unnecessarily includes that particular feature, structure, or characteristic. Furthermore, these phrases do not necessarily refer to the same embodiment. Additionally, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is suggested that those skilled in the art would recognize that such a feature, structure, or characteristic can be implemented in conjunction with other embodiments, whether explicitly described or not. Furthermore, it should be appreciated that items included in the list in the form of "at least one A, B, and C" can represent (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C). Similarly, items listed in the form of "at least one of A, B, or C" can represent (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C).

[0027] In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried or stored by a transient or non-transient machine-readable (e.g., computer-readable) storage medium, which may be read and executed by one or more processors. A machine-readable storage medium may be embodied in any storage device, mechanism, or other physical structure (e.g., volatile or non-volatile memory, media disk, or other media device) for storing or transmitting information in a machine-readable form.

[0028] In the accompanying drawings, some structural or methodological features may be shown in a specific arrangement and / or order. However, it should be appreciated that such a specific arrangement and / or order may not be necessary. Rather, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. Furthermore, the inclusion of structural or methodological features in a particular figure does not imply that such features are required in all embodiments, and in some embodiments, these features may be omitted or may be combined with other features.

[0029] Figure 1 A conceptual overview of a data center 100 is shown, which can generally represent a data center or other type of computing network, wherein one or more technologies described herein may be implemented according to various embodiments. Figure 1 As shown, a data center 100 typically contains multiple racks, each capable of housing computing devices with a corresponding set of physical resources. Figure 1 In a specific, non-limiting example depicted, data center 100 includes four racks 102A to 102D housing computing devices, which include corresponding sets of physical resources (PCRs) 105A to 105D. According to this example, a common set of physical resources 106 for data center 100 includes individual sets of physical resources 105A to 105D distributed among racks 102A to 102D. Physical resources 106 may include various types of resources, such as processors, coprocessors, accelerators, field-programmable gate arrays (FPGAs), memory, and storage devices. Embodiments are not limited to these examples.

[0030] The illustrative data center 100 differs from a typical data center in many ways. For example, in the illustrative embodiment, the circuit board (“board”) on which components such as CPUs, memory, and other parts are housed is designed to improve thermal performance. Specifically, in the illustrative embodiment, the board is shallower than a typical board. In other words, the board is shorter from front to back, with cooling fans located within it. This reduces the length of the path that air must take through the components on the board. Furthermore, the components on the board are spaced further apart than on a typical circuit board, and these components are configured to reduce or eliminate shadows (i.e., one component is in the airflow path of another component). In the illustrative embodiment, processing components such as processors are located on the top side of the board, while nearby memory such as DIMMs is located on the bottom side. Due to the enhanced airflow provided by this design, components can operate at higher frequencies and power levels than in a typical system, thereby improving performance. In addition, the board is configured to blind-mate with power and data communication cables in each rack 102A, 102B, 102C, 102D, enhancing their ability to be quickly removed, upgraded, reinstalled, and / or replaced. Similarly, the various components located on the board (e.g., processors, accelerators, memory, and data storage drives) are configured to be easily upgraded due to their increasing spacing from each other. In the illustrative embodiment, the components also include hardware proof features to demonstrate their authenticity.

[0031] Furthermore, in the illustrative embodiment, data center 100 utilizes a single network architecture (“structure”) that supports multiple other network architectures, including Ethernet and Omni-Path. In the illustrative embodiment, boards are coupled to switches via fiber optic cables, which provide higher bandwidth and lower latency than typical twisted-pair cabling (e.g., Category 5, Category 5e, Category 6, etc.). Due to the high-bandwidth, low-latency interconnects and network architecture, data center 100 can aggregate physically fragmented resources, such as memory, accelerators (e.g., graphics accelerators, FPGAs, ASICs, etc.), and data storage drives, during use and provide them to computing resources (e.g., processors) as needed, enabling computing resources to access pooled resources as if they were local. The illustrative data center 100 also receives utilization information for various resources, predicts resource utilization for different types of workloads based on past resource utilization, and dynamically reallocates resources based on this information.

[0032] The racks 102A, 102B, 102C, and 102D of data center 100 may include physical design features that facilitate automation of various types of maintenance tasks. For example, data center 100 may be implemented using racks designed for robot access and accepting and accommodating robot-manipulated resource boards. Furthermore, in the illustrative embodiment, racks 102A, 102B, 102C, and 102D include an integrated power supply that receives a voltage higher than typical for power supplies. The increased voltage enables the power supply to provide additional power to the components on each board, allowing the components to operate at frequencies higher than typical.

[0033] Figure 2 An exemplary logical configuration of rack 202 in data center 100 is shown. Figure 2 As shown, rack 202 can typically accommodate multiple boards, each of which may include a corresponding set of physical resources. Figure 2 In a particular non-limiting example depicted, rack 202 accommodates plates 204-1 to 204-4 comprising a corresponding set of physical resources 205-1 to 205-4, each set of physical resources constituting part of a set of physical resources 206 included in rack 202. Regarding Figure 1 If rack 202 represents, for example, rack 102A, then physical resource 206 may correspond to physical resource 105A included in rack 102A. In the context of this example, physical resource 105A may therefore consist of a corresponding set of physical resources, including physical storage resource 205-1, physical accelerator resource 205-2, physical memory resource 205-3, and physical computing resource 205-5 contained in boards 204-1 to 204-4 of rack 202. Embodiments are not limited to this example. Each board may contain a pool of each of various types of physical resources (e.g., computing, memory, accelerator, storage devices). Through boards with robot-accessible and robot-manipulated resources, each type of resource can be upgraded independently of each other and with its own optimized refresh rate.

[0034] Figure 3 An example of a data center 300 is shown, which can generally represent one or more technologies described herein that can be implemented according to various embodiments. Figure 3 In a specific, non-limiting example depicted, data center 300 includes racks 302-1 to 302-32. In various embodiments, the racks of data center 300 may be arranged in a manner that defines and / or accommodates various access paths. For example, as... Figure 3As shown, the racks of data center 300 can be arranged in a manner that defines and / or accommodates access paths 311A, 311B, 311C, and 311D. In some embodiments, the presence of such access paths typically enables automated maintenance equipment (e.g., robotic maintenance equipment) to physically access the computing devices housed in the various racks of data center 300 and perform automated maintenance tasks (e.g., replacing faulty boards, upgrading boards). In various embodiments, the dimensions of access paths 311A, 311B, 311C, and 311D, the dimensions of racks 302-1 to 302-32, and / or one or more other aspects of the physical layout of data center 300 can be selected to facilitate such automated operation. The embodiments are not limited to this context.

[0035] Figure 4 An example of a data center 400 is shown, which can generally represent a data center that can implement one or more of the technologies described herein according to various embodiments. Figure 4 As shown, data center 400 may feature an optical structure 412. The optical structure 412 typically includes a combination of optical signaling media (e.g., optical cables) and optical switching infrastructure, through which any particular board in data center 400 can send signals to (and receive signals from) every other board in data center 400. The signaling connectivity provided by the optical structure 412 to any given board may include connections to other boards in the same rack and boards in other racks. Figure 4 In a specific, non-limiting example depicted, data center 400 includes four racks 402A to 402D. Racks 402A to 402D house corresponding pairs of boards 404A-1 and 404A-2, 404B-1 and 404B-2, 404C-1 and 404C-2, and 404D-1 and 404D-2. Thus, in this example, data center 400 includes a total of eight boards. Each such board can have a signaling connection to each of the seven other boards in data center 400 via optical structure 412. For example, via optical structure 412, board 404A-1 in rack 402A can have signaling connections with board 404A-2 in rack 402A, and six other boards 404B-1, 404B-2, 440C-1, 440C-2, 440D-1, and 404D-2 distributed among other racks 402B, 402C, and 402D in data center 400. The embodiments are not limited to this example.

[0036] Figure 5 An overview of a connectivity scheme 500 is shown, which can generally represent, in some embodiments, connectivity across various boards in a data center (e.g., Figure 1 , Figure 3 and Figure 4A link-layer connection is established between any of the example data centers 100, 300, and 400. The connectivity scheme 500 can be implemented using an optical architecture characterized by a dual-mode optical switching infrastructure 514. The dual-mode optical switching infrastructure 514 typically includes a switching infrastructure capable of receiving communications according to multiple link-layer protocols over the same uniform set of optical signaling media and appropriately switching such communications. In various embodiments, the dual-mode optical switching infrastructure 514 can be implemented using one or more dual-mode optical switches 515. In various embodiments, the dual-mode optical switch 515 typically includes a high cardinality switch. In some embodiments, the dual-mode optical switch 515 may include a multi-layer switch, such as a four-layer switch. In various embodiments, the dual-mode optical switch 515 may feature integrated silicon photonics, which enables the dual-mode optical switch to switch communications with significantly reduced latency compared to conventional switching devices. In some embodiments, the dual-mode optical switch 515 may constitute a blade switch 530 in a ridge structure, which further includes one or more dual-mode optical ridge switches 520.

[0037] In various embodiments, a dual-mode optical switch is capable of receiving Ethernet protocol communication carrying the Internet Protocol (IP packets) and communication according to a second high-performance computing (HPC) link layer protocol (e.g., Intel's Omni-Path architecture, Infiniband) via the optical signaling medium of its optical structure. Figure 5 As reflected here, for any particular pair of boards 504A and 504B with optical signaling connections to the optical structure, connection scheme 500 can therefore provide support for link-layer connections via Ethernet and HPC links. Thus, a single high-bandwidth, low-latency switching structure can support both Ethernet and HPC communication. The embodiments are not limited to this example.

[0038] Figure 6 A general overview of rack architecture 600 is shown, which may represent, according to some embodiments. Figures 1 to 4 The architecture of any particular rack shown. Figure 6 As shown, the rack architecture 600 typically features multiple board spaces into which boards can be inserted, each board space being robot-accessible via rack access area 601. Figure 6 In the specific non-limiting example shown, the rack architecture 600 is characterized by five board spaces 603-1 to 603-5. Board spaces 603-1 to 603-5 are characterized by corresponding multifunction connector modules (MPCMs) 616-1 to 616-5.

[0039] Figure 7 An example of board 704, which can represent this type of board, is shown. For example... Figure 7As shown, board 704 may include a set of physical resources 705, and an MPCM 716, which is designed to be inserted into board space (e.g., when board 704 is inserted into board space). Figure 6 When coupled to a mating MPCM in any board space 603-1 to 603-5, board 704 may also feature an expansion connector 717. The expansion connector 717 typically includes a socket, slot, or other type of connection element capable of accepting one or more types of expansion modules, such as expansion board 718. By coupling to a mating connector on expansion board 718, expansion connector 717 can provide physical resource 705 with access to supplemental computing resource 705B residing on expansion board 718. Embodiments are not limited to this context.

[0040] Figure 8 An example of a rack architecture 800 is shown, which can be implemented to accommodate boards characterized by scalability (e.g., ...). Figure 7 The board 704 provides support. Figure 8 In a specific non-limiting example depicted, rack architecture 800 includes seven board spaces 803-1 to 803-7, characterized by corresponding MPCMs 816-1 to 816-7. Board spaces 803-1 to 803-7 include corresponding main regions 803-1A to 803-7A and corresponding extension regions 803-1B to 803-7B. With respect to each such board space, when the corresponding MPCM is coupled to a mating MPCM of an inserted board, the main region typically constitutes a board space area that physically accommodates the inserted board. In the case where the inserted board is configured with such a module, the extension region typically constitutes a board space area that can physically accommodate an extension module, for example... Figure 7 The expansion board 718.

[0041] Figure 9 An example of rack 902 is shown, which may represent a configuration according to some embodiments. Figure 8 The rack architecture is implemented using the 800 rack. Figure 9 In a specific, non-limiting example depicted, rack 902 is characterized by seven board spaces 903-1 to 903-7, which include corresponding main regions 903-1A to 903-7A and corresponding extended regions 903-1B to 903-7B. In various embodiments, temperature control in rack 902 can be achieved using an air cooling system. For example, as... Figure 9As reflected in the description, rack 902 may feature multiple fans 919, which are typically arranged to provide air cooling within various board spaces 903-1 to 903-7. In some embodiments, the height of the board space is greater than that of a conventional "1U" server. In such embodiments, fans 919 may typically include relatively slow, large-diameter cooling fans compared to fans used in conventional rack configurations. Operating larger-diameter cooling fans at lower speeds can extend fan lifespan while still providing the same cooling capacity, compared to smaller-diameter cooling fans operating at higher speeds. The boards are physically shallower than conventional rack sizes. Furthermore, components are arranged on each board to reduce thermal shadows (i.e., no tandem arrangement along the airflow direction). Therefore, wider, shallower boards allow for improved device performance, as the device can operate at higher thermal enclosures (e.g., 250W) due to improved cooling (i.e., no thermal shadows, more space between devices, larger heatsink space, etc.).

[0042] MPCMs 916-1 to 916-7 can be configured to provide the inserted board with access to power derived from the respective power modules 920-1 to 920-7, each power module drawing power from an external power supply 921. In some embodiments, the external power supply 921 can supply alternating current (AC) power to the rack 902, and the power modules 920-1 to 920-7 can be configured to convert this AC power into direct current (DC) power for supply to the inserted board. In some embodiments, for example, the power modules 920-1 to 920-7 can be configured to convert 277 volts AC power into 12 volts DC power to be supplied to the inserted board via the respective MPCMs 916-1 to 916-7. The embodiments are not limited to this example.

[0043] MPCMs 916-1 to 916-7 can also be configured to provide an optical signaling connection to the inserted board with the dual-mode optical switching infrastructure 914, which can connect with... Figure 5The dual-mode optical switching infrastructure 514 is the same as or similar to that of the MPCM 916-1 to 916-7. In various embodiments, the optical connectors included in the MPCMs 916-1 to 916-7 can be designed to couple with mating optical connectors included in the MPCM of the inserted board to provide such board with optical signaling connectivity to the dual-mode optical switching infrastructure 914 via optical cables 922-1 to 922-7 of various lengths. In some embodiments, each such length of optical cable can extend from its corresponding MPCM to an optical interconnect loom 923 outside the board space of the rack 902. In various embodiments, the optical interconnect loom 923 can be arranged through other types of carrier elements such as support posts or brackets 902. The embodiments are not limited to this context. Since the inserted board is connected to the optical switching infrastructure via the MPCM, resources that would normally be required to manually configure rack cabling to accommodate the newly inserted board can be saved.

[0044] Figure 10 An example of board 1004 is shown, which may represent a design for use with, according to some embodiments, for... Figure 9 The board 1004 is used in conjunction with rack 902. Board 1004 may feature an MPCM 1016, which includes an optical connector 1016A and a power connector 1016B, and is designed to couple with a mating MPCM in the board space by inserting the MPCM 1016 into the board space. Coupled with such a mating MPCM, the power connector 1016 can be coupled to a power connector included in the mating MPCM. This typically allows physical resource 1005 of board 1004 to draw power from an external source via the power connector 1016 and a power transmission medium 1024 that electrically couples the power connector 1016 to physical resource 1005.

[0045] Board 1004 may also include a dual-mode optical network interface circuit 1026. The dual-mode optical network interface circuit 1026 typically includes components capable of... Figure 9 The dual-mode optical switching infrastructure 914 supports circuitry that communicates via optical signaling media for each of multiple link-layer protocols. In some embodiments, the dual-mode optical network interface circuitry 1026 is capable of Ethernet protocol communication and communication according to a second high-performance protocol. In various embodiments, the dual-mode optical network interface circuitry 1026 may include one or more optical transceiver modules 1027, each capable of transmitting and receiving optical signals on each of one or more optical channels. Embodiments are not limited to this context.

[0046] Coupling MPCM 1016 to a mating MPCM in a given rack space allows optical connector 1016A to be coupled to the optical connector included in the mating MPCM. This typically establishes an optical connection between the board's optical fiber and dual-mode optical network interface circuitry 1026 via each of a set of optical channels 1025. Dual-mode optical network interface circuitry 1026 can communicate with the physical resources 1005 of board 1004 via telecommunication medium 1028. Aside from the board size and the arrangement of components on the board to provide improved cooling and enable operation at relatively high thermal enclosures (e.g., 250W), as referenced above... Figure 9 In some embodiments, the plate may also include one or more additional features to facilitate air cooling, such as heat pipes and / or radiators arranged to dissipate heat generated by physical resources 1005. It is worth noting that, although... Figure 10 The exemplary board 1004 depicted does not feature an expansion connector, but any given board featuring design elements of board 1004 according to some embodiments may also feature an expansion connector. The embodiments are not limited to this context.

[0047] Figure 11 An example of a data center 1100 is shown, which can generally represent one or more technologies described herein that can be implemented according to various embodiments. Figure 11 The reflected implementation allows for the creation of a physical infrastructure management framework 1150A to facilitate the management of the physical infrastructure 1100A of the data center 1100. In various embodiments, one function of the physical infrastructure management framework 1150A may be to manage automated maintenance functions within the data center 1100, such as using robotic maintenance equipment to service computing devices within the physical infrastructure 1100A. In some embodiments, the physical infrastructure 1100A may feature an advanced telemetry system that performs telemetry reporting robust enough to support remote automated management of the physical infrastructure 1100A. In various embodiments, the telemetry information provided by such an advanced telemetry system may support features such as fault prediction / prevention capabilities and capacity planning capabilities. In some embodiments, the physical infrastructure management framework 1150A may also be configured to manage the authentication of physical infrastructure components using hardware authentication technology. For example, a robot may verify the authenticity of a component prior to installation by analyzing information collected from radio frequency identification (RFID) tags associated with each component to be installed. The embodiments are not limited to this context.

[0048] like Figure 11As shown, the physical infrastructure 1100A of the data center 1100 may include an optical structure 1112, which may include a dual-mode optical switching infrastructure 1114. The optical structure 1112 and the dual-mode optical switching infrastructure 1114 can be respectively... Figure 4 The optical structure 412 and Figure 5 The dual-mode optical switching infrastructure 514 is the same as or similar to that of the 1100 data center and can provide high-bandwidth, low-latency, multi-protocol connectivity between boards. As described above, refer to Figure 1 In various embodiments, the availability of this connectivity enables the decomposition and dynamic aggregation of resources such as accelerators, memory, and storage devices. In some embodiments, for example, one or more aggregated accelerator boards 1130 may be included in the physical infrastructure 1100A of the data center 1100, each physical infrastructure 1100A may include pools of accelerator resources, such as coprocessors and / or FPGAs, which may be used for global access by other boards via optical structure 1112 and dual-mode optical switching infrastructure 1114.

[0049] In another example, in various embodiments, one or more pooled storage boards 1132 may be included in a physical infrastructure 1100A of a data center 1100, each physical infrastructure 1100A including a pool of storage resources globally accessible to other boards via an optical structure 1112 and a dual-mode optical switching infrastructure 1114. In some embodiments, such pooled storage boards 1132 may include a pool of solid-state storage devices (e.g., solid-state drives (SSDs)). In various embodiments, one or more high-performance processing boards 1134 may be included in a physical infrastructure 110A of the data center 1100. In some embodiments, the high-performance processing board 1134 may include a pool of high-performance processors and enhanced air cooling to produce a thermal envelope of up to 250W or higher. In various embodiments, any given high-performance processing board 1134 may feature an expansion connector 1117 that can accept a remote memory expansion board, such that the remote memory locally available to the high-performance processing board 1134 is decoupled from the processor and nearby memory contained on the board. In some embodiments, such a high-performance processing board 1134 may be configured with remote memory using an expansion board including low-latency SSD storage. Optical infrastructure allows on-board computing resources to utilize remote accelerator / FPGA, memory, and / or SSD resources, which can be distributed across the board on any other rack within the same rack or data center. Remote resources can be located on top of the reference... Figure 5 The described spine-leaf network architecture involves one switch hop or two switch hops. The embodiments are not limited to this context.

[0050] In various embodiments, one or more abstraction layers may be applied to the physical resources of physical infrastructure 1100A to define virtual infrastructure, such as software-defined infrastructure 1100B. In some embodiments, virtual computing resources 1136 of software-defined infrastructure 1100B may be allocated to support the provision of cloud service 1140. In various embodiments, a specific set of virtual computing resources 1136 may be grouped to be provided to cloud service 1140 in the form of SDI service 1138. Examples of cloud service 1140 may include, but are not limited to, Software as a Service (SaaS) service 1142, Platform as a Service (PaaS) service 1144, and Infrastructure as a Service (IaaS) service 1146.

[0051] In some embodiments, a virtual infrastructure management framework 1150B can be used to manage the software-defined infrastructure 1100B. In various embodiments, the virtual infrastructure management framework 1150B can be designed to combine the management of virtual computing resources 1136 and / or SDI services 1138 to the allocation of cloud services 1140 to implement workload fingerprinting and / or machine learning techniques. In some embodiments, the virtual infrastructure management framework 1150B can be combined with performing such resource allocation to utilize / consult telemetry data. In various embodiments, an application / service management framework 1150C can be implemented to provide QoS management capabilities for cloud services 1140. The embodiments are not limited to this context.

[0052] Now for reference Figure 12 You can refer to the above. Figure 1 , Figure 3 , Figure 4 and Figure 11 The data centers 100, 300, 400, and 1100 described implement a system 1200 for sharing virtual memory within an accelerator board. In an illustrative embodiment, sharing virtual memory within an accelerator board can mean pooled access to memory resources by the accelerator device, wherein the pool of memory resources is generated through a virtual mapping of physical addresses to be utilized by the accelerator board in system 1200. Thus, memory access requests from the accelerator board are analyzed to determine physical addresses based on the virtual addresses identified by the memory access requests, wherein the physical addresses are determined based on address mappings that associate logical or virtual addresses with physical addresses. The accelerator device is used to accelerate the functionality of the system. For example, the accelerator device can be used to accelerate various applications running on the system's computing board.

[0053] In an illustrative embodiment, system 1200 includes a coordinator server 1202 that communicates with compute board 1204, accelerator board A 1206, and accelerator board B 1208. While only one compute board and two accelerator boards are shown, any number of compute boards and / or accelerator boards used in system 1200 can be present. In some embodiments, system 1200 may include a memory board 1210 that communicates with coordinator server 1202 and other components of system 1200 (e.g., boards 1204, 1206, 1208). One or more of boards 1204, 1206, 1208, and 1210 can be grouped into managed nodes, for example via coordinator server 1202, to collectively perform workloads, such as applications. A managed node can be represented as a collection of resources (e.g., physical resources 206), such as computing resources (e.g., physical computing resources 205-4), memory resources (e.g., physical memory resources 205-3), storage resources (e.g., physical storage resources 205-1), or other resources (e.g., physical accelerator resources 205-2) from the same or different boards (e.g., boards 204-1, 204-2, 204-3, 204-4, etc.) or racks (e.g., one or more racks 302-1 to 302-32). Furthermore, managed nodes can be created, defined, or “spinned” by the coordinator server 1202 when workloads are assigned to managed nodes or at any other time, and managed nodes can exist regardless of whether any workloads are currently assigned to them. System 1200 can reside in a data center and provide storage and computing services (e.g., cloud services) to client devices (not shown) that communicate with system 1200 via a network (not shown). Coordinator server 1202 can support cloud operating environments such as OpenStack, and managed nodes established by coordinator server 1202 can execute one or more applications or processes (i.e., workloads) on behalf of users of client devices, such as virtual machines or containers. In an illustrative embodiment, compute board 1204 utilizes central processing unit (CPU) 1212 to execute workload 1214 (e.g., applications). Additionally, accelerator board A 1206 includes memory controller 1216, which can be embodied as any device or circuit capable of routing memory access requests based on memory mapping. Accelerator board A 1206 also includes one or more accelerator devices 1218, 1220 (e.g., physical accelerator resources 205-2), and accelerator board B 1208 includes memory controller 1234 and one or more accelerator devices 1236, 1238 (e.g., physical accelerator resources 205-2).Furthermore, in the illustrative embodiments, each of accelerator devices 1218, 1220, 1236, and 1238 includes field-programmable gate arrays (FPGAs) 1222, 1228, 1240, and 1246 and memories 1226, 1232, 1244, and 1250, and each of FPGAs 1222, 1228, 1240, and 1246 includes cores 1224, 1230, 1242, and 1248. In other embodiments, one or more of accelerator devices 1218, 1220, 1236, and 1238 may include other devices or circuitry capable of accelerating the execution of workloads, such as application-specific integrated circuits (ASICs), coprocessors, etc.

[0054] In operation, system 1200 can utilize one or more cores 1224, 1230, 1242, 1248 to access physical memory within accelerator devices 1218, 1220, 1236, 1238. In an illustrative embodiment, memories 1226, 1232, 1244, 1250 are shared among accelerator boards 1206, 1208 based on a mapping of logical addresses for each physical address used to reference a region of memory. In operation, accelerator devices 1218, 1220, 1236, 1238 can send memory access requests containing logical addresses to memory controllers 1216, 1234 for processing and determination of the physical address associated with the logical address. For this purpose, memory controllers 1216, 1234 can use the address mapping described below. Therefore, after determining the physical address, memory controllers 1216 and 1234 route accelerator devices 1218, 1220, 1236, and 1238 to the corresponding memories 1226, 1232, 1244, and 1250 by sending a notification that associates the logical address with the physical address located in the corresponding memory 1226, 1232, 1244, and 1250. This allows accelerator devices 1218, 1220, 1236, and 1238 to access the corresponding memories 1226, 1232, 1244, and 1250. In some embodiments, memory controllers 1216 and 1234 may also route accelerator devices 1218, 1220, 1236, and 1238 (e.g., route memory access requests generated by the accelerator devices) to memory device 1254 located on memory board 1210.

[0055] Now for reference Figure 13 One or more of accelerator boards 1206, 1208 may be embodied as accelerator board 1302 capable of performing the functions described herein, including routing memory access requests among boards 1204, 1206, 1208, 1210 and / or coordinator server 1202.

[0056] refer to Figure 13 The illustrative accelerator board 1302 includes accelerators 1304 and 1306, a memory controller 1308, and communication circuitry 1310. Furthermore, each of accelerators 1304 and 1306 includes accelerator devices 1312 and 1316 and memories 1314 and 1318. The communication circuitry includes a network interface controller (NIC) 1320. Of course, in other embodiments, the accelerator board 1302 may include other or additional components, such as those typically found in accelerator boards. Additionally, in some embodiments, one or more of the illustrative components may be incorporated into another component or otherwise formed part of another component.

[0057] Accelerator devices 1312, 1316 can be embodied as any type of device or collection of devices capable of performing the various computational functions described below. In some embodiments, each of accelerator devices 1312, 1316 can be embodied as an FPGA, an application-specific integrated circuit (ASIC), reconfigurable hardware or hardware circuitry, or other special-purpose hardware to perform the functions described herein.

[0058] Memory modules 1314 and 1318 can be embodied as any type of volatile (e.g., dynamic random access memory (DRAM), etc.) or non-volatile memory or data storage device capable of performing the functions described herein. Volatile memory can be a storage medium that requires power to maintain the state of data stored by the medium. Non-limiting examples of volatile memory can include various types of random access memory (RAM), such as dynamic random access memory (DRAM) or static random access memory (SRAM). One particular type of DRAM that can be used in a memory module is synchronous dynamic random access memory (SDRAM). In certain embodiments, the DRAM of the memory component may conform to standards promulgated by JEDEC, such as JESD79F for DDR SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, JESD79-4A for DDR4 SDRAM, JESD209 for low-power DDR (LPDDR), JESD209-2 for LPDDR2, JESD209-3 for LPDDR3, and JESD209-4 for LPDDR4 (these standards are available at www.jedec.org). These standards (and similar standards) may be referred to as DDR-based standards, and the communication interface of a memory device implementing such a standard may be referred to as a DDR-based interface.

[0059] In one embodiment, the memory device is a block-addressable memory device, such as a device based on NAND or NOR technology. The memory device may also include future-generation non-volatile devices, such as three-dimensional cross-point memory devices, or other byte-addressable in-situ write-free non-volatile memory devices. In one embodiment, the memory device may be or may include memory devices using chalcogenide glass, multi-threshold NAND flash memory, NOR flash memory, single-level or multi-level phase-change memory (PCM), resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), antiferroelectric memory, magnetoresistive random access memory (MRAM) using memristor technology, resistive and bridged random access memory (CB-RAM) including metal oxide-based and oxygen vacancy-based memory, or spin-transfer torque (STT)-MRAM, spintronic junction-based devices, magnetic tunnel junction (MTJ-based devices, DW (domain wall) and SOT (spin-orbit transfer) based devices, thyristor-based memory devices, or combinations of any of the above devices, or other memories. Memory devices can refer to the die itself and / or the packaged memory product.

[0060] In some embodiments, the 3D crosspoint memory may include a transistorless stackable crosspoint architecture, wherein memory cells are located at the intersection of word lines and bit lines and are individually addressable, and wherein bit storage is based on variations in body resistance. In operation, memories 1314, 1318 may store various software and data used during operation, such as address mapping data, memory access request data, key data, applications, programs, libraries, and drivers.

[0061] The memory controller 1308 may be embodied as any type of switch capable of performing the functions described herein. In some embodiments, the memory controller 1308 may be embodied as a local memory switch, an inter-FPGA architecture switch, a high-speed serial interface (HSSI) switch, a host interface and / or architecture interface unit (FIU) (e.g., a network interface controller (NIC)).

[0062] The communication circuit 1310 can be embodied as any communication circuit, device, or combination thereof capable of communicating between computing devices (e.g., coordinator server 1202 and / or one or more boards 1204, 1206, 1208, 1210) via a network. The communication circuit 1310 can be configured to use any one or more communication technologies (e.g., wired or wireless communication) and associated protocols (e.g., Ethernet, etc.). This communication can be achieved using devices such as WiMAX. The NIC 1320 can be similarly embodied as any communication circuit, device, or combination thereof capable of communicating over a network between computing devices (e.g., coordinator server 1202 and / or one or more boards 1204, 1206, 1208, 1210).

[0063] Now for reference Figure 14 The computing board 1402 (similar to computing board 1204) can be embodied as any type of computing device capable of performing the functions described herein, including performing workload 1214. For example... Figure 14 As shown, the illustrative computing board 1402 includes a computing engine 1404, communication circuitry 1406, and one or more data storage devices 1408. In some embodiments, the computing board 1402 may include peripheral devices 1410. Of course, in other embodiments, the computing board 1402 may include other or additional components, such as components typically found in computing boards. Additionally, in some embodiments, one or more of the illustrative components may be incorporated into another component or otherwise formed part of another component.

[0064] The computing engine 1404 can be embodied as any type of device or collection of devices capable of performing the various computing functions described below. In some embodiments, the computing engine 1404 can be embodied as a single device, such as an integrated circuit, embedded system, field-programmable gate array (FPGA), system-on-a-chip (SoC), or other integrated system or device. Additionally, in some embodiments, the computing engine 1404 includes or is embodied as a processor 1412 and a memory 1414. The processor 1412 can be embodied as any type of processor capable of performing the functions described herein. For example, the processor 1412 can be embodied as a single-core or multi-core processor, microcontroller, or other processor or processing / control circuitry. In some embodiments, the processor 1412 can be embodied as, include, or coupled to an FPGA, application-specific integrated circuit (ASIC), reconfigurable hardware or hardware circuitry, or other special-purpose hardware to perform the functions described herein.

[0065] Memory 1414 may be embodied as any type of volatile (e.g., dynamic random access memory (DRAM) or non-volatile memory or data storage device capable of performing functions similar to those described herein for memories 1314, 1318.

[0066] Communication circuit 1406 may be embodied as any communication circuit, device, or combination thereof capable of communicating between computing devices (e.g., coordinator server 1202 and / or one or more boards 1204, 1206, 1208, 1210) via a network. Communication circuit 1310 may be configured to use any one or more communication technologies (e.g., wired or wireless communication) and associated protocols (e.g., Ethernet, etc.). This communication can be achieved using devices such as WiMAX. The NIC 1416 can be similarly embodied as any communication circuit, device, or combination thereof capable of communicating over a network between computing devices (e.g., coordinator server 1202 and / or one or more boards 1204, 1206, 1208, 1210).

[0067] As described above, in some embodiments, the computing board 1402 may include one or more peripheral devices 1410. Such peripheral devices 1410 may include any type of peripheral device typically found in computing devices, such as a display, speakers, mouse, keyboard and / or other input / output devices, interface devices and / or other peripheral devices.

[0068] The coordinator server 1202 and the storage board 1210 can have the same Figure 14 Similar components are described above. The descriptions of those components of computing board 1402 also apply to the descriptions of components of coordinator server 1202 and memory board 1210, and for clarity, they will not be repeated here. Furthermore, it should be appreciated that coordinator server 1202 and memory board 1210 may include other components, sub-components, and devices typically found in computing devices, which have not been discussed above with reference to computing board 1402, and are not discussed here for clarity.

[0069] As described above, the coordinator server 1202 and boards 1204, 1206, 1208, and 1210 illustratively communicate via a network (not shown), which can be any type of wired or wireless communication network, including global networks (e.g., the Internet), local area networks (LANs) or wide area networks (WANs), cellular networks (e.g., Global System for Mobile Communications (GSM), 3G, Long Term Evolution (LTE), WiMAX, etc.), digital subscriber line (DSL) networks, wired networks (e.g., coaxial networks, fiber optic networks, etc.) or any combination thereof.

[0070] Now for reference Figure 15Accelerator board 1302 can establish environment 1500 during operation. Accelerator boards 1206, 1208 and their components can similarly be embodied as accelerator board 1302 and establish environment 1500 during operation. Illustrative environment 1500 includes network communicator 1502 and shared memory manager 1504. Each component of environment 1500 can be embodied as hardware, firmware, software, or a combination thereof. Thus, in some embodiments, one or more components of environment 1500 can be embodied as a collection of circuits or electronic devices (e.g., network communicator circuitry 1502, shared memory manager circuitry 1504, etc.). It should be appreciated that in such embodiments, one or more of network communicator circuitry 1502 or shared memory manager circuitry 1504 can form one or more of any other components of accelerators 1304, 1306, memory controller 1308, communication circuitry 1310, and / or accelerator board 1302. In the illustrative embodiment, environment 1500 includes address mapping data 1510, which may be embodied as any data established by coordinator server 1202, compute board 1204, and / or accelerator boards 1206, 1208 during the execution of one or more workloads by boards 1204, 1206, 1208, 1210, and this data represents a mapping between logical addresses and physical addresses. Address mapping data 1510 may include information that can be used to determine the physical address of a logical address identified in a memory access request. That is, a memory pool may be created and stored in address mapping data 1510, which contains logical addresses to be referenced by accelerator devices to point to physical addresses. Additionally, illustrative environment 1500 includes memory access request data 1512, which may be embodied as any data indicating memory access requests received from various accelerator devices 1218, 1220, 1236, 1238 in system 1200. The memory access request data 1512 may include information indicating which accelerator devices 1218, 1220, 1236, and 1238 are requesting access to a specific logical address and the corresponding physical access. The memory access request data 1512 may store the logical address and its corresponding physical address pair to be quickly referenced by the accelerator devices 1218, 1220, 1236, and 1238.

[0071] In the illustrative environment 1500, a network communicator 1502, which may be embodied as hardware, firmware, software, virtualization hardware, emulation architecture, and / or combinations thereof as described above, is configured to facilitate inbound and outbound network communications (e.g., network traffic, network packets, network flows, etc.) to and from accelerator board 1302. To this end, the network communicator 1502 is configured to receive and process data packets from one system or computing device (e.g., computing board 1204, accelerator board 1206 or 1208, memory board 1210, and / or coordinator server 1202), and prepare and send data packets to another computing device or system (e.g., computing board 1204, accelerator board 1206 or 1208, memory board 1210, and / or coordinator server 1202). Therefore, in some embodiments, at least a portion of the functionality of the network communicator 1502 may be performed by communication circuitry 1310, and in the illustrative embodiment, by NIC 1320.

[0072] A shared memory manager 1504, which may be manifested as hardware, firmware, software, virtualization hardware, emulation architecture, and / or a combination thereof, is configured to determine physical addresses based on logical addresses specified by accelerator devices 1218, 1220, 1236, and 1238. Additionally, the shared memory manager 1504 identifies whether the logical address is on the local floor, on the requesting accelerator device, or on another board. To this end, in the illustrative embodiment, the shared memory manager 1504 includes a memory address translator 1506 and a memory request router 1508. In the illustrative embodiment, the memory address translator 1506 is configured to determine physical addresses based on logical addresses using address mapping data 1510 by matching the logical address with the corresponding physical address stored in the address mapping data 1510. The memory address translator 1506 is also configured to update the address mapping data 1510 in response to receiving a notification from the host or computer board 1204 and / or the coordinator server 1202. For example, this might occur when any memory device is added to or removed from system 1200.

[0073] In an illustrative embodiment, memory request router 1508 is configured to receive memory access requests (e.g., read / write to a logical address) from accelerator devices and route the memory access requests to physical addresses, which may be on another accelerator device, an accelerator board, or local memory. If the physical address is in local memory, memory request router 1508 can inform the requesting accelerator device where the memory is being requested from. Memory request router 1508 can communicate with network communicator 1502 and memory address translator 1506 to retrieve the physical address associated with the logical address and can pass it to the requesting accelerator device.

[0074] Now for reference Figure 16 In use, accelerator board 1302 can execute method 1600 for sharing virtual memory in a system including one or more accelerator boards (e.g., accelerator boards 1206, 1208 in system 1200). For simplicity, method 1600 is described below as being executed by accelerator board 1302. However, it should be understood that in other embodiments, method 1600 can be executed by one or more other devices (e.g., boards 1204, 1206, 1208, 1210 and / or coordinator server 1202). Method 1600 begins at block 1602, where accelerator board 1302 determines whether a notification of an address mapping change has been received. In the illustrative embodiment, accelerator board 1302 may receive notification of an address mapping change from coordinator server 1202 and / or compute board 1204. Furthermore, in instances where an additional memory device is added to or removed from system 1200, the notification of the change is used to update any changes in the association between logical addresses and physical addresses. If accelerator board 1302 receives a notification of a change, method 1600 proceeds to block 1604, where, in some embodiments, accelerator board 1302 updates the mapping of logical addresses and associated physical addresses (e.g., address mapping data 1510). However, if no notification of a change is received, method 1600 proceeds to block 1610, where accelerator board 1302 determines whether a memory access request has been received, as described in more detail herein. Returning to reference block 1604, when updating address mapping data 1510, accelerator board 1302 may determine which logical addresses and associated physical addresses need to be updated (e.g., the logical addresses and associated physical addresses referenced in the received notification), as indicated by block 1606. After determining which addresses need to be updated, method 1600 proceeds to block 1608, where accelerator board 1302 updates the mapping based on the indicated change (e.g., a modified memory address).

[0075] In block 1610, accelerator board 1302 determines whether a memory access request has been received from the accelerator device. As described above, a memory access request can be manifested as a request to read or write to a logical address. If accelerator board 1302 determines that a memory access request has not yet been received from the accelerator device, method 1600 returns to block 1602 to determine whether a change notification has been received. However, when accelerator board 1302 receives a memory access request, method 1600 proceeds to block 1612, where accelerator board 1302 identifies the requested memory region by memory controller 1308. Additionally, in block 1614, accelerator board 1302 identifies the memory region using the logical address specified in the memory access request. After identifying the requested memory region, method 1600 proceeds to block 1616, where accelerator board 1302 uses memory controller 1308 to determine the physical address associated with the memory region. Therefore, in the illustrative embodiment, method 1600 proceeds to block 1618, where accelerator board 1302 uses a mapping of logical addresses and associated physical addresses (e.g., address mapping data 1510) to determine the physical addresses associated with memory regions.

[0076] Now for reference Figure 17In block 1620, accelerator board 1302 then uses memory controller 1308 to route memory access requests to memory devices associated with the determined physical addresses. In some embodiments, in block 1622, accelerator board 1302 routes memory access requests to another board via network interface controller 1320. To route memory access requests to another board, method 1600 continues to block 1624, where accelerator board 1302 sends memory access requests to a compute board (e.g., compute board 1204) associated with a workload, for which functionality is accelerated by the accelerator device. In one embodiment, in block 1626, accelerator board 1302 routes memory access requests to another accelerator device on the same accelerator board (e.g., from accelerator device 1218 to accelerator device 1220). In one embodiment, at block 1628, accelerator board 1302 routes a memory access request to the local memory (e.g., memory 1226) of an accelerator device (e.g., accelerator device 1218). Additionally, after routing the memory access request to the local memory of the accelerator device, at block 1630, accelerator board 1302 sends a notification to the requesting accelerator device that the logical address of the memory access request is associated with a physical address in the local memory of the requesting accelerator device. After sending the notification, at block 1632, the requesting accelerator device accesses its local memory. In one embodiment, at block 1634, accelerator board 1302 routes the memory access request to the memory device (e.g., memory device 1254) of a memory board (e.g., memory board 1210). To this end, method 1600 continues to block 1636, where accelerator board 1302 sends the notification that the logical address is associated with a physical address in the memory device of the memory board to the requesting accelerator device. After sending the notification, in box 1638, the requesting accelerator device accesses memory device 1254 of memory board 1210. After routing the memory access request to memory device 1254 associated with the determined physical address, method 1600 returns to... Figure 16 Box 1602 is used to continue monitoring for any received notifications of changes.

[0077] Now for reference Figure 18The illustrative virtual topology 1800 illustrates the connections between workload 1802 (e.g., an application), local accelerator board 1804, and shared memories 1810, 1820. Local accelerator board 1804 includes an accelerator device 1806 embodied as an FPGA including a core 1808. Shared memory 1810 is provided by two accelerator devices 1812, 1816 (e.g., similar to accelerator devices 1218, 1220) embodied as FPGAs, each accelerator device including a core 1814, 1818 and an associated memory device (e.g., similar to memories 1226, 1232). Additionally, shared memory 1820 is provided by an accelerator device 1822 (e.g., similar to accelerator device 1236) including an FPGA and an associated memory device (e.g., similar to memory 1244), the FPGA including a core 1824. Kernels 1808, 1814, 1818, and 1824 can request access to the shared memory regions 1810 and 1820 by sending memory access requests to their respective memory controllers 1308 according to the method described above 1500.

[0078] Now for reference Figure 19 The illustrative address mapping 1900 shows multiple virtual address (e.g., logical address) spaces of the FPGA mapped to the physical address space, such as... Figure 19 As shown in the center. The virtual address space used for the FPGA can be directly associated with the FPGA's physical address space (e.g., in a memory device directly connected to the FPGA), or the virtual address space can be mapped to the physical address space corresponding to a memory device local to a different FPGA. In some embodiments, different cores registered in the same FPGA or different FPGAs can have different virtual-to-physical mappings.

[0079] Now for reference Figure 20The illustrative system 2000 includes components and functions similar to those of system 1200. System 2000 includes a memory host 2001, an FPGA(A) 2002 on board 0, an FPGA(A) 2004 on board 1, and an FPGA(B) 2006 on board 0. FPGA(A) includes FPGA 2008, a switch interface 2010, a host interface 2012, a memory controller 2014, an inter-FPGA architecture switch 2016, an architecture interface unit (FIU) 2018, local memory 2020, and a target inter-FPGA architecture 2022. FPGA 2008 includes a core 2024 for requesting memory access. Memory access requests from kernel 2024 are sent to switch interface 2010, which contains a first-level system address decoder (SAD) that identifies whether the memory access request is redirected to host interface 2012, memory controller 2014, or inter-FPGA structure switch 2016 (which contains a global SAD). Host interface 2012 connects to FIU 2018, which contains a global SAD, communicates with memory host 2001, and is connected to board 1 2004 via structure 2032 to communicate with the FPGA(C) on board 1 2034 for remote memory FPGA 2036 access. If the memory access request specifies a logical address associated with a physical address on memory, memory controller 2014 connects to local memory 2020. Inter-FPGA structure switch 2016 is connected to target inter-FPGA structure 2022 to connect to memory controller 2038 of FPGA(B)2006 so as to access memory 2042 of FPGA(B)2006 located on the same board 0 as FPGA(A)2002.

[0080] Example

[0081] The following provides illustrative examples of the techniques disclosed herein. Embodiments of these techniques may include any one or more of the examples described below, as well as any combination thereof.

[0082] Example 1 includes an accelerator board comprising: an accelerator device; a memory controller coupled to the accelerator device; and circuitry for: receiving a memory access request from the accelerator device via the memory controller for access to a memory region, wherein the request identifies the memory region using a logical address; determining a physical address associated with the memory region based on a mapping between the logical address and an associated physical address; and routing the memory access request to the memory device associated with the determined physical address, wherein the memory access request includes the determined physical address.

[0083] Example 2 includes the subject of Example 1, and wherein the circuitry is further configured to: receive a notification from a computing board indicating a change in the mapping between logical addresses and associated physical addresses; and update the mapping based on the indicated change.

[0084] Example 3 includes the subject of any one of Examples 1 and 2, and wherein the circuitry is further configured to: receive a notification from a coordinator server indicating a change in the mapping of logical addresses and associated physical addresses; and update the mapping according to the indicated change.

[0085] Example 4 includes the subject of any one of Examples 1-3, and wherein receiving a memory access request from an accelerator device includes receiving a memory access request from a field-programmable gate array (FPGA).

[0086] Example 5 includes the subject of any one of Examples 1-4, and wherein routing a memory access request includes sending a memory access request from a memory controller to another board via a network interface controller on the accelerator board.

[0087] Example 6 includes the subject of any one of Examples 1-5, and wherein routing a memory access request further includes sending the memory access request from the memory controller to a compute board associated with a workload for which the functionality is accelerated by an accelerator device of the accelerator board.

[0088] Example 7 includes the subject of any one of Examples 1-6, and wherein routing a memory access request includes routing the memory access request to another accelerator device on the same accelerator board.

[0089] Example 8 includes the subject of any one of Examples 1-7, and wherein the other accelerator device is a field-programmable gate array (FPGA).

[0090] Example 9 includes the subject of any one of Examples 1-8, and wherein routing a memory access request includes routing the memory access request to the local memory of the accelerator device that sent the request.

[0091] Example 10 includes the subject of any one of Examples 1-9, and wherein routing to local memory includes: sending a notification via a memory controller that associates a logical address with a physical address in the local memory of the requester accelerator device; and using the requester accelerator device to access the local memory of the accelerator device.

[0092] Example 11 includes the subject matter of any one of Examples 1-10, and wherein the accelerator device is an application-specific integrated circuit (ASIC).

[0093] Example 12 includes the subject of any one of Examples 1-11, and wherein routing a memory access request includes routing the memory access request to a memory device on the memory board.

[0094] Example 13 includes the subject of any one of Examples 1-12, and wherein routing to the memory device includes sending a notification via a memory controller to the requester accelerator device that associates a logical address with a physical address in the memory device of the memory board; and using the requester accelerator device to access the memory device of the memory board.

[0095] Example 14 includes a method comprising: receiving a memory access request from an accelerator device for accessing a memory region via a memory controller coupled to an accelerator device on an accelerator board, wherein the request uses a logical address to identify the memory region; determining a physical address associated with the memory region based on a mapping between the logical address and an associated physical address; and routing the memory access request via the memory controller to a memory device associated with the determined physical address, wherein the memory access request includes the determined physical address.

[0096] Example 15 includes the subject of Example 14, and further includes: receiving a notification from a computing board indicating a change in the mapping of logical addresses and associated physical addresses; and updating the mapping by a memory controller in accordance with the indicated change.

[0097] Example 16 includes the subject matter of any one of Examples 14 and 15, and further includes: receiving a notification from a coordinator server indicating a change in the mapping of logical addresses and associated physical addresses; and updating the mapping by a memory controller in accordance with the indicated change.

[0098] Example 17 includes the subject of any one of Examples 14-16, and wherein receiving a memory access request from an accelerator device includes receiving a memory access request from a field-programmable gate array (FPGA).

[0099] Example 18 includes the subject of any of Examples 14-17, and wherein routing a memory access request includes sending the memory access request to another board via the network interface controller on the accelerator board.

[0100] Example 19 includes the subject of any one of Examples 14-18, and wherein routing a memory access request further includes sending the memory access request from the memory controller to the compute board associated with the workload, for which the functionality is accelerated by the accelerator device of the accelerator board.

[0101] Example 20 includes the subject of any one of Examples 14-19, and wherein routing a memory access request includes routing the memory access request to another accelerator device on the same accelerator board.

[0102] Example 21 includes the subject of any one of Examples 14-20, and wherein the other accelerator device is a field-programmable gate array (FPGA).

[0103] Example 22 includes the subject of any one of Examples 14-21, and wherein routing a memory access request includes routing the memory access request to the local memory of the accelerator device that sent the request.

[0104] Example 23 includes the subject of any one of Examples 14-22, and wherein routing to local memory includes: sending a notification via a memory controller that associates a logical address with a physical address in the local memory of the requester accelerator device; and using the requester accelerator device to access the local memory of the accelerator device.

[0105] Example 24 includes the subject matter of any one of Examples 14-23, and wherein the accelerator device is an application-specific integrated circuit (ASIC).

[0106] Example 25 includes the subject of any one of Examples 14-24, and wherein routing a memory access request includes routing the memory access request to another memory device on the memory board.

[0107] Example 26 includes the subject of any one of Examples 14-25, wherein routing to another memory device includes: sending a notification via a memory controller that associates a logical address with a physical address in another memory device on the memory board to a requester accelerator device; and using the requester accelerator device to access the other memory device on the memory board.

[0108] Example 27 includes one or more machine-readable storage media, including a plurality of instructions stored thereon, which, in response to being executed, cause the accelerator board to perform any of the methods in Examples 14-26.

[0109] Example 28 includes an accelerator board comprising units for performing the methods of any one of Examples 14-26.

[0110] Example 29 includes an accelerator board comprising: one or more processors; and one or more memory devices storing a plurality of instructions which, when executed by the one or more processors, cause the accelerator board to perform the method of any of Examples 14-26.

[0111] Example 30 includes an accelerator board including network communicator circuitry for receiving memory access requests from an accelerator device for accessing a memory region, wherein the requests utilize logical addresses to identify the memory region; and shared memory manager circuitry for determining a physical address associated with the memory region based on a mapping between logical addresses and associated physical addresses; and routing the memory access request to a memory device associated with the determined physical address, wherein the memory access request includes the determined physical address.

[0112] Example 31 includes the subject of Example 30, and wherein the network communicator circuitry is further configured to: receive a notification from a computing board indicating a change in the mapping of logical addresses and associated physical addresses; and wherein the shared memory manager circuitry is further configured to update the mapping according to the indicated change.

[0113] Example 32 includes the subject matter of any one of Examples 30 and 31, and wherein the network communicator circuitry is further configured to: receive a notification from a coordinator server indicating a change in the mapping of logical addresses and associated physical addresses; and wherein the shared memory manager circuitry is further configured to update the mapping according to the indicated change.

[0114] Example 33 includes the subject of any one of Examples 30-32, and wherein receiving a memory access request from an accelerator device includes receiving a memory access request from a field-programmable gate array (FPGA).

[0115] Example 34 includes the subject of any one of Examples 30-33, and wherein routing a memory access request includes sending the memory access request to another board via the network interface controller on the accelerator board.

[0116] Example 35 includes the subject of any one of Examples 30-34, and wherein routing a memory access request further includes sending the memory access request to a compute board associated with a workload for which the functionality is accelerated by an accelerator device of the accelerator board.

[0117] Example 36 includes the subject of any one of Examples 30-35, and wherein routing a memory access request includes routing the memory access request to another accelerator device on the same accelerator board.

[0118] Example 37 includes the subject of any one of Examples 30-36, and wherein the other accelerator device is a field-programmable gate array (FPGA).

[0119] Example 38 includes the subject of any one of Examples 30-37, and wherein routing a memory access request includes routing the memory access request to the local memory of the accelerator device that sent the request.

[0120] Example 39 includes the subject of any one of Examples 30-38, and wherein routing to local memory includes: sending a notification that associates a logical address with a physical address in the local memory of the requester accelerator device; and accessing the local memory of the accelerator device.

[0121] Example 40 includes the subject matter of any one of Examples 30-39, and wherein the accelerator device is an application-specific integrated circuit (ASIC).

[0122] Example 41 includes the subject of any one of Examples 30-40, and wherein routing a memory access request includes routing the memory access request to a memory device on the memory board.

[0123] Example 42 includes the subject of any one of Examples 30-41, and wherein routing to the memory device includes: sending a notification that associates a logical address with a physical address in the memory device of the memory board to the requesting accelerator device; and accessing the memory device of the memory board.

[0124] Example 43 includes an accelerator board comprising circuitry for receiving a memory access request from an accelerator device coupled to the accelerator board for accessing a memory region, wherein the request uses a logical address to identify the memory region; unitry for determining a physical address associated with the memory region based on a mapping between the logical address and an associated physical address; and circuitry for routing the memory access request via the memory controller to a memory device associated with the determined physical address, wherein the memory access request includes the determined physical address.

[0125] Example 44 includes the subject matter of Example 43, and wherein the circuitry for receiving a memory access request includes circuitry for receiving a notification from the computing board indicating a change in the mapping between a logical address and an associated physical address; and the accelerator board also includes circuitry for updating the mapping by the memory controller based on the indicated change.

[0126] Example 45 includes the subject matter of any one of Examples 43 and 44, and wherein the circuitry for receiving a memory access request further includes: circuitry for receiving a notification from a coordinator server indicating a change in the mapping between logical addresses and associated physical addresses; and the accelerator board further includes circuitry for updating the mapping by the memory controller based on the indicated change.

[0127] Example 46 includes the subject matter of any one of Examples 43-45, and wherein the circuitry for receiving a memory access request from an accelerator device includes circuitry for receiving a memory access request from a field-programmable gate array (FPGA).

[0128] Example 47 includes the subject of any one of Examples 43-46, and wherein the circuitry for routing memory access requests includes circuitry for sending memory access requests from a memory controller to another board via a network interface controller on the accelerator board.

[0129] Example 48 includes the subject of any one of Examples 43-47, and wherein the circuitry for routing memory access requests further includes: circuitry for sending memory access requests from the memory controller to the computing board associated with the workload, for which the functionality is accelerated by the accelerator device of the accelerator board.

[0130] Example 49 includes the subject of any one of Examples 43-48, and wherein the circuitry for routing memory access requests includes circuitry for routing memory access requests to another accelerator device on the same accelerator board.

[0131] Example 50 includes the subject of any one of Examples 43-49, and wherein the other accelerator device is a field-programmable gate array (FPGA).

[0132] Example 51 includes the subject of any one of Examples 43-50, and wherein the circuitry for routing memory access requests includes circuitry for routing the memory access request to the local memory of the accelerator device that sent the request.

[0133] Example 52 includes the subject matter of any one of Examples 43-51, and wherein the circuitry for routing to local memory includes: circuitry for sending a notification via a memory controller to the requester accelerator device that associates a logical address with a physical address in the local memory of the requester accelerator device; and circuitry for using the requester accelerator device to access the local memory of the accelerator device.

[0134] Example 53 includes the subject matter of any one of Examples 43-52, and wherein the accelerator device is an application-specific integrated circuit (ASIC).

[0135] Example 54 includes the subject matter of any one of Examples 43-53, and wherein the circuitry for routing memory access requests includes circuitry for routing memory access requests to another memory device on the memory board.

[0136] Example 55 includes the subject matter of any one of Examples 43-54, and wherein the circuitry for routing to another memory device includes circuitry for sending a notification via a memory controller to the requester accelerator device that associates a logical address with a physical address in another memory device on the memory board; and circuitry for accessing the other memory device on the memory board using the requester accelerator device.

Claims

1. An accelerator plate, comprising: Accelerator equipment; A memory controller, coupled to the accelerator device; as well as Circuit, used for: The memory controller receives a memory access request from the accelerator device to access a memory region, wherein the request uses a logical address to identify the memory region; The physical address associated with the memory region is determined based on the mapping between logical addresses and associated physical addresses; and The memory access request is routed to a memory device associated with a determined physical address, wherein the memory access request includes the determined physical address; The circuit is also used for: Receive a notification from the computing board or coordinator server indicating a change in the mapping between the logical address and the associated physical address; and Update the mapping based on the changes in the indication.

2. The accelerator plate according to claim 1, wherein, Receiving the memory access request from the accelerator device includes receiving the memory access request from a field-programmable gate array (FPGA).

3. The accelerator plate according to claim 1, wherein, Routing the memory access request includes sending the memory access request from the memory controller to another board via the network interface controller on the accelerator board.

4. The accelerator plate according to claim 3, wherein, Routing the memory access request further includes sending the memory access request from the memory controller to a compute board associated with a workload, wherein, for the workload, the functionality is accelerated by the accelerator device of the accelerator board.

5. The accelerator plate according to claim 1, wherein, Routing the memory access request includes routing the memory access request to another accelerator device on the same accelerator board.

6. The accelerator plate according to claim 5, wherein, The other accelerator device is a field-programmable gate array (FPGA).

7. The accelerator plate according to claim 1, wherein, Routing the memory access request includes routing the memory access request to the local memory of the accelerator device that sent the request.

8. The accelerator plate according to claim 7, wherein, Routing to the local storage includes: The notification, via the memory controller, associates the logical address with the physical address in the local memory of the requester accelerator device; and The requester accelerator device is used to access the local memory of the accelerator device.

9. The accelerator plate according to claim 1, wherein, The accelerator device is an application-specific integrated circuit (ASIC).

10. The accelerator plate according to claim 1, wherein, Routing the memory access request includes routing the memory access request to the memory device on the memory board.

11. The accelerator plate according to claim 10, wherein, Routing to the memory device includes: The memory controller sends a notification associating the logical address with the physical address in the memory device of the memory board to the requester accelerator device; and Access to the memory device on the memory board is made using the requester accelerator device.

12. An accelerator plate comprising: Circuitry for receiving memory access requests from the accelerator device coupled to the accelerator board for accessing a memory region by a memory controller of the accelerator device, wherein the request uses a logical address to identify the memory region. A unit for determining the physical address associated with the memory region based on the mapping between logical addresses and associated physical addresses; and Circuitry for routing the memory access request to a memory device associated with a determined physical address via the memory controller, wherein the memory access request includes the determined physical address; The circuitry for receiving the memory access request includes: circuitry for receiving a notification from a computing board or coordinator server, the notification indicating a change in the mapping between the logical address and the associated physical address; and the accelerator board further includes circuitry for updating the mapping by the memory controller based on the indicated change.

13. The accelerator plate according to claim 12, wherein, The circuitry for receiving the memory access request from the accelerator device includes: circuitry for receiving the memory access request from a field-programmable gate array (FPGA).

14. The accelerator plate according to claim 12, wherein, The circuitry for routing the memory access request includes circuitry for sending the memory access request from the memory controller to another board via the network interface controller on the accelerator board.

15. The accelerator plate according to claim 14, wherein, The circuitry for routing the memory access request further includes circuitry for sending the memory access request from the memory controller to a computing board associated with a workload, wherein, for the workload, the functionality is accelerated by the accelerator device of the accelerator board.

16. The accelerator plate according to claim 12, wherein, The circuitry for routing the memory access request includes circuitry for routing the memory access request to another accelerator device on the same accelerator board.

17. The accelerator plate according to claim 16, wherein, The other accelerator device is a field-programmable gate array (FPGA).

18. The accelerator plate according to claim 12, wherein, The circuitry for routing the memory access request includes circuitry for routing the memory access request to the local memory of the accelerator device that sent the request.

19. The accelerator plate according to claim 18, wherein, The circuitry for routing to the local memory includes: Circuitry for sending a notification, via the memory controller, associating the logical address with a physical address in the local memory of the requester accelerator device; and Circuitry for accessing the local memory of the accelerator device using the requester's accelerator device.

20. The accelerator plate according to claim 12, wherein, The circuitry for routing the memory access request includes circuitry for routing the memory access request to another memory device on the memory board.

21. The accelerator plate according to claim 20, wherein, The circuitry for routing to the other memory device includes: Circuitry for sending a notification, via the memory controller, associating the logical address with a physical address in another memory device on the memory board to the requester accelerator device; and Circuitry for accessing the other memory device on the memory board using the requester accelerator device.

22. A method for providing a memory region for an accelerator board, comprising: The memory controller of the accelerator device coupled to the accelerator board receives a memory access request from the accelerator device to access a memory region, wherein the request identifies the memory region using a logical address; The physical address associated with the memory region is determined based on the mapping between logical addresses and associated physical addresses; The memory access request is routed to a memory device associated with a determined physical address via the memory controller, wherein the memory access request includes the determined physical address; The method further includes: Receive a notification from the computing board or coordinator server indicating a change in the mapping between the logical address and the associated physical address; and The memory controller updates the mapping based on the indicated changes.

23. The method according to claim 22, wherein, Receiving the memory access request from the accelerator device includes receiving the memory access request from a field-programmable gate array (FPGA).

24. The method according to claim 22, wherein, Routing the memory access request includes sending the memory access request to another board via the memory controller through the network interface controller on the accelerator board.

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