Apparatus and method for performing real part multiplication and addition-subtraction

Abstract

The exemplary method includes: multiplying the packed N-bit real data elements in a first source register by the packed M-bit real data elements in a second source register; multiplying the packed N-bit imaginary data elements in the first source register by the packed M-bit imaginary data elements in the second source register to generate at least four real products; subtracting the first real product from the second real product and subtracting the third real product from the fourth real product to respectively generate first and second temporary results; adding the first temporary result to the first packed N-bit data element, subtracting the first temporary result from the first packed N-bit data element, adding the second temporary result to the second packed N-bit data element, and subtracting the second temporary result from the second packed N-bit data element to respectively generate first through fourth pre-scaled results; scaling the first through fourth pre-scaled results to respectively generate first through fourth final results; and storing the first through fourth final results in the specified data element locations.

Description

Background Art Technical Field

[0001] Embodiments of the present invention generally relate to the field of computer processors. More specifically, embodiments relate to apparatus and methods for performing multiplication and addition and / or subtraction of real parts (potentially, accompanied by scaling, rounding, and saturation).

[0002] Description of Related Art

[0003] An instruction set or instruction set architecture (ISA) is the part of a computer architecture that deals with programming, including native data types, instructions, register architecture, addressing modes, memory architecture, interrupt and exception handling, and external input and output (I / O). It should be noted that the term "instruction" generally refers to a macro-instruction in this document - that is, an instruction provided to the processor for execution - rather than a micro-instruction or micro-operation - that is, the micro-instruction or micro-operation is the result of the processor's decoder decoding the macro-instruction. The micro-instruction or micro-operation can be configured to instruct an execution unit on the processor to perform an operation to implement the logic associated with the macro-instruction.

[0004] The ISA is different from the microarchitecture, which is a collection of processor design techniques for implementing the instruction set. Processors with different microarchitectures can share a common instruction set. For example, the Pentium 4 processor, Core TM (Core TM ) processors, and multiple processors from Advanced Micro Devices, Inc. in Sunnyvale, California, implement nearly identical versions of the x86 instruction set (with some extensions added with updated versions), but have different internal designs. For example, the same register architecture of the ISA can be implemented in different ways using well-known techniques in different microarchitectures, including dedicated physical registers, one or more dynamically allocated physical registers using a register renaming mechanism (e.g., using a register alias table (RAT), a reorder buffer (ROB), and a retirement register file). Unless otherwise specified, the phrases "register architecture", "register file", and "register" are used in this document to refer to the register architecture, register file, and register that are visible to the software / programmer and the way instructions specify registers. In cases where a distinction is needed, the adjectives "logical", "architectural", or "software visible" will be used to indicate registers / register files in the register architecture, while different adjectives will be used to specify registers in a given microarchitecture (e.g., physical registers, reorder buffers, retirement registers, register pools).

[0005] Multiplication-accumulation is a common digital signal processing operation that calculates the product of two numbers and adds the product to an accumulated value. Existing single instruction multiple data (SIMD) microarchitectures implement the multiplication-accumulation operation by executing a sequence of instructions. For example, a multiplication instruction can be utilized, followed by a 4-way addition, and then an accumulation using the destination quadword data to perform the multiplication-accumulation to generate two 64-bit saturated results. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] A better understanding of the present invention can be obtained from the following detailed description in conjunction with the following drawings, in which:

[0007] Figure 1A and Figure 1B are block diagrams illustrating a general vector-friendly instruction format and its instruction templates according to an embodiment of the present invention;

[0008] Figures 2A - 2C is a block diagram illustrating an exemplary VEX instruction format according to an embodiment of the present invention;

[0009] Figure 3 is a block diagram of a register architecture according to an embodiment of the present invention; and

[0010] Figure 4A is a block diagram illustrating both an exemplary in-order fetch, decode, retire pipeline and an exemplary out-of-order issue / execution pipeline with register renaming according to an embodiment of the present invention;

[0011] Figure 4B is a block diagram illustrating an exemplary embodiment of an in-order fetch, decode, retire core to be included in a processor and an exemplary out-of-order issue / execution architecture core with register renaming according to an embodiment of the present invention;

[0012] Figure 5A is a block diagram of a single processor core and its connection to an on-die interconnect network;

[0013] Figure 5B illustrates according to an embodiment of the present invention Figure 5A an expanded view of a portion of the processor core in

[0014] Figure 6 is a block diagram of a single-core processor and a multi-core processor with an integrated memory controller and a graphics device according to an embodiment of the present invention;

[0015] Figure 7 illustrates a block diagram of a system according to an embodiment of the present invention;

[0016] Figure 8 illustrates a block diagram of a second system according to an embodiment of the present invention;

[0017] Figure 9 The figure shows a block diagram of a third system according to an embodiment of the present invention;

[0018] Figure 10 The figure shows a block diagram of a system-on-chip (SoC) according to an embodiment of the present invention;

[0019] Figure 11 The figure shows a block diagram of converting binary instructions in a source instruction set into binary instructions in a target instruction set by using a software instruction converter according to an embodiment of the present invention;

[0020] Figure 12 The figure shows a processor architecture on which an embodiment of the present invention can be implemented;

[0021] Figure 13 The figure shows a plurality of packed data elements including real-valued and complex-valued according to one embodiment;

[0022] Figure 14 The figure shows a packed data processing architecture according to an embodiment of the present invention;

[0023] Figure 15 The figure shows an exemplary implementation of a fast Fourier transform (FFT);

[0024] Figure 16 The figure shows an embodiment of a data processing architecture for implementing an FFT operation;

[0025] Figures 17A - 17B The figure shows a method according to an embodiment of the present invention;

[0026] Figures 18A - 18B The figure shows a method according to an embodiment of the present invention. Detailed Description of the Invention

[0027] In the following description, for the purpose of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present invention described below. However, it will be apparent to one of ordinary skill in the art that some of these specific details may not be required to practice the embodiments of the present invention. In other instances, well-known structures and devices are shown in block diagram form to avoid obscuring the basic principles of the embodiments of the present invention.

[0028] Exemplary Processor Architectures, Instruction Formats, and Data Types

[0029] The instruction set includes one or more instruction formats. A given instruction format defines various fields (number of bits, position of bits) to specify the operation to be performed (opcode) and the operand(s) on which the operation is to be performed, etc. Some instruction formats are further decomposed by the definition of instruction templates (or sub-formats). For example, an instruction template of a given instruction format can be defined as different subsets of the fields of that instruction format (the included fields are typically in the same order, but at least some fields have different bit positions as fewer fields are included), and / or defined as having a given field interpreted in a different way. Thus, each instruction of the ISA is expressed using a given instruction format (and if defined, according to a given one of the instruction templates in that instruction format), and includes fields for specifying the operation and operands. For example, an exemplary ADD (addition) instruction has a specific opcode and instruction format, and the specific instruction format includes an opcode field for specifying the opcode and operand fields for selecting the operands (source 1 / destination and source 2); and the appearance of the ADD instruction in the instruction stream will result in specific contents in the operand fields for selecting specific operands.

[0030] Embodiments of the (multiple) instructions described herein can be embodied in different formats. Additionally, exemplary systems, architectures, and pipelines are detailed below. Embodiments of the (multiple) instructions can be executed on such systems, architectures, and pipelines, but are not limited to those detailed.

[0031] General vector-friendly instruction format

[0032] A vector-friendly instruction format is an instruction format suitable for vector instructions (e.g., there are specific fields dedicated to vector operations). Although embodiments are described in which both vector and scalar operations are supported by the vector-friendly instruction format, alternative embodiments use only vector operations via the vector-friendly instruction format.

[0033] Figures 1A - 1B is a block diagram illustrating a general vector-friendly instruction format and its instruction templates according to an embodiment of the present invention. Figure 1A is a block diagram illustrating a general vector-friendly instruction format and its Class A instruction templates according to an embodiment of the present invention; and Figure 1B is a block diagram illustrating a general vector-friendly instruction format and its Class B instruction templates according to an embodiment of the present invention. Specifically, Class A and Class B instruction templates are defined for the general vector-friendly instruction format 100, both of which include instruction templates for memoryless access 105 and instruction templates for memory access 120. The term "general" in the context of the vector-friendly instruction format refers to an instruction format that is not tied to any specific instruction set.

[0034] While embodiments of the present invention will be described in which a vector-friendly instruction format supports the following: a 64-byte vector operand length (or size) with a 32-bit (4-byte) or 64-bit (8-byte) data element width (or size) (and thus, a 64-byte vector is composed of 16 double-word-sized elements, or alternatively, 8 quad-word-sized elements); a 64-byte vector operand length (or size) with a 16-bit (2-byte) or 8-bit (1-byte) data element width (or size); a 32-byte vector operand length (or size) with a 32-bit (4-byte), 64-bit (8-byte), 16-bit (2-byte), or 8-bit (1-byte) data element width (or size); and a 16-byte vector operand length (or size) with a 32-bit (4-byte), 64-bit (8-byte), 16-bit (2-byte), or 8-bit (1-byte) data element width (or size); alternative embodiments may support larger, smaller, and / or different vector operand sizes (e.g., a 256-byte vector operand) with larger, smaller, or different data element widths (e.g., a 128-bit (16-byte) data element width).

[0035] Figure 1A The Class A instruction templates in include: 1) within the instruction template without memory access 105, an instruction template showing a fully rounded control type operation 110 without memory access and an instruction template of a data transformation type operation 115 without memory access; and 2) within the instruction template with memory access 120, an instruction template showing the timeliness 125 of memory access and an instruction template of the non-timeliness 130 of memory access. Figure 1B The Class B instruction templates in include: 1) within the instruction template without memory access 105, an instruction template showing a write mask controlled partially rounded control type operation 112 without memory access and an instruction template of a write mask controlled vsize type operation 117 without memory access; and 2) within the instruction template with memory access 120, an instruction template showing the write mask control 127 of memory access.

[0036] The general vector-friendly instruction format 100 includes the following fields in the order listed as shown in Figures 1A - 1B as follows.

[0037] Format field 140 - The specific value (instruction format identifier value) in this field uniquely identifies the vector-friendly instruction format and thus identifies that the instruction appears in the instruction stream in the vector-friendly instruction format. Thus, this field is optional in the sense that it is not required for an instruction set that only has the general vector-friendly instruction format.

[0038] Base operation field 142 - The content of which differentiates different base operations.

[0039] Register index field 144 - whose content directly or through address generation specifies the location of source or destination operands in registers or in memory. These fields include a sufficient number of bits to select N registers from a PxQ (e.g., 32x512, 16x128, 32x1024, 64x1024) register file. Although in one embodiment N can be up to three source registers and one destination register, alternative embodiments may support more or fewer source and destination registers (e.g., may support up to two sources, where one of these sources also serves as a destination; may support up to three sources, where one of these sources also serves as a destination; may support up to two sources and one destination).

[0040] Modifier field 146 - whose content differentiates instructions in general vector instruction format that specify memory access from those that do not; i.e., differentiates between instruction templates with no memory access 105 and those with memory access 120. Memory access operations read and / or write to the memory hierarchy (in some cases, using values in registers to specify source and destination addresses), while non-memory access operations do not (e.g., source and / or destination are registers). Although in one embodiment, this field also selects between three different ways to perform memory address calculation, alternative embodiments may support more, fewer, or different ways to perform memory address calculation.

[0041] Extended operation field 150 - whose content differentiates which one of various different operations, in addition to the base operation, is to be performed. This field is context-dependent. In one embodiment of the present invention, this field is divided into a class field 168, an alpha field 152, and a beta field 154. The extended operation field 150 allows multiple sets of common operations to be performed in a single instruction rather than in 2, 3, or 4 instructions.

[0042] Scale field 160 - whose content allows the content of the index field used for memory address generation (e.g., for address generation using (2 比例 * index + base) to be scaled.

[0043] Displacement field 162A - whose content is used as part of memory address generation (e.g., for address generation using (2 比例 * index + base + displacement).

[0044] Displacement factor field 162B (note that the displacement field 162A directly juxtaposed on the displacement factor field 162B indicates the use of one or the other) - the content of which is used as part of address generation; it specifies the displacement factor that will scale the size (N) of the memory access - where N is the number of bytes in the memory access (e.g., for address generation using (2 比例 * index + base address + scaled displacement)). Redundant low-order bits are ignored, and thus the content of the displacement factor field is multiplied by the total size (N) of the memory operand to generate the final displacement that will be used in calculating the effective address. The value of N is determined by the processor hardware at runtime based on the full opcode field 174 (described later in this document) and the data manipulation field 154C. The displacement field 162A and the displacement factor field 162B are optional in the sense that they are not used in instruction templates without memory access 105 and / or different embodiments may implement only one of the two or neither of the two.

[0045] Data element width field 164 - the content of which differentiates which of the multiple data element widths will be used (used for all instructions in some embodiments; only for some instructions in other embodiments). This field is optional in the sense that it is not needed if only one data element width is supported and / or some aspect of the opcode is used to support the data element width.

[0046] Write mask field 170 - whose content controls, on a per data element position basis, whether the data element positions in the destination vector operand reflect the results of the base operation and the extension operation. Class A instruction templates support merge-write masking, while Class B instruction templates support both merge-write masking and zero-write masking. When merging, the vector mask allows any set of elements in the destination to be protected from update during the execution of any operation (specified by the base operation and the extension operation); in another embodiment, the old value of each element of the destination where the corresponding mask bit has 0 is maintained. In contrast, when zeroing, the vector mask allows any set of elements in the destination to be zeroed during the execution of any operation (specified by the base operation and the extension operation); in one embodiment, the elements of the destination are set to 0 when the corresponding mask bit has a 0 value. A subset of this functionality is the ability to control the vector length of the operation being performed (i.e., the span from the first to the last element being modified), however, the elements being modified do not have to be contiguous. Thus, the write mask field 170 allows partial vector operations, which include loads, stores, arithmetic, logic, etc. Although embodiments of the invention have been described in which the content of the write mask field 170 selects one of a plurality of write mask registers that contains the write mask to be used (and thus, the content of the write mask field 170 indirectly identifies the masking to be performed), alternative embodiments alternatively or additionally allow the content of the mask write field 170 to directly specify the masking to be performed.

[0047] Immediate field 172 - whose content allows the specification of an immediate value. This field is optional in the sense that it does not exist in a general vector friendly format that does not support immediates and does not exist in instructions that do not use immediates.

[0048] Class field 168 - whose content differentiates between different classes of instructions. Refer to Figures 1A - 1B , the content of this field selects between Class A and Class B instructions. In Figures 1A - 1B , rounded rectangles are used to indicate that a particular value exists in the field (e.g., Class A 168A and Class B 168B for the class field 168 in Figures 1A - 1B respectively).

[0049] Class A instruction templates

[0050] In the case of the instruction template for Class A non-memory access 105, the α field 152 is interpreted as an RS field 152A whose content differentiates which one of different expansion operation types is to be performed (e.g., for the instruction templates of rounding-type operations 110 without memory access and data transformation-type operations 115 without memory access, rounding 152A.1 and data transformation 152A.2 are specified respectively), and the β field 154 differentiates which one of the operations of the specified type is to be performed. In the instruction template for non-memory access 105, the scale field 160, displacement field 162A, and displacement factor field 162B do not exist.

[0051] Instruction template for non-memory access - fully rounded control type operation

[0052] In the instruction template for the fully rounded control type operation 110 without memory access, the β field 154 is interpreted as a rounding control field 154A whose (multiple) content provides static rounding. Although in the described embodiments of the present invention the rounding control field 154A includes a suppress all floating-point exceptions (SAE) field 156 and a rounding operation control field 158, alternative embodiments may support both concepts, may encode both concepts into the same field, or have only one or the other of these concepts / fields (e.g., may have only the rounding operation control field 158).

[0053] SAE field 156 - whose content differentiates whether to disable exception event reporting; when the content of the SAE field 156 indicates enabling suppression, a given instruction does not report any kind of floating-point exception flag and does not invoke any floating-point exception handler.

[0054] Rounding operation control field 158 - whose content differentiates which one of a set of rounding operations is to be performed (e.g., round up, round down, round towards zero, and round to nearest). Thus, the rounding operation control field 158 allows the rounding mode to be changed instruction by instruction. In one embodiment of the present invention in which the processor includes a control register for specifying the rounding mode, the content of the rounding operation control field 158 overrides the register value.

[0055] Instruction template for non-memory access - data transformation type operation

[0056] In the instruction template for the data transformation type operation 115 without memory access, the β field 154 is interpreted as a data transformation field 154B whose content differentiates which one of multiple data transformations is to be performed (e.g., no data transformation, mix, broadcast).

[0057] In the case of the instruction template for Class A memory access 120, the α field 152 is interpreted as an eviction hint field 152B whose content differentiates which eviction hint is to be used (inFigure 1A In it, for the instruction templates of memory access timeliness 125 and memory access non - timeliness 130, timeliness 152B.1 and non - timeliness 152B.2 are respectively specified), and the β field 154 is interpreted as a data manipulation field 154C, the content of which differentiates which one of multiple data manipulation operations (also called primitives) is to be executed (for example, no manipulation, broadcast, up - conversion of the source, and down - conversion of the destination). The instruction template of the memory access 120 includes a scale field 160 and optionally includes a displacement field 162A or a displacement factor field 162B.

[0058] Vector memory instructions use conversion support to perform vector loads from memory and vector stores to memory. Like ordinary vector instructions, vector memory instructions transfer data to / from memory in a data - element - by - data - element manner, where the actually transferred elements are specified by the content of the vector mask selected as the write mask.

[0059] Instruction template for memory access - Timely

[0060] Timely data is data that may be reused quickly enough to benefit from cache operations. However, this is a hint, and different processors can implement it in different ways, including completely ignoring the hint.

[0061] Instruction template for memory access - Non - timely

[0062] Non - timely data is data that is unlikely to be reused quickly enough to benefit from cache operations in the first - level cache and should be given eviction priority. However, this is a hint, and different processors can implement it in different ways, including completely ignoring the hint.

[0063] Class B instruction template

[0064] In the case of the Class B instruction template, the α field 152 is interpreted as a write - mask control (Z) field 152C, the content of which differentiates whether the write masking controlled by the write - mask field 170 should be merged or zeroed.

[0065] In the case of the instruction template for a class B non-memory access 105, a portion of the β field 154 is interpreted as an RL field 157A, the content of which differentiates which one of different extended operation types is to be performed (e.g., for the instruction template of the write mask control partial rounding control type operation 112 for non-memory access and the instruction template of the write mask control VSIZE type operation 117 for non-memory access, rounding 157A.1 and vector length (VSIZE) 157A.2 are specified respectively), while the remaining portion of the β field 154 differentiates which one of the operations of the specified type is to be performed. In the instruction template for non-memory access 105, the scale field 160, displacement field 162A, and displacement factor field 162B do not exist.

[0066] In the instruction template for the write mask control partial rounding control type operation 110 for non-memory access, the remaining portion of the β field 154 is interpreted as a rounding operation control field 159A, and exception event reporting is disabled (the given instruction does not report any kind of floating-point exception flag and does not invoke any floating-point exception handler).

[0067] The rounding operation control field 159A - like the rounding operation control field 158, the content of which differentiates which one of a set of rounding operations is to be performed (e.g., round up, round down, round towards zero, and round to nearest). Thus, the rounding operation control field 159A allows the rounding mode to be changed instruction by instruction. In one embodiment of the present invention in which the processor includes a control register for specifying the rounding mode, the content of the rounding operation control field 158 overrides the register value.

[0068] In the instruction template for the write mask control VSIZE type operation 117 for non-memory access, the remaining portion of the β field 154 is interpreted as a vector length field 159B, the content of which differentiates which one of multiple data vector lengths is to be performed (e.g., 128 bytes, 256 bytes, or 512 bytes).

[0069] In the case of the instruction template for a class B memory access 120, a portion of the β field 154 is interpreted as a broadcast field 157B, the content of which differentiates whether a broadcast type data manipulation operation is to be performed, while the remaining portion of the β field 154 is interpreted as a vector length field 159B. The instruction template for memory access 120 includes a scale field 160 and optionally includes a displacement field 162A or a displacement factor field 162B.

[0070] For a general vector friendly instruction format 100, a complete opcode field 174 is shown to include a format field 140, a base operation field 142, and a data element width field 164. Although one embodiment is shown in which the complete opcode field 174 includes all of these fields, in embodiments that do not support all of these fields, the complete opcode field 174 includes fewer than all of these fields. The complete opcode field 174 provides an operation code (opcode).

[0071] An extended operation field 150, a data element width field 164, and a write mask field 170 allow these features to be specified on a per-instruction basis in a general vector friendly instruction format.

[0072] The combination of the write mask field and the data element width field creates various types of instructions because these instructions allow the mask to be applied based on different data element widths.

[0073] The various instruction templates that occur within classes A and B are beneficial in different scenarios. In some embodiments of the present invention, different processors or different cores within a processor may support only class A, only class B, or may support both classes. For example, a high-performance general out-of-order core intended for general computing may support only class B, a core intended primarily for graphics and / or scientific (throughput) computing may support only class A, and a core intended for both general computing and graphics and / or scientific (throughput) computing may support both class A and class B (of course, a core with some mix of templates and instructions from both classes, but not all templates and instructions from both classes, is within the scope of the present invention). Similarly, a single processor may include multiple cores, all of which support the same class, or where different cores support different classes. For example, in a processor with separate graphics and general cores, one core in the graphics core intended primarily for graphics and / or scientific computing may support only class A, while one or more in the general core may be high-performance general out-of-order cores with register renaming that support only class B for general computing. Another processor without a separate graphics core may include one or more general in-order or out-of-order cores that support both class A and class B. Of course, in different embodiments of the present invention, features from one class may also be implemented in other classes. This will cause programs written in a high-level language to be (e.g., just-in-time compiled or statically compiled) into various different executable forms, including: 1) a form having only instructions of the (multiple) classes supported by the target processor for execution; or 2) a form having alternative routines and control flow code that use different combinations of instructions from all classes, where the control flow code selects these routines for execution based on the instructions supported by the processor currently executing the code.

[0074] VEX instruction format

[0075] VEX encoding allows instructions to have more than two operands and allows SIMD vector registers to be longer than 28 bits. The use of the VEX prefix provides a three-operand (or more-operand) syntax. For example, a previous two-operand instruction performed an operation that overwrote a source operand such as A = A + B. The use of the VEX prefix enables the operands to perform a non-destructive operation such as A = B + C.

[0076] Figure 2A The figure shows an exemplary AVX instruction format, including a VEX prefix 202, a real opcode field 230, a Mod R / M byte 240, a SIB byte 250, a displacement field 262, and an IMM8 272. Figure 2B The figure shows which fields from Figure 2A constitute the complete opcode field 274 and the base operation field 241. Figure 2C The figure shows which fields from Figure 2A constitute the register index field 284.

[0077] The VEX prefix (bytes 0-2) 202 is encoded in a three-byte form. The first byte is the format field 290 (VEX byte 0, bits [7:0]), which contains an explicit C4 byte value (a unique value for differentiating the C4 instruction format). The second and third bytes (VEX bytes 1-2) include several bit fields that provide dedicated capabilities. Specifically, the REX field 205 (VEX byte 1, bits [7-5]) consists of the VEX.R bit field (VEX byte 1, bit [7] – R), the VEX.X bit field (VEX byte 1, bit [6] – X), and the VEX.B bit field (VEX byte 1, bit [5] – B). The other fields of these instructions encode the lower three bits (rrr, xxx, and bbb) of the register index as known in the art, such that Rrrr, Xxxx, and Bbbb can be formed by incrementing VEX.R, VEX.X, and VEX.B. The opcode mapping field 215 (VEX byte 1, bits [4:0] – mmmmm) includes content for encoding the implicit leading opcode byte. The W field 264 (VEX byte 2, bit [7] – W) – denoted by the notation VEX.W and provides different functions depending on the instruction. The role of VEX.vvvv 220 (VEX byte 2, bits [6:3] - vvvv) can include the following: 1) VEX.vvvv encodes the first source register operand specified in inverted (1's complement) form and is valid for instructions with two or more source operands; 2) VEX.vvvv encodes the destination register operand specified in 1's complement form for certain vector displacements; or 3) VEX.vvvv does not encode any operand, and this field is reserved and should contain 1111b. If the VEX.L 268 size field (VEX byte 2, bit [2] - L) = 0, it indicates a 28-bit vector; if VEX.L = 1, it indicates a 256-bit vector. The prefix encoding field 225 (VEX byte 2, bits [1:0] - pp) provides additional bits for the base operation field 241.

[0078] The real opcode field 230 (byte 3) is also referred to as the opcode byte. A part of the opcode is specified in this field.

[0079] The MOD R / M field 240 (byte 4) includes the MOD field 242 (bits [7-6]), the Reg field 244 (bits [5-3]), and the R / M field 246 (bits [2-0]). The functions of the Reg field 244 can include the following: encoding the destination register operand or the source register operand (rrr of Rrrr); or being regarded as an opcode extension and not being used to encode any instruction operand. The functions of the R / M field 246 can include the following: encoding the instruction operand that references the memory address; or encoding the destination register operand or the source register operand.

[0080] Scale, Index, Base (SIB) - The content of the scale field 250 (byte 5) includes SS252 (bits [7-6]), which is used for memory address generation. The content of SIB.xxx 254 (bits [5-3]) and SIB.bbb 256 (bits [2-0]) has been mentioned previously for the register indexes Xxxx and Bbbb.

[0081] The displacement field 262 and the immediate field (IMM8) 272 contain data.

[0082] Exemplary Register Architecture

[0083] Figure 3 is a block diagram of a register architecture 300 according to an embodiment of the present invention. In the illustrated embodiment, there are 32 vector registers 310 that are 512 bits wide; these registers are referred to as zmm0 to zmm31. The lower 256 bits of the lower 16 zmm registers overlay on the registers ymm0-15. The lower 128 bits of the lower 16 zmm registers (the lower 128 bits of the ymm registers) overlay on the registers xmm0-15.

[0084] General-Purpose Registers 325 - In the illustrated embodiment, there are sixteen 64-bit general-purpose registers that are used with the existing x86 addressing modes to address memory operands. These registers are referred to by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 to R15.

[0085] The scalar floating-point stack register file (x87 stack) 345, on which the MMX packed integer flat register file 350 overlaps - In the illustrated embodiment, the x87 stack is an eight-element stack for performing scalar floating-point operations on 32 / 64 / 80-bit floating-point data using the x87 instruction set extension; while using the MMX registers to perform operations on 64-bit packed integer data and saving operands for some operations performed between the MMX and XMM registers.

[0086] Alternative embodiments of the present invention may use wider or narrower registers. Additionally, alternative embodiments of the present invention may use more, fewer, or different register files and registers.

[0087] Exemplary Core Architectures, Processors, and Computer Architectures

[0088] Processor cores can be implemented in different ways, for different purposes, and in different processors. For example, implementations of such cores can include: 1) general-purpose in-order cores intended for general computing; 2) high-performance general-purpose out-of-order cores intended for general computing; 3) specialized cores intended primarily for graphics and / or scientific (throughput) computing. Implementations of different processors can include: 1) a CPU that includes one or more general-purpose in-order cores intended for general computing and / or one or more general-purpose out-of-order cores intended for general computing; and 2) a coprocessor that includes one or more specialized cores intended primarily for graphics and / or scientific (throughput). Such different processors result in different computer system architectures, which can include: 1) a coprocessor on a chip separate from the CPU; 2) a coprocessor in the same package as the CPU but on a separate die; 3) a coprocessor on the same die as the CPU (in which case, such a coprocessor is sometimes referred to as specialized logic or as a specialized core, such specialized logic such as integrated graphics and / or scientific (throughput) logic); and 4) a system-on-a-chip that can include the described CPU (sometimes referred to as the (multiple) application core or (multiple) application processors), the coprocessor described above, and additional functionality on the same die. An exemplary core architecture is then described, followed by exemplary processors and computer architectures. Circuits (units) including example cores, processors, etc. are described in detail herein.

[0089] Exemplary Core Architecture

[0090] Figure 4A is a block diagram illustrating an exemplary in-order pipeline and an exemplary register-renamed out-of-order issue / execution pipeline in accordance with embodiments of the present invention. Figure 4B is a block diagram showing an exemplary embodiment of an in-order architecture core to be included in a processor and an exemplary register-renamed out-of-order issue / execution architecture core in accordance with embodiments of the present invention. Figures 4A - 4B The solid boxes in illustrate the in-order pipeline and in-order core, while the optional addition of the dashed boxes illustrates the register-renamed, out-of-order issue / execution pipeline and core. Given that the in-order aspects are a subset of the out-of-order aspects, the out-of-order aspects will be described.

[0091] In Figure 4AIn the processor pipeline 400, it includes an instruction fetch stage 402, a length decoding stage 404, a decoding stage 406, an allocation stage 408, a renaming stage 410, a scheduling (also known as dispatch or issue) stage 412, a register read / memory read stage 414, an execution stage 416, a write-back / memory write stage 418, an exception handling stage 422, and a commit stage 424.

[0092] Figure 4B A processor core 490 is shown, which includes a front-end unit 430 that is coupled to an execution engine unit 450, and both the front-end unit 430 and the execution engine unit 450 are coupled to a memory unit 470. The core 490 can be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As another option, the core 490 can be a specialized core, such as, for example, a network or communication core, a compression engine, a coprocessor core, a general-purpose computing graphics processing unit (GPGPU) core, a graphics core, and so on.

[0093] The front-end unit 430 includes a branch prediction unit 432 that is coupled to an instruction cache unit 434, the instruction cache unit 434 is coupled to an instruction translation lookaside buffer (TLB) 436, the instruction translation lookaside buffer 436 is coupled to an instruction fetch unit 438, and the instruction fetch unit 438 is coupled to a decoding unit 440. The decoding unit 440 (or decoder) can decode instructions and generate, as output, one or more micro-operations, microcode entry points, microinstructions, other instructions, or other control signals that are decoded from the original instructions, or otherwise reflect the original instructions, or are derived from the original instructions. The decoding unit 440 can be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLAs), microcode read-only memories (ROMs), etc. In one embodiment, the core 490 includes a microcode ROM or other medium that stores microcode for certain macro instructions (e.g., in the decoding unit 440, or otherwise within the front-end unit 430). The decoding unit 440 is coupled to a rename / allocator unit 452 in the execution engine unit 450.

[0094] The execution engine unit 450 includes a rename / allocator unit 452 that is coupled to a retirement unit 454 and a collection 456 of one or more scheduler units. The (multiple) scheduler units 456 represent any number of different schedulers, including reservation stations, a central instruction window, and the like. The (multiple) scheduler units 456 are coupled to the (multiple) physical register file units 458. Each of the (multiple) physical register file units 458 represents one or more physical register files, where different physical register files store one or more different data types, such as scalar integers, scalar floating points, packed integers, packed floating points, vector integers, vector floating points, status (e.g., an instruction pointer that is the address of the next instruction to be executed), and so on. In one embodiment, the (multiple) physical register file units 458 include a vector register unit and a scalar register unit. These register units may provide architectural vector registers, vector mask registers, and general-purpose registers. The (multiple) physical register file units 458 are overlapped by the retirement unit 454 to illustrate various ways in which register renaming and out-of-order execution can be implemented (e.g., using the (multiple) reorder buffers and the (multiple) retirement register files; using the (multiple) future files, the (multiple) history buffers, the (multiple) retirement register files; using register maps and register pools, and so on). The retirement unit 454 and the (multiple) physical register file units 458 are coupled to the (multiple) execution clusters 460. The (multiple) execution clusters 460 include a collection 462 of one or more execution units and a collection 464 of one or more memory access units. The execution units 462 can perform various operations (e.g., shift, add, subtract, multiply) and can operate on various data types (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). Although some embodiments may include multiple execution units dedicated to a particular function or set of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. The (multiple) scheduler units 456, the (multiple) physical register file units 458, and the (multiple) execution clusters 460 are shown as potentially multiple because certain embodiments create separate pipelines for certain types of data / operations (e.g., a scalar integer pipeline, a scalar floating point / packed integer / packed floating point / vector integer / vector floating point pipeline, and / or a memory access pipeline each having its own scheduler unit, (multiple) physical register file units, and / or execution cluster - and in the case of a separate memory access pipeline, certain embodiments are implemented where only the execution cluster of that pipeline has the (multiple) memory access units 464). It should also be understood that in the case of using separate pipelines, one or more of these pipelines may be out-of-order issue / execution, and the remaining pipelines may be in-order.

[0095] A set 464 of memory access units is coupled to a memory unit 470 that includes a data TLB unit 472, which is coupled to a data cache unit 474, which is coupled to a second level (L2) cache unit 476. In one exemplary embodiment, the memory access unit 464 may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit 472 in the memory unit 470. An instruction cache unit 434 is also coupled to the second level (L2) cache unit 476 in the memory unit 470. The L2 cache unit 476 is coupled to one or more other levels of cache and ultimately to main memory.

[0096] As an example, an exemplary register-renaming out-of-order issue / execution core architecture may implement a pipeline 400 as follows: 1) Instruction fetch 438 performs a fetch stage 402 and a length decoding stage 404; 2) A decode unit 440 performs a decode stage 406; 3) A rename / allocator unit 452 performs an allocation stage 408 and a rename stage 410; 4) A (plural) scheduler unit 456 performs a schedule stage 412; 5) A (plural) physical register file unit 458 and a memory unit 470 perform a register read / memory read stage 414; An execution cluster 460 performs an execution stage 416; 6) The memory unit 470 and the (plural) physical register file unit 458 perform a write-back / memory write stage 418; 7) Each unit may be involved in an exception handling stage 422; and 8) A retirement unit 454 and the (plural) physical register file unit 458 perform a commit stage 424.

[0097] The core 490 may support one or more instruction sets (e.g., the x86 instruction set (with some extensions added with more recent versions); the MIPS instruction set of MIPS Technologies, Inc., in Sunnyvale, California; the ARM instruction set of ARM Holdings, Inc., in Sunnyvale, California (with optional additional extensions such as NEON)), including the (plural) instructions described herein. In one embodiment, the core 490 includes logic for supporting SIMD (e.g., AVX1, AVX2) instruction set extensions, thereby allowing operations used by many multimedia applications to be performed using SIMD data.

[0098] It should be understood that the core may support multithreading (executing a set of two or more parallel operations or threads), and this multithreading may be accomplished in various ways, including time division multithreading, simultaneous multithreading (where a single physical core provides a logical core for each of the threads for which the physical core is simultaneously multithreading), or a combination thereof (e.g., time division fetching and decoding and thereafter such as Simultaneous multithreading in hyperthreading technology).

[0099] Although register renaming has been described in the context of out-of-order execution, it should be understood that register renaming can be used in an in-order architecture. Although the illustrated embodiments of the processor also include separate instruction and data cache units 434 / 474 and a shared L2 cache unit 476, alternative embodiments may have a single internal cache for both instructions and data, such as, for example, a first-level (L1) internal cache or multiple levels of internal caches. In some embodiments, the system may include a combination of internal caches and external caches outside the core and / or processor. Alternatively, all caches may be outside the core and / or processor.

[0100] Specific exemplary in-order core architecture

[0101] Figures 5A - 5B A block diagram illustrating a more specific exemplary in-order core architecture, which would be one of several logic blocks (including other cores of the same type and / or different types) in a chip. Depending on the application, the logic block communicates with some fixed-function logic, memory I / O interfaces, and other necessary I / O logic via a high-bandwidth interconnect network (e.g., a ring network).

[0102] Figure 5A A block diagram of a single processor core according to an embodiment of the present invention, its connection to the on-die interconnect network 502, and a local subset 504 of its second-level (L2) cache. In one embodiment, the instruction decoder 500 supports the x86 instruction set with a compact data instruction set extension. The L1 cache 506 allows low-latency access to the cache memory for data entering the scalar and vector units. Although in one embodiment (for simplicity of design), the scalar unit 508 and the vector unit 510 use separate register sets (scalar registers 512 and vector registers 514, respectively), and the data transferred between these registers is written to memory and then read back from the first-level (L1) cache 506, alternative embodiments of the present invention may use different methods (e.g., using a single register set or including a communication path that allows data to be transferred between the two register banks without being written and read back).

[0103] The local subset 504 of the L2 cache is part of the global L2 cache, which is partitioned into multiple separate local subsets, one for each processor core. Each processor core has a direct access path to its own local subset 504 of the L2 cache. Data read by a processor core is stored in its L2 cache subset 504 and can be quickly accessed in parallel with other processor cores accessing their own local L2 cache subsets. Data written by a processor core is stored in its own L2 cache subset 504 and flushed from other subsets if necessary. A ring network ensures data sharing consistency. The ring network is bidirectional to allow agents such as processor cores, L2 caches, and other logic blocks to communicate with each other within the chip. In some embodiments, each ring data path is 1024 bits wide in each direction.

[0104] Figure 5B is part of a processor core according to an embodiment of the present invention Figure 5A expanded view. Figure 5B The L1 data cache 506A portion includes the L1 cache 506, and more details regarding the vector unit 510 and vector registers 514. Specifically, the vector unit 510 is a 16-wide vector processing unit (VPU) (see 16-wide ALU 528) that executes one or more of integer, single-precision floating-point, and double-precision floating-point instructions. The VPU supports mixing of register inputs through a mixing unit 520, numerical conversion through numerical conversion units 522A-B, and replication of memory inputs through a replication unit 524.

[0105] A processor with an integrated memory controller and graphics device

[0106] Figure 6 is a block diagram of a processor 600 that can have more than one core, can have an integrated memory controller, and can have an integrated graphics device according to an embodiment of the present invention. Figure 6 The solid box diagram in shows a processor 600 having a single core 602A, a system agent 610, and a set 616 of one or more bus controller units, while the optional addition of the dashed box diagram shows an alternative processor 600 having multiple cores 602A-N, a set 614 of one or more integrated memory controller units in the system agent unit 610, and dedicated logic 608.

[0107] Thus, different implementations of the processor 600 can include: 1) a CPU, where the dedicated logic 608 is integrated graphics and / or scientific (throughput) logic (which can include one or more cores), and the cores 602A-N are one or more general-purpose cores (e.g., general-purpose in-order cores, general-purpose out-of-order cores, a combination of both); 2) a coprocessor, where the cores 602A-N are a large number of dedicated cores intended primarily for graphics and / or scientific (throughput); and 3) a coprocessor, where the cores 602A-N are a large number of general-purpose in-order cores. Thus, the processor 600 can be a general-purpose processor, a coprocessor, or a special-purpose processor, such as, for example, a network or communication processor, a compression engine, a graphics processor, a GPGPU (general-purpose graphics processing unit), a high-throughput integrated many-core (MIC) coprocessor (including 30 or more cores), an embedded processor, and so on. The processor can be implemented on one or more chips. The processor 600 can be part of one or more substrates, and / or can be implemented on one or more substrates using any of a variety of process technologies, such as, for example, BiCMOS, CMOS, or NMOS.

[0108] The memory hierarchy includes one or more levels of caches 604A-N within the cores 602A-N, a collection 606 of one or more shared cache units, and an external memory (not shown) coupled to a collection 614 of integrated memory controller units. The collection 606 of shared cache units can include one or more intermediate-level caches, such as, a second-level (L2), third-level (L3), fourth-level (L4) or other levels of cache, a last-level cache (LLC), and / or a combination of the foregoing. Although in one embodiment, a ring-based interconnect unit 612 interconnects the integrated graphics logic 608, the collection 606 of shared cache units, and the system agent unit 610 / (multiple) integrated memory controller units 614, alternative embodiments can use any number of well-known techniques to interconnect such units. In one embodiment, coherence is maintained between one or more cache units 606 and the cores 602A-N.

[0109] In some embodiments, one or more of the cores 602A-N are capable of multi-threading. The system agent 610 includes those components that coordinate and operate the cores 602A-N. The system agent unit 610 can include, for example, a power control unit (PCU) and a display unit. The PCU can be the logic and components required to regulate the power states of the cores 602A-N and the integrated graphics logic 608, or can include such logic and components. The display unit is used to drive one or more externally connected displays.

[0110] The cores 602A-N may be homogeneous or heterogeneous in terms of the architectural instruction set; i.e., two or more of the cores 602A-N may be capable of executing the same instruction set, while other cores may be capable of executing only a subset of that instruction set or a different instruction set.

[0111] Exemplary Computer Architecture

[0112] Figures 7 - 10 is a block diagram of an exemplary computer architecture. Other system designs and configurations known in the art for laptop devices, desktop computers, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, cellular telephones, portable media players, handheld devices, and various other electronic devices are also suitable. In general, a wide variety of systems or electronic devices capable of incorporating a processor and / or other execution logic as disclosed herein are generally suitable.

[0113] Now referring Figure 7 , shown is a block diagram of a system 700 in accordance with an embodiment of the present invention. System 700 may include one or more processors 710, 715, which are coupled to a controller hub 720. In one embodiment, controller hub 720 includes a graphics memory controller hub (GMCH) 790 and an input / output hub (IOH) 750 (which may be on separate chips); GMCH 790 includes a memory and graphics controller to which a memory 740 and a coprocessor 745 are coupled; IOH 750 couples input / output (I / O) devices 760 to GMCH 790. Alternatively, one or both of the memory and graphics controllers are integrated within the processor (as described herein), memory 740 and coprocessor 745 are directly coupled to processor 710, and controller hub 720 is in a single chip with IOH 750.

[0114] The optionality of additional processor 715 is indicated by a dashed line in Figure 7 . Each processor 710, 715 may include one or more of the processing cores described herein and may be a certain version of processor 600.

[0115] Memory 740 may be, for example, dynamic random access memory (DRAM), phase change memory (PCM), or a combination of the two. For at least one embodiment, controller hub 720 communicates with the (multiple) processors 710, 715 via a multi-drop bus such as a front-side bus (FSB), a point-to-point interface, or a similar connection 795.

[0116] In one embodiment, the coprocessor 745 is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communications processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, and the like. In one embodiment, the controller hub 720 may include an integrated graphics accelerator.

[0117] There can be various differences in a series of quality metrics, including architecture, microarchitecture, thermal, power consumption characteristics, etc., between the physical resources 710, 715.

[0118] In one embodiment, the processor 710 executes instructions that control general types of data processing operations. Coprocessor instructions may be embedded within these instructions. The processor 710 identifies these coprocessor instructions as being of a type that should be executed by the attached coprocessor 745. Accordingly, the processor 710 issues these coprocessor instructions (or control signals representing coprocessor instructions) on a coprocessor bus or other interconnect to the coprocessor 745. The (multiple) coprocessor 745 receives and executes the received coprocessor instructions.

[0119] Now refer to Figure 8 , shown is a block diagram of a first more specific exemplary system 800 according to an embodiment of the present invention. As Figure 8 shown, the multiprocessor system 800 is a point-to-point interconnect system and includes a first processor 870 and a second processor 880 coupled via a point-to-point interconnect 850. Each of the processors 870 and 880 may be a certain version of the processor 600. In one embodiment of the present invention, the processors 870 and 880 are the processors 710 and 715, respectively, and the coprocessor 838 is the coprocessor 745. In another embodiment, the processors 870 and 880 are the processor 710 and the coprocessor 745, respectively.

[0120] The processors 870 and 880 are shown as including integrated memory controller (IMC) units 872 and 882, respectively. The processor 870 also includes point-to-point (P-P) interfaces 876 and 878 as part of its bus controller unit; similarly, the second processor 880 includes P-P interfaces 886 and 888. The processors 870, 880 may exchange information via the P-P interface 850 using the point-to-point (P-P) interface circuits 878, 888. As Figure 8 shown, the IMCs 872 and 882 couple the processors to the respective memories, namely memory 832 and memory 834, which may be portions of the main memories locally attached to the respective processors.

[0121] Processors 870, 880 may each exchange information with chipset 890 via respective P-P interfaces 852, 854 using point-to-point interface circuits 876, 894, 886, 898. Chipset 890 may optionally exchange information with coprocessor 838 via high performance interface 892. In one embodiment, coprocessor 838 is a special purpose processor such as, for example, a high throughput MIC processor, a network or communications processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, and the like.

[0122] A shared cache (not shown) may be included in either processor, or external to both processors but connected to these processors via a P-P interconnect such that if the processors are placed in a low power mode, the local cache information of either or both processors may be stored in the shared cache.

[0123] Chipset 890 may be coupled to a first bus 816 via interface 896. In one embodiment, first bus 816 may be a Peripheral Component Interconnect (PCI) bus or a bus such as a PCI Express bus or another I / O interconnect bus, but the scope of the present invention is not limited thereto.

[0124] As Figure 8 shown, various I / O devices 814 may be coupled to first bus 816 along with bus bridge 818, which couples first bus 816 to second bus 820. In one embodiment, one or more additional processors 815 such as a coprocessor, a high throughput MIC processor, a GPGPU, an accelerator (such as, for example, a graphics accelerator or a Digital Signal Processing (DSP) unit), a Field Programmable Gate Array or any other processor are coupled to first bus 816. In one embodiment, second bus 820 may be a Low Pin Count (LPC) bus. In one embodiment, various devices may be coupled to second bus 820, including for example a keyboard and / or mouse 822, a communication device 827, and a storage unit 828, which may include, for example, a disk drive or other mass storage device with instructions / code and data 830. Additionally, audio I / O 824 may be coupled to second bus 820. Note that other architectures are possible. For example, instead of Figure 8 the point-to-point architecture, the system may implement a multi-branch bus or other such architecture.

[0125] Now referring Figure 9 , shown is a block diagram of a second more specific exemplary system 900 in accordance with an embodiment of the present invention. Figure 8 and 9 Similar elements in Figure 9 are denoted with similar reference numerals, and Figure 8certain aspects to avoid confusion Figure 9 other aspects of

[0126] Figure 9 As shown, processors 870 and 880 may each include integrated memory and I / O control logic (“CL”) 971 and 982, respectively. Thus, CL 972 and 982 include integrated memory controller units and include I / O control logic. Figure 9 As shown, not only memories 832 and 834 are coupled to CL 972 and 982, but also I / O device 914 is coupled to control logics 972 and 982. Conventional I / O device 915 is coupled to chipset 890.

[0127] Now referring to Figure 10 , shown is a block diagram of SoC 1000 according to an embodiment of the present invention. Figure 6 Similar elements in Figure 10 are designated with similar reference numerals. Additionally, the dashed boxes are optional features on a more advanced SoC. In

[0128] Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementations. Embodiments of the present invention may be implemented as a computer program or program code executing on a programmable system including at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0129] The program code (such as Figure 8The code 830) illustrated in the figure is applied to the input instructions to perform the functions described herein and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, a processing system includes any system having a processor, such as, for example, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.

[0130] The program code can be implemented in a high-level procedural programming language or an object-oriented programming language in order to communicate with the processing system. If desired, the program code can also be implemented in assembly language or machine language. In fact, the mechanisms described herein are not limited to the scope of any particular programming language. In any case, the language can be a compiled language or an interpreted language.

[0131] One or more aspects of at least one embodiment can be implemented by representative instructions stored on a machine-readable medium that represent various logics in a processor, which instructions, when read by the machine, cause the machine to fabricate the logics for performing the techniques described herein. Such representations, referred to as “IP cores,” can be stored on a tangible machine-readable medium and can be supplied to various customers or production facilities to be loaded into the manufacturing machines that actually fabricate the logics or processors.

[0132] Such machine-readable storage media can include, but are not limited to, non-transitory, tangible arrangements of articles manufactured or formed by a machine or device, which include storage media such as a hard disk; any other type of disk, including floppy disks, optical disks, compact disk read-only memory (CD-ROM), rewritable compact disk (CD-RW), and magneto-optical disks; semiconductor devices such as read-only memory (ROM), random access memory (RAM) such as dynamic random access memory (DRAM) and static random access memory (SRAM), erasable programmable read-only memory (EPROM), flash memory, electrically erasable programmable read-only memory (EEPROM); phase change memory (PCM); magnetic or optical cards; or any other type of medium suitable for storing electronic instructions.

[0133] Accordingly, embodiments of the present invention also include non-transitory, tangible machine-readable media that contain instructions or contain design data, such as a hardware description language (HDL), that define the structures, circuits, devices, processors, and / or system features described herein. These embodiments are also referred to as program products.

[0134] Emulation (including binary translation, code morphing, etc.)

[0135] In some cases, an instruction converter may be used to convert instructions from a source instruction set to a target instruction set. For example, the instruction converter may transform (e.g., using static binary translation, dynamic binary translation including dynamic compilation), morph, emulate, or otherwise convert an instruction or instructions to be processed by a core into one or more other instructions. The instruction converter may be implemented in software, hardware, firmware, or a combination thereof. The instruction converter may be on the processor, off the processor, or partly on the processor and partly off the processor.

[0136] Figure 11 is a block diagram of an example of using a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set. In the illustrated example, the instruction converter is a software instruction converter, but alternatively, the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof. Figure 11 shows that a first compiler 1104 may be used to compile a program in the form of a high-level language 1102 to generate first binary code (e.g., x86) 1106 that can be natively executed by a processor 1116 having at least one first instruction set core. In some embodiments, the processor 1116 having at least one first instruction set core represents any processor that performs substantially the same functions as an Intel processor having at least one x86 instruction set core by compatibly executing or otherwise performing: 1) an essential portion of the instruction set of the Intel x86 instruction set core, or 2) a target code version of an application or other software targeted to run on an Intel processor having at least one x86 instruction set core to achieve substantially the same results as an Intel processor having at least one x86 instruction set core. The first compiler 1104 represents a compiler operable to generate binary code 1106 (e.g., target code) in a first instruction set that can be executed on the processor 1116 having at least one first instruction set core with or without additional linking processing. Similarly, Figure 11It is shown that an alternative instruction set compiler 1108 can be used to compile a program in the form of a high-level language 1102 to generate alternative instruction set binary code 1110 that can be natively executed by a processor 1114 that does not have at least one first instruction set core (e.g., a processor having a core that executes the MIPS instruction set of MIPS Technologies, Inc. of Sunnyvale, California, and / or the ARM instruction set of ARM Holdings plc of Sunnyvale, California). An instruction converter 1112 is used to convert the first binary code 1106 into code that can be natively executed by a processor 1114 that does not have a first instruction set core. This converted code is not likely to be the same as the alternative instruction set binary code 1110 because instruction converters capable of doing so are difficult to manufacture; however, the converted code will perform the general operations and is composed of instructions from the alternative instruction set. Thus, the instruction converter 1112 represents software, firmware, hardware, or a combination thereof that allows a processor or other electronic device that does not have a first instruction set processor or core to execute the first binary code 1106 through emulation, simulation, or any other process.

[0137] Apparatus and method for digital signal processing instructions

[0138] Digital signal processing (DSP) instructions are described below. In one embodiment, the circuitry and logic for performing DSP operations are integrated within the execution engine unit 450 shown in Figure 4B and within various cores described above (see, for example, Figure 6 and Figure 10 cores 602A-N in) and / or within the vector unit 510 shown in Figure 5A For example, various source and destination registers can be SIMD registers in the (multiple) physical register file units 458 in Figure 4B and / or vector registers 310 in Figure 3 The multiplication circuitry, adder circuitry, accumulator circuitry, and other circuitry described below can be integrated within the execution components of the architectures described above. By way of example and not limitation, the execution components include the (multiple) execution units 462 in Figure 4B However, it should be noted that the basic principles of the present invention are not limited to these specific architectures.

[0139] One embodiment of the present invention includes circuitry and / or logic for processing Digital Signal Processing (DSP) instructions. Specifically, one embodiment includes a multiply-accumulate (MAC) architecture having eight 16x16-bit multipliers and two 64-bit accumulators. The Instruction Set Architecture (ISA) described below can process various multiplication and MAC operations on 128-bit packed (8-bit, 16-bit, or 32-bit data elements) integer, fixed-point, and complex data types. Additionally, certain instructions have direct support for highly efficient Fast Fourier Transform (FFT) and Finite Impulse Response (FIR) filtering, as well as post-processing of accumulated data through shift, round, and saturate operations.

[0140] One embodiment of the new DSP instructions uses opcode encoding based on the VEX.128 prefix, and several of the SSE / SSE2 / AVX instructions that handle post-processing of data are used with the DSP ISA. The VEX-encoded 128-bit DSP instructions with memory operands can have relaxed memory alignment requirements.

[0141] In one embodiment, the instructions also support various integer and fixed-point data types, including:

[0142] 1) Q31 data type with more than 16 bits, for signals requiring Analog-to-Digital Conversion (ADC) and Digital-to-Analog Conversion (DAC);

[0143] 2) Q15 data type commonly used in DSP algorithms;

[0144] 3) 16-bit complex data type; and

[0145] 4) 32-bit complex data type.

[0146] The Instruction Set Architecture described herein is for a wide range of standard DSP (e.g., FFT, filtering, pattern matching, correlation, polynomial estimation, etc.) and statistical operations (e.g., mean, moving average, variance, etc.).

[0147] Target applications of embodiments of the present invention include sensors, audio, classification tasks for computer vision, and speech recognition. The DSP ISA described herein includes a wide range of instructions applicable to Deep Neural Networks (DNN), Automatic Speech Recognition (ASR), sensor fusion using Kalman filtering, and other major DSP applications, etc. Given a weight sequence {w1, w2, … w k} and an input sequence {x1, x2, x3, … x n}, many image processing and machine learning tasks require computing y i = w1x i + w2x i+1+…+w k x i+k-1 The defined result sequence {y1, y2, y3, … y n+1-k}.

[0148] Figure 12 The figure shows an exemplary processor 1255 including embodiments of the present invention that can be implemented thereon. The exemplary processor 1255 includes a plurality of cores 0-N for simultaneously executing multiple instruction threads. The illustrated embodiment includes DSP instruction decoding circuitry / logic 1231 within decoder 1230 and DSP instruction execution circuitry / logic 1241 within execution unit 1240. These pipelined components can perform the operations described herein in response to the decoding and execution of DSP instructions. Although only the details of a single core (core 0) are shown in Figure 12 , it will be understood that each of the other cores of processor 1255 can include similar components.

[0149] Before describing the specific details of embodiments of the present invention, a description of the components of the exemplary processor 1255 is provided directly below. Each of the plurality of cores 0-N can include a memory management unit 1290 for performing memory operations (such as load / store operations), a set of general-purpose registers (GPRs) 1205, a set of vector registers 1206, and a set of mask registers 1207. In one embodiment, a plurality of vector data elements are packed into each vector register 1206, and each vector register 1206 can have a width of 512 bits for storing two 256-bit values, four 128-bit values, eight 64-bit values, sixteen 32-bit values, etc. However, the basic principles of the present invention are not limited to any particular size / type of vector data. In one embodiment, the mask registers 1207 include eight 64-bit operand mask registers for performing bit masking operations on the values stored in the vector registers 1206 (e.g., implemented as mask registers k0-k7 described herein). However, the basic principles of the present invention are not limited to any particular mask register size / type.

[0150] Each core 0-N may include a dedicated first-level (L1) cache 1212 and a second-level (L2) cache 1211 for caching instructions and data according to the specified cache management policy. The L1 cache 1212 includes a separate instruction cache 1220 for storing instructions and a separate data cache 1221 for storing data. The instructions and data stored in each processor cache are managed in cache line granularity, and the cache line can be of a fixed size (e.g., 64 bytes, 128 bytes, 512 bytes in length). Each core of this exemplary embodiment has an instruction fetch unit 1210 for fetching instructions from the main memory 1200 and / or the shared third-level (L3) cache 1216. The instruction fetch unit 1210 includes various well-known components, including: a next instruction pointer 1203 for storing the address of the next instruction to be fetched from the memory 1200 (or one of the caches); a translation lookaside buffer (ITLB) 1204 for storing the mapping of the most recently used virtual-to-physical instruction addresses to improve the address translation speed; a branch prediction unit 1202 for speculatively predicting instruction branch addresses; and a branch target buffer (BTB) 1201 for storing branch addresses and target addresses.

[0151] As mentioned, the decoding unit 1230 includes DSP instruction decoding circuitry / logic 1231 for decoding the DSP instructions described herein into micro-operations or "uops" and DSP instruction execution circuitry / logic 1241 for executing the DSP instructions. The writeback / retirement unit 1250 retires the executed instructions and writes back the results.

[0152] Packed Complex Butterfly Operation

[0153] One embodiment of the present invention includes instructions for performing a hybrid 32 / 16-bit radix-2 FFT butterfly operation. In one implementation, the entire butterfly operation is performed using 32-bit complex inputs (32-bit real part and 32-bit imaginary part) and 16-bit complex rotation factors. In FFT terminology, the rotation factors include the trigonometric constant coefficients that are multiplied by the input data when performing the FFT. The result of this implementation is a set of 32-bit complex values.

[0154] In one embodiment, the complex data for the first and second input functions (F1[k] and F2[k]) is stored in a packed data source register. The first instruction executes the complex number for the second input function (F2[k]) stored in the first packed data register (e.g., xmm2) with the rotation factor (W) in the second packed data register (e.g., xmm3) N k) complex packed multiply. Adds to or subtracts from the data of the first input function (F1[k]) stored in the third packed data source register (e.g., xmm1) the real part of the complex result. The 49-bit result of the real number is scaled based on an immediate value (e.g., imm8[1:0]), and is rounded and saturated to extract 32 bits from the 50-bit immediate result before writing the complex output to the destination register (e.g., 128-bit xmm1).

[0155] Additionally, one implementation includes a second instruction that also performs a packed multiply of the complex number for the second input function (F2[k]) stored in the first packed data register (e.g., xmm2) with a rotation factor (W N k ) complex number stored in the second packed data register (e.g., xmm3). Adds to or subtracts from the data of the first input function (F1[k]) stored in the third packed data source register (e.g., xmm1) the imaginary part of the complex result. The 49-bit result of the real number is scaled based on an immediate value (e.g., imm8[1:0]), and is rounded and saturated to extract 32 bits from the 50-bit immediate result before writing the complex output to the destination register (e.g., 128-bit xmm1).

[0156] In one embodiment, the real and imaginary parts of a given complex number are stored as 16-bit packed data values within a 128-bit vector register (such as the xmm registers described herein). In a particular implementation, the 16-bit real value is stored in a data element position adjacent to the corresponding 16-bit imaginary value (i.e., where the real and imaginary parts specify the complete complex number). However, note that the basic principles of the present invention are not limited to any of these particular data element sizes or arrangements.

[0157] Figure 13 The figure shows the bit distribution in an exemplary source register (SRCx). In an embodiment where the real and imaginary parts of each complex number are stored in adjacent data element positions, for example, the real part may be stored as data element A, and the corresponding imaginary part may be stored as data element B. In this arrangement, data elements C, E, and G store additional real parts, and data elements D, F, and H store the additional corresponding imaginary parts, respectively. In other embodiments, the real and imaginary parts are reversed in the above description (i.e., data element A includes the imaginary part, and data element B includes the real part). However, the following description will assume an arrangement where data elements A, C, E, and G are real and data elements B, D, F, and H are imaginary.

[0158] The operations described below may be performed in response to the execution of a single instruction. One embodiment may sometimes be referred to herein as VPCR2BFRSDRE, which performs complex multiplications of complex packed data elements from first and second source registers, and adds / subtracts the real parts of these multiplications from the packed data elements in the third source register. Another embodiment may sometimes be referred to herein as VPCR2BFRSDIMM, which performs complex multiplications of complex packed data elements from first and second source registers, and adds / subtracts the real parts of these multiplications from the packed data elements in the third source register. However, it should be noted that the underlying principles of the invention are not limited to all the details provided for these instructions.

[0159] Figure 14 The diagram shows an exemplary architecture for executing instructions and performing the FFT operations described herein. As mentioned, these instructions may use memory stored in Figure 14 1402, SRC2 1401, and SRC3 1402. In the illustrated embodiment, SRC2 1401 stores data elements S2A-S2H, source register SRC3 1402 stores data elements S3A-S3H, and SRC1 / DEST 1460 stores data elements S1A-S1H (S2 is used as an abbreviation for SRC2, S3 is used as an abbreviation for SRC3, and S1 is used as an abbreviation for SRC1 / DEST).

[0160] In one embodiment, eight multipliers 1405 are included to multiply data elements in SRC2 1401 with data elements in SRC3 1402 to generate up to eight products, depending on the instruction being executed. The first and second sets of adder networks 1410-1411 add and subtract products, depending on the instruction, and in some embodiments described below, also add / subtract values ​​to / from SRC1 / DEST 1460.

[0161] The accumulation circuit including adders 1420-1421 may combine the above results with previously accumulated results (if any) stored in SRC1 / DEST register 1460, but some embodiments described herein do not perform accumulation. These results may then be saturated (i.e., if one or more of the values ​​are greater than the supported maximum value, the maximum value is output) by saturation circuits 1440-1441 and stored back in destination register (SRC1 / DEST) 1460 via output multiplexer 1450.

[0162] exist Figure 15 The figure shows the use of two input functions F1[k] and F2[k] and a "twiddle factor" WN k Exemplary butterfly operations. In FFT terminology, twiddle factors include the trigonometric constant coefficients that multiply data (e.g., F2[k] in the illustrated example) during the algorithm process. Specifically, one or more multipliers 1510 multiply the value of W N k by the value of F2[k], and adders 1520 - 1521 add to / subtract from the value of F1[k] these results to generate the results X[k] and X[k + N / 2] as follows:

[0163] X[k] = F1[k] + W N k ×F2[k]

[0164]

[0165] wherein,

[0166] as described below, in one embodiment, multiplier 1510 includes Figure 14 the multipliers in, and adders 1520 - 1521 include adder networks 1410 - 1411. Figure 16 Another view of the architecture is provided that has additional details related to the execution of FFT operations as described herein (e.g., data lines 1601 - 1602 for providing data from SRC1 / DEST register 1460 to adder networks 1410 - 1411 respectively).

[0167] 1. First Exemplary Vector Packed Complex Butterfly Instruction

[0168] As mentioned above, when executing the first instruction (e.g., VPCR2BFRSDRE), the complex data for one input function {F2[k + 1], F2[k]} can be stored in the packed data element locations in SRC2 1401, and for the twiddle factors {X (unused 32 bits), W N [k + 1]}, X (unused 32 bits), W NThe complex data of [k]} can be stored in the packed data element positions in SRC31402. In one embodiment, the real and imaginary packed data elements in SRC21401 are 32 bits, and the real and imaginary packed data elements in SRC3 are 16 bits. Thus, in order to multiply the input function by the rotation factor as described below, the multiplier 1405 performs a series of 32×16 multiplications. Specifically, when executing the first instruction, the input multiplier 1403 supplies each 32-bit real data element and 32-bit imaginary data element from SRC2 1401 and the 16-bit real data element and 16-bit imaginary data element from SRC3 1402 to the multiplier 1405, which performs the multiplications as described in the following code:

[0169] TEMP0[47:0]←(SRC2[31:0]*SRC3[15:0]);

[0170] TEMP1[47:0]←(SRC2[63:32]*SRC3[31:16]);

[0171] TEMP2[47:0]←(SRC2[95:64]*SRC3[79:64]);

[0172] TEMP3[47:0]←(SRC2[127:96]*SRC3[95:80]);

[0173] In this example, the multiplication SRC2[31:0]*SRC3[15:0] multiplies the 32-bit real part of the input function F2[k] (F2[k].r hereinafter) by the real part of the rotation factor W N [k] (W N [k].r hereinafter). The value of F2[k].r is stored in the 32-bit packed data element position A-B (bits 31:0) in SRC21401, and the value of W N [k].r is stored in the 16-bit packed data element position A (15:0) in SRC3 1402. The result of this multiplication is the first real value F2[k].r*W N [k].r.

[0174] Similarly, the multiplication SRC2[63:32]*SRC3[31:16] multiplies the 32-bit imaginary part of the input function F2[k] (F2[k].i hereinafter) by the imaginary part of the rotation factor W N [k] (W N [k].i hereinafter). As indicated, the value of F2[k].i is stored in the 32-bit packed data element position C-D (bits 63:32) in SRC2 1401, and WN The value of [k].i is stored in the packed data element location B(31:16) in SRC31402. The result of this multiplication is the second real value F2[k].i * W N [k].i.

[0175] The remaining two multiplications operate in substantially the same manner, but use the packed data elements for F2[k + 1] and W N [k + 1] in SRC2 and SRC3 respectively. For example, the operation SRC2[95:64] * SRC3[79:64] multiplies the real part of F2[k + 1] (F2[k + 1].r hereinafter) by the real part of W N [k + 1] (W N [k + 1].r hereinafter), and the operation SRC2[127:96] * SRC3[95:80] multiplies the imaginary part of F2[k + 1] (F2[k + 1].i hereinafter) by the imaginary part of W N [k + 1] (W N [k + 1].i hereinafter). In this example, F2[k + 1].r is stored in the 32 - bit packed data element location E - F in SRC2 1401, and F2[k + 1].i is stored in the 32 - bit packed data element location G - H in SRC2 1401. Similarly, W N [k + 1].r is stored in the 16 - bit packed data element location E in SRC3 1402, and W N [k + 1].i is stored in the 16 - bit packed data element location F in SRC3 1402. The results of these multiplications are the third real value F2[k + 1].r * W N [k + 1].r and the fourth real value F2[k + 1].i * W N [k + 1].i.

[0176] Once calculated as described above, each product is stored in a temporary storage location. In the illustrated embodiment, for example, the value F2[k].r * W N [k].r is stored in TEMP0, F2[k].i * W N [k].i is stored in TEMP1, F2[k + 1].r * W N [k + 1].r is stored in TEMP2, and F2[k + 1].i * W N [k + 1].i is stored in TEMP3.

[0177] In one embodiment, the results from the temporary storage are provided to adder networks 1410 - 1411, which add and / or subtract different combinations of these temporary results with the values in SRC1. Specifically, adder networks 1410 - 1411 perform the operations:

[0178] TEMP4[48:0] ← ({SRC1[31:0], 15'b0} + (TEMP0 - TEMP1));

[0179] TEMP5[48:0] ← ({SRC1[31:0], 15'b0} - (TEMP0 - TEMP1));

[0180] TEMP6[48:0] ← ({SRC1[95:64], 15'b0} + (TEMP2 - TEMP3));

[0181] TEMP7[48:0] ← {SRC1[95:64], 15'b0} - (TEMP2 - TEMP3));

[0182] In the case of SRC1, 15'b0 indicates that 15 consecutive zeros are added to the SRC1 value. The result and the TEMP0, TEMP1, TEMP2, and TEMP3 values are then sign - extended to 49 bits. This sign - extension and / or zero - extension can be performed by extension circuitry / logic in adder networks 1410 - 1411 or elsewhere.

[0183] As indicated above, regardless of how the extension is performed, adder networks 1410 - 1411 determine the differences of TEMP0 - TEMP1 and TEMP2 - TEMP3, and add / subtract these values to / from the SRC1 data elements A - B (bits [31:0]) and E - F (bits [95:64]). These temporary results are stored in the 49 bits of TEMP4 - TEMP7. When using the first and second functions (F1[k], F2[k]) and the rotation factor (W N [k]), the following real values are determined:

[0184] TEMP4[48:0] = X[k].r

[0185] TEMP5[48:0] = X[k + N / 2].r

[0186] TEMP6[48:0] = X[k + 1].r

[0187] TEMP7[48:0] = X[k + 1+N / 2].r

[0188] In one embodiment, adder networks 1410-1411 then perform a number of additional operations to generate four 32-bit values stored in the SRC1 / DEST 1460 register. For example, the temporary result may be scaled, rounded, and / or saturated to a double word (32-bit) value based on an immediate number and one or more control registers. In one particular implementation, as indicated in Table A below, the 49-bit real number above is scaled based on imm8[1:0].

[0189] Imm8[1] Imm8[0] Description 0 0 No shift 0 1 Shift right by 1 bit 1 0 Shift right by 2 bits 1 1 Reserved (no shift)

[0190] Table A

[0191] According to this embodiment, the value 00 indicates no shift, 01 indicates a right shift of 1 bit, and 10 indicates a right shift of 2 bits.

[0192] Additionally, the rounding and saturation circuitry may round and / or saturate the resulting value as needed to obtain a 32-bit value to be stored in one of the positions in the SRC1 / DEST 1460 register location. For example, in one embodiment, the following operations are performed:

[0193] DEST[31:0] ← ScaleRoundAndSaturateToSignedDword(TEMP4[48:0], MXCSR, DEST[31:0], imm8);

[0194] DEST[63:32] ← ScaleRoundAndSaturateToSignedDword(TEMP5[48:0], MXCSR, DEST[63:32], imm8);

[0195] DEST[95:64] ← ScaleRoundAndSaturateToSignedDword(TEMP6[48:0], MXCSR, DEST[95:64], imm8); and

[0196] DEST[127:96] ← ScaleRoundAndSaturateToSignedDword(TEMP7[48:0], MXCSR, DEST[127:96], imm8).

[0197] As indicated, these operations may be performed according to the control data specified in the MXCSR control and status register and the immediate value imm8.

[0198] In Figures 17A - 17BThe figure shows a method according to an embodiment of the present invention. The method can be implemented within the context of the system architecture described above, but is not limited to any particular system or processor architecture.

[0199] At 1701, a first instruction is fetched, which has fields for an opcode, an immediate value, first, second, and third source operands, and a packed data destination operand, where the first, second, and third source operands include packed complex numbers having real and imaginary values. At 1702, the first instruction is decoded (e.g., decoded into a plurality of micro-operations to be executed on the Figure 14 architecture therein). At 1703, the real and imaginary values associated with the first, second, and third source operands are stored as packed data elements in first, second, and third source registers (e.g., SRC2, SRC3, SRC1 / DEST), respectively. Subsequently, the first instruction is scheduled for execution. As mentioned, in one embodiment, the source operands are stored in 128-bit packed data registers that store 16-bit or 32-bit packed data elements, each packed data element including a real or imaginary value.

[0200] At 1704, the decoded first instruction is executed to multiply a packed real N-bit data element in a first source register (e.g., SRC2) with a packed real M-bit data element in a second source register (e.g., SRC3), and to multiply a packed imaginary N-bit data element in the first source register with a packed imaginary M-bit data element in the second source register to generate at least four real products. In one embodiment, N = 32 and M = 16. However, the basic principles of the present invention are not limited to this implementation.

[0201] At 1705, a first selected real product is subtracted from a second selected real product to generate a first temporary result (e.g., TEMP0 - TEMP1), and a third selected real product is subtracted from a fourth selected real product to generate a second temporary result (e.g., TEMP2 – TEMP3). As described above, the first, second, third, and fourth real products may be sign-extended to a specified size (e.g., 49 bits) before or after obtaining these differences.

[0202] At 1706, add the first temporary result to the first packed N-bit data element from the third source register to generate a first pre-scaled result, and subtract the first temporary result from the first packed N-bit data element to generate a second pre-scaled result. At 1707, add the second temporary result to the second packed N-bit data element from the third source register to generate a third pre-scaled result, and subtract the second temporary result from the second packed N-bit data element to generate a fourth pre-scaled result. Similarly, the first and second N-bit data elements can be sign-extended to a specified bit size (e.g., 49 bits) before performing the above addition and subtraction.

[0203] At 1708, scale the first, second, third, and fourth pre-scaled results based on the size (e.g., 32 bits) of the packed data element position in the destination register where the scaled values of the first, second, third, and fourth pre-scaled results will be stored, thereby generating first, second, third, and fourth scaled results. As mentioned, rounding and saturation can be performed on the pre-scaled results or the scaled results. The final packed data result in this embodiment includes real data elements. As described above, in one embodiment, the scaling is specified by certain bits (e.g., imm8[1:0]) within an immediate value.

[0204] At 1709, store the first, second, third, and fourth final results in the packed data positions within the destination register.

[0205] 2. Second Exemplary Vector Packed Complex Butterfly Instruction

[0206] As mentioned above, when the second instruction (e.g., VPCR2BFRSDIMM) is executed, complex data can be stored in a similar manner. For example, the data for one input function {F2[k + 1], F2[k]} can be stored in the packed data element position in SRC2 1401, and for the rotation factors {X (unused 32 bits), W N [k + 1]}, X (unused 32 bits), W NThe complex data of [k]} can be stored in the packed data element positions in SRC3 1402. In one embodiment, the real and imaginary packed data elements in SRC2 1401 are 32-bit, and the real and imaginary packed data elements in SRC3 are 16-bit. Thus, in order to multiply the input function by the rotation factor as described below, the multiplier 1405 performs a series of 32×16 multiplications. Specifically, when executing the first instruction, the input multiplier 1403 supplies each real 32-bit data element and imaginary 32-bit data element from SRC2 1401 and the real 16-bit data element and imaginary 16-bit data element from SRC3 1402 to the multiplier 1405, which performs the multiplications as described in the following code:

[0207] TEMP0[47:0]←(SRC2[63:32]*SRC3[15:0]);

[0208] TEMP1[47:0]←(SRC2[31:0]*SRC3[31:16]);

[0209] TEMP2[47:0]←(SRC2[127:96]*SRC3[79:64]);

[0210] TEMP3[47:0]←(SRC2[95:64]*SRC3[95:80]);

[0211] In this example, the multiplication SRC2[63:32]*SRC3[15:0] multiplies the 32-bit imaginary part of the input function F2[k] (F2[k].i hereinafter) by the real part of the rotation factor W N [k] (W N [k].r hereinafter). The value of F2[k].i is read from the 32-bit packed data element position C-D (bits 63:32) in SRC2 1401, and the value of W N [k].r is read from the 16-bit packed data element position A (15:0) in SRC3 1402. The result of this multiplication is the first imaginary value F2[k].i*W N [k].r.

[0212] Similarly, the multiplication SRC2[31:0]*SRC3[31:16] multiplies the 32-bit real part of the input function F2[k] (F2[k].r hereinafter) by the imaginary part of the rotation factor W N [k] (W N [k].i hereinafter). As indicated, the value of F2[k].r is stored in the 32-bit packed data element position A-B (bits 31:0) in SRC2 1401, and WN The value of [k].i is stored in the packed data element location B(31:16) in SRC31402. The result of this multiplication is the second imaginary value F2[k].r * W N [k].i.

[0213] The remaining two multiplications operate in substantially the same manner, but use the packed data elements for F2[k + 1] and W N [k + 1] in SRC2 and SRC3 respectively. For example, the operation SRC2[127:96] * SRC3[79:64] multiplies the imaginary part of F2[k + 1] (F2[k + 1].i hereinafter) with W N [k + 1]'s real part (W N [k + 1].r), and the operation SRC2[95:64] * SRC3[95:80] multiplies the real part of F2[k + 1] (F2[k + 1].r hereinafter) with W N [k + 1]'s imaginary part (W N [k + 1].i). In this example, F2[k + 1].i is stored in the 32-bit packed data element locations G - H in SRC2 1401, and F2[k + 1].r is stored in the 32-bit packed data element locations E - F in SRC2 1401. Similarly, W N [k + 1].r is stored in the 16-bit packed data element location E in SRC3 1402, and W N [k + 1].i is stored in the 16-bit packed data element location F in SRC3 1402. The results of these multiplications are the third imaginary value F2[k + 1].i * W N [k + 1].r and the fourth imaginary value F2[k + 1].r * W N [k + 1].i.

[0214] Once calculated as described above, each product is stored in a temporary storage location. In the illustrated embodiment, for example, the value F2[k].i * W N [k].r is stored in TEMP0, F2[k].r * W N [k].i is stored in TEMP1, F2[k + 1].i * W N [k + 1].r is stored in TEMP2, and F2[k + 1].r * W N [k + 1].i is stored in TEMP3.

[0215] In one embodiment, the results from the temporary storage are provided to adder networks 1410-1411, which add and / or subtract different combinations of these temporary results with the values in SRC1. Specifically, adder networks 1410-1411 perform the operations:

[0216] TEMP4[48:0] ← ({SRC1[63:32], 15'b0} + (TEMP0 + TEMP1));

[0217] TEMP5[48:0] ← ({SRC1[63:32], 15'b0} - (TEMP0 + TEMP1));

[0218] TEMP6[48:0] ← ({SRC1[127:96], 15'b0} + (TEMP2 + TEMP3));

[0219] TEMP7[48:0] ← ({SRC1[127:96], 15'b0} - (TEMP2 + TEMP3));

[0220] In the case of SRC1, 15'b0 indicates that 15 consecutive zeros are added to the SRC1 value. The result and the TEMP0, TEMP1, TEMP2, and TEMP3 values can then be sign-extended to 49 bits. This sign extension and / or zero extension can be performed by extension circuitry / logic in adder networks 1410-1411 or elsewhere.

[0221] As indicated above, regardless of how the extension is performed, adder networks 1410-1411 determine the sums TEMP0 + TEMP1 and TEMP2 + TEMP3, and add / subtract these values to / from the SRC1 data elements C-D (bits [63:32]) and G-H (bits [127:96]). These temporary results are stored in the 49 bits of TEMP4-TEMP7. When using the first and second functions (F1[k], F2[k]) and the rotation factor (W N [k]), the following complex values are determined:

[0222] TEMP4[48:0] = X[k].i

[0223] TEMP5[48:0] = X[k + N / 2].i

[0224] TEMP6[48:0] = X[k + 1].i

[0225] TEMP7[48:0] = X[k + 1 + N / 2].i

[0226] In one embodiment, adder networks 1410 - 1411 then perform a number of additional operations to generate four 32 - bit values that are stored into the SRC1 / DEST 1460 registers. For example, the temporary results may be scaled, rounded, and / or saturated to double - word (32 - bit) values based on an immediate value and one or more control registers. In a particular implementation, as indicated in Table A above, the 49 - bit imaginary number above is scaled based on imm8[1:0]. According to Table A, the value 00 indicates no shift, 01 indicates a right shift by 1 bit, and 10 indicates a right shift by 2 bits.

[0227] Additionally, the rounding and saturation circuitry may round and / or saturate the resulting values as needed to obtain 32 - bit values that will be stored in one of the locations in the SRC1 / DEST 1460 register locations. For example, in one embodiment, the following operations are performed:

[0228] DEST[31:0] ← ScaleRoundAndSaturateToSignedDword(TEMP4[48:0], MXCSR, DEST[31:0], imm8);

[0229] DEST[63:32] ← ScaleRoundAndSaturateToSignedDword(TEMP5[48:0], MXCSR, DEST[63:32], imm8);

[0230] DEST[95:64] ← ScaleRoundAndSaturateToSignedDword(TEMP6[48:0], MXCSR, DEST[95:64], imm8); and

[0231] DEST[127:96] ← ScaleRoundAndSaturateToSignedDword(TEMP7[48:0], MXCSR, DEST[127:96], imm8).

[0232] As indicated, these operations may be performed based on the control data specified in the MXCSR control and status register and the immediate value imm8.

[0233] In Figures 18A - 18B illustrates a method according to an embodiment of the present invention. The method may be implemented within the context of the system architecture described above, but is not limited to any particular system or processor architecture.

[0234] At 1801, a first instruction is fetched, the first instruction having fields for an opcode, an immediate, first, second, and third source operands, and a packed data destination operand, the first, second, and third source operands including packed complex numbers having real and imaginary values. At 1802, the first instruction is decoded (e.g., decoded into a plurality of micro-operations to be executed on the architecture in Figure 14 . At 1803, the real and imaginary values associated with the first, second, and third source operands are stored as packed data elements in first, second, and third source registers (e.g., SRC2, SRC3, SRC1 / DEST), respectively. Subsequently, the first instruction is scheduled for execution. As mentioned, in one embodiment, the source operands are stored in 128-bit packed data registers that store 16-bit or 32-bit packed data elements, each packed data element including a real or imaginary value.

[0235] At 1804, the decoded first instruction is executed to multiply a packed real N-bit data element in a first source register (e.g., SRC2) by a packed imaginary M-bit data element in a second source register (e.g., SRC3), and to multiply a packed imaginary N-bit data element in the first source register by a packed real M-bit data element in the second source register to generate at least four imaginary products. In one embodiment, N = 32 and M = 16. However, the basic principles of the present invention are not limited to this implementation.

[0236] At 1805, a first selected imaginary product is added to a second selected imaginary product to generate a first temporary result (e.g., TEMP0 + TEMP1), and a third selected imaginary product is added to a fourth selected imaginary product to generate a second temporary result (e.g., TEMP2 + TEMP3). As described above, the first, second, third, and fourth real products may be sign-extended to a specified size (e.g., 49 bits) before or after obtaining these sums.

[0237] At 1806, the first temporary result is added to a first packed N-bit data element from a third source register to generate a first pre-scaled result, and the first temporary result is subtracted from the first packed N-bit data element to generate a second pre-scaled result. At 1807, the second temporary result is added to a second packed N-bit data element from the third source register to generate a third pre-scaled result, and the second temporary result is subtracted from the second packed N-bit data element to generate a fourth pre-scaled result. Similarly, the first and second N-bit data elements may be sign-extended to a specified bit size (e.g., 49 bits) before performing the above additions and subtractions.

[0238] At 1808, the first, second, third, and fourth pre-scaled results are scaled based on the size (e.g., 32 bits) of the packed data element position in the destination register where the scaled values will be stored. As mentioned, rounding and saturation can be performed on the pre-scaled results or the scaled results. In this embodiment, the first, second, third, and fourth final packed data results (i.e., after scaling and / or rounding / saturation) include imaginary data elements. As described above, in one embodiment, the scaling is specified by certain bits (e.g., imm8[1:0]) within an immediate value.

[0239] At 1809, the first, second, third, and fourth final results are stored in the packed data positions within the destination register.

[0240] As mentioned, in one embodiment, the above operations are performed to implement a complete FFT butterfly operation that uses 32-bit complex (32-bit real + 32-bit imaginary) inputs and 16-bit complex rotation factors to generate 32-bit complex (32-bit real part + 32-bit imaginary part) outputs. More specifically, these embodiments can be used to perform a hybrid 32 / 16-bit radix-2 FFT butterfly operation.

[0241] In the foregoing specification, embodiments of the invention have been described with reference to specific exemplary embodiments of the invention. However, it will be apparent that various modifications and changes can be made to these embodiments without departing from the broader spirit and scope of the invention as set forth in the appended claims. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

[0242] Embodiments of the invention may include the steps that have been described above. These steps can be embodied in machine-executable instructions that can be used to cause a general-purpose or special-purpose processor to perform these steps. Alternatively, these steps can be performed by a special-purpose hardware component that includes hardwired logic for performing these steps, or by any combination of programmed computer components and custom hardware components.

[0243] As described herein, an instruction may refer to a specific configuration of hardware, such as an application specific integrated circuit (ASIC) configured to perform certain operations or having a predetermined function, or software instructions stored in a memory embodied in a non-transitory computer-readable medium. Thus, the techniques shown in the figures may be implemented using code and data stored on and executed on one or more electronic devices (e.g., a terminal station, a network element, etc.). Such electronic devices use computer machine-readable media such as non-transitory computer machine-readable storage media (e.g., magnetic disks; optical disks; random access memory; read only memory; flash devices; phase change memory) and transitory computer machine-readable communication media (e.g., electrical, optical, acoustic, or other forms of propagated signals - such as carrier waves, infrared signals, digital signals, etc.) to store and communicate (internally and / or over a network with other electronic devices) code and data. Additionally, such electronic devices typically include a set of one or more processors coupled to one or more other components such as one or more storage devices (non-transitory machine-readable storage media), user input / output devices (e.g., a keyboard, a touch screen, and / or a display), and a network connection. The coupling of the set of processors to the other components is typically through one or more buses and bridges (also known as bus controllers). The storage device and the signals carrying network traffic represent one or more machine-readable storage media and machine-readable communication media, respectively. Thus, the storage device of a given electronic device typically stores code and / or data for execution on the set of one or more processors of that electronic device. Of course, one or more portions of embodiments of the present invention may be implemented using different combinations of software, firmware, and / or hardware. Throughout this detailed description, numerous specific details are set forth for purposes of explanation in order to provide a thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that the present invention may be practiced without some of these specific details. In some instances, well-known structures and functions are not described in detail so as not to obscure the subject matter of the present invention. Accordingly, the scope and spirit of the present invention should be determined according to the appended claims.

Claims

1. A processor, comprising: A decoder for decoding a first instruction to generate a decoded instruction; A first source register for storing a first plurality of packed N-bit real data elements and packed N-bit imaginary data elements; A second source register for storing a second plurality of packed M-bit real data elements and packed M-bit imaginary data elements; A third source register for storing a third plurality of packed N-bit real data elements and packed N-bit imaginary data elements; An execution circuit for executing the decoded instruction, the execution circuit comprising: A multiplier circuit for multiplying the packed N-bit real data elements in the first source register by the packed M-bit real data elements in the second source register, and for multiplying the packed N-bit imaginary data elements in the first source register by the packed M-bit imaginary data elements in the second source register to generate at least four real products; An adder circuit for subtracting a first selected real product from a second selected real product to generate a first temporary result, and for subtracting a third selected real product from a fourth selected real product to generate a second temporary result, The adder circuit is used to add the first temporary result to a first packed N-bit data element from the third source register to generate a first pre-scaled result, to subtract the first temporary result from the first packed N-bit data element to generate a second pre-scaled result, to add the second temporary result to a second packed N-bit data element from the third source register to generate a third pre-scaled result, and to subtract the second temporary result from the second packed N-bit data element to generate a fourth pre-scaled result; A scaling circuit for scaling the first pre-scaled result, the second pre-scaled result, the third pre-scaled result and the fourth pre-scaled result to a specified bit width to generate a first final result, a second final result, a third final result and a fourth final result; and A destination register for storing the first final result, the second final result, the third final result and the fourth final result in specified data element positions.

2. The processor according to claim 1, wherein, The scaling operation is performed according to the bit values in the immediate value of the first instruction.

3. The processor according to claim 2, wherein, The bit values in the immediate value include a first value for indicating no shift, a second value for indicating a 1-bit shift, and a third value for indicating a 2-bit shift.

4. The processor according to claim 1 or 3, wherein, N = 32 and M = 16, and wherein the first source register, the second source register and the third source register include 128-bit packed data registers.

5. The processor according to claim 1, wherein, The real data elements and imaginary data elements stored in the first source register and the third source register include complex data for an input function of an N×M fast Fourier transform (FFT), and wherein the second source register includes real data elements and imaginary data elements for rotation factors of the FFT.

6. The processor according to claim 1 or 5, wherein The adder circuit is used to sign-extend the first selected real product, the second selected real product, the third selected real product and the fourth selected real product or the first temporary result and the second temporary result to the specified bit width.

7. The processor according to claim 6, wherein, The adder circuit is used to further sign-extend the first packed N-bit data element and the second packed N-bit data element from the third source register.

8. The processor according to claim 1 or 7, further comprising: A rounding and / or saturation circuit for performing rounding and / or saturation on the pre-scaled result and / or the first final result, the second final result, the third final result, and the fourth final result.

9. A processor, comprising: A decoder for decoding a first instruction to generate a decoded instruction; A first source register for storing a first plurality of packed N-bit real data elements and packed N-bit imaginary data elements; A second source register for storing a second plurality of packed M-bit real data elements and packed M-bit imaginary data elements; A third source register for storing a third plurality of packed N-bit real data elements and packed N-bit imaginary data elements; An execution circuit for executing the decoded instruction, the execution circuit comprising: A multiplier circuit for multiplying the packed N-bit real data elements in the first source register by the packed M-bit imaginary data elements in the second source register, and for multiplying the packed N-bit imaginary data elements in the first source register by the packed M-bit real data elements in the second source register to generate at least four imaginary products; An adder circuit for adding a first selected imaginary product to a second selected imaginary product to generate a first temporary result, and for adding a third selected imaginary product to a fourth selected imaginary product to generate a second temporary result, The adder circuit is used to add the first temporary result to a first packed N-bit data element from the third source register to generate a first pre-scaled result, to subtract the first temporary result from the first packed N-bit data element to generate a second pre-scaled result, to add the second temporary result to a second packed N-bit data element from the third source register to generate a third pre-scaled result, and to subtract the second temporary result from the second packed N-bit data element to generate a fourth pre-scaled result; A scaling circuit for scaling the first pre-scaled result, the second pre-scaled result, the third pre-scaled result, and the fourth pre-scaled result to a specified bit width to generate a first final result, a second final result, a third final result, and a fourth final result; and A destination register for storing the first final result, the second final result, the third final result, and the fourth final result in specified data element positions.

10. The processor according to claim 9, wherein, The scaling operation is performed according to the bit values in the immediate value of the first instruction.

11. The processor according to claim 10, wherein, The bit values in the immediate value include a first value for indicating no shift, a second value for indicating a 1-bit shift, and a third value for indicating a 2-bit shift.

12. The processor according to claim 9 or 11, wherein, N = 32 and M = 16, and wherein the first source register, the second source register, and the third source register include 128-bit packed data registers.

13. The processor according to claim 9, wherein, The real and imaginary data elements stored in the first source register and the third source register include complex data for an input function of an N×M fast Fourier transform (FFT), and wherein the second source register includes real and imaginary data elements for a twiddle factor of the FFT.

14. The processor according to claim 9 or 13, wherein The adder circuit is configured to sign-extend the first selected imaginary product, the second selected imaginary product, the third selected imaginary product, and the fourth selected imaginary product, or the first temporary result and the second temporary result, to a specified bit width.

15. The processor according to claim 14, wherein, The adder circuit is further configured to sign-extend the first packed N-bit data element and the second packed N-bit data element from the third source register.

16. The processor according to claim 9 or 15, further comprising: A rounding and / or saturation circuit configured to perform rounding and / or saturation on the pre-scaled result and / or the first final result, the second final result, the third final result, and the fourth final result.

17. The processor according to claim 16, wherein, The first plurality of packed N-bit real data elements and packed N-bit imaginary data elements include data from a first input function, the second plurality of packed M-bit real data elements and packed M-bit imaginary data elements include data from a twiddle factor, and the third plurality of packed N-bit real data elements and packed N-bit imaginary data elements include data from a second input function.

18. A method for data processing, comprising: Decoding a first instruction to generate a decoded instruction; Storing a first plurality of packed N-bit real data elements and packed N-bit imaginary data elements in a first source register; Storing a second plurality of packed M-bit real data elements and packed M-bit imaginary data elements in a second source register; Storing a third plurality of packed N-bit real data elements and packed N-bit imaginary data elements in a third source register; Multiplying the packed N-bit real data elements in the first source register by the packed M-bit real data elements in the second source register; Multiplying the packed N-bit imaginary data elements in the first source register by the packed M-bit imaginary data elements in the second source register to generate at least four real products; Subtracting a first selected real product from a second selected real product to generate a first temporary result, and subtracting a third selected real product from a fourth selected real product to generate a second temporary result; Adding the first temporary result to a first packed N-bit data element from the third source register to generate a first pre-scaled result, subtracting the first temporary result from the first packed N-bit data element to generate a second pre-scaled result, adding the second temporary result to a second packed N-bit data element from the third source register to generate a third pre-scaled result, and subtracting the second temporary result from the second packed N-bit data element to generate a fourth pre-scaled result; Scaling the first pre-scaled result, the second pre-scaled result, the third pre-scaled result, and the fourth pre-scaled result to a specified bit width to generate a first final result, a second final result, a third final result, and a fourth final result; And Store the first final result, the second final result, the third final result, and the fourth final result in the specified data element locations.

19. The method according to claim 18, wherein, The scaling operation is performed according to the bit values in the immediate operand of the first instruction.

20. The method according to claim 19, wherein, The bit values in the immediate operand include a first value for indicating no shift, a second value for indicating a 1-bit shift, and a third value for indicating a 2-bit shift.

21. The method according to claim 18 or 20, wherein N = 32 and M = 16, and wherein the first source register, the second source register, and the third source register include 128-bit packed data registers.

22. The method according to claim 18, wherein, The real and imaginary data elements stored in the first source register and the third source register include complex data for an input function of an N×M fast Fourier transform (FFT), and wherein the second source register includes real and imaginary data elements for a twiddle factor of the FFT.

23. The method according to claim 18 or 22, further comprising: Sign extend the first selected real product, the second selected real product, the third selected real product, and the fourth selected real product, or the first temporary result and the second temporary result, to the specified bit width.

24. The method according to claim 23, further comprising: Sign extend the first packed N-bit data element and the second packed N-bit data element from the third source register.

25. The method according to claim 18 or 24, further comprising: Perform rounding and / or saturation on the pre-scaled result and / or the first final result, the second final result, the third final result, and the fourth final result.

26. A machine-readable medium having program code stored thereon, which when executed by a machine, causes the machine to perform the following operations: Decode a first instruction to generate a decoded instruction; Store a first plurality of packed N-bit real data elements and packed N-bit imaginary data elements in a first source register; Store a second plurality of packed M-bit real data elements and packed M-bit imaginary data elements in a second source register; Store a third plurality of packed N-bit real data elements and packed N-bit imaginary data elements in a third source register; Multiply the packed N-bit real data elements in the first source register by the packed M-bit real data elements in the second source register; Multiply the packed N-bit imaginary data elements in the first source register by the packed M-bit imaginary data elements in the second source register to generate at least four real products; Subtract the first selected real product from the second selected real product to generate a first temporary result, and subtract the third selected real product from the fourth selected real product to generate a second temporary result; Add the first temporary result to the first packed N-bit data element from the third source register to generate a first pre-scaled result, subtract the first temporary result from the first packed N-bit data element to generate a second pre-scaled result, add the second temporary result to the second packed N-bit data element from the third source register to generate a third pre-scaled result, and subtract the second temporary result from the second packed N-bit data element to generate a fourth pre-scaled result; Scale the first pre-scaled result, the second pre-scaled result, the third pre-scaled result, and the fourth pre-scaled result to the specified bit width to generate a first final result, a second final result, a third final result, and a fourth final result; and Store the first final result, the second final result, the third final result, and the fourth final result in the specified data element locations.

27. The machine-readable medium according to claim 26, wherein, The scaling operation is performed according to the bit values in the immediate number of the first instruction.

28. The machine-readable medium according to claim 27, wherein, The bit values in the immediate number include a first value for indicating no shift, a second value for indicating a 1-bit shift, and a third value for indicating a 2-bit shift.

29. The machine-readable medium according to claim 26 or 28, wherein, N = 32 and M = 16, and wherein the first source register, the second source register, and the third source register include 128-bit packed data registers.

30. The machine-readable medium according to claim 26, wherein, The real data elements and imaginary data elements stored in the first source register and the third source register include complex data for the input function of an N×M fast Fourier transform (FFT), and wherein the second source register includes real data elements and imaginary data elements for the rotation factors of the FFT.

31. The machine-readable medium according to claim 26 or 30, further comprising program code for causing the machine to perform the following operations: Sign-extend the first selected real product, the second selected real product, the third selected real product, and the fourth selected real product or the first temporary result and the second temporary result to the specified bit width.

32. The machine-readable medium according to claim 31, further comprising program code for causing the machine to perform the following operations: Sign-extend the first packed N-bit data element and the second packed N-bit data element from the third source register.

33. The machine-readable medium according to claim 26 or 32, further comprising program code for causing the machine to perform the following operations: Perform rounding and / or saturation on the pre-scaled results and / or the first final result, the second final result, the third final result, and the fourth final result.

34. An apparatus for data processing, comprising: means for decoding a first instruction to generate a decoded instruction; means for storing a first plurality of packed N-bit real data elements and packed N-bit imaginary data elements in a first source register; means for storing a second plurality of packed M-bit real data elements and packed M-bit imaginary data elements in a second source register; means for storing a third plurality of packed N-bit real data elements and packed N-bit imaginary data elements in a third source register; Apparatus for multiplying the packed N-bit real data elements in the first source register by the packed M-bit real data elements in the second source register; Apparatus for multiplying the packed N-bit imaginary data elements in the first source register by the packed M-bit imaginary data elements in the second source register to generate at least four real products; Apparatus for subtracting a first selected real product from a second selected real product to generate a first temporary result and subtracting a third selected real product from a fourth selected real product to generate a second temporary result; Apparatus for adding the first temporary result to a first packed N-bit data element from the third source register to generate a first pre-scaled result, subtracting the first temporary result from the first packed N-bit data element to generate a second pre-scaled result, adding the second temporary result to a second packed N-bit data element from the third source register to generate a third pre-scaled result, and subtracting the second temporary result from the second packed N-bit data element to generate a fourth pre-scaled result; Apparatus for scaling the first pre-scaled result, the second pre-scaled result, the third pre-scaled result, and the fourth pre-scaled result to a specified bit width to generate a first final result, a second final result, a third final result, and a fourth final result; and Apparatus for storing the first final result, the second final result, the third final result, and the fourth final result in specified data element positions.

35. The apparatus according to claim 34, wherein, The scaling operation is performed according to bit values in the immediate value of the first instruction.

36. The apparatus according to claim 35, wherein, The bit values in the immediate value include a first value for indicating no shift, a second value for indicating a 1-bit shift, and a third value for indicating a 2-bit shift.

37. The device according to claim 34 or 36, wherein, N = 32 and M = 16, and wherein the first source register, the second source register, and the third source register include 128-bit packed data registers.

38. The device according to claim 34, wherein, The real data elements and imaginary data elements stored in the first source register and the third source register include complex data for an input function of an N×M fast Fourier transform (FFT), and wherein the second source register includes real data elements and imaginary data elements for rotation factors of the FFT.

39. The apparatus according to claim 34 or 38, further comprising: Sign-extending the first selected real product, the second selected real product, the third selected real product, and the fourth selected real product, or the first temporary result and the second temporary result, to a specified bit width.

40. The apparatus according to claim 39, further comprising: Sign-extending the first packed N-bit data element and the second packed N-bit data element from the third source register.

41. The apparatus according to claim 34 or 40, further comprising: Performing rounding and / or saturation on the pre-scaled results and / or the first final result, the second final result, the third final result, and the fourth final result.

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