Methods for forming hybrid socket structures for packaged interconnect applications and the resulting structures

Abstract

Methods / structures for forming package structures are described. These methods / structures may include conductive pins, comprising: a cantilever beam portion physically coupled to a first side of the package substrate; a contact portion wherein terminal ends of the contact portion are physically and electrically coupled to the board; a housing structure including a housing cavity, wherein the contact portion is at least partially disposed within the housing cavity; and conductive material disposed on the housing side and / or near the surface of the housing cavity. The placement of the conductive material is optimized to meet the requirements of Double Data Rate (DDR) and / or Fast Peripheral Component Interface (PCIe) interfaces.

Description

Background Technology

[0001] With increasing bandwidth demands for future generations of Dynamic Data Rate (DDR) memory and High-Speed ​​Peripheral Component Interconnect (PCIe) technologies, improvements are needed in the design of individual components of the input / output (I / O) channels to meet desired electrical performance specifications. For example, the sockets that interconnect microelectronic packages to the motherboard can be a significant source of channel loss and crosstalk, thus limiting channel margin at higher speeds. Therefore, improved socket design can enable interconnect technologies for future high-speed DDR and PCIe links. Attached Figure Description

[0002] Although this specification concludes with claims that particularly point out and expressly claim certain embodiments, the advantages of these embodiments can be more readily determined from the following description when read in conjunction with the accompanying drawings, wherein:

[0003] Figure 1a This is a cross-sectional view of the socket structure according to an embodiment. Figure 1b This is a top view of the socket structure according to an embodiment.

[0004] Figure 2 This is a cross-sectional view showing the packaging structure according to an embodiment.

[0005] Figures 3a-3c This represents an electrical performance diagram according to an embodiment.

[0006] Figure 4 A flowchart illustrating a method for forming an encapsulation structure according to an embodiment.

[0007] Figure 5 A schematic diagram illustrating a computing device according to an embodiment. Detailed Implementation

[0008] In the following detailed description, reference is made to the accompanying drawings, which illustrate specific embodiments in which the methods and structures can be practiced. These embodiments have been described in sufficient detail to enable those skilled in the art to practice them. It should be understood that the various embodiments, while different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein in connection with one embodiment may be implemented in other embodiments without departing from the spirit and scope of the embodiments. Furthermore, it should be understood that the position or arrangement of the various elements in each disclosed embodiment may be modified without departing from the spirit and scope of the embodiments.

[0009] Therefore, the following detailed description should not be considered limiting, and the scope of the embodiments is defined only by the appended claims as properly interpreted and by the full scope of equivalent transformations to which the claims are entitled. In the drawings, similar reference numerals may refer to the same or similar functions in several views. The terms “above,” “to,” “between,” and “on” as used herein may refer to the relative position of a layer with respect to other layers. A layer “above,” “on,” or “joined” to another layer may be in direct contact with the other layer or may have one or more intermediate layers. A layer between “layers” may be in direct contact with the layer or may have one or more intermediate layers. Layers and / or structures “adjacent” to each other may or may not have intermediate structures / layers between them. Layers (multiple layers) / structures (multiple structures) that are directly on or in direct contact with a layer (multiple layer) / structure (multiple structure) may not have intermediate layers (multiple intermediate layers) / structures (multiple structures) between them.

[0010] Various embodiments of the present invention can be formed or performed on a substrate such as a packaging substrate. The packaging substrate can include any suitable type of substrate capable of providing electrical communication between a die (e.g., an integrated circuit (IC) die) and a next-level component (e.g., a circuit board) to which the microelectronic package can be coupled. In another embodiment, the substrate can include any suitable type of substrate capable of providing electrical communication between an IC die and an upper IC package coupled to a lower IC / die package, and in yet another embodiment, the substrate can include any suitable type of substrate capable of providing electrical communication between an upper IC package and a next-level component coupled to the IC package.

[0011] The substrate can also provide structural support for the die / device. For example, in one embodiment, the substrate may include a multilayer substrate—comprising alternating layers of dielectric material and metal—built around a core layer (dielectric or metal core). In another embodiment, the substrate may include a coreless multilayer substrate. Other types of substrates and substrate materials may also be used in the disclosed embodiments (e.g., ceramic, sapphire, glass, etc.). Furthermore, according to one embodiment, the substrate may include alternating layers of dielectric material and metal built onto the die itself—a process sometimes referred to as a “solderless built-in process.” With this approach, conductive interconnects may or may not be required (because in some cases the built-in layer can be disposed directly above the die).

[0012] The die / device can include any type of integrated circuit device. In one embodiment, the die can include a processing system (single-core or multi-core). For example, the die can include a microprocessor, graphics processor, signal processor, network processor, chipset, etc. In one embodiment, the die can include a system-on-a-chip (SoC) having multiple functional units (e.g., one or more processing units, one or more graphics units, one or more communication units, one or more signal processing units, one or more security units, etc.). However, it should be understood that the disclosed embodiments are not limited to any particular type or category of device / die.

[0013] For example, conductive interconnect structures can be disposed on the sides of a die / device and can include any type of structure and material capable of providing electrical communication between the die / device and the substrate or another die / device. In embodiments, the conductive interconnect structure may include conductive terminals on the die (e.g., pads, bumps, cylindrical bumps, pillars, blocks, or other suitable structures or combinations thereof) and corresponding conductive terminals on the substrate (e.g., pads, bumps, cylindrical bumps, pillars, blocks, or other suitable structures or combinations thereof). Solder (e.g., in the form of balls or bumps) can be disposed on the terminals of the substrate and / or die / device, and these terminals can then be connected using a solder reflow process. Of course, it should be understood that many other types of interconnects and materials are possible (e.g., wire bonding extending between the die and the substrate).

[0014] The terminals on the die may comprise any suitable material or any suitable combination of materials, whether arranged in multiple layers or combined to form one or more alloys and / or one or more intermetallic compounds. For example, the terminals on the die may comprise copper, aluminum, gold, silver, nickel, titanium, tungsten, and any combination of these and / or other metals. In other embodiments, the terminals may comprise one or more non-metallic materials (e.g., conductive polymers). The terminals on the substrate may also comprise any suitable material or any suitable combination of materials, whether arranged in multiple layers or combined to form one or more alloys and / or one or more intermetallic compounds.

[0015] For example, the terminals on the substrate may include copper, aluminum, gold, silver, nickel, titanium, tungsten, and any combination of these and / or other metals. Any suitable solder material can be used to connect the mating terminals of the die and the substrate, respectively. For example, the solder material may include any one or more of tin, copper, silver, gold, lead, nickel, indium, and any combination of these and / or other metals. The solder may also include one or more additives and / or fillers to modify the solder properties (e.g., change the reflow temperature).

[0016] Embodiments of methods for forming package structures are described, such as methods for forming hybrid socket structures that include geometrically optimized structures for reducing crosstalk in single-ended I / O and for matching impedance in differential-ended I / O applications. These methods / structures may include conductive pins comprising: a cantilever beam portion physically coupled to a first side of the package substrate; a contact portion wherein terminal ends of the contact portion are physically and electrically coupled to the board; a housing structure including a housing cavity wherein the contact portion is at least partially disposed within the housing cavity; and conductive material disposed on the side surface of the housing and / or adjacent to the surface of the housing cavity. The conductive material may be selectively customized / added to meet the requirements of DDR and / or PCIe interfaces.

[0017] The methods / structures described herein can utilize the same socket design for both single-ended and differential I / O applications. In the embodiments, the socket design of the embodiments described herein can be optimized primarily for single-ended channel applications by focusing mainly on crosstalk mitigation and then introducing an additional amount of metal inside and / or around the socket housing structure. This additional metal shielding reduces impedance discontinuities to meet the electrical objectives of differential channels.

[0018] As DDR and PCI technologies evolve, bandwidth demands necessitate improved I / O channel performance to reduce channel losses and crosstalk, thereby enhancing socket performance and margins at higher speeds. DDR channel margins tend to exhibit more issues related to crosstalk between adjacent networks, while PCIe channel margins are often more affected by impedance mismatches. The hybrid socket design described in this paper implements interconnect technologies for future high-speed DDR and PCIe link applications. For example, the embodiments described herein enable a single-socket technology that can be used for both DDR and PCIe signaling simultaneously.

[0019] Figure 1a A portion of a socket array structure is shown, with a single socket structure 108 illustrated. For example, socket structure 108 may include a portion of a planar grid array (LGA) socket. Socket structure 108 may include conductive pins 112, which may include a cantilever portion 112' and a contact portion 112'". For example, conductive pins 112 may include conductive materials such as copper and copper alloys. The contact portion 112' of conductive pins 112 may be disposed within a housing structure 116 (shown as a portion of housing structure 116), which may include a first side 117, a second side 119 opposite the first side, and a sidewall 121. Housing structure 116 may further include a height 115, which may be optimized to reduce pin-to-pin crosstalk and to reduce the inductance and capacitance of socket 108.

[0020] The housing structure 116 may include a dielectric material, such as a material with high dielectric constant and low loss, such as a dielectric material in the liquid crystal polymer (LCP) family. In an embodiment, the housing structure 116 may also include a housing cavity 114, wherein the contact portion 112” of the conductive pin 112 may be disposed within the housing cavity 114 of the housing structure 116. In an embodiment, a conductive material / plating 124 may be disposed near and / or on the surface of the housing cavity 114. In an embodiment, the conductive material / plating 124 may include a copper material and may include conductive vias adjacent to the housing cavity 114. In an embodiment, the housing cavity 114 may include any suitable dielectric material within the cavity, such as a dielectric material with high dielectric constant and low dielectric loss, such as any suitable LCP material, such as Kevlar, Vectran, or Zenite.

[0021] In one embodiment, a conductive material plating 124 (which may include any suitable conductive material, such as copper) may be further disposed on a first side 117 of the housing 116 and / or a bottom side 119 of the housing 116. In another embodiment, the conductive material / plating 124 may be disposed on the entire sidewall 121 of the housing structure 116 or on a portion of the sidewall 121 of the housing structure 116. In one embodiment, the conductive plating 124 may be formed, for example, by drilling a through-hole in the housing dielectric material surrounding / adjacent to the socket housing cavity and subsequently plating the conductive material 124 into the through-hole. The conductive material 124 may be formed at desired locations optimized for a particular socket design using any other suitable process.

[0022] The conductive material / plating 124 can be used to optimize the performance of systems employing the socket structure 108, such as systems including PCIe and / or DDR devices / structures, which may include high-speed single-ended and / or differential interconnect structures. The socket 108 can be configured to optimize signal impedance and crosstalk specifications for DDR and PCIe applications by optimizing various structural features of the socket 108.

[0023] In one embodiment, the cantilever beam 112' can be widened to reduce the impedance of the socket 108, and the socket impedance can also be reduced by adding a metal plating 124 around the housing and housing cavity. In another embodiment, the cantilever beam portion 112' can be physically and electrically coupled to a conductive pad 110 disposed on the package substrate 102. In another embodiment, the terminal end of the pin portion 112' can be physically and electrically coupled to a solder structure 118, such as a solder ball. For example, the solder structure 118 can be coupled to a board 122, such as a motherboard.

[0024] Figure 1b A top view of a portion of the socket structure 108, for example Figure 1bThe socket structure 108. The contact portion 112” of the conductive pin can be disposed within the housing cavity 114. The housing cavity may include a dielectric material 123 adjacent to the contact 112”, which may include a low-loss, high-dielectric-constant dielectric material. According to specific design optimization requirements, a conductive material / plating 124 may be disposed on the surface of the housing cavity 114. According to design optimization requirements, a housing structure 116 may be adjacent to the housing cavity 114, and the conductive material plating 124 may be disposed on the housing structure 116.

[0025] Figure 2 A cross-sectional view of a package structure / component 200 is shown, which includes multiple socket structures 208, such as... Figure 1a An optimized connector structure 108 is provided. Multiple connectors 208 can be disposed between the packaging substrate 202 and the plate 222. In an embodiment, the multiple connectors 208 can be disposed within a housing structure 216. The housing structure 216 may include multiple housing cavities 214, wherein each contact portion 212” of the conductive pin 212 can be disposed within a respective housing cavity 214.

[0026] The terminal ends of the contact pin portion 212” can be physically coupled to the solder ball structure 218, which can be coupled to the conductive pad 220 disposed on the board 222 (e.g., motherboard 222). Each conductive pin 212 may also include a cantilever beam portion 212', which can be physically coupled to the conductive pad 210 disposed on the package substrate 202. In an embodiment, conductive material 224 may be disposed on the first side 217 and / or the second side 219 of the housing structure 116, and / or on the sidewall 217, and may be disposed along the entire sidewall. In another embodiment, conductive material 224 may be disposed on the housing The conductive material / plating 224 may be disposed on the surface of the cavity 214 and between adjacent or non-adjacent cavity structures / sidewalls. The specific amount and placement / location of the conductive material / plating 224 may vary depending on the specific electrical parameters required to optimize a particular application. The conductive material / plating 224 may include copper, for example, and may be formed / disposed on the surface of the cavity and / or cavity structure. In embodiments, the conductive material 224 may include a thickness between about 5 micrometers and about 10 micrometers. In embodiments, the conductive material 224 may extend along the entire height of the cavity structure 216 and substantially the entire length along the first and second sides of the cavity structure 216.

[0027] The substrate 202 can be coupled to at least one die / device 204 via a plurality of conductive interconnect structures 206. The at least one die / device 204 may include any number of dies stacked on top of each other, or may include a device comprising any number of dies including a functional array. In embodiments, at least one of the at least one die 204 may include a dynamic random access memory (DRAM) die, and may include a double data rate (DDR) die, such as a DDR4 die and / or a DDR5 die.

[0028] Board 222 may comprise any suitable type of circuit board or other substrate capable of providing electrical communication between one or more of the various components disposed on board 222. In one embodiment, for example, board 222 may comprise a printed circuit board (PCB) comprising multiple metal layers separated from each other by a dielectric material and interconnected by conductive vias. Any one or more metal layers may be formed in a desired circuit pattern to transmit electrical signals between components coupled to board 222—possibly in conjunction with other metal layers. However, it should be understood that the disclosed embodiments are not limited to the PCB described above, and board 222 may comprise any other suitable substrate.

[0029] According to one embodiment, package component 200 includes one or more processing systems and one or more memory devices. In another embodiment, package component 200 includes one or more processing systems and may include a wireless communication system (or, alternatively, include one or more components of a communication system). In embodiments, package component 200 includes a graphics processing system. Component 200 may include part of any type of computing system, such as a handheld computing system (e.g., a mobile phone, smartphone, music player, etc.), a mobile computing system (e.g., a laptop, netbook, tablet, etc.), a desktop computing system, or a server. In one embodiment, component 200 includes a solid-state drive (SSD).

[0030] The embodiments described herein provide improvements in crosstalk reduction and impedance matching. The embodiments include a single optimal socket design suitable for both DDR and PCIe. By optimizing variables involved in the socket design, such as housing height, cantilever beam design, pin configuration, and housing structure, the hybrid socket architecture described herein enables the use of a single socket design for both DDR and PCIe links, providing optimal impedance matching for all I / O and minimizing crosstalk between socket pins.

[0031] The embodiments provide hybrid designs for microelectronic sockets, such as planar grid array (LGA) sockets, which address various requirements of single-ended and differential interconnects. Electrical targets for DDR are typically specified based on crosstalk levels, and electrical performance targets for PCIe are typically defined based on impedance loss characteristics. The socket structures presented herein are optimized to tightly meet both DDR and PCIe performance targets and can be achieved by optimizing parameters such as electrical length / height scaling, contact design optimization, housing design optimization, and metal plating / shielding optimization.

[0032] While the metal plating for DDR interfaces can be optimized to improve shielding between signal pins of adjacent sockets, in some embodiments, the plating for PCIe interfaces provided herein is optional and can be optimized to better match impedance to the nominal values ​​for PCIe differential channel links. The embodiments provide a basic socket housing and pin structure common to both PCIe and DDR interfaces to avoid increasing the cost and complexity of platform design, wherein the socket can be adjusted / optimized to meet the requirements of both DDR and PCIe channel links by adding metal plating around and inside the housing cavity, respectively.

[0033] As signal speeds and the need for smaller form factors increase over time, pin-to-pin crosstalk mitigation becomes crucial for achieving these features. The embodiments described herein address the requirements driven by both DDR and PCIe signaling by using the same geometry for both the socket housing and the pins. This allows for a single-slot technology for the platform, which benefits inventory management, complexity, and design. From a performance perspective, the embodiments address differential impedance matching challenges by adjusting the plating of the socket design provided herein. Simultaneously, the plating is optimized differently to accommodate crosstalk on single-ended buses such as DDR. The embodiments can be applied to any package-to-board connection via the socket structure, such as LGA-based interconnects, memory, boards, multi-chip 3D packages, including CPUs combined with other devices. The embodiments enable server applications including high-speed I / O technologies such as DDR5 and PCIe G5. The embodiments allow pluggable solutions to continue providing customers with the flexibility they need in terms of inventory control and adaptability to later design changes.

[0034] Figures 3a-3c Electrical performance diagrams of packaging systems, such as package component / system 200, are shown, which utilize the socket structure of embodiments herein. Figure 3aIn, for example, regarding crosstalk observed in vertical links including several layers of the package, socket interconnects, and plated vias of the board, socket performance in areas with cell-to-cell shielding for DDR will be compared with non-optimized socket designs of the prior art. Voltage (mV) 304 is plotted relative to time in picoseconds (302). Two patterns representing the conservative bowtie pattern are shown: one utilizing a non-optimized prior art socket 308, and an optimized socket 310 according to an embodiment.

[0035] Also shown is an aggressive signal: an optimized socket pattern 306 with a ground pin ratio of approximately 4:1. Vertical transitions in the channel typically have inductance-dominated crosstalk, which is exacerbated in aggressive patterns. Therefore, in the case of a 4:1 pattern with optimized socket 306 according to embodiments herein, coupled via technology is used to mitigate crosstalk at package vias, sockets, and plated-through-hole (PTH) locations. Far-end crosstalk (FEXT) is calculated using a step of 1V with a rise time of 100ps, as shown in Figure 3A. When the same pin pattern is used for both sockets, shielded socket 306 is observed to give a lower FEXT of -12mV. When the 4:1 pattern is used for shielded sockets, slightly better performance is achieved compared to prior art socket 308, but this results in a pin count saving. Note that this also includes some compensation for package-level crosstalk using coupled via technology. This can be used for DDR drive performance and / or pin count saving purposes.

[0036] On the other hand, for PCIe cases, the addition or removal of metal plating inside and around the housing can be done in a manner that brings the impedance close to the nominal value. For example, the impedance can be modified by reducing some shielding features to adjust the impedance. Figure 3a The result shown is a socket with metal shielding. It has been found that simply introducing a plating layer into the housing minimizes impedance discontinuities. Figure 3b The time-domain reflectometry (TDR) impedance 305, measured at time 307, is shown for a differential pair of socket pins. Profile 310 is used for the hybrid socket of the embodiments herein, where the plating is optimized for the PCIe interface, and a prior art socket 308 is shown.

[0037] For example, for the optimized socket 310 of the embodiment, under the target nominal impedance of 85 ohms, by, for example Figure 1a The impedance discontinuity caused by the socket decreased from 113 ohms to 87 ohms. Figure 3cInsertion loss 309 is shown for differential pairs of socket pins for various frequencies 303 in GHz. A socket profile 310 for the optimized socket used in this embodiment is shown compared to a prior art socket 308. The optimized socket profile 310 shows an impedance improvement, where insertion loss can be reduced by more than approximately 60% at the PCIe G5 Nyquist frequency of 16 GHz, providing a very promising solution.

[0038] Curve 308 of the prior art illustrates the impedance loss of the prior art socket structure (see again). Figure 3b ).exist Figure 3b The first drop observed was a result of capacitive coupling between the LGA pads and the package bottom layer. The socket exhibited a high impedance that must be reduced to match the nominal value. This can be achieved by reducing the socket inductance or increasing the socket capacitance. This article lists some geometric features / factors that can be adjusted to optimize the socket design for DDR and PCIe interfaces.

[0039] Housing geometry: can reduce the dielectric height H (e.g., as shown in the image). Figure 2 (As shown) to reduce pin-to-pin crosstalk in the socket. This also reduces socket inductance and capacitance. Better impedance matching can be achieved using an optimal housing height. Housing material: One of the high-performance materials commonly used for socket housings is liquid crystal polymer (LCP), an injection-molded plastic. The choice of housing dielectric material includes those that include high dielectric constants while maintaining low dielectric losses, which allows for increased capacitance for impedance balancing purposes. Contact pins: The cantilever beam portion of the contact pin can be widened (e.g., see...). Figure 1a The cantilever beam portion 112'), and the vertical portion of the pin surrounded by the housing can be modified (e.g., Figure 1a The pin portion 112' is coated with a metal layer to reduce the socket impedance. Therefore, the socket loss characteristics of the socket structure in the embodiments herein can be optimized.

[0040] Metal Plating: This feature can be optimized for DDR and PCIe applications respectively. For DDR, metal can be added to provide shielding between socket pins and / or to provide good electrical connection between ground pins. Conductive metal / shielding features can be added to the top and bottom of the socket contacts according to optimization requirements. This can be achieved by plating isolation features (e.g., forming metal on the housing cavity wall) and / or forming via structures adjacent to the pin structure (e.g., such as...). Figure 1a (As shown) to achieve pin-to-pin shielding.

[0041] Figure 4A method 400 for optimizing the aforementioned factors / features according to embodiments herein is illustrated. It should be understood that these factors can be optimized for each specific application, depending on the desired specific design specifications. In step 402, a housing structure for a pin structure is provided, wherein the housing structure includes a first side opposite to the second side. The pin structure may also include a pin portion and a cantilever beam portion. In embodiments, the cantilever beam portion may include various widths (which conform to pitch-based electrical and mechanical constraints), for example, between about 10% and about 50% of the pin pitch, which may vary to optimize DDR and / or PCIe applications. In step 404, at least a portion of the pin structure may be placed within a housing cavity disposed within the housing structure. The housing structure may include multiple housing cavities, wherein multiple socket structures may be placed in each housing cavity.

[0042] In step 406, a high-dielectric-constant, low-loss dielectric material can be formed within the housing cavity. In embodiments, the housing structure may also include a high-dielectric-constant, low-dielectric-loss material, and may or may not include the same material as the low-loss, high-dielectric-constant material disposed within the housing cavity. In embodiments, the height of the housing structure including the dielectric material can be formed / selected to reduce and / or optimize the number of individual sockets disposed within the housing structure (e.g., ...). Figure 2 Pin-to-pin crosstalk between the sockets (as shown in the diagram). Optimizing the housing height can reduce socket inductance and capacitance, and achieve excellent impedance matching.

[0043] In step 408, a conductive material may be formed on or adjacent to at least one surface of the housing structure. Furthermore, the conductive material / plating can be used to optimize either DDR or PCIe scenarios, respectively. For DDR, metal can be formed to provide shielding between the pins of the socket, and a good electrical connection can be provided between the ground pin and the shielding feature at both the top and bottom of the housing structure. Pin-to-pin shielding can be achieved by adding conductive material / conductive plating to the surface of and / or adjacent to the housing cavity. In embodiments, the conductive material added adjacent to the housing cavity may include conductive vias.

[0044] The structures described in this embodiment can be coupled to any suitable type of structure capable of providing electrical connectivity between a microelectronic device (e.g., a die) disposed within a package structure and a next-level component (e.g., a circuit board) to which the package structure can be coupled. The device / package structures and components of the embodiments described herein may include circuit elements, such as logic circuitry for a processor die. The structures described herein may include metallization layers and insulating materials, as well as conductive contacts / bumps that can couple the metal layers / interconnects to external devices / layers. In some embodiments, the structure may also include multiple dies, which, according to a particular embodiment, may be stacked on top of each other. In embodiments, the dies may be partially or fully embedded within the package structure.

[0045] The various embodiments of the device structures described herein can be used in system-on-a-chip (SoC) products and can be applied in devices such as smartphones, laptops, tablets, wearable devices, and other electronic mobile devices. In various embodiments, the package structure can be included in laptops, netbooks, ultrabooks, personal digital assistants (PDAs), ultra-mobile PCs, mobile phones, desktop computers, servers, printers, scanners, monitors, set-top boxes, entertainment control units, digital cameras, portable music players, or digital camcorders, as well as wearable devices. In further embodiments, the packaged devices described herein can be included in any other electronic device that processes data.

[0046] Figure 5 This is a schematic diagram of a computing device 500, which can be implemented in conjunction with embodiments of the packaging structure described herein. For example, any suitable component of the computing device 500 may be included or incorporated in the packaging structure / assembly, such as... Figure 2 As shown, the hybrid socket structure can be optimized for impedance and / or crosstalk specifications. In an embodiment, computing device 500 houses board 502, such as motherboard 502. Board 502 may include multiple components, including but not limited to processor 504, on-die memory 506, and at least one communication chip 508. Processor 504 may be physically and electrically coupled to board 502. In some embodiments, at least one communication chip 506 may also be physically and electrically coupled to board 502. In a further embodiment, communication chip 508 is part of processor 504.

[0047] Depending on its application, computing device 500 may include other components that may or may not be physically and electrically coupled to board 502 and may or may not be communicatively coupled to each other. These other components include, but are not limited to: volatile memory (e.g., DRAM) 509, non-volatile memory (e.g., ROM) 510, flash memory (not shown), graphics processing unit (GPU) 512, chipset 514, antenna 516, display 518 (e.g., touchscreen display), touchscreen controller 520, battery 522, audio codec (not shown), video codec (not shown), global positioning system (GPS) device 526, integrated sensor 528, speaker 530, camera 532, compact disc (CD) (not shown), digital multi-purpose disc (DVD) (not shown), etc. These components may be connected to system board 502, mounted to system board, or combined with any other components.

[0048] The communication chip 508 implements wireless and / or wired communication for transmitting data to and from the computing device 500. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, technologies, communication channels, etc., that can transmit data via non-solid media using modulated electromagnetic radiation. This term does not imply that the associated device does not contain any wires, although they may be absent in some embodiments. The communication chip 508 can implement any of a plurality of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, LTE, Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its Ethernet derivatives, and any other wireless and wired protocols designated as 3G, 4G, 5G, and beyond.

[0049] The computing device 500 may include multiple communication chips 508. For example, a first communication chip may be dedicated to short-range wireless communication, such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated to long-range wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc. The term "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory to transform that electronic data into other electronic data that can be stored in registers and / or memory.

[0050] In several embodiments, computing device 500 may be a laptop, netbook, notebook computer, ultrabook, smartphone, tablet computer, personal digital assistant (PDA), ultra-mobile PC, wearable device, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital camcorder. In further embodiments, computing device 500 may be any other electronic device that processes data.

[0051] Embodiments of the packaging structure described herein can be implemented as part of one or more memory chips, controllers, CPUs (central processing units), microchips, or integrated circuits interconnected using a motherboard, application-specific integrated circuits (ASICs), and / or field-programmable gate arrays (FPGAs).

[0052] Example

[0053] Example 1 is a microelectronic packaging structure, including: a conductive pin, including: a cantilever beam portion physically coupled to a first side of a packaging substrate; a contact portion, wherein the terminal ends of the contact portion are physically and electrically coupled to the board; a housing structure, including a housing cavity, wherein the contact portion is at least partially disposed within the housing cavity; and a conductive material disposed near the surface of the housing cavity.

[0054] Example 2 includes the microelectronic package structure of Example 1, wherein the conductive material includes conductive vias disposed adjacent to the housing cavity.

[0055] Example 3 includes an example microelectronic package structure, wherein the housing structure includes a conductive material disposed on the sidewall of the housing structure.

[0056] Example 4 includes the microelectronic packaging structure of Example 1, and also includes a conductive material disposed on a first side of the housing structure.

[0057] Example 5 includes the microelectronic packaging structure of Example 1, and further includes a conductive material disposed on a second side of the housing.

[0058] Example 6 includes the microelectronic packaging structure of Example 1, wherein the housing structure includes a dielectric material, the dielectric material including a high dielectric constant and low dielectric loss material.

[0059] Example 7 includes the microelectronic packaging structure of Example 6, wherein the dielectric material is selected from the group consisting of liquid crystal polymer materials.

[0060] Example 8 includes the microelectronic package structure of Example 1, wherein the microelectronic package structure includes a fast peripheral component interconnect (PCIe) socket, and the substrate includes a dynamic data rate (DDR) memory die.

[0061] Example 9 is a method of forming a microelectronic package structure, comprising: providing a housing structure for a conductive pin, wherein the housing structure includes a first side opposite to a second side; placing a portion of the conductive pin within a housing cavity disposed within the housing structure; forming a high dielectric constant, low loss dielectric material within the housing cavity adjacent to the conductive pin; and forming a conductive material on at least one of the surfaces of the housing cavity or the housing structure.

[0062] Example 10 includes the method of forming a microelectronic package structure of Example 9, further comprising physically coupling a cantilever beam portion of a conductive pin to a first side of a package substrate, and physically coupling the terminal ends of the conductive pin beam to the board.

[0063] Example 11 includes the method of forming a microelectronic package structure of Example 9, and further includes forming a conductive material on a first side of the housing structure.

[0064] Example 12 includes the method of forming a microelectronic package structure of Example 9, and further includes forming a conductive material on a second side of the housing structure.

[0065] Example 13 includes the method of forming a microelectronic package structure of Example 9, further comprising that the housing structure includes a high dielectric constant, low loss dielectric material.

[0066] Example 14 includes the method of forming a microelectronic package structure of Example 10, wherein providing a housing structure includes providing a housing structure including a height for reducing the impedance of the package structure.

[0067] Example 15 includes the method of forming a microelectronic package structure of Example 9, and further includes forming a conductive material on the sidewall of the housing structure.

[0068] Example 16 includes the method of forming a microelectronic package structure of Example 10, wherein the package substrate further includes DDR memory, and the microelectronic package structure includes a PCIe socket.

[0069] Example 17 is a microelectronic system comprising: a package substrate including at least one die; a socket structure physically and electrically coupled to the at least one die, wherein the socket structure includes: a cantilever beam physically coupled to a first side of the package substrate; a pin physically coupled to the cantilever beam, wherein the pin is at least partially disposed within a housing cavity of the housing structure; a conductive material disposed near a surface of the housing cavity; and a terminal end of the pin physically coupled to the board.

[0070] Example 18 includes the microelectronic system of Example 17, wherein the socket structure includes a portion of an LGA socket.

[0071] Example 19 includes the microelectronic system of Example 17, wherein the at least one die includes a DDR memory die.

[0072] Example 20 includes the microelectronic system of Example 17, wherein the system includes a PCIe interface.

[0073] Example 21 includes the microelectronic system of Example 17, wherein the system includes a DDR interface.

[0074] Example 22 includes the microelectronic system of Example 20, wherein the system includes a high-speed single-ended interconnect.

[0075] Example 23 includes the microelectronic system of Example 17, wherein the system includes differential terminal interconnects.

[0076] Example 24 includes the microelectronic system of Example 17, wherein the system is capable of providing a data rate greater than about 2.0 GB / link.

[0077] Example 25 includes the microelectronic system of Example 17, wherein the conductive material includes a conductive plating material.

[0078] While the foregoing description has specified specific steps and materials that can be used in the methods of the embodiments, those skilled in the art will understand that many modifications and substitutions can be made. Therefore, it is intended that all such modifications, alterations, substitutions, and additions be considered to fall within the spirit and scope of the embodiments as defined by the appended claims. Furthermore, the accompanying drawings provided herein illustrate only portions of exemplary microelectronic devices and related packaging structures relevant to the practice of the embodiments. Therefore, the embodiments are not limited to the structures described herein.

Claims

1. A microelectronic packaging connector structure, comprising: Conductive pins, including: The cantilever beam portion is physically coupled to the first side of the packaging substrate; and The contact pin portion, wherein the terminal ends of the contact pin portion are physically and electrically coupled to the board; A housing structure including a housing cavity, wherein the stylus portion is at least partially disposed within the housing cavity; and A first conductive material is disposed on the side wall of the housing cavity. The housing structure includes a second conductive material disposed on at least a portion of the sidewall of the housing structure.

2. The microelectronic packaging connector structure according to claim 1, wherein, The first conductive material includes copper.

3. The microelectronic packaging connector structure according to any one of the preceding claims, wherein, The first conductive material forms a conductive via.

4. The microelectronic packaging socket structure according to any one of claims 1-2 further includes a conductive material disposed on a first side of the housing structure.

5. The microelectronic packaging socket structure according to any one of claims 1-2 further includes a conductive material disposed on a second side of the housing structure.

6. The microelectronic packaging connector structure according to any one of claims 1-2, wherein, The housing structure includes a dielectric material, which includes a material with high dielectric constant and low dielectric loss.

7. The microelectronic packaging connector structure according to claim 6, wherein, The dielectric material is selected from the group consisting of liquid crystal polymer materials.

8. The microelectronic packaging connector structure according to any one of claims 1-2, wherein, The microelectronic package socket structure includes a PCIe fast peripheral interconnect (PCIe) socket, and the substrate includes a dynamic data rate (DDR) memory die.

9. A method for forming a microelectronic package socket structure, comprising: A housing structure for a conductive pin is provided, wherein the housing structure includes a first side opposite to a second side; A portion of the conductive pin is placed inside a housing cavity within the housing structure; A high-dielectric-constant, low-loss dielectric material is formed within the housing cavity adjacent to the conductive pin; and Conductive material is formed on at least a portion of the sidewall of the housing structure and on the sidewall of the housing cavity.

10. The method for forming a microelectronic package socket structure according to claim 9 further includes physically coupling the cantilever beam portion of the conductive pin to a first side of the package substrate, and physically coupling the terminal end of the conductive pin to the board.

11. The method for forming a microelectronic package socket structure according to any one of claims 9-10 further comprises forming a conductive material on a first side of the housing structure.

12. The method for forming a microelectronic package socket structure according to any one of claims 9-10 further comprises forming a conductive material on a second side of the housing structure.

13. The method for forming a microelectronic package socket structure according to any one of claims 9-10 further includes, The shell structure comprises a high dielectric constant and low loss dielectric material.

14. The method for forming a microelectronic package socket structure according to claim 10, wherein, Providing the housing structure includes providing a housing structure with a height for reducing the impedance of the packaging structure.

15. The method for forming a microelectronic package socket structure according to any one of claims 9-10, wherein, An additional housing cavity is provided adjacent to the housing cavity, wherein the additional housing cavity includes an additional conductive pin and also includes a conductive material formed on the sidewall of the additional housing cavity.

16. The method for forming a microelectronic package socket structure according to claim 10, wherein, The packaging substrate also includes DDR memory, and the microelectronic packaging interface structure includes a PCIe interface.

17. A microelectronic system, comprising: A packaging substrate, comprising at least one die; A socket structure physically and electrically coupled to the at least one die, wherein the socket structure includes: A cantilever beam, which is physically coupled to a first side of the packaging substrate; A stylus, which is physically coupled to the cantilever beam, wherein the stylus is at least partially disposed within the housing cavity of the housing structure; A first conductive material is disposed on the side wall of the housing cavity; and The terminal end of the stylus is physically coupled to the plate. The housing structure includes a second conductive material disposed on at least a portion of the sidewall of the housing structure.

18. The microelectronic system according to claim 17, wherein, The socket structure includes a portion of a planar grid array (LGA) socket.

19. The microelectronic system according to any one of claims 17-18, wherein, The at least one die includes a DDR memory die.

20. The microelectronic system according to any one of claims 17-18, wherein, The system includes a PCIe interface.

21. The microelectronic system according to any one of claims 17-18, wherein, The system includes a DDR interface.

22. The microelectronic system according to claim 20, wherein, The system includes a high-speed single-ended interconnect.

23. The microelectronic system according to any one of claims 17-18, wherein, The system includes differential interconnects.

24. The microelectronic system according to any one of claims 17-18, wherein, The system is capable of providing a data rate of more than approximately 2.0 GB per link.

25. The microelectronic system according to claim 24, wherein, The first conductive material includes a conductive plating material.

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