System, apparatus and method for multiplication, negation and accumulation of vector packed signed values

Abstract

Embodiments of systems, apparatus, and methods for multiplication, negation, and accumulation of data values ​​in a processor are described. For example, execution circuitry executes decoded instructions to multiply selected data values ​​from a plurality of packed data element positions in first and second packed data source operands to generate a plurality of first result values, sum the plurality of first result values ​​to generate one or more second result values, negate the one or more second result values ​​to generate one or more third result values, accumulate the one or more third result values ​​with one or more data values ​​from a destination operand to generate one or more fourth result values, and store the one or more third result values ​​in one or more packed data element positions in the destination operand.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of computer processor architectures. More particularly, embodiments relate to instructions that, when executed, result in multiplication, negation, and accumulation of vector packed signed data values. Background Art

[0002] An instruction set or instruction set architecture (ISA) is the part of a computer architecture that is relevant to programming, including native data types, instructions, register structure, addressing modes, memory architecture, interrupt and exception handling, and external input and output (I / O). Here, the term "instruction" generally refers to a macroinstruction, that is, an instruction provided to a processor for execution, as distinguished from a microinstruction or micro-operation, that is, the result of a processor's decoder decoding a macroinstruction. A microinstruction or micro-operation can be configured to instruct an execution unit on a processor to perform an operation to implement the logic associated with the macroinstruction.

[0003] ISA is different from microarchitecture, which is a collection of processor design technologies used to implement an instruction set. Processors with different microarchitectures can share a common instruction set. For example, Intel® Pentium 4 processor, Intel® Core TM The processors from Advanced MicroDevices, Inc. of Sunnyvale, California, implement almost the same version of the x86 instruction set (with some extensions that have been added with newer versions), but have different internal designs. For example, the same register architecture of the ISA can be implemented in different ways in different micro-architectures using well-known techniques, including dedicated physical registers, one or more dynamically allocated physical registers using a register renaming mechanism (e.g., using a register alias table (RAT), a reorder buffer (ROB), and a retirement register file). Unless otherwise specified, the terms register architecture, register file, and register are used in this article to refer to what is visible to the software / programmer and the way in which instructions specify registers. Where a distinction is required, the adjectives "logical", "architectural", or "software visible" will be used to indicate registers / files in a register architecture, while different adjectives will be used to specify registers (e.g., physical registers, reorder buffers, retirement registers, register pools) in a given micro-architecture.

[0004] Multiply-accumulate is a common digital signal processing operation that calculates the product of two numbers and adds the product to an accumulation value. Existing single instruction multiple data (SIMD) microarchitectures implement multiply-accumulate operations by executing a sequence of instructions. For example, a multiply-accumulate may be performed using a multiply instruction, followed by a 4-way addition, and then accumulated with the destination quad word length data to generate two 64-bit saturated results. Since these sequences of instructions are run for each operation, this results in lower performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The present invention may best be understood by referring to the following description and accompanying drawings which illustrate embodiments of the invention. In the drawings:

[0006] Figure 1 illustrates an exemplary execution of a vector packed signed multiply, negate, and accumulate instruction according to an embodiment;

[0007] Figure 2 An embodiment of a method executed by a processor to process multiplication, negation, and logic instructions according to an embodiment is illustrated;

[0008] Figures 3A-3C The diagram shows a sample instruction format;

[0009] Figure 4 is a block diagram of a register architecture according to one embodiment of the present invention;

[0010] Figure 5A-5B The diagram shows an in-order pipeline and an in-order core;

[0011] Figure 6A-6B illustrates a block diagram of a more specific exemplary in-order core architecture, which would be one of several logic blocks in a chip (including other cores of the same type and / or different types);

[0012] Figure 7 is a block diagram of a processor that may have more than one core, may have an integrated memory controller, and may have integrated graphics according to an embodiment of the present invention;

[0013] Figure 8-11 is a block diagram of an exemplary computing architecture; and

[0014] Fig.12 A block diagram contrasting the use of a software instruction converter for converting binary instructions in a source instruction set to binary instructions in a target instruction set is illustrated in accordance with an embodiment of the present invention. DETAILED DESCRIPTION

[0015] The following description describes a method and apparatus for implementing vector packed signed multiplication, negation and accumulation of signed word values. In the following description, many specific details are set forth to provide a more detailed understanding of the present invention, such as logic implementation, opcodes, methods for specifying operands, resource partitioning / sharing / repeated implementation, types and interrelationships of system components, and logic partitioning / integration selection. However, those skilled in the art will appreciate that the present invention can be practiced without such specific details. In other instances, control structures, gate circuits, and full software instruction sequences are not shown in detail to avoid confusing the present invention. By including the description, those skilled in the art will be able to implement appropriate functionality without undue experimentation.

[0016] References in the specification to "one embodiment," "an embodiment," "an example embodiment," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but each embodiment may not necessarily include this particular feature, structure, or characteristic. In addition, such words do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is considered to be within the knowledge of those skilled in the art to affect such feature, structure, or characteristic in conjunction with other embodiments, whether or not explicitly described.

[0017] Text within brackets and boxes with dashed edges (e.g., large dashed lines, small dashed lines, dot-dashed lines, and dots) may be used herein to illustrate optional operations that add additional features to embodiments of the present invention. However, such notations should not be construed to mean that these notations are the only options or optional operations and / or that boxes with solid edges are not optional in certain embodiments of the present invention.

[0018] In the following description and claims, the terms "coupled" and "connected," along with their derivatives, may be used. It should be understood that these terms are not intended as synonyms for each other. "Coupled" is used to indicate that two or more elements that may or may not be in direct physical or electrical contact with each other cooperate or interact with each other. "Connected" is used to indicate the establishment of communication between two or more elements that are coupled to each other.

[0019] Signed word vector multiplication, negation, and accumulation

[0020] In one embodiment, new vector packed instructions are disclosed that implement multiplication, negation, and accumulation of signed word values. Whereas previous implementations required executing a sequence of instructions to generate outputs corresponding to multiplication, negation, and accumulation of signed word values, the embodiments disclosed herein provide a single instruction and associated circuitry to perform these operations on word values ​​of vector source registers. These embodiments improve the computer itself by speeding up the execution of these operations (and therefore generally using less power) relative to executing multiple separate instructions.

[0021] As indicated above, execution of one or more instructions disclosed herein causes execution circuitry (or an execution unit) to perform a multiply, negate, and accumulate operation on source data. In some embodiments, execution of the multiply, negate, and accumulate instruction causes execution circuitry to multiply selected data values ​​from a plurality of packed data element positions in first and second packed data source operands to generate a plurality of first result values; sum the plurality of first result values ​​to generate one or more second result values; negate the one or more second result values ​​to generate one or more third result values; accumulate the one or more third result values ​​with one or more data values ​​from a destination operand to generate one or more fourth result values; and store the one or more fourth result values ​​in one or more packed data element positions in the destination operand. In some embodiments, execution of the instruction further includes saturating the one or more fourth result values ​​using a saturation circuit and storing the saturated result in one or more packed data element positions in the destination operand.

[0022] Figure 1 One embodiment of a circuit for executing instructions that cause vector packed signed values ​​to be multiplied, negated, and accumulated is illustrated. The multiply, negate, and accumulate instruction format includes fields for a destination (packed data destination (SRC1 / DEST) 120) and two sources (vector packed data source 2 (SRC2) 102 and vector packed data source 3 (SRC3) 104). For example, SRC2 102 and SRC3 104 can each include eight word values. Although in Figure 1 In the illustrated example of , each source is 128 bits and each data element is 16 bits, but the underlying principles described herein are not limited to any specific source or data element size. For example, in other embodiments, data source sizes of 128 bits, 256 bits, 512 bits, etc. can be used. Similarly, vector data element sizes of 32 bits, 64 bits, 128 bits, etc. can be used. As indicated, the execution of the instruction multiplies, negates, and accumulates the values ​​stored in the SRC2 102 and SRC3 104 sources. In this example, multiplication is performed first, followed by negation of the input value, accumulation, and optional saturation.

[0023] Vector packed data source 2 102 includes eight packed data elements (shown as packed data element positions AH). Depending on the implementation, vector packed data source 2 102 is a packed data register (e.g., an XMM, YMM, ZMM, vector, SIMD, D, or S register) or a memory location. Similarly, vector packed data source 3 104 includes eight packed data elements (also shown as packed data element positions AH). Depending on the implementation, vector packed data source 3 104 is a packed data register (e.g., an XMM, YMM, ZMM, vector, SIMD, D, or S register) or a memory location.

[0024] Two packed data sources 102, 104 are fed into the execution circuit to be operated on. As shown, the execution circuit can include an input multiplexer (input mux) 106, which passes the values ​​from the packed data sources 102, 104 to a plurality of multiplexers 107. As discussed, the corresponding values ​​of the packed data sources 102, 104 are multiplied, and the results are then negated, accumulated and optionally saturated, as described in more detail below.

[0025] The multipliers 107 are capable of performing vector multiplication on the data sources 102, 104, wherein each multiplier multiplies a selected vector data element from SRC2 102 with a selected vector data element from SRC3 104. In some embodiments, each input value may be a signed value. Figure 1 , the multiplier 107 generates the following values ​​S2(H)*S3(H), S2(G)*S3(G), S2(F)*S3(F), S2(E)*S3(E), S2(D)*S3(D), S2(C)*S3(C), S2(B)*S3(B), S2(A)*S3(A), where S2 identifies the first source 102 and S3 identifies the second source 104, and A, B, C, D, E, F, G, and H identify packed data element positions ordered from lowest to highest data element position in the data sources 102, 104. Note that although multiple multipliers are shown, in some embodiments, the same multiplier is used to multiply each pair of values.

[0026] exist Figure 1 In the embodiment shown in , the adder network 108, 110 is capable of combining the output of the multiplier 107. Therefore, the multiplication, negation and accumulation instructions calculate the product of the corresponding pairs of values ​​in the source and sum the corresponding product values. The pseudo code representation is shown below:

[0027] TEMP0[33:0] ← (SRC2[63:48]*SRC3[63:48])+(SRC2[47:32]*SRC3[47:32])+(SRC2[31:16]*SRC3[31:16])+(SRC2[15:0]*SRC3[15:0]))

[0028] TEMP1[33:0] ← (SRC2[127:112]*SRC3[127:112])+(SRC2[111:96]*SRC3[111:96])+(SRC2[95:80]*SRC3[95:80])+(SRC2[79:64]*SRC3[79:64]

[0029] As shown, the result of multiplying and summing the word values ​​contained in the lower 64 bits of SRC2 and SRC3 can be stored in the first temporary register TEMP0, and the result of multiplying and summing the word values ​​contained in the upper 64 bits of SRC2 and SRC3 can be stored in the second temporary register TEMP1.

[0030] In one embodiment, the value stored in the first temporary register TEMP0 can be negated and stored in the third temporary register TEMP2, and the value stored in the second temporary register TEMP1 can be negated and stored in the fourth temporary register TEMP3. For example, the negation of the values ​​stored in the TEMP0 and TEMP1 temporary registers can be performed by the adder network 108, 110 or other circuits. A pseudo-code representation of the negation of the values ​​in the TEMP0 and TEMP1 temporary registers is shown below:

[0031] TEMP2[33:0] ← ~TEMP0[33:0]+1'b1 (* Negate and wrap around *)

[0032] TEMP3[33:0] ← ~TEMP1[33:0]+1'b1 (*negate and wrap*)

[0033] The vector packed data destination 120 stores the results from the adder networks 108 and 110 via the accumulators 112, 114. Depending on the implementation, the vector packed data source 1 / destination 120 is a packed data register (e.g., XMM, YMM, ZMM, vector, SIMD, D, S or other register) or a memory location. In this illustration, the packed data destination 120 is the same as the packed data source 1, however, this need not be the case. In some embodiments, each result can be sign-extended and accumulated to the corresponding 64 bits of the value in the destination register before being added to the appropriate accumulator 112, 114. For example, as shown in the pseudo-code representation below, the result stored in the third temporary register TEMP2 can be sign-extended and then stored in the lower 64 bits of the destination 120, and the result stored in the fourth register TEMP3 can be sign-extended and stored in the higher 64 bits of the destination 120.

[0034] DEST[63:0] ← AddToQuadWord({30{TEMP2

[33] }}, TEMP2[33:0]}, DEST[63:0]);

[0035] DEST[127:64] ← AddToQuadWord({30{TEMP3

[33] }}, TEMP3[33:0]}, DEST[127:64]);

[0036] In some embodiments, the sign-extended results may be saturated using saturation circuits 122, 124 before the results are stored in the vector packed data destination.

[0037] One embodiment of a format for a multiply, negate, and accumulate instruction is VPNDPWSSQ DEST1, SRC2, SRC3, where DEST1 is a field for a packed data destination register operand, and SRC2 and SRC3 are fields for a source such as a packed data register or memory. In some embodiments, the instruction can be VEX encoded.

[0038] In some embodiments, the encoding of the multiply, negate, and accumulate instructions includes a scale-index-base (SIB) type memory addressing operand that indirectly identifies a plurality of indexed destination locations in memory. In one embodiment, the SIB type memory operand may include an encoding that identifies a base register. The contents of the base register may represent a base address in memory from which the address of a specific destination location in memory is calculated. For example, the base address may be the address of the first position in a block of potential destination locations for an extended vector instruction. In one embodiment, the SIB type memory operand may include an encoding that identifies an index register. Each element of the index register may specify an index or offset value that may be used to calculate the address of a corresponding destination location within the block of potential destination locations from the base address. In one embodiment, the SIB type memory operand may include an encoding that specifies a scale factor to be applied to each index value when calculating the corresponding destination address. For example, if a scale factor value of four is encoded in the SIB type memory operand, each index value obtained from an element of the index register may be multiplied by four and then added to the base address to calculate the destination address.

[0039] In one embodiment, a SIB-type memory operand of the form vm32{x,y,z} may identify a vector array of memory operands specified using SIB-type memory addressing. In this example, a common base address register, a constant scaling factor, and a vector index register containing individual elements (each of which is a 32-bit index value) are used to specify an array of memory addresses. The vector index register may be a 128-bit (e.g., XMM) register (vm32x), a 256-bit (e.g., YMM) register (vm32y), or a 512-bit (e.g., ZMM) register (vm32z). In another embodiment, a SIB-type memory operand of the form vm64{x,y,z} may identify a vector array of memory operands specified using SIB-type memory addressing. In this example, a common base address register, a constant scaling factor, and a vector index register containing individual elements (each of which is a 64-bit index value) are used to specify an array of memory addresses. The vector index register may be a 128-bit (eg, XMM) register (vm64x), a 256-bit (eg, YMM) register (vm64y), or a 512-bit (eg, ZMM) register (vm64z).

[0040] Figure 2 , a method according to one embodiment is illustrated in FIG. The operations in the flow chart will be described with reference to the exemplary embodiments of other figures. However, the operations of the flow chart can be performed by embodiments of the present invention that are different from those discussed with reference to other figures, and the embodiments of the present invention discussed with reference to these other figures can perform operations that are different from those discussed with reference to the flow chart.

[0041] At operation 202, the process fetches an instruction from a code storage device by a fetch circuit, the instruction having fields for an opcode, first and second packed data source operands, and a packed data destination operand. In one embodiment, the destination operand and the first and second source operands are vector packed data.

[0042] The decode circuitry decodes the fetched instructions at block 204. For example, the fetched multiply, negate, and accumulate instructions are decoded by a decode circuitry, such as the decode circuitry described in detail herein.

[0043] At block 206, execution of the decoded instruction on the data identified by the source operands is scheduled by the execution circuitry. In one embodiment, the first source operand identifies a first source register storing a first plurality of signed input values, and the second source operand identifies a second source register storing a second plurality of signed input values. In some embodiments, the decoded instruction further indicates whether the result value is to be saturated.

[0044] At block 208, the execution circuitry executes the decoded instruction to multiply selected data values ​​from a plurality of packed data element positions in the first and second packed data source operands to generate a plurality of first result values; sum the plurality of first result values ​​to generate one or more second result values; negate the one or more second result values ​​to generate one or more third result values; accumulate the one or more third results with the one or more data values ​​from the destination operand to generate one or more fourth result values; optionally, saturate the one or more fourth result values; and store the one or more fourth result values ​​in one or more packed data element positions in the destination operand.

[0045] For example, see again Figure 1 , a plurality of multipliers 107 can multiply selected data values ​​from a plurality of packed data element positions in first and second packed data source operands (e.g., data sources 102, 104) to generate a plurality of first result values. The plurality of first result values ​​can be summed by one or more adder networks (e.g., adder networks 108, 110) to generate one or more second result values, and the adder network (or other circuitry) can further negate the one or more second result values ​​to generate one or more third result values. The one or more third result values ​​can be accumulated by one or more accumulators 112, 114 with one or more data values ​​from a destination operand (e.g., vector packed data destination 120). In some embodiments, the one or more third results can be optionally saturated by saturation circuits 122, 124. One or more fourth result values ​​can be stored in one or more packed data element positions in the destination operand, for example, in data element positions of the vector packed data destination 120.

[0046] In one embodiment, executing the decoded instruction further includes multiplexing data values ​​from a plurality of packed data element positions in the first and second packed data source operands to at least one multiplier circuit. For example, the data values ​​of the first and second packed data sources 102, 104 can be multiplexed by input multiplexer 106 to multiplexer 107. Figure 1 As shown in , data values ​​of the first and second packed data sources 102, 104 are multiplexed based on data values ​​sharing the same packed data element position in the first and second packed data source operands (e.g., the data value at position H of packed data source 3 104 is sent for multiplication with the corresponding data value at position H of packed data source 2 102).

[0047] In one embodiment, storing the one or more third result values ​​includes storing one result in an upper half of the packed data destination operand (e.g., the result from adder network 108 and accumulator 112 is stored in an upper half of packed data destination 120) and storing another result in a lower half of the packed data destination operand (e.g., the result from adder 110 and accumulator 114 is stored in a lower half of packed data destination 120).

[0048] Exemplary embodiments are described in detail below.

[0049] 1. A method for executing an instruction, the method comprising: decoding, by a decoding circuit, an instruction having fields for first and second packed data source operands and a packed data destination operand; executing, by the execution circuit, the decoded instruction by: multiplying selected data values ​​from a plurality of packed data element positions in the first and second packed data source operands to generate a plurality of first result values; summing the plurality of first result values ​​to generate one or more second result values; negating the one or more second result values ​​to generate one or more third result values; accumulating the one or more third result values ​​and one or more data values ​​from a destination operand to generate one or more fourth result values; and storing the one or more fourth result values ​​in one or more packed data element positions in the destination operand.

[0050] 2. The method of example 1, wherein executing the decoded instruction by the decode circuitry further comprises multiplexing data values ​​from a plurality of packed data element positions in the first and second packed data source operands to the at least one multiplier circuit.

[0051] 3. The method of Example 2, wherein data values ​​from a plurality of packed data element positions in the first and second packed data source operands are multiplexed to the at least one multiplier circuit based on data values ​​sharing the same packed data element position in the first and second packed data source operands.

[0052] 4. The method of example 1, wherein the one or more second result values ​​are generated by one or more adder networks.

[0053] 5. The method of example 1, wherein storing the one or more third result values ​​comprises storing the result value in an upper half of the packed data destination operand and storing the result value in a lower half of the packed data destination operand.

[0054] 6. The method of example 1, wherein multiplying the selected data value comprises: performing operations S1H*S2H, S1G*S2G, S1F*S2F, and S1E*S2E and operations S1D*S2D, S1C*S2C, S1B*S2B, and S1A*S2A to generate a plurality of first result values, wherein S1 identifies a first packed data source operand, S2 identifies a second packed data source operand, and A, B, C, D, E, F, G, and H identify packed data element positions ordered from a lowest to a highest data element position in the first and second packed data source operands.

[0055] 7. The method of Example 6, wherein summing the plurality of first result values ​​comprises performing an operation (S1H*S2H)+(S1G*S2G)+(S1F*S2F)+(S1E*S2E) and performing an operation (S1H*S2H)+(S1G*S2G)+(S1B*S2B)+(S1A*S2A) to generate one or more second result values.

[0056] 8. The method of example 1, further comprising, in response to detecting that a value of the one or more third result values ​​is above a threshold, storing a maximum value in a corresponding position of the destination operand.

[0057] 9. An apparatus comprising: a decoder that decodes an instruction having fields for first and second packed data source operands and a packed data destination operand; and execution circuitry that executes the decoded instruction to: multiply selected data values ​​from a plurality of packed data element positions in the first and second packed data source operands to generate a plurality of first result values; sum the plurality of first result values ​​to generate one or more second result values; negate the one or more second result values ​​to generate one or more third result values; accumulate the one or more third result values ​​and one or more data values ​​from a destination operand to generate one or more fourth result values; and store the one or more fourth result values ​​in one or more packed data element positions in the destination operand.

[0058] 10. The apparatus of example 9, wherein the instruction to be decoded by the decode circuitry further comprises multiplexing data values ​​from a plurality of packed data element positions in the first and second packed data source operands to the at least one multiplier circuit.

[0059] 11. The apparatus of example 9, wherein data values ​​from a plurality of packed data element positions in the first and second packed data source operands are multiplexed to the at least one multiplier circuit based on data values ​​sharing the same packed data element position in the first and second packed data source operands.

[0060] 12. The apparatus of example 9, wherein the one or more second result values ​​are generated by one or more adder networks.

[0061] 13. The apparatus of example 9, wherein storing the one or more third result values ​​comprises storing the result value in an upper half of the packed data destination operand and storing the result value in a lower half of the packed data destination operand.

[0062] 14. The apparatus of Example 9, wherein multiplying the selected data value comprises: performing operations S1H*S2H, S1G*S2G, S1F*S2F, and S1E*S2E and operations S1D*S2D, S1C*S2C, S1B*S2B, and S1A*S2A to generate a plurality of first result values, wherein S1 identifies a first packed data source operand, S2 identifies a second packed data source operand, and A, B, C, D, E, F, G, and H identify packed data element positions ordered from a lowest to a highest data element position in the first and second packed data source operands.

[0063] 15. The apparatus of Example 9, wherein summing the plurality of first result values ​​comprises performing an operation (S1H*S2H)+(S1G*S2G)+(S1F*S2F)+(S1E*S2E) and performing an operation (S1H*S2H)+(S1G*S2G)+(S1B*S2B)+(S1A*S2A) to generate one or more second result values.

[0064] 16. The apparatus of example 9, further comprising storing a maximum value in a corresponding position of the destination operand in response to detecting that a value of the one or more third result values ​​is above a threshold.

[0065] 17. A non-transitory machine-readable medium storing instructions which, when executed by a processor, cause the processor to perform a method, the method comprising: decoding an instruction having fields for first and second packed data source operands and a packed data destination operand; executing, by execution circuitry, the decoded instruction to: multiply selected data values ​​from a plurality of packed data element positions in the first and second packed data source operands to generate a plurality of first result values; sum the plurality of first result values ​​to generate one or more second result values; negate the one or more second result values ​​to generate one or more third result values; accumulate the one or more third result values ​​and one or more data values ​​from a destination operand to generate one or more fourth result values; and store the one or more fourth result values ​​in one or more packed data element positions in the destination operand.

[0066] 18. The non-transitory machine readable medium of Example 17, wherein the instructions to be decoded by the decode circuitry further comprise multiplexing data values ​​from a plurality of packed data element positions in the first and second packed data source operands to the at least one multiplier circuit.

[0067] 19. The non-transitory machine readable medium of Example 18, wherein data values ​​from a plurality of packed data element positions in the first and second packed data source operands are multiplexed to at least one multiplier circuit based on data values ​​sharing the same packed data element position in the first and second packed data source operands.

[0068] 20. The non-transitory machine readable medium of example 17, wherein the one or more second result values ​​are generated by one or more adder networks.

[0069] 21. The non-transitory machine readable medium of example 17, wherein storing the one or more fourth result values ​​comprises storing the result value in an upper half of the packed data destination operand and storing the result value in a lower half of the packed data destination operand.

[0070] 22. The non-transitory machine-readable medium of Example 17, wherein multiplying the selected data value comprises: performing operations S1H*S2H, S1G*S2G, S1F*S2F, and S1E*S2E and operations S1D*S2D, S1C*S2C, S1B*S2B, and S1A*S2A to generate a plurality of first result values, wherein S1 identifies a first packed data source operand, S2 identifies a second packed data source operand, and A, B, C, D, E, F, G, and H identify packed data element positions ordered from lowest to highest data element position in the first and second packed data source operands.

[0071] 23. The non-transitory machine-readable medium of Example 17, wherein summing the plurality of first result values ​​comprises performing an operation (S1H*S2H)+(S1G*S2G)+(S1F*S2F)+(S1E*S2E) and performing an operation (S1H*S2H)+(S1G*S2G)+(S1B*S2B)+(S1A*S2A) to generate one or more second result values.

[0072] 24. The non-transitory machine readable medium of example 17, further comprising, in response to detecting that a value of the one or more third result values ​​is above a threshold, storing a maximum value in a corresponding position of the destination operand.

[0073] Detailed demonstration system, processor and simulation

[0074] Examples of hardware, software, etc. for executing the instructions described above are described in detail herein. For example, described below are detailed aspects of instruction execution, including various pipeline stages such as fetch, decode, schedule, execute, retire, etc.

[0075] The instruction set includes one or more instruction formats. A given instruction format defines various fields (number of bits, position of bits) to specify, among other things, the operation to be performed (opcode) and the operands on which the operation will be performed. Some instruction formats are further decomposed by the definition of instruction templates (or subformats). For example, the instruction templates of a given instruction format may be defined to have different subsets of the fields of the instruction format (the fields included are typically in the same order, but at least some fields have different bit positions due to the inclusion of fewer fields), and / or defined to have given fields interpreted in different ways. Therefore, each instruction of the ISA is expressed using a given instruction format (and, if defined, a given template of the instruction template of the instruction format), and includes fields for specifying operations and operands. For example, the exemplary ADD instruction has a specific opcode and an opcode field that specifies the opcode and an operand field (source 1 / destination and source 2) for selecting operands. The appearance of this ADD instruction in the instruction stream will have specific content in the operand field that selects a specific operand.

[0076] Demonstration instruction format

[0077] Embodiments of one or more instructions described herein may be implemented in different formats. In addition, exemplary systems, architectures, and pipelines are described in detail below. Embodiments of one or more instructions may be executed on such systems, architectures, and pipelines, but are not limited to those described in detail.

[0078] VEX instruction format

[0079] VEX encoding allows instructions to have more than two operands, and allows SIMD vector registers to be longer than 128 bits. The use of the VEX prefix provides a three-operand (or more) syntax. For example, the previous two-operand instructions perform operations such as A=A+B that overwrite the source operands. The use of the VEX prefix enables operands to perform non-destructive operations such as A=B+C.

[0080] Figure 3A An exemplary AVX instruction format is illustrated, including a VEX prefix 302 , a true opcode field 330 , a Mod R / M byte 340 , a SIB byte 350 , a displacement field 362 , and an IMM8 372 . Figure 3B The diagram shows Figure 3A Which fields constitute the full opcode field 374 and the basic operation field 341. Figure 3C The diagram shows Figure 3A Which fields of constitute the register index field 344.

[0081] The VEX prefix (bytes 0-2) 302 is encoded in three-byte form. The first byte is the format field 390 (VEX byte 0, bits [7:0]), which contains an explicit C4 byte value (a unique value used to distinguish the C4 instruction format). The second and third bytes (VEX bytes 1 and 2) include multiple bit fields that provide specific capabilities. Specifically, the REX field 305 (VEX byte 1, bits [7:5]) consists of a VEX.R bit field (VEX byte 1, bits [7]–R), a VEX.X bit field (VEX byte 1, bits [6]–X), and a VEX.B bit field (VEX byte 1, bits [5]–B). The other fields of the instruction encode the lower three bits of the register index (rrr, xxx, and bbb) as is known in the art, such that Rrrr, Xxxx, and Bbbb can be formed by adding VEX.R, VEX.X, and VEX.B. The opcode map field 315 (VEX byte 1, bits [4:0]–mmmmm) includes content for encoding the implied leading opcode byte. The W field 364 (VEX byte 2, bits [7]–W) is represented by the notation VEX.W and provides different functions depending on the instruction. The effect of VEX.vvvv 320 (VEX byte 2, bits [6:3]-vvvv) may include the following: 1) VEX.vvvv encodes the first source register operand specified in inverted (1s complement) form and is valid for instructions with 2 or more source operands; 2) VEX.vvvv encodes the destination register operand specified in 1s complement form for certain vector shifts; or 3) VEX.vvvv does not encode any operand, the field is reserved and should contain 1111b. If the VEX.L 368 size field (VEX byte 2, bit [2]-L) = 0, it indicates a 128-bit vector; if VEX.L = 1, it indicates a 256-bit vector. The prefix encoding field 325 (VEX byte 2, bits [1:0]-pp) provides additional bits for the base operation field 341.

[0082] The true opcode field 330 (byte 3) is also called the opcode byte. A portion of the opcode is specified in this field.

[0083] The MOD R / M field 340 (byte 4) includes a MOD field 342 (bits [7:6]), a Reg field 344 (bits [5:3]), and an R / M field 346 (bits [2:0]). The role of the Reg field 344 may include the following: encoding a destination register operand or a source register operand (rrr's rrr), or being treated as an opcode extension and not used to encode any instruction operand. The role of the R / M field 346 may include the following: encoding an instruction operand that references a memory address, or encoding a destination register operand or a source register operand.

[0084] The contents of the Scale, Index, Base (SIB)-Scale field 350 (Byte 5) include SS 352 (bits [7:6]) which is used for memory address generation. The contents of SIB.xxx 354 (bits [5:3]) and SIB.bbb 356 (bits [2:0]) have been previously referred to relative to register indexes Xxxx and Bbbb.

[0085] The displacement field 362 and the immediate field (IMM8) 372 contain data.

[0086] Exemplary Register Architecture

[0087] Figure 4 is a block diagram of a register architecture 400 according to one embodiment of the present invention. In the illustrated embodiment, there are 32 vector registers 410 that are each 512 bits wide; these registers are referenced as zmm0 through zmm31. The lower order 256 bits of the lower 410 zmm registers are overlaid on registers ymm0-15. The lower order 128 bits of the lower 410 zmm registers (the lower order 128 bits of the ymm registers) are overlaid on registers xmm0-15.

[0088] General registers 425 - In the illustrated embodiment, there are sixteen 64-bit general registers that are used to address memory operands in conjunction with existing x86 addressing modes. These registers are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.

[0089] Scalar floating point stack register file (x87 stack) 445, on which the MMX packed integer flat register file 450 is aliased - in the illustrated embodiment, the x87 stack is an eight-element stack used to perform scalar floating point operations on 32 / 64 / 80-bit floating point data using the x87 instruction set extension. The MMX registers are used to perform operations on 64-bit packed integer data and are also used to hold operands for some operations performed between MMX and XMM registers.

[0090] Alternative embodiments of the present invention may use wider or narrower registers. In addition, alternative embodiments of the present invention may use more, fewer, or different register files and registers.

[0091] Exemplary Core Architectures, Processors, and Computer Architectures

[0092] Processor cores can be implemented in different ways, for different purposes, and in different processors. For example, implementations of such cores may include: 1) general-purpose in-order cores intended for general-purpose computing; 2) high-performance general-purpose out-of-order cores intended for general-purpose computing; 3) dedicated cores intended primarily for graphics and / or scientific (throughput) computing. Implementations of different processors may include: 1) a CPU including one or more general-purpose in-order cores intended for general-purpose computing and / or one or more general-purpose out-of-order cores intended for general-purpose computing; and 2) a coprocessor including one or more dedicated cores intended primarily for graphics and / or science (throughput). Such different processors lead to different computer system architectures, which may include: 1) a coprocessor on a separate chip from the CPU; 2) a coprocessor on a separate die in the same package as the CPU; 3) a coprocessor on the same die as the CPU (in which case such a coprocessor is sometimes referred to as dedicated logic, such as integrated graphics and / or scientific (throughput) logic, or referred to as a dedicated core); and 4) a system on a chip that may include the described CPU (sometimes referred to as an application core or application processor), the coprocessor described above, and additional functionality on the same die. An exemplary core architecture is described next, followed by a description of an exemplary processor and computer architecture. Detailed description herein is circuitry (units) including exemplary cores, processors, etc.

[0093] Exemplary Core Architecture

[0094] In-order and out-of-order core block diagram

[0095] Figure 5A is a block diagram illustrating both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue / execution pipeline according to embodiments of the present invention. Figure 5B is a block diagram illustrating both an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue / execution architecture core to be included in a processor in accordance with embodiments of the present invention. Figure 5A - The solid line boxes in B show the in-order pipeline and in-order core, while the optional addition of dashed line boxes shows the register renaming, out-of-order issue / execution pipeline and core. Given that the in-order aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described.

[0096] exist Figure 5A, processor pipeline 500 includes a fetch stage 502, a length decode stage 504, a decode stage 506, an allocation stage 508, a rename stage 510, a schedule (also known as dispatch or issue) stage 512, a register read / memory read stage 514, an execute stage 516, a write back / memory write stage 518, an exception handling stage 522, and a commit stage 524.

[0097] Figure 5B A processor core 590 is shown, which includes a front end unit 530 coupled to an execution engine unit 550, and both are coupled to a memory unit 570. The core 590 can be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As yet another option, the core 590 can be a special-purpose core, such as, for example, a network or communication core, a compression engine, a co-processor core, a general-purpose computing graphics processing unit (GPGPU) core, a graphics core, etc.

[0098] The front end unit 530 includes a branch prediction unit 532 coupled to an instruction cache unit 534, which is coupled to an instruction translation lookaside buffer (TLB) 536, which is coupled to an instruction fetch unit 538, which is coupled to a decode unit 540. The decode unit 540 (or decoder) can decode instructions and generate outputs as one or more micro-operations, microcode entry points, microinstructions, other instructions, or other control signals, which are decoded from, or otherwise reflect, or are derived from the original instructions. The decode unit 540 can be implemented using a variety of different mechanisms. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLA), microcode read-only memories (ROMs), and the like. In one embodiment, the core 590 includes a microcode ROM or another medium (e.g., in the decode unit 540 or otherwise within the front end unit 530) that stores microcode for certain macroinstructions. Decode unit 540 is coupled to rename / allocator unit 552 in execution engine unit 550 .

[0099] The execution engine unit 550 includes a rename / allocator unit 552 coupled to a retirement unit 554 and a set of one or more scheduler units 556. The scheduler units 556 represent any number of different schedulers, including reservation stations, central instruction windows, and the like. The scheduler units 556 are coupled to physical register file units 558. Each of the physical register file units 558 represents one or more physical register files, and different physical register files thereof store one or more different data types, such as scalar integers, scalar floating points, packed integers, packed floating points, vector integers, vector floating points, status (e.g., an instruction pointer that is the address of the next instruction to be executed), and the like. In one embodiment, the physical register file units 558 include vector register units and scalar register units. These register units may provide architectural vector registers, vector mask registers, and general purpose registers. The physical register file unit 558 is overlapped by the retirement unit 554 to illustrate various ways in which register renaming and out-of-order execution can be implemented (e.g., using a reorder buffer and a retirement register file; using a future stack, a history buffer, and a retirement register file; using a register map and a pool of registers; etc.). The retirement unit 554 and the physical register file unit 558 are coupled to an execution cluster 560. The execution cluster 560 includes a set of one or more execution units 562 and a set of one or more memory access units 564. The execution unit 562 can perform various operations (e.g., shifts, additions, subtractions, multiplications) and on various types of data (e.g., scalar floating point, packed integers, packed floating point, vector integers, vector floating point). While some embodiments may include multiple execution units dedicated to a particular function or set of functions, other embodiments may include multiple execution units or only one execution unit that all perform all functions. Scheduler unit 556, physical register file unit 558, and execution cluster 560 are shown as possibly plural because some embodiments create separate pipelines for certain types of data / operations (e.g., scalar integer pipelines, scalar floating point / packed integer / packed floating point / vector integer / vector floating point pipelines, and / or memory access pipelines, each with their own scheduler unit, physical register file unit, and / or execution cluster—and in the case of a separate memory access pipeline, certain embodiments where only the execution cluster of this pipeline has a memory access unit 564 are implemented). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue / execution, and the remainder in-order.

[0100] A set of memory access units 564 are coupled to a memory unit 570, which includes a data TLB unit 572 coupled to a data cache unit 574, which is coupled to a level 2 (L2) cache unit 576. In one exemplary embodiment, the memory access units 564 may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit 572 in the memory unit 570. The instruction cache unit 534 is further coupled to a level 2 (L2) cache unit 576 in the memory unit 570. The L2 cache unit 576 is coupled to one or more other levels of cache memory and ultimately to main memory.

[0101] By way of example, the exemplary register renaming, out-of-order issue / execution core architecture may implement the following pipeline 500: 1) instruction fetch 538 performs fetch and length decode stages 502 and 504; 2) decode unit 540 performs decode stage 506; 3) rename / allocator unit 552 performs allocation stage 508 and rename stage 510; 4) scheduler unit 556 performs schedule stage 512; 5) physical register file unit 558 and memory unit 570 perform register read / memory read stage 514; execution cluster 560 performs execute stage 516; 6) memory unit 570 and physical register file unit 558 perform write back / memory write stage 518; 7) various units may be involved in exception handling stage 522; and 8) retirement unit 554 and physical register file unit 558 perform commit stage 524.

[0102] Core 590 may support one or more instruction sets (e.g., the x86 instruction set (with some extensions that have been added with newer versions); the MIPS instruction set from MIPS Technologies of Sunnyvale, CA; the ARM instruction set from ARM Holdings of Sunnyvale, CA (with optional additional extensions such as NEON)), including the instructions described herein. In one embodiment, core 590 includes logic to support packed data instruction set extensions (e.g., AVX1, AVX2), thereby allowing operations used by many multimedia applications to be performed using packed data.

[0103] It should be understood that a core may support multithreading (executing two or more parallel sets of operations or threads) and may do so in a variety of ways, including time-segmented multithreading, simultaneous multithreading (where a single physical core provides a logical core for each of the threads, that physical core is performing simultaneous multithreading), or a combination thereof (e.g., time-segmented fetch and decode followed by simultaneous multithreading such as in Intel® Hyper-Threading Technology).

[0104] Although register renaming is described in the context of out-of-order execution, it should be understood that register renaming can be used in an in-order architecture. Although the illustrated embodiment of the processor also includes separate instruction and data cache memory units 534 / 574 and a shared L2 cache memory unit 576, alternative embodiments may have a single internal cache memory for both instructions and data, such as, for example, a level 1 (L1) internal cache memory, or multiple levels of internal cache memory. In some embodiments, the system may include a combination of internal cache memories and external cache memories external to the core and / or processor. Alternatively, all cache memories may be external to the core and / or processor.

[0105] Specific Exemplary In-Order Core Architecture

[0106] Fig. 6A -B shows a block diagram of a more specific exemplary in-order core architecture where the core will be one of several logic blocks in a chip (including other cores of the same type and / or different types). The logic block communicates with some fixed function logic, memory I / O interfaces, and other necessary I / O logic via a high bandwidth interconnect network (e.g., a ring network) depending on the application.

[0107] Fig. 6A is a block diagram of a single processor core along with its connection to an on-die interconnect network 602 and along with its local subset of a level 2 (L2) cache 604 in accordance with an embodiment of the present invention. In one embodiment, the instruction decoder 600 supports the x86 instruction set with a packed data instruction set extension. The L1 cache 606 allows low latency access to cache memory into the scalar and vector units. While in one embodiment (to simplify the design), the scalar unit 608 and the vector unit 610 use separate register sets (scalar registers 612 and vector registers 614, respectively), and data transferred between them is written to memory and then read back from the level 1 (L1) cache 606, alternative embodiments of the present invention may use different approaches (e.g., using a single register set or including a communication path that allows data to be transferred between the two register files without being written and read back).

[0108] The local subset of L2 cache memory 604 is part of the global L2 cache memory, which is divided into separate local subsets, one for each processor core. Each processor core has a direct access path to its own local subset of L2 cache memory 604. Data read by a processor core is stored in its L2 cache memory subset 604 and can be quickly accessed, in parallel with other processor cores accessing their own local L2 cache memory subsets. Data written by a processor core is stored in its own L2 cache memory subset 604 and is flushed from other subsets if necessary. The ring network ensures the consistency of shared data. The ring network is bidirectional to allow agents such as processor cores, L2 cache memories, and other logic blocks to communicate with each other within the chip. In some embodiments, each ring data-path is 1024-bit wide per direction.

[0109] Figure 6B According to an embodiment of the present invention Fig. 6A An expanded view of a portion of a processor core. Figure 6B The L1 data cache 606A portion of the L1 cache 604 is included, as well as more details about the vector unit 610 and vector registers 614. Specifically, the vector unit 610 is a 10-wide vector processing unit (VPU) (see 16-wide ALU 628) that executes one or more of integer, single-precision floating, and double-precision floating instructions. The VPU supports shuffling register inputs through a shuffle unit 620, value conversion through value conversion units 622A-B, and copying through a copy unit 624 on memory inputs.

[0110] Processor with integrated memory controller and graphics

[0111] Figure 7 is a block diagram of a processor 700 that may have more than one core, may have an integrated memory controller, and may have integrated graphics in accordance with an embodiment of the present invention. Figure 7 The solid line box in the figure shows a processor 700 with a single core 702A, a system agent 710, a set of one or more bus controller units 716, while the optional addition of the dashed line box shows an alternative processor 700 with multiple cores 702A-N, a set of one or more integrated memory controller units 714 in the system agent unit 710, and dedicated logic 708.

[0112] Thus, different implementations of processor 700 may include: 1) a CPU with dedicated logic 708 that is integrated graphics and / or scientific (throughput) logic (which may include one or more cores), and cores 702A-N that are one or more general purpose cores (e.g., general purpose in-order cores, general purpose out-of-order cores, combinations of the two cores); 2) a coprocessor with cores 702A-N that are a large number of dedicated cores intended primarily for graphics and / or science (throughput); and 3) a coprocessor with cores 702A-N that are a large number of general purpose in-order cores. Thus, processor 700 may be a general purpose processor, a coprocessor, or a dedicated processor, such as, for example, a network or communication processor, a compression engine, a graphics processor, a GPGPU (general purpose graphics processing unit), a high throughput many integrated core (MIC) coprocessor (including 30 or more cores), an embedded processor, and the like. The processor may be implemented on one or more chips. Processor 700 may be implemented on and / or be part of one or more substrates using any of a number of processing technologies (such as, for example, BiCMOS, CMOS, or NMOS).

[0113] The memory hierarchy includes one or more levels of cache memory within the cores 704A-N, a set or one or more of shared cache memory units 706, and external memory (not shown) coupled to a set of integrated memory controller units 714. The set of shared cache memory units 706 may include one or more mid-level cache memories, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache memory, a last level cache (LLC), and / or combinations thereof. Although in one embodiment, a ring-based interconnect unit 712 interconnects the integrated graphics logic 708, the set of shared cache memory units 706, and the system agent unit 710 / integrated memory controller unit 714, alternative embodiments may use any number of well-known techniques for interconnecting such units. In one embodiment, coherency between the one or more cache memory units 706 and the cores 702-AN is maintained.

[0114] In some embodiments, one or more of the cores 702A-N have multi-threaded capabilities. System agent 710 includes those components that coordinate and operate cores 702A-N. System agent unit 710 may include, for example, a power control unit (PCU) and a display unit. The PCU may be or include logic and components required to adjust the power state of the integrated graphics logic 708 and cores 702A-N. The display unit is used to drive one or more externally connected displays.

[0115] Cores 702A-N may be homogeneous or heterogeneous with respect to the architectural instruction set; that is, two or more of cores 702A-N may have the capability to execute the same instruction set, while other cores may have the capability to execute a different instruction set or only a subset of that instruction set.

[0116] Exemplary Computer Architecture

[0117] Figure 8-12 is a block diagram of an exemplary computer architecture. Other system designs and configurations known in the art for laptop computers, desktop computers, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, cellular phones, portable media players, handheld devices, and various other electronic devices are also suitable. In general, a wide variety of systems or electronic devices that can incorporate processors and / or other execution logic as disclosed herein are generally suitable.

[0118] Reference now Figure 8 , shown is a block diagram of a system 800 according to one embodiment of the present invention. The system 800 may include one or more processors 810, 815 coupled to a controller hub 820. In one embodiment, the controller hub 820 includes a graphics memory controller hub (GMCH) 890 and an input / output hub (IOH) 850 (which may be on separate chips); the GMCH 890 includes a memory and a graphics controller to which a memory 840 and a co-processor 845 are coupled; the IOH 850 couples an input / output (I / O) device 860 to the GMCH 890. Alternatively, one or both of the memory and the graphics controller are integrated within a processor (as described herein), the memory 840 and the co-processor 845 are coupled directly to the processor 810, and the controller hub 820 in a single chip with the IOH 850.

[0119] The optional nature of the additional processor 815 is Figure 8 Each processor 810 , 815 may include one or more of the processing cores described herein, and may be a version of processor 700 .

[0120] The memory 840 may be, for example, dynamic random access memory (DRAM), phase change memory (PCM), or a combination of the two. For at least one embodiment, the controller hub 820 communicates with the processors 810, 815 via a multi-drop bus such as a front side bus (FSB) or similar connection 895.

[0121] In one embodiment, the coprocessor 845 is a special purpose processor such as, for example, a high throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, etc. In one embodiment, the controller hub 820 may include an integrated graphics accelerator.

[0122] There can be a variety of differences between the physical resources 810, 815 with respect to the spectrum of specifications including architectural, microarchitectural, thermal, power consumption characteristics, and the like.

[0123] In one embodiment, the processor 810 executes instructions that control general types of data processing operations. Embedded within the instructions may be coprocessor instructions. The processor 810 recognizes these coprocessor instructions as being of a type that should be executed by the attached coprocessor 845. Therefore, the processor 810 issues these coprocessor instructions (or control signals representing coprocessor instructions) to the coprocessor 845 on a coprocessor bus or other interconnect. One or more coprocessors 845 accept and execute the received coprocessor instructions.

[0124] Reference now Fig. 9 , shown is a block diagram of a first more specific exemplary system 900 according to an embodiment of the present invention. Fig. 9 As shown in FIG. 1 , multiprocessor system 900 is a point-to-point interconnect system and includes a first processor 970 and a second processor 980 coupled via a point-to-point interconnect 950. Each of processors 970 and 980 may be a version of processor 700. In one embodiment of the present invention, processors 970 and 980 are processors 810 and 815, respectively, and coprocessor 938 is coprocessor 845. In another embodiment, processors 970 and 980 are processor 810 and coprocessor 845, respectively.

[0125] Processors 970 and 980 are shown to include integrated memory controller (IMC) units 972 and 982, respectively. Processor 970 also includes point-to-point (PP) interfaces 976 and 978 as part of its bus controller unit; similarly, second processor 980 includes PP interfaces 986 and 988. Using PP interface circuits 978, 988, processors 970, 980 can exchange information via point-to-point (PP) interface 950. Fig. 9 As shown in FIG. 8 , IMCs 972 and 982 couple the processors to respective memories (namely, memory 932 and memory 934 ), which may be portions of main memory locally attached to the respective processors.

[0126] Using point-to-point interface circuits 976, 994, 986, 998, processors 970, 980 may each exchange information with a chipset 990 via respective PP interfaces 952, 954. Chipset 990 may optionally exchange information with a co-processor 938 via a high performance interface 992. In one embodiment, co-processor 938 is a special purpose processor such as, for example, a high throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, and the like.

[0127] A shared cache memory (not shown) may be included in either processor or external to both processors, again connected to the processors via the PP interconnect, such that if the processors are placed in a low power mode, local cache memory information for either or both processors may be stored in the shared cache memory.

[0128] Chipset 990 may be coupled to first bus 916 via interface 996. In one embodiment, first bus 916 may be a Peripheral Component Interconnect (PCI) bus, or a bus such as PCI Express or another I / O interconnect bus, although the scope of the invention is not so limited.

[0129] like Fig. 9 As shown in , various I / O devices 914 may be coupled to the first bus 916 along with a bus bridge 918 that couples the first bus 916 to a second bus 920. In one embodiment, one or more additional processors 915 such as a co-processor, a high throughput MIC processor, a GPGPU, an accelerator (such as, for example, a graphics accelerator or a digital signal processing (DSP) unit), a field programmable gate array, or any other processor are coupled to the first bus 916. In one embodiment, the second bus 920 may be a low pin count (LPC) bus. Various devices may be coupled to the second bus 920 including, for example, a keyboard and / or mouse 922, communication devices 927, and a storage unit 928 such as a hard drive or other mass storage device, which may include instructions / code and data 930 (in one embodiment). Further, an audio I / O 924 may be coupled to the second bus 916. Note that other architectures are possible. For example, instead of Fig. 9 Instead of a point-to-point architecture, the system may implement a multi-point bus or another such architecture.

[0130] Reference now Fig.10 , shown is a block diagram of a second more specific exemplary system 1000 according to an embodiment of the present invention. Fig. 9 and 10 Like elements in FIG. 1 are marked with like reference numerals, and Fig. 9 Some aspects of Fig.10is omitted to avoid Fig.10 Other aspects of the .

[0131] Fig.10 It is shown that processors 970, 980 may respectively include integrated memory and I / O control logic ("CL") 1072 and 1082. Thus, CL 1072, 1082 includes an integrated memory controller unit and includes I / O control logic. Fig.10 It is shown that not only the memory 932, 934 is coupled to the CL 972, 982, but also the I / O device 1014 is coupled to the control logic 972, 982. The legacy I / O device 1015 is coupled to the chipset 990.

[0132] Reference now Fig.11 , shown is a block diagram of a SoC 1100 according to an embodiment of the present invention. Figure 7 Similar elements in the FIGURE are labeled with similar reference numerals. Likewise, dashed boxes are optional features on more advanced SoCs. Fig.11 , the interconnect unit 1102 is coupled to: an application processor 1110, which includes a set of one or more cores 702A-N, a cache unit 704A-N, and a shared cache memory unit 706; a system agent unit 710; a bus controller unit 716; an integrated memory controller unit 714; a set or one or more of co-processors 1120, which may include integrated graphics logic, an image processor, an audio processor, and a video processor; a static random access memory (SRAM) unit 1130; a direct memory access (DMA) unit 1132; and a display unit 1140 for coupling to one or more external displays. In one embodiment, the co-processors 1120 include special-purpose processors such as, for example, network or communication processors, compression engines, GPGPUs, high-throughput MIC processors, embedded processors, and the like.

[0133] Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementation means. Embodiments of the present invention may be implemented as program code or a computer program executed on a programmable system, the programmable system comprising at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0134] Such as Figure 8The program code of code 930 shown in can be applied to input instructions to perform the functions described herein and generate output information. The output information can be applied to one or more output devices in a known manner. For the purpose of this application, the processing system includes any system with a processor (such as, for example: a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor).

[0135] The program code can be implemented in a high-level procedural or object-oriented programming language to communicate with the processing system. If desired, the program code can also be implemented in assembly or machine language. In fact, the mechanism described herein is not limited to the scope of any specific programming language. In any case, the language can be a compiled or interpreted language.

[0136] One or more aspects of at least one embodiment may be implemented by representative instructions stored on a machine-readable medium, which represent various logic within a processor, which when read by a machine causes the machine to make logic for performing the techniques described herein. Such representations (known as "IP cores") may be stored on a tangible, machine-readable medium and supplied to various customers or manufacturing facilities to load into a fabrication machine that actually makes the logic or processor.

[0137] Such machine-readable storage media may include, without limitation, a non-transitory, tangible arrangement of an article made or formed by a machine or device, including storage media (such as hard disks, any other type of disk including floppy disks, optical disks, compact disk-read only memory (CD-ROM), compact disk-rewritable (CD-RW), and magneto-optical disks), semiconductor devices (such as read-only memory (ROM), random access memory (RAM) such as dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read-only memory (EPROM), flash memory, electrically erasable programmable read-only memory (EEPROM), phase change memory (PCM), magnetic or optical cards, or any other type of medium suitable for storing electronic instructions).

[0138] Therefore, embodiments of the present invention also include non-transitory, tangible machine-readable media containing instructions or containing design data, such as hardware description language (HDL), which defines the structures, circuits, devices, processors and / or system features described herein. Such embodiments may also be referred to as program products.

[0139] Emulation (including binary translation, code morphing, etc.)

[0140] In some cases, an instruction converter may be used to convert instructions from a source instruction set to a target instruction set. For example, the instruction converter may translate (e.g., using static binary translation, dynamic binary translation including dynamic compilation), deform, emulate, or otherwise convert instructions to one or more other instructions to be processed by the core. The instruction converter is implemented in software, hardware, firmware, or a combination thereof. The instruction converter may be on the processor, off the processor, or partially on the processor and partially off the processor.

[0141] Fig.12 1 is a block diagram that compares the use of a software instruction converter to convert binary instructions in a source instruction set into binary instructions in a target instruction set according to an embodiment of the present invention. In the illustrated embodiment, the instruction converter is a software instruction converter, although alternatively the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof. Fig.12 Using a first compiler 1204, a program in a high-level language 1202 is shown to be compiled to generate a first binary code (e.g., x86) 1206 that can be natively executed by a processor 1216 with at least one first instruction set core. In some embodiments, the processor 1216 with at least one first instruction set core represents any processor that can perform substantially the same functions as an Intel processor with at least one x86 instruction set core by compatibly executing or otherwise processing (1) a substantial portion of the instruction set of the Intel x86 instruction set core, or (2) an object code version of an application or other software that is intended to run on an Intel processor with at least one x86 instruction set core, so as to achieve substantially the same results as an Intel processor with at least one x86 instruction set core. The first compiler 1204 represents a compiler that is operable to generate binary code 1206 (e.g., object code) of a first instruction set that can be executed on a processor 1216 with at least one first instruction set core with or without additional linking processing. Similarly, Fig.12It is shown that using an alternative instruction set compiler 1208, a program in a high-level language 1202 can be compiled to generate an alternative instruction set binary code 1210, which can be natively executed by a processor 1214 without at least one first instruction set core (e.g., a processor with a core that executes the MIPS instruction set of MIPS Technologies of Sunnyvale, CA and / or executes the ARM instruction set of ARM Holdings of Sunnyvale, CA). An instruction converter 1212 is used to convert the first binary code 1206 into code that can be natively executed by a processor 1214 without a first instruction set core. This converted code is unlikely to be the same as the alternative instruction set binary code 1210 because an instruction converter that can do so is difficult to make; however, the converted code will perform general operations and be composed of instructions from the alternative instruction set. Therefore, the instruction converter 1212 represents software, firmware, hardware, or a combination thereof that allows a processor or another electronic device that does not have a first instruction set processor or core to execute the first binary code 1206 through simulation, emulation, or any other process.

[0142] The present invention also provides the following technical solutions:

[0143] 1. A method comprising:

[0144] decoding, by a decode circuit, an instruction having fields for first and second packed data source operands, and a packed data destination operand;

[0145] The decoded instruction is executed by the execution circuitry through the following operations:

[0146] multiplying selected data values ​​from a plurality of packed data element positions in the first and second packed data source operands to generate a plurality of first result values;

[0147] summing the plurality of first result values ​​to generate one or more second result values;

[0148] negating the one or more second result values ​​to generate one or more third result values;

[0149] accumulating the one or more third result values ​​with one or more data values ​​from the destination operand to generate one or more fourth result values; and

[0150] The one or more fourth result values ​​are stored in one or more packed data element positions in the destination operand.

[0151] 2. The method of claim 1, wherein executing the decoded instruction by the decoding circuit further comprises multiplexing data values ​​from the plurality of packed data element positions in the first and second packed data source operands to at least one multiplier circuit.

[0152] 3. A method as described in technical solution 2, wherein the data values ​​from the multiple packed data element positions in the first and second packed data source operands are multiplexed to the at least one multiplier circuit based on the data values ​​sharing the same packed data element position in the first and second packed data source operands.

[0153] 4. A method as described in Technical Solution 1, wherein the one or more second result values ​​are generated by one or more adder networks.

[0154] 5. The method of claim 1 , wherein storing the one or more third result values ​​comprises storing the result value in an upper half of the packed data destination operand and storing the result value in a lower half of the packed data destination operand.

[0155] 6. The method of claim 1, wherein multiplying the selected data values ​​comprises:

[0156] performing operations S1H*S2H, S1G*S2G, S1F*S2F, and S1E*S2E and operations S1D*S2D, S1C*S2C, S1B*S2B, and S1A*S2A to generate the plurality of first result values,

[0157] wherein S1 identifies the first packed data source operand, S2 identifies the second packed data source operand, and A, B, C, D, E, F, G, and H identify the packed data element positions ordered from lowest to highest data element position in the first and second packed data source operands.

[0158] 7. A method as described in Technical Solution 6, wherein summing the multiple first result values ​​includes performing operations (S1H*S2H)+(S1G*S2G)+(S1F*S2F)+(S1E*S2E) and performing operations (S1H*S2H)+(S1G*S2G)+(S1B*S2B)+(S1A*S2A) to generate the one or more second result values.

[0159] 8. The method as described in technical solution 1 further includes, in response to detecting that a value of the one or more third result values ​​is higher than a threshold, storing a maximum value in a corresponding position of the destination operand.

[0160] 9. A device comprising:

[0161] a decoder for decoding an instruction having fields for first and second packed data source operands, and a packed data destination operand; and

[0162] An execution circuit configured to execute the decoded instruction to:

[0163] multiplying selected data values ​​from a plurality of packed data element positions in the first and second packed data source operands to generate a plurality of first result values;

[0164] summing the plurality of first result values ​​to generate one or more second result values;

[0165] negating the one or more second result values ​​to generate one or more third result values;

[0166] accumulating the one or more third result values ​​with one or more data values ​​from the destination operand to generate one or more fourth result values; and

[0167] The one or more fourth result values ​​are stored in one or more packed data element positions in the destination operand.

[0168] 10. An apparatus as described in technical solution 9, wherein the instruction to be decoded by the decoding circuit further includes multiplexing data values ​​from the multiple packed data element positions in the first and second packed data source operands to at least one multiplier circuit.

[0169] 11. An apparatus as described in technical solution 10, wherein based on data values ​​sharing the same packed data element position in the first and second packed data source operands, the data values ​​from the multiple packed data element positions in the first and second packed data source operands are multiplexed to the at least one multiplier circuit.

[0170] 12. A device as described in Technical Solution 9, wherein the one or more second result values ​​are generated by one or more adder networks.

[0171] 13. A device as described in technical solution 9, wherein storing the one or more third result values ​​includes storing the result value in the upper half of the packed data destination operand and storing the result value in the lower half of the packed data destination operand.

[0172] 14. The device of claim 9, wherein multiplying the selected data values ​​comprises:

[0173] performing operations S1H*S2H, S1G*S2G, S1F*S2F, and S1E*S2E and operations S1D*S2D, S1C*S2C, S1B*S2B, and S1A*S2A to generate the plurality of first result values,

[0174] wherein S1 identifies the first packed data source operand, S2 identifies the second packed data source operand, and A, B, C, D, E, F, G, and H identify the packed data element positions ordered from lowest to highest data element position in the first and second packed data source operands.

[0175] 15. A device as described in technical solution 14, wherein summing the multiple first result values ​​includes performing operations (S1H*S2H)+(S1G*S2G)+(S1F*S2F)+(S1E*S2E) and performing operations (S1H*S2H)+(S1G*S2G)+(S1B*S2B)+(S1A*S2A) to generate the one or more second result values.

[0176] 16. The device as described in technical solution 9 further includes storing a maximum value in a corresponding position of the destination operand in response to detecting that a value of the one or more third result values ​​is higher than a threshold.

[0177] 17. A non-transitory machine-readable medium storing instructions, which, when executed by a processor, cause the processor to perform operations comprising:

[0178] decoding an instruction having fields for first and second packed data source operands and a packed data destination operand, and

[0179] The decoded instructions are executed by the execution circuitry to:

[0180] multiplying selected data values ​​from a plurality of packed data element positions in the first and second packed data source operands to generate a plurality of first result values;

[0181] summing the plurality of first result values ​​to generate one or more second result values;

[0182] negating the one or more second result values ​​to generate one or more third result values;

[0183] accumulating the one or more third result values ​​with one or more data values ​​from the destination operand to generate one or more fourth result values; and

[0184] The one or more fourth result values ​​are stored in one or more packed data element positions in the destination operand.

[0185] 18. A non-transitory machine-readable medium as described in technical solution 17, wherein the instruction to execute the decoding by the decoding circuit further includes multiplexing data values ​​from the multiple packed data element positions in the first and second packed data source operands to at least one multiplier circuit.

[0186] 19. A non-transitory machine-readable medium as described in technical solution 18, wherein based on the data values ​​sharing the same packed data element positions in the first and second packed data source operands, the data values ​​from the multiple packed data element positions in the first and second packed data source operands are multiplexed to the at least one multiplier circuit.

[0187] 20. A non-transitory machine-readable medium as described in technical solution 17, wherein the one or more second result values ​​are generated by one or more adder networks.

[0188] 21. A non-transitory machine-readable medium as described in technical solution 17, wherein storing the one or more fourth result values ​​includes storing the result value in the upper half of the packed data destination operand and storing the result value in the lower half of the packed data destination operand.

[0189] 22. The non-transitory machine-readable medium of claim 17, wherein multiplying the selected data values ​​comprises:

[0190] performing operations S1H*S2H, S1G*S2G, S1F*S2F, and S1E*S2E and operations S1D*S2D, S1C*S2C, S1B*S2B, and S1A*S2A to generate the plurality of first result values,

[0191] wherein S1 identifies the first packed data source operand, S2 identifies the second packed data source operand, and A, B, C, D, E, F, G, and H identify the packed data element positions ordered from lowest to highest data element position in the first and second packed data source operands.

[0192] 23. A non-transitory machine-readable medium as described in technical solution 22, wherein summing the multiple first result values ​​includes performing operations (S1H*S2H)+(S1G*S2G)+(S1F*S2F)+(S1E*S2E) and performing operations (S1H*S2H)+(S1G*S2G)+(S1B*S2B)+(S1A*S2A) to generate the one or more second result values.

[0193] 24. The non-transitory machine-readable medium as described in technical solution 17 further includes storing a maximum value in a corresponding position of the destination operand in response to detecting that a value of the one or more third result values ​​is higher than a threshold.

Claims

1. A method for executing an instruction, the method comprising: decoding, by a decode circuit, an instruction having fields for first and second packed data source operands, and a packed data destination operand; The decoded instruction is executed by the execution circuitry through the following operations: multiplying selected data values ​​from a plurality of packed data element positions in the first and second packed data source operands to generate a plurality of first result values; summing the plurality of first result values ​​to generate one or more second result values; negating the one or more second result values ​​to generate one or more third result values; Accumulating the one or more third result values ​​to generate one or more fourth result values; as well as The one or more fourth result values ​​are stored in one or more packed data element positions in the destination operand.

2. The method of claim 1 , wherein executing the decoded instruction by the execution circuitry further comprises multiplexing data values ​​from the plurality of packed data element positions in the first and second packed data source operands to at least one multiplier circuit.

3. The method of claim 2 , wherein the data values ​​from the plurality of packed data element positions in the first and second packed data source operands are multiplexed to the at least one multiplier circuit based on data values ​​sharing the same packed data element position in the first and second packed data source operands. The method of claim 1 , wherein the one or more second result values ​​are generated by one or more adder networks.

5. The method of claim 1, wherein storing the one or more third result values ​​comprises storing a result value in an upper half of the packed data destination operand and storing a result value in a lower half of the packed data destination operand.

6. The method of claim 1, wherein said multiplying said selected data values ​​comprises: performing operations S1H*S2H, S1G*S2G, S1F*S2F, and S1E*S2E and operations S1D*S2D, S1C*S2C, S1B*S2B, and S1A*S2A to generate the plurality of first result values, wherein S1 identifies the first packed data source operand, S2 identifies the second packed data source operand, and A, B, C, D, E, F, G, and H identify the packed data element positions ordered from lowest to highest data element position in the first and second packed data source operands.

7. The method of claim 6, wherein summing the plurality of first result values ​​comprises performing an operation (S1H*S2H)+(S1G*S2G)+(S1F*S2F)+(S1E*S2E) and performing an operation (S1H*S2H)+(S1G*S2G)+(S1B*S2B)+(S1A*S2A) to generate the one or more second result values. 8 . The method of claim 1 , further comprising, in response to detecting that a value of the one or more third result values ​​is above a threshold, storing a maximum value in a corresponding position of the destination operand.

9. A device for executing an instruction, comprising: a decoder to decode an instruction having fields for first and second packed data source operands, and a packed data destination operand; as well as An execution circuit configured to execute the decoded instruction to: multiplying selected data values ​​from a plurality of packed data element positions in the first and second packed data source operands to generate a plurality of first result values; summing the plurality of first result values ​​to generate one or more second result values; negating the one or more second result values ​​to generate one or more third result values; Accumulating the one or more third result values ​​to generate one or more fourth result values; as well as The one or more fourth result values ​​are stored in one or more packed data element positions in the destination operand.

10. The apparatus of claim 9, wherein executing the decoded instruction by the execution circuitry further comprises multiplexing data values ​​from the plurality of packed data element positions in the first and second packed data source operands to at least one multiplier circuit.

11. The apparatus of claim 10 , wherein the data values ​​from the plurality of packed data element positions in the first and second packed data source operands are multiplexed to the at least one multiplier circuit based on data values ​​sharing the same packed data element position in the first and second packed data source operands.

12. The apparatus of claim 9, wherein the one or more second result values ​​are generated by one or more adder networks.

13. The apparatus of claim 9, wherein storing the one or more third result values ​​comprises storing a result value in an upper half of the packed data destination operand and storing a result value in a lower half of the packed data destination operand.

14. The apparatus of claim 9, wherein said multiplying said selected data values ​​comprises: performing operations S1H*S2H, S1G*S2G, S1F*S2F, and S1E*S2E and operations S1D*S2D, S1C*S2C, S1B*S2B, and S1A*S2A to generate the plurality of first result values, wherein S1 identifies the first packed data source operand, S2 identifies the second packed data source operand, and A, B, C, D, E, F, G, and H identify the packed data element positions ordered from lowest to highest data element position in the first and second packed data source operands.

15. The apparatus of claim 9, wherein summing the plurality of first result values ​​comprises performing an operation (S1H*S2H)+(S1G*S2G)+(S1F*S2F)+(S1E*S2E) and performing an operation (S1H*S2H)+(S1G*S2G)+(S1B*S2B)+(S1A*S2A) to generate the one or more second result values.

16. The apparatus of claim 9, further comprising storing a maximum value in a corresponding position of the destination operand in response to detecting that a value of the one or more third result values ​​is above a threshold.

17. A machine-readable medium comprising codes, which when executed cause a machine to perform the method of any one of claims 1 to 8.

18. A device for executing an instruction, the device comprising: means for decoding an instruction having fields for first and second packed data source operands, and a packed data destination operand; Components for executing decoded instructions, including: means for multiplying selected data values ​​from a plurality of packed data element positions in the first and second packed data source operands to generate a plurality of first result values; means for summing the plurality of first result values ​​to generate one or more second result values; means for negating the one or more second result values ​​to generate one or more third result values; means for accumulating the one or more third result values ​​to generate one or more fourth result values; and Means for storing the one or more fourth result values ​​in one or more packed data element locations in the destination operand.

19. The apparatus of claim 18, wherein the means for executing the decoded instructions further comprises: Means for multiplexing data values ​​from the plurality of packed data element positions in the first and second packed data source operands to at least one multiplier circuit.

20. The apparatus of claim 19, wherein the data values ​​from the plurality of packed data element positions in the first and second packed data source operands are multiplexed to the at least one multiplier circuit based on data values ​​sharing the same packed data element position in the first and second packed data source operands.

21. The apparatus of claim 18, wherein the one or more second result values ​​are generated by one or more adder networks.

22. The apparatus of claim 18, wherein storing the one or more third result values ​​comprises storing a result value in an upper half of the packed data destination operand and storing a result value in a lower half of the packed data destination operand.

23. The apparatus of claim 18, wherein the means for multiplying the selected data values ​​comprises: means for performing the following operations: performing the operations S1H*S2H, S1G*S2G, S1F*S2F and S1E*S2E and the operations S1D*S2D, S1C*S2C, S1B*S2B and S1A*S2A to generate the plurality of first result values, wherein S1 identifies the first packed data source operand, S2 identifies the second packed data source operand, and A, B, C, D, E, F, G, and H identify the packed data element positions ordered from lowest to highest data element position in the first and second packed data source operands.

24. The apparatus of claim 23, wherein summing the plurality of first result values ​​comprises performing an operation (S1H*S2H)+(S1G*S2G)+(S1F*S2F)+(S1E*S2E) and performing an operation (S1H*S2H)+(S1G*S2G)+(S1B*S2B)+(S1A*S2A) to generate the one or more second result values.

25. The apparatus of claim 18, further comprising means for storing a maximum value in a corresponding position of the destination operand in response to detecting that a value of the one or more third result values ​​is above a threshold.

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