A fault-tolerant adaptive routing method based on ant colony algorithm

An ant colony algorithm and self-adaptive technology, applied in computing, computing models, instruments, etc., can solve the problems of reducing delay, routing table storage overhead, singleness, etc., to achieve the effect of reducing data transmission delay and realizing network load

CN109660456BActive Publication Date: 2021-04-02SOUTHEAST UNIV
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Publication Date
2021-04-02

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Abstract

The invention discloses a fault-tolerant self-adaptive routing method based on ant colony algorithm, which includes: marking the position of each node in a two-dimensional network and setting the routing table; detecting a faulty node, if there is a faulty node, calculating the number of nodes adjacent to the faulty node The fault value of the node and the effective buffer length; if there is no faulty node, use the adaptive routing algorithm to find and obtain one or more routing paths to be selected; select an optimal routing path from the routing paths to be selected according to the evaluation scale, Update the pheromone routing table according to the ant colony routing algorithm; check whether the destination node is reached, and if so, end the routing; otherwise, judge whether there is a deadlock in the routing path, and end if there is a deadlock; otherwise, re-detect the faulty node. Based on the ant colony algorithm, the path selection mechanism in the fault-tolerant adaptive routing algorithm is optimized and the pheromone routing table is updated. In the case of faulty nodes, the data transmission delay of the entire network on chip is reduced, and the network load is balanced.
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Description

technical field

[0001] The invention relates to the technical field of routing of on-chip networks, in particular to a fault-tolerant adaptive routing method based on an ant colony algorithm. Background technique

[0002] With the development of semiconductor technology, chips are gradually developing from single-core to multi-core and even many-core, which requires more and more attention to the interconnection of the system when designing the chip architecture. However, the current mainstream bus-based interconnection method can no longer meet the needs of the growing chip scale. In response to this situation, researchers have proposed a chip interconnection method based on a network on chip. In an on-chip network, if the network scale is small, deterministic routing is generally used because it is simple to implement and can meet performance requirements; as the network scale increases, adaptive routing algorithms are used because deterministic routing has a large It may...

Examples

Embodiment

[0037] Such as figure 1 As shown, a fault-tolerant adaptive routing method based on ant colony algorithm includes the following steps:

[0038] Step 1 Initialize the routing table:

[0039] In a two-dimensional network, a two-dimensional coordinate system is used to mark the position of each node. In addition to the conventional storage entry and exit nodes, the routing table also needs to add pheromones, FPDs and FVs.

[0040] Among them, pheromone is used in ant colony algorithm; FPD is used to calculate EBL; FV is used to record whether the distance between the node and the fault node has an impact on pheromone.

[0041] Step 2 Check the faulty node:

[0042] Start the self-test circuit in the chip. Generally, the chip contains a self-test circuit, and the self-test circuit is used to check whether there is a faulty node. If yes, mark these faulty nodes and go to step three; if not, go to step four.

[0043] Step 3 Start the fault reminder mechanism:

[0044] Start the...