Memory device including circuit for detecting word line defects and method of operating the same

Abstract

A memory device including a circuit for detecting word line defects and an operation method thereof are provided. The memory device includes: a memory cell array including a first memory cell disposed on a substrate and a second memory cell located above the first memory cell; a first word line connected to the first memory cell and a second word line connected to the second memory cell, the second word line being disposed above the first word line; and a word line defect detection circuit configured to monitor the number of pulses of a pump clock signal when a first voltage is applied to the first word line to detect a defect of the first word line. A voltage generator is configured to apply a second voltage different from the first voltage to the second word line to program the second memory cell when the number of pulses of the pump clock signal is less than a reference value.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority benefit of Korean Patent Application No. 10-2017-0140000 filed on October 26, 2017 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a memory device including a circuit for detecting a word line defect and an operating method thereof. Background Art

[0004] A storage device is a storage device that can store data and can read the data when needed. Storage devices can be roughly classified into non-volatile memory (NVM), in which the stored data does not disappear even when power is not supplied, and volatile memory (VM), in which the stored data disappears when power is not supplied.

[0005] In order to control a plurality of memory cells provided in a memory device, various wirings may be provided and used inside the memory device. Examples of these wirings may include bit lines and word lines connected to the memory cells.

[0006] As the size of storage devices becomes increasingly smaller, the spacing between wirings arranged therein becomes narrower. Therefore, various defects may occur, such as bridging defects that electrically connect wirings that are insulated from each other. Since these defects lead to deterioration of the operating performance of the storage device, research on improving the defects is needed. Summary of the invention

[0007] An aspect of the present disclosure provides a storage device having improved data storage reliability and operation performance.

[0008] Another aspect of the present disclosure provides a method for operating a storage device having improved data storage reliability and operation performance.

[0009] According to some aspects of the present disclosure, a storage device is provided. The storage device includes: a storage cell array, the storage cell array includes a first storage cell arranged on a substrate and a second storage cell above the first storage cell; a first word line connected to the first storage cell and a second word line connected to the second storage cell, the second word line being arranged above the first word line; a clock generator, the clock generator being configured to generate a pumping clock signal when a pumping voltage is lower than a reference pumping voltage; a voltage generator, the voltage generator being configured to generate the pumping voltage in response to the pumping clock signal, and to generate a first voltage and a second voltage different from the first voltage based on the pumping voltage; and a word line defect detection circuit, the word line defect detection circuit being configured to monitor the number of pulses of the pumping clock signal when the first voltage is applied to the first word line to detect a defect of the first word line. The voltage generator is configured to apply the second voltage to the second word line to program the second storage cell when the number of pulses of the pumping clock signal is less than a reference value.

[0010] According to some aspects of the present disclosure, a method for operating a storage device is provided. The method for operating a storage device includes: providing a storage cell array, the storage cell array including a first storage cell disposed on a substrate, a first word line connected to the first storage cell, a second storage cell disposed above the first storage cell, and a second word line disposed above the first word line and connected to the second storage cell; generating a pumping clock signal when a pumping voltage is lower than a reference pumping voltage; generating a pumping voltage in response to the pumping clock signal, generating a first voltage based on the pumping voltage and generating a second voltage different from the first voltage; detecting a defect of the first word line by monitoring a first number of pulses of the pumping clock signal when the first voltage is applied to the first word line; and programming the second storage cell by applying the second voltage to the second word line when the first number of pulses of the pumping clock signal is less than a first reference value.

[0011] According to some aspects of the present disclosure, a storage device is provided. The storage device includes: a storage cell array, the storage cell array includes a first storage cell arranged on a substrate, a second storage cell arranged above the first storage cell, and a third storage cell arranged above the second storage cell; a first word line connected to the first storage cell, a second word line connected to the second storage cell, and a third word line connected to the third storage cell, the second word line is arranged above the first word line, and the third word line is arranged above the second word line; a clock generator, the clock generator is configured to generate a pumping clock signal when the pumping voltage is lower than a reference pumping voltage; a voltage generator, the voltage generator is configured to generate the pumping voltage in response to the pumping clock signal, and generate a first programming voltage and a second programming voltage different from the first programming voltage based on the pumping voltage; a word line defect detection circuit, the word line defect detection circuit is configured to monitor a first number of pulses of the pumping clock signal when the first programming voltage is applied to the first word line to detect a defect of the first word line. When the first number of pulses of the pump clock signal is less than a first reference value, the word line defect detection circuit is configured to monitor a second number of pulses of the pump clock signal when the first programming voltage is applied to the second word line to detect a defect of the second word line. The voltage generator is configured to apply the second programming voltage to the third word line to program the third memory cell when the second number of pulses of the pump clock signal is less than a first reference value. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other aspects and features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0013] Figure 1 is a block diagram illustrating a non-volatile storage system according to some embodiments;

[0014] Figure 2 It is used to illustrate the Figure 1 A block diagram of a non-volatile storage device;

[0015] Figure 3 It is used to illustrate the Figure 2 Block diagram of a voltage generator;

[0016] Figure 4 It is used to illustrate the Figure 2 and Figure 3 A diagram of a pump clock signal;

[0017] Figure 5 It is used to illustrate the Figure 2A block diagram of a pass-fail determination circuit;

[0018] Figure 6 and Figure 7 It is used to illustrate Figure 2 A diagram of a memory cell array;

[0019] Figure 8 and Fig. 9 is a diagram for explaining a word line defect detection operation of a nonvolatile memory device according to some embodiments;

[0020] Fig.10 is a flow chart illustrating the operation of a non-volatile storage device according to some embodiments;

[0021] Fig.11 and Fig.12 It is used to specifically describe the Fig.10 A diagram of the operation of a non-volatile memory device shown in;

[0022] Fig.13 is a flowchart for illustrating the operation of a nonvolatile memory device according to some embodiments;

[0023] Fig.14 and Fig.15 It is used to specifically describe the Fig.13 A diagram of the operation of a non-volatile memory device shown in;

[0024] Fig.16 is a flowchart for illustrating the operation of a nonvolatile memory device according to some embodiments;

[0025] Fig.17 and Fig.18 It is used to specifically describe the Fig.16 A diagram of the operation of a non-volatile memory device shown in;

[0026] Fig.19 It is used to illustrate the Fig.16 A diagram showing the effect of the operation of a nonvolatile memory device. DETAILED DESCRIPTION

[0027] By referring to the following detailed description of the preferred embodiments and the accompanying drawings, it is easier to understand the advantages and features of the present disclosure and the methods for achieving them. However, the present disclosure can be implemented in many different forms and should not be interpreted as being limited to the embodiments set forth herein. In the accompanying drawings, the thickness of layers and regions is exaggerated for clarity.

[0028] Figure 1 is a block diagram illustrating a non-volatile storage system according to some embodiments.

[0029] refer to Figure 1 , the nonvolatile memory system includes a memory controller 200 and a nonvolatile memory device 100 . Figure 1 Examples of the non-volatile memory system shown may include flash-based data storage media such as memory cards, USB memories, and SSDs (Solid State Drives), but are not limited to these examples.

[0030] The memory controller 200 may be connected to a host (HOST) and a nonvolatile memory device 100. As shown, the memory controller 200 may be configured to access the nonvolatile memory device 100 in response to a request from the host (HOST). The memory controller 200 may be configured to provide an interface between the nonvolatile memory device 100 and the host (HOST). In addition, the memory controller 200 may be configured to drive firmware for controlling the nonvolatile memory device 100.

[0031] The memory controller 200 may control the operation of the nonvolatile memory device 100. Specifically, the memory controller 200 may provide a command (CMD), an address (ADDR), a control signal (CTRL), and data (DATA) along input / output lines connected to the nonvolatile memory device 100.

[0032] The control signal (CTRL) provided by the memory controller 200 to the nonvolatile memory device 100 may include, for example but not limited to, chip enable (CE), light enable (WE), read enable (RE), and the like.

[0033] The memory controller 200 may further include an error correction code (ECC) circuit that corrects an error bit of the nonvolatile memory device 100. The ECC circuit may correct an error bit included in the data. However, the present disclosure is not limited thereto, and the ECC circuit may be provided as part of the nonvolatile memory device 100 as needed.

[0034] Each of the memory controller 200 and the nonvolatile memory device 100 may be provided as one chip, one package, one module, etc. For example, the memory controller 200 and the nonvolatile memory device 100 may be installed using packages such as a stacked package (PoP), a ball grid array (BGA), a chip scale package (CSP), a plastic tape wiring chip carrier (PLCC), a plastic dual in-line package (PDIP), a die in waffle pack, a die in wafer form, a chip on board (COB), a ceramic dual in-line package (CERDIP), a plastic metric quad flat package (MQFP), a thin quad flat package (TQFP), a small outline package (SOIC), a reduced small outline integrated package (SSOP), a thin small outline package (TSOP), a thin quad flat package (TQFP), a system-in-package (SIP), a multi-chip package (MCP), a wafer-level manufacturing package (WFP), and a wafer-level processing stack package (WSP).

[0035] In the following, reference will be made to Figure 2 The configuration of the nonvolatile memory device 100 is described in more detail.

[0036] Figure 2 It is used to illustrate the Figure 1 A block diagram of a non-volatile memory device.

[0037] refer to Figure 2 , the nonvolatile memory device 100 includes a word line defect detection circuit 120 , an address decoder 130 , an input / output circuit 140 , a control logic 150 , a memory cell array 160 , and a voltage generation unit 170 .

[0038] The non-volatile memory device 100 may include, but is not limited to, for example, a NAND flash memory, a vertical NAND (VNAND), a NOR flash memory, a resistance random access memory (RRAM), a phase change memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), a spin transfer torque random access memory (STT-RAM), etc. In the following, the technical concept of the present disclosure will be described by an example in which the non-volatile memory device 100 is a vertical NAND flash memory (VNAND). However, the scope of the technical concept according to the present disclosure is not limited to these examples. That is, the embodiments of the technical concept according to the present disclosure can be applied to the above-mentioned non-volatile memory.

[0039] The word line defect detection circuit 120 may detect defects of wiring provided in the memory cell array 160. Specifically, the word line defect detection circuit 120 may detect defects existing in the bit lines and word lines provided in the memory cell array 160, for example, using a pumping clock signal (CLK_P). In this manner, when the word line defect detection circuit 120 detects a defect, the word line defect detection circuit 120 may provide defect information to the control logic 150.

[0040] The voltage generating unit 170 may include a voltage generator 110 and a clock generator 111 .

[0041] The voltage generator 110 may generate an operating voltage (Vg) required for operating the nonvolatile memory device 100. Examples of the operating voltage (Vg) include, but are not limited to, a programming voltage, a pass voltage, a read voltage, a read pass voltage, a verification voltage, an erase voltage, a common source line voltage, a well bias voltage, etc. The voltage generator 110 may generate a word line voltage required for programming new data in a memory cell arranged in the memory cell array 160, reading data stored in the memory cell, or erasing data stored in the memory cell. Hereinafter, reference will be made to the operating voltage (Vg). Figure 3 The voltage generator 110 is described in more detail.

[0042] The plurality of memory cells of the memory cell array 160 may be disposed in a p-type well region (eg, a pocket p-well) in a substrate.

[0043] The clock generator 111 may generate one or more pumping clock signals (CLK_P) based on a system clock signal (CLK) (or an external clock signal) received from the outside of the nonvolatile memory device 100 during a program operation or an erase operation and a determination signal (DET) received from the voltage generator 110. The system clock (CLK) input to the clock generator 111 may be used to provide timing to other circuits of the nonvolatile memory device 100, and may be generated based on a clock signal input to the nonvolatile memory device 100. As an example, when the pumping voltage signal (or pumping voltage) (Vp) of the voltage generator 110 is lower than the reference pumping voltage (Vpump_REF), the clock generator 111 may generate the pumping clock signal (CLK_P). In this case, the level of the pumping voltage (Vp) and the level of the reference pumping voltage (Vpump_REF) may be positive values. As another example, when the negative pumping voltage (-Vp) of the voltage generator 110 is higher than the negative reference pumping voltage (-Vpump_REF), the clock generator 111 may generate a pumping clock signal (CLK_P). In this case, the level of the negative pumping voltage (-Vp) and the level of the negative reference pumping voltage (-Vpump_REF) may be negative values. The pumping clock signal (CLK_P) may include a plurality of pulses and may be generated by connecting an input terminal providing a system clock signal (CLK) to an output terminal providing a pumping clock signal (CLK_P) to selectively pass the system clock signal (CLK) to the output terminal in response to a determination signal DET. A specific example thereof will be given later.

[0044] Figure 3 It is used to illustrate the Figure 2 Block diagram of a voltage generator.

[0045] refer to Figure 3 , the voltage generator 110 may include a charge pump 112 , a determination signal generator 113 , and a regulator 114 .

[0046] The charge pump 112 may include a plurality of charge pump circuits and a control circuit. Each of the plurality of charge pump circuits may be enabled or disabled by the control circuit, and may perform a charge pumping operation by utilizing a pumping clock signal (CLK_P) and a power supply voltage (Vcc) provided from the clock generator 111. For example, the charge pump 112 may generate a plurality of pumping voltage signals (Vp) by using one or more pumping clock signals (CLK_P).

[0047] The regulator 114 adjusts the pump voltage signal (Vp) output from the charge pump 112 to generate an operating voltage (Vg), and can be used to generate an operating voltage (Vg) through the address decoder ( Figure 2130) provides the generated operating voltage (Vg) to the memory cell array ( Figure 2 of 160).

[0048] The determination signal generator 113 may generate a determination signal (DET) by comparing the pumping voltage signal (Vp) output from the charge pump 112 with the reference pumping voltage (Vpump_REF). The generated determination signal (DET) is provided to the clock generator 111 and may be used to generate a pumping clock signal (CLK_P). For example, the pumping voltage signal (Vp) may include a plurality of pumping voltage signals (Vp), and the reference pumping voltage (Vpump_REF) may include a plurality of reference pumping voltages (Vpump_REF).

[0049] In the following, reference will be made to Figure 4 The process of generating the pump clock signal (CLK_P) is described together in more detail.

[0050] Figure 4 It is used to illustrate the Figure 2 and Figure 3 Figure 2. Pump clock signal of the pump.

[0051] refer to Figure 3 and Figure 4 , the determination signal generator 113 may compare the pump voltage signal (Vp) output from the charge pump 112 with the reference pump voltage (Vpump_REF) to generate a determination signal (DET). Figure 4 As shown in, the determination signal (DET) can maintain a high level (i.e., a logic high level) in the portion where the pumping voltage signal (Vp) is lower than the reference pumping voltage (Vpump_REF) among the portions where the pumping voltage signal (Vp) rises and / or falls, and can maintain a low level (i.e., a logic low level) in other portions.

[0052] The determination signal (DET) generated by the determination signal generator 113 is provided to the clock generator 111, and the clock generator 111 can calculate (e.g., AND calculate) the system clock signal (CLK) and the determination signal (DET) to generate the pump clock signal (CLK_P). Figure 4 As shown, in the pumping clock signal (CLK_P), the portion where the charge pump 112 generates the pumping voltage signal (Vp) for generating the operating voltage (Vg) (i.e., where the operating voltage (Vg) is applied to the memory cell array ( Figure 2 In the part 160), there is a signal in the form of a pulse.

[0053] Although the above has been used Figure 3 and Figure 4An example configuration of the voltage generator 110 that generates the operating voltage (Vg) required to operate the nonvolatile memory device 100 and generates the determination signal (DET) for generating the pump clock signal (CLK_P) is described, but the embodiment is not limited thereto. The configuration of the voltage generator 110 may be modified and provided differently as needed.

[0054] Reference again Figure 2 , the word line defect detection circuit 120 (e.g., a pass-fail determination circuit) may receive a pumping clock signal (CLK_P) from the voltage generator 110 and monitor the pumping clock signal (CLK_P) to determine whether a defect exists in the wiring included in the memory cell array 160. Specifically, the pass-fail determination circuit receives the pumping clock signal (CLK_P) from the clock generator 111, compares the number of pulses of the received pumping clock signal (CLK_P) with a reference value (REF_C) within a period of time (e.g., while a programming voltage is applied to a corresponding word line, while an erase voltage is applied to a well region in a substrate, or while a pass voltage is applied to a word line adjacent to a word line performing a programming operation), and may determine a defect in the wiring in the memory cell array 160 to which the operating voltage (Vg) is being applied. More specifically, the pass-fail determination circuit compares the number of pulses included in the pump clock signal (CLK_P) with the reference value (REF_C) to determine whether the word line ( Figure 7 For example, the reference value (REF_C) may be stored in a register included in the nonvolatile memory device 100 or the memory controller 200.

[0055] If it is determined that on a specific word line ( Figure 7 If there is a defect in a specific word line (WL1 to WL8), the pass-fail determination circuit can provide a pass-fail result signal (P / F) to the control logic 150 indicating that the specific word line ( Figure 7 A signal indicating that there is a defect in WL1 to WL8 of the word line or a signal indicating that the defective word line ( Figure 7 The memory blocks (BLK1 to BLKz) of WL1 to WL8 are processed as defective products.

[0056] In the following, reference will be made to Figure 5 The pass-fail determination circuit is described in more detail.

[0057] Figure 5 It is used to illustrate the Figure 2 Block diagram of the pass-fail decision circuit.

[0058] refer to Figure 5 The pass-fail determination circuit may include a counter 121 and a comparator 122 .

[0059] The counter 121 receives the pumping clock signal (CLK_P), counts the number of pulses (C1) included in the pumping clock signal (CLK_P), and can output the result. Specifically, the counter 121 receives the pumping clock signal (CLK_P), counts the number of pulses (C1) included in each cycle of the pumping clock signal (CLK_P), and can output the result.

[0060] The comparator 122 may compare the reference value (REF_C) and the number of pulses (C1) included in the pumping clock signal (CLK_P) provided from the counter 121, thereby generating and outputting a pass-fail result signal (P / F). In some embodiments, when the number of pulses (C1) included in the pumping clock signal (CLK_P) is greater than or equal to the reference value (REF_C), the comparator 122 may generate and output a pass-fail result signal (P / F) in the form of a signal indicating that one or more specific word lines ( Figure 7 WL1 to WL8) have a defect, or indicate that a defective word line ( Figure 7 The signal of the defective block is used to detect one or more memory blocks (BLK1 to BLKz) of WL1 to WL8 of FIG.

[0061] Already referenced Figure 5 An exemplary configuration of a pass-fail determination circuit that monitors the pumping clock signal (CLK_P) to determine defects of wiring included in the memory cell array 160 is described. However, the embodiment is not limited thereto. The configuration of the pass-fail determination circuit may be modified and provided variously as needed.

[0062] Reference again Figure 2 , the address decoder 130 may select one of the plurality of memory blocks (BLK1 to BLKz) in response to the address (ADDR). Here, the address (ADDR) may include a plurality of addresses. In addition, the address decoder 130 may be connected to the memory cell array 160 via a plurality of word lines (WL), at least one string selection line (SSL) and at least one ground selection line (GSL). The address decoder 130 may use the decoded row address to select one of the word lines (WL), the string selection line (SSL) and the ground selection line (GSL). In addition, the address decoder 130 may decode the column address in the address (ADDR). Here, the decoded column address may be sent to the input / output circuit 140. In some embodiments, the address decoder 130 may include a row decoder, a column decoder, an address buffer, and the like.

[0063] The input / output circuit 140 may be connected to the memory cell array 160 via a bit line (BL). The input / output circuit 140 may be provided to receive a decoded column address from the address decoder 130. The input / output circuit 140 may select a bit line (BL) using the decoded column address.

[0064] The input / output circuit 140 may include a plurality of page buffers that store data to be programmed when the nonvolatile memory device 100 performs a programming operation, or store a plurality of read data when performing a read operation. Here, each of the plurality of page buffers may include a plurality of latches. During a programming operation, the data stored in the plurality of page buffers may be programmed to a page (e.g., a group of memory cells) corresponding to a memory block selected via a bit line (BL). During a read operation, data read from a page corresponding to a selected memory block may be stored in a page buffer via a bit line (BL). In addition, the input / output circuit 140 may read data from a first region of the memory cell array 160, and may store the read data in a second region of the memory cell array 160. For example, an input / output circuit 140 may be provided to perform copy-back.

[0065] The control logic 150 may control the overall operation (programming, reading, erasing, etc.) of the nonvolatile memory device 100. Specifically, the control logic 150 may control the voltage generator 110, the pass-fail determination circuit, the address decoder 130, and the input / output circuit 140 during the operation of the nonvolatile memory device 100. The control logic 150 may operate in response to a control signal (CTRL) or a command (CMD) input externally.

[0066] The memory cell array 160 may be provided as, for example, a three-dimensional memory array structure. The three-dimensional memory array may have a vertical directionality and may include a plurality of vertical NAND strings in which at least one memory cell is located above another memory cell. At least one memory cell may include, for example, a charge trapping layer. Each vertical NAND string may include at least one selection transistor located above the memory cell. The at least one selection transistor has the same structure as the memory cell and may be formed monolithically with the memory cell. The term monolithic refers to the fact that the layers of each level of the three-dimensional array are deposited directly on the layers of the lower levels of the three-dimensional array.

[0067] The three-dimensional memory array includes a plurality of levels, and word lines or bit lines shared between the levels may be arranged. The nonvolatile memory device 100 may be a flash memory device in which a charge storage layer is composed of a conductive floating gate, or a charge trap flash (CTF) memory device in which a charge storage layer is composed of an insulating film. Hereinafter, the nonvolatile memory device 100 will be described as an example based on the assumption that the nonvolatile memory device 100 is a vertical NAND flash memory device.

[0068] The memory cell array 160 may include a plurality of memory blocks (BLK1 to BLKz). Each of the memory blocks (BLK1 to BLKz) is connected to the address decoder 130 through a plurality of word lines (WL), at least one string selection line (SSL), and at least one ground selection line (GSL), and may be connected to the input / output circuit 140 through a plurality of bit lines (BL). In some embodiments, the plurality of word lines (WL) may have a stacked plate structure.

[0069] Each of the plurality of memory blocks (BLK1 to BLKz) may have a plurality of strings of three-dimensional structures, which are arranged on a substrate along a first direction and a second direction different from the first direction and arranged along a third direction perpendicular to a plane formed by the first direction and the second direction. Here, each of the plurality of strings may include at least one string selection transistor, a plurality of memory cells, and at least one ground selection transistor connected in series between a bit line and a common source line (CSL). Here, each of the plurality of memory cells may store at least one bit. In some embodiments, at least one dummy cell may be included between at least one string selection transistor and the plurality of memory cells. In some embodiments, at least one dummy cell may be included between the plurality of memory cells and at least one ground selection transistor. Hereinafter, reference will be made to Figure 6 and Figure 7 The memory blocks (BLK1 to BLKz) of the memory cell array 160 are described in more detail.

[0070] Figure 6 and Figure 7 It is used to illustrate Figure 2 Diagram of a memory cell array.

[0071] refer to Figure 6 The memory block (BLK1) may be formed in a direction perpendicular to the substrate (SUB). For example, an n+ doping region including impurities may be formed in the substrate (SUB).

[0072] The gate electrode 165 and the insulating film 164 may be alternately stacked on the substrate (SUB). The data storage film 161 may be formed between the gate electrode 165 and the insulating film 164.

[0073] The column can penetrate the gate electrode 165 and the insulating film 164 in the vertical direction. As shown in the figure, the column can be formed into a V shape. The column can be connected to the substrate (SUB) through the gate electrode 165 and the insulating film 164. The inside of the column is filled with a dielectric pattern 163, and can be made of an insulating material such as silicon oxide. The outside of the column is a vertical active pattern 162, and can be made of a channel semiconductor.

[0074] The gate electrode 165 of the memory block (BLK1) may be connected to a ground selection line (GSL), a plurality of word lines (WL1 to WL8), and a string selection line (SSL). The vertical active pattern 162 formed outside the pillar of the memory block (BLK1) may be connected to a plurality of bit lines (BL1 to BL3). Figure 6 A configuration in which one memory block (BLK1) has two selection lines (GSL and SSL), eight word lines (WL1 to WL8), and three bit lines (BL1 to BL3) is shown, but the embodiment is not limited thereto. If necessary, the number of wirings may be variously modified and provided.

[0075] Figure 7 is an exemplary equivalent circuit diagram of a memory block (BLK1). Figure 7 , the cell strings (NS11 to NS33) may be disposed between the bit lines (BL1 to BL3) and the common source line (CSL). Each cell string (eg, NS11) may include a ground selection transistor (GST), a plurality of memory cells (MC1 to MC8), and a string selection transistor (SST).

[0076] The string selection transistor (SST) may be connected to a string selection line (SSL). The string selection line (SSL) may be divided into a first string selection line to a third string selection line (SSL1 to SSL3). A ground selection transistor (GST) may be connected to a first ground selection line to a third ground selection line (GSL1 to GSL3). In some embodiments, the first ground selection line to the third ground selection line (GSL1 to GSL3) may be connected to each other. The string selection transistor (SST) may be connected to a bit line (BL), and the ground selection transistor (GST) may be connected to a common source line (CSL).

[0077] A plurality of memory cells (MC1 to MC8) may be connected to corresponding word lines (WL1 to WL8), respectively. A group of memory cells connected to one word line and programmed at the same time may be referred to as a page. As shown in the figure, a memory block (BLK1) may include a plurality of pages. In addition, a plurality of pages may be connected to one word line. Figure 7 , a word line (eg, WL4 ) at the same height as the common source line (CSL) may be commonly connected to three pages.

[0078] These pages may be a unit for data programming and reading, and a memory block (BLK1) may be a unit for data erasure. That is, when the nonvolatile memory device performs a programming or reading operation, data in units of pages may be programmed or read, and when the nonvolatile memory device performs an erasing operation, data may be erased in units of memory blocks. For example, data stored in all memory cells (MC1 to MC8) included in one memory block may be erased at one time.

[0079] Each memory cell in the memory cells (MC1 to MC8) can store one bit of data or two or more bits of data. A memory cell capable of storing one bit of data in one memory cell (MC1 to MC8) may be referred to as a single-layer cell (SLC) or a single-bit cell. A memory cell capable of storing two or more bits of data in one memory cell may be referred to as a multi-layer cell (MLC) or a multi-bit cell. In the case of a 2-bit MLC, two pages of data may be stored in one physical page. Therefore, six pages of data may be stored in a memory cell (MC4) connected to a word line (WL4).

[0080] Here, the following will refer to Figure 3 , Figure 8 and Fig. 9 The word line defect detection operation of the nonvolatile memory device 100 is described in detail.

[0081] Figure 8 and Fig. 9 is a diagram for explaining a word line defect detection operation of a nonvolatile memory device according to some embodiments.

[0082] First, refer to Figure 2 , Figure 3 and Figure 8 , when there is no defect in the word lines (WL(n-1), WLn, and WL(n+1)) included in the memory block (BLK), the charge pump 112 outputs a normal pumping voltage signal (Vp_n), and the determination signal generator 113 compares the normal pumping voltage signal (Vp_n) output from the charge pump 112 with the reference pumping voltage (Vpump_REF) to generate a determination signal (DET). The clock generator 111 can generate a pumping clock signal (CLK_P) according to the system clock signal (CLK) using the determination signal (DET) output from the determination signal generator 113. Since this has been mentioned above with reference to Figure 4 A description has been given, so a more detailed description will not be provided.

[0083] refer to Figure 2 , Figure 3 and Fig. 9, if there is a bridge (B) defect in the word lines (WL(n-1), WLn, and WL(n+1)) included in the memory block (BLK) as shown in the figure, the charge pump 112 may output a bridge pumping voltage signal (Vp_b). Compared with the normal pumping voltage signal (Vp_n), the bridge pumping voltage signal (Vp_b) may take time to reach the target voltage, but this may be because the word lines (WL(n-1), WLn, and WL(n+1)) are connected to each other through the bridge (B), resulting in current leakage. For example, due to the bridge (B) generated between at least one adjacent word line (WL(n-1), WLn, and WL(n+1)), the charge pump 112 may take more time to generate the target level voltage.

[0084] When this phenomenon occurs, the charge pump 112 may take more time to reach the reference pump voltage (Vpump_REF). Therefore, compared with the normal case where there is no defect between the adjacent word lines (WL(n-1), WLn and WL(n+1)), Figure 8 ), the period of the determination signal (DET) may become longer. Therefore, compared with the normal case ( Figure 8 ), the number of pulses included in the pump clock signal (CLK_P) becomes larger. Figure 8 and Fig. 9 In the example of , the number of pulses included in the pump clock signal (CLK_P) increases from 1 to 3.

[0085] The nonvolatile memory device 100 according to the present embodiment can use this principle to detect defects of word lines (WL(n-1), WLn, and WL(n+1)) in a memory block (BLK). For example, when the reference value ( Figure 5 If REF_C is preset to 2, Figure 8 As shown in FIG. 1 , if the number of pulses included in the pump clock signal (CLK_P) is 1, the nonvolatile memory device 100 can determine that the word lines (WL(n-1), WLn, and WL(n+1)) in the memory block (BLK) are normal. Fig. 9 As shown in FIG. 1 , the number of pulses included in the pump clock signal (CLK_P) is 3, the nonvolatile memory device 100 can determine that there are defects in the word lines (WL(n-1), WLn, and WL(n+1)) in the memory block (BLK). For example, by calculating the number of pulses included in the pump clock signal (CLK_P) ( Figure 5 C1) and the reference value ( Figure 5By comparing with REF_C), it is possible to detect whether there are defects in the word lines (WL(n-1), WLn and WL(n+1)) in the storage block (BLK).

[0086] Although for ease of understanding, Fig. 9 1 and 2 clearly distinguish between the normal pumping voltage signal (Vp_n) and the bridge pumping voltage signal (Vp_b), but the actual output of the charge pump 112 may be provided differently from the illustrated case. For example, the output of the charge pump 112 may be modified and provided to any other configuration in which the number of pulses included in the pumping clock signal (CLK_P) is increased.

[0087] Hereinafter, an operation of detecting whether there are defects in word lines (WL(n-1), WLn, and WL(n+1)) in a memory block (BLK) will be described in a user mode in which the nonvolatile memory device 100 programs data, reads data, and erases data by communicating with a host (HOST).

[0088] First, refer to Figures 10 to 12 The operation of detecting whether there is a defect in the word lines (WL(n-1), WLn, and WL(n+1)) in the memory block (BLK) during the erase operation is described. Figures 13 to 15 An operation of detecting whether a defect exists in word lines (WL(n-1), WLn, and WL(n+1)) in a memory block (BLK) during execution of a program operation is described.

[0089] Fig.10 is a flowchart illustrating the operation of the nonvolatile memory device 100 according to some embodiments. Fig.11 and Fig.12 It is used to specifically describe the Fig.10 2 and 3. The operation of the nonvolatile memory device 100 is shown in FIG.

[0090] refer to Fig.10 , the counter is reset (S100). For example, referring to Figure 5 , the pass-fail determination circuit can reset the counter 121 to perform a new defect detection operation.

[0091] Next, refer to Fig.10 , performing an erase operation while counting the number of pulses included in the pump clock signal (CLK_P) (S110). Figure 2 and Figure 6, in order to erase a memory block (e.g., BLK1) included in the memory cell array 160, the voltage generator 110 generates a first erase voltage (Vpwell) supplied to the p-well region and a second erase voltage smaller than the first erase voltage supplied to the word lines (e.g., WL8 to WL1) in the memory block (BLK1). At this time, the pass-fail determination circuit may count the number of pulses included in the pumping clock signal (CLK_P) while applying the first erase voltage and the second erase voltage to the p-well region and the word lines (WL1 to WL8) in the memory block (BLK1), respectively.

[0092] Next, refer to Fig.10 , it is determined whether the number of pulses included in the pumping clock signal (CLK_P) is greater than or equal to the reference value (REF_C) (S120).

[0093] Therefore, when the number of pulses included in the pumping clock signal (CLK_P) is greater than or equal to the reference value (REF_C), since there is a high possibility that a defect exists in at least one word line, the erase operation is terminated after the memory block (BLK1) including the word line (WL2) is designated as a bad block (S130).

[0094] On the contrary, when the number of pulses included in the pump clock signal (CLK_P) is less than the reference value (REF_C), since it is determined that there is no defect in the word line (WL8 to WL1), it is verified whether the erase operation (S140) of the word line (WL8 to WL1) of the memory block (BLK1) is completed. When the result of the verification is that the erase operation of the word line (WL8 to WL1) fails (S150-failure), the above-mentioned erase operation is repeated again by applying an erase voltage greater than the first erase voltage previously applied to the p-well region. When the result of the verification is that a specific erase voltage is applied to the p-well region and the erase operation of the word line (WL8 to WL1) still fails (S150-failure), the above-mentioned erase operation may not be repeated, and the erase operation may be stopped. When the erase operation of the word line (WL8 to WL1) in the memory block (BLK1) has passed (S150-pass), the erase operation (S150-pass) is terminated.

[0095] For example, refer to Figure 2 , the pass-fail determination circuit may determine whether the number of pulses included in the pumping clock signal (CLK_P) is greater than or equal to a reference value (REF_C).

[0096] When the number of pulses included in the pump clock signal (CLK_P) is greater than or equal to the reference value (REF_C), the pass-fail determination circuit may provide the following notification to the control logic 150 in the form of a pass-fail result signal (P / F), namely, it is necessary to designate a storage block (BLK1) including a defective word line (WL2) to which a second erase voltage is applied as a bad block.

[0097] Conversely, when the number of pulses included in the pumping clock signal (CLK_P) is less than the reference value (REF_C), the control logic 150 verifies whether the erase operation of the memory block (BLK1) has been completed, and may repeat the erase operation until the erase operation is completed at a specific erase voltage.

[0098] In the following, reference Fig.11 and Fig.12 , a comparison will be made between the case where there are no defects in the word line and the case where there are defects.

[0099] first, Fig.11 This is a timing diagram when there is no defect in the word lines ( WL8 to WL1 ) in the memory block ( BLK1 ).

[0100] refer to Fig.11 , a user mode signal (RnBx) is enabled in the first part (E1), and a first erase voltage may be applied to the substrate (e.g., a p-well region of the substrate) for erasing data of a memory cell in the memory block (BLK1). At this time, a second erase voltage smaller than the first erase voltage may be applied to the word lines (WL8 to WL1) in the memory block (BLK1).

[0101] In the second part (E2), when the second erase voltage reaches the target voltage, the clock count signal (CLKCNT) is enabled, and the pump clock signal (CLK_P) can be counted. Since there are no defects in the word lines (WL8 to WL1), the erase operation can be continuously performed until the third part (E3). In some embodiments, these erase operations can be performed by repeatedly applying a predetermined erase voltage to the memory cell array (e.g., to the p-well region and the word line) multiple times.

[0102] When the erase operation of the memory block (BLK1) is completed, the erase operation can be completed by disabling the user mode signal (RnBx) after stopping the application of the erase voltage in the fourth section (E4). In the fourth section (E4), the nonvolatile memory device 100 can be verified whether the erase operation that has been completed can be performed. When performing this operation, since no defects are found in the word line, the pass-fail result signal (P / F) can remain disabled.

[0103] Next, Fig.12is a timing diagram when there is a defect in at least one word line (eg, WL2 ).

[0104] refer to Fig.12 , a user mode signal (RnBx) is enabled in the first part (E1), and a first erase voltage (Vpwell) may be applied to the p-well region for an erase operation of the memory block (BLK1). At this time, a second erase voltage smaller than the first erase voltage may be applied to the word lines (WL8 to WL1) in the memory block (BLK1).

[0105] In the second part (E2), the clock counting signal (CLK CNT) is enabled and the pumping clock signal (CLK_P) can be counted. In this case, since the number of pulses of the pumping clock signal (CLK_P) is greater than or equal to the reference value (REF_C), it can be determined that there is a defect in the word line (WL2).

[0106] Therefore, with the above reference Fig.11 Unlike the situation described, the erase operation can be stopped directly in the third part (E3). For example, the first erase voltage (Vpwell) is stopped from being applied to the p-well region, and the second erase voltage can also be stopped from being applied to the word line (WL8 to WL1). In addition, the pass-fail result signal (P / F) can be enabled, and the storage block (BLK1) can be designated as a bad block. Then, since the user mode signal (RnBx) is immediately disabled, the erase operation of the storage block (BLK1) can be stopped. As described above, when a word line defect is found during the execution of an erase operation, unnecessary power consumption can be prevented by immediately stopping the application of the erase voltage.

[0107] Fig.13 is a flowchart for explaining the operation of a nonvolatile memory device according to some embodiments. Fig.14 and Fig.15 It is used to specifically describe the Fig.13 A diagram illustrating the operation of a nonvolatile memory device.

[0108] refer to Fig.13 , the counter is reset (S200). For example, referring to Figure 5 , the pass-fail determination circuit can reset the counter 121 to perform a new defect detection operation.

[0109] Next, refer to Fig.13 , performing a programming operation while counting the number of pulses included in the pumping clock signal (CLK_P) (S210). Figure 2 and Figure 7, the voltage generator 110 may generate a programming voltage to be supplied to a word line (e.g., WL2) among the word lines (WL1 to WL8) to program a memory cell (MC2) connected to the word line (WL2) or a page of memory cells including the memory cell (MC2). At this time, the pass-fail determination circuit may count the number of pulses included in the pumping clock signal (CLK_P) while applying the programming voltage to the word line (WL2) among the word lines (WL1 to WL8).

[0110] Next, refer to Fig.13 , it is determined whether the number of pulses included in the pumping clock signal (CLK_P) is greater than or equal to the reference value (REF_C) (S220).

[0111] Therefore, when the number of pulses included in the pumping clock signal (CLK_P) is greater than or equal to the reference value (REF_C) (S220-Yes), because there is a high possibility that there is a defect in the word line (WL2), the programming operation is terminated after the storage block including the word line (WL2) is designated as a bad block (S230).

[0112] On the contrary, when the number of pulses included in the pumping clock signal (CLK_P) is less than the reference value (REF_C) (S220-No), because it is determined that there is no defect in the word line (WL2), it is verified whether the programming operation of the memory cells of the word line (WL2) or the page has been completed (S240). This may include performing a read verification of the memory cell page of the word line WL2 to determine that those memory cells to be programmed in the programming step have sufficiently increased their threshold voltages. When the result of the verification is that the programming operation of the word line (WL2) has not been completed (S250-Fail), the above-mentioned programming operation is repeated again by applying a programming voltage greater than the previously applied programming voltage to the word line (WL2). When the result of the verification is that a specific programming voltage is applied to the word line (WL2) and the programming operation of the word line (WL2) has not been completed (S250-Fail), the above-mentioned programming operation is no longer repeated and the programming operation of the word line (WL2) can be stopped. When the program operation on the word line (WL2) is completed (S250-pass), the program operation is terminated. Next, a program operation on the remaining word lines (eg, word lines other than WL2) may be performed.

[0113] For example, refer to Figure 2 , the pass-fail determination circuit may determine whether the number of pulses included in the pumping clock signal (CLK_P) is greater than or equal to a reference value (REF_C).

[0114] When the number of pulses included in the pump clock signal (CLK_P) is greater than or equal to the reference value (REF_C), the pass-fail determination circuit (P / F) may provide the following notification to the control logic 150 in the form of a pass-fail result signal (P / F), namely, it is necessary to designate a storage block (BLK1) including a defective word line (WL2) to which a programming voltage is applied as a bad block.

[0115] Conversely, when the number of pulses included in the pumping clock signal (CLK_P) is less than the reference value (REF_C), the control logic 150 can verify whether the programming operation of the word line (WL2) or the page has been completed, and can repeat the programming operation until the programming operation on the word line (WL2) is completed.

[0116] In the following, reference Fig.14 and Fig.15 , description will be made by comparing a case where there is no defect in a word line and a case where there is a defect.

[0117] first, Fig.14 is a timing diagram for a case where there is no defect in the word line.

[0118] refer to Fig.14 , after the user mode signal (RnBx) is enabled, a predetermined program voltage (Vpgm) may be applied to the word line (eg, WL2).

[0119] As shown in the figure, each programming voltage (Vpgm) is applied to the word line (WL2) at each time point (T1, T2, ..., Tn-1 and Tn, n is a natural number), and when the number of pulses included in the pump clock signal (CLK_P) is less than the reference value (REF_C), because there is no defect in the word line (WL2), the programming operation on the word line (WL2) can be continuously performed. In some embodiments, the programming operation can be performed by repeatedly applying a predetermined programming voltage (e.g., a programming voltage with a gradually increasing level as shown) to the word line (WL2) of the memory cell array for multiple times.

[0120] In some examples, the reference value (REF_C) may have different values ​​in each programming loop (eg, as the program voltage Vpgm increases, the reference value (REF_C) may increase).

[0121] In some examples, the reference value (REF_C) can have the same value in each programming loop.

[0122] When the program operation of the word line ( WL2 ) or the page is completed, the program operation may be completed by disabling the user mode signal (RnBx) after stopping the application of the program voltage.

[0123] Next, Fig.15 is a timing diagram for the case where a defect exists in a word line.

[0124] refer to Fig.15 , after the user mode signal (RnBx) is enabled, a predetermined program voltage may be applied to the word line (WL2).

[0125] Due to a defect in the word line (WL2), there may be a case where the number of pulses included in the pump clock signal (CLK_P) is greater than or equal to the reference value (REF_C), and at the same time, for example, at a time point (T n-1 ) applies a specific programming voltage to the word line (WL2).

[0126] In this way, when there is a situation where the number of pulses included in the pump clock signal (CLK_P) is greater than or equal to the reference value (REF_C), the programming operation can be stopped immediately. For example, the application of the corresponding programming voltage to the word line (WL2) can be stopped immediately. In addition, by disabling the user mode signal (RnBx), the programming operation can be stopped to complete the programming of the memory cell page even if additional programming cycles may have been applied. For example, when a word line defect is found during the execution of the programming operation, unnecessary power consumption can be prevented by immediately stopping the application of the programming voltage.

[0127] Fig.16 is a flowchart for explaining the operation of a nonvolatile memory device according to some embodiments. Fig.17 and Fig.18 It is used to specifically describe the Fig.16 A diagram illustrating the operation of a nonvolatile memory device.

[0128] refer to Fig.16 , perform an erase operation (S300) of the memory block (BLK1). The erase operation may be similar to that described above, for example, with reference to Fig.10 However, the embodiments of the technical concept according to the present disclosure are not limited thereto, and the erase operation of the storage block may be simply performed while referring to Fig.10 The erase operation described omits the process of determining whether a word line defect exists.

[0129] Thereafter, it is checked whether the erase operation of the memory block (BLK1) is completed (S310).

[0130] If the check result is that the erase operation of the memory block (BLK1) has failed (S310-failed), the memory block (BLK1) is designated as a bad block (S350). Since the operation of designating the memory block (BLK1) as a bad block has been described in detail above, a repeated description will not be provided.

[0131] On the contrary, when the result of the check is that the erase operation of the memory block (BLK1) has passed (S310-pass), the counter reset is performed (S320). Since the counter reset operation has also been described in detail above, a repeated description will not be provided.

[0132] Thereafter, during application of the first program voltage (V1) to the word line (eg, WL4), a first program operation on the word line (WL4) is performed while counting the number of pulses included in the pumping clock signal (CLK_P) (S330).

[0133] For example, refer to Figure 2 and Fig.17 , the voltage generator 110 may generate a first programming voltage (V1), and the first programming voltage (V1) is to be provided to the lower word line group (G2) included in the memory cell array 160, for example, the word lines WL4 to WL1. In addition, the generated first programming voltage (V1) may be sequentially provided to the word lines (WL4) to (WL1) included in the lower word line group (G2). At this time, the first programming voltage (V1) may not be provided to the lower word line group (G1), for example, the word lines WL8 to WL5 included in the memory cell array 160.

[0134] The pass-fail determination circuit may count the number of pulses included in the pumping clock signal (CLK_P) while sequentially applying the first program voltage (V1) to the word line (WL4) to the word line (WL1).

[0135] Next, refer to Fig.16 , it is determined whether the number of pulses included in the pumping clock signal (CLK_P) is greater than or equal to the reference value (REF_C) (S340).

[0136] Therefore, when the number of pulses included in the pumping clock signal (CLK_P) is greater than or equal to the reference value (REF_C) (S340-Yes), since there is a defect in at least one word line (e.g., WL4) included in the lower word line group (G2), the programming operation is terminated after the memory block (BLK1) including the word lines (WL4 to WL1) is designated as a bad block (S350).

[0137] On the contrary, when the number of pulses included in the pumping clock signal (CLK_P) is less than the reference value (REF_C) (S340-No), since there is no defect in the word line (e.g., WL4) included in the lower word line group (G2), the first programming operation on the remaining word lines (WL3 to WL1) may be repeated until the first programming operation on the word lines (WL4 to WL1) is completed (S360), and the memory cells (MC1 to MC8) of the word lines (WL8 to WL1) or pages are programmed with the second programming voltage (V2) (S370). For example, the voltage level of the second programming voltage (V2) may be the same as that of the first programming voltage (V2). Fig.14 Time point T 1 The voltage level of the programming voltage (Vpgm) at is the same.

[0138] In one embodiment, the voltage level of the first programming voltage (V1) may be the same as or lower than the voltage level of the second programming voltage (V2).

[0139] In operation S370, a program operation on a word line (eg, WL8) is performed at a second program voltage (V2), and the program voltage may be set as follows: Fig.14 The programming operation on the word line (e.g., WL8) is repeated with the program voltage having a gradually increasing level as shown until the programming operation on the word line (WL8) is completed. When the programming operation on the word line (WL8) is completed, the programming operation on the remaining word lines (WL7 to WL1) can be performed in the same manner. The programming operation on the word lines WL8 to WL5 can be performed in the same manner as described above with reference to, for example. Figure 3 In this case, the reference value (REF_C) for monitoring the number of pulses of the pump clock signal (CLK_P) when the second programming voltage (V2) is applied to each word line (e.g., WL8 to WL5) may be different from the reference value (REF_C) for monitoring the number of pulses of the pump clock signal (CLK_P) when the first programming voltage (V1) is applied to each word line (e.g., WL4 to WL1). In example embodiments, the programming operation for the word lines WL8 to WL5 may be simply performed while the reference value (REF_C) for monitoring the number of pulses of the pump clock signal (CLK_P) when the second programming voltage (V2) is applied to each word line (e.g., WL8 to WL5) may be different from the reference value (REF_C) for monitoring the number of pulses of the pump clock signal (CLK_P) when the first programming voltage (V1) is applied to each word line (e.g., WL4 to WL1). Fig.13 The program operation on the word lines WL8 to WL5 is described with the process of determining whether a word line defect exists omitted.

[0140] In an example embodiment, after an erase operation is completed on a memory block including memory cells connected to a word line (e.g., WL4), data "1" may be stored in the memory cells connected to the word line (WL4). When a first programming voltage (V1) is applied to the word line (WL4), a threshold voltage of the memory cells connected to the word line (WL4) may shift. Therefore, while an erase mode is programmed to the memory cells connected to the word line (WL4), the word line defect detection circuit may monitor the number of pulses of the pump clock signal. For example, during programming of the erase mode, the data state in the corresponding memory cell may not change from the state of the erased data.

[0141] For example, refer to Figure 2 and Fig.18 , the voltage generator 110 may generate a second programming voltage (V2) to be provided to the word lines (WL8 to WL1) included in the memory cell array 160. Here, the second programming voltage (V2) is a voltage for programming data provided from the host (HOST) to the memory cells (MC1 to MC8), and may be greater than the above-mentioned first programming voltage (V1). By sequentially providing the generated second programming voltage (V2) to the word line (WL8) to the word line (WL1), the memory cells (MC1 to MC8) of the word line (WL8 to WL1) or the page may be programmed.

[0142] In summary, in the operation of the nonvolatile memory device according to the present embodiment, before applying the second programming voltage (V2) to store data in the memory cells (MC1 to MC8), it is first checked whether there is a defect in the lower word line group (G2) with a low level first programming voltage (V1) that does not affect the durability of the word lines (WL4 to WL1). Fig.19 Describe the effects of the operation of a nonvolatile storage device.

[0143] Fig.19 It is used to illustrate the Fig.16 A diagram showing the effect of the operation of a nonvolatile memory device.

[0144] refer to Fig.19 In a vertical NAND flash memory device, a memory block (BLK) may have a shape as shown in the figure, in which the width of the lower portion is narrow and the width of the upper portion is wide. According to this shape, the interval (d2) between two adjacent word lines of the lower word line (WLB) disposed in the lower portion may be smaller than the interval (d1) between two adjacent word lines of the upper word line (WLU) disposed in the upper portion.

[0145] In this manner, when the interval (d2) is narrow, a bridge defect may occur relatively frequently in the lower word line (WLB) disposed in the lower portion.

[0146] For example, in order to improve the expansion characteristics of program data, a method (programming order) of sequentially performing programming from an upper word line (WLU) disposed in an upper portion of a memory block (BLK) to a word line (WLB) disposed in a lower portion may be used.

[0147] In this way, when programming is performed in order from the upper word line (WLU) to the lower word line (WLB) disposed in the lower part, the programming operation and the word line defect detection operation are performed simultaneously. Since a bridge defect occurs relatively more frequently in the lower word line (WLB) disposed in the lower part, in the process of applying a programming voltage to the lower word line (WLB) disposed in the lower part, the bridge defect occurring in the lower word line (WLB) disposed in the lower part affects the upper part, and it is likely to damage the data of the memory cell in the programmed upper part.

[0148] Therefore, in the operation of the nonvolatile memory device according to the present embodiment, before programming the data received from the host (HOST) in the order from the upper word line (WLU) disposed in the upper part of the memory block (BLK) to the lower word line (WLB) disposed in the lower part, it is preliminarily checked whether a bridge defect of the lower word line (WLB) susceptible to defects exists. Since the durability of the lower word line (WLB) should not be a problem in the process of checking such defects, a first programming voltage (V1) much smaller than a second programming voltage (V2) used for programming data is used to check whether a bridge defect exists on the lower word line (WLB).

[0149] When programming is performed in this manner, storage reliability of data stored in a memory cell can be improved, and since a program operation is immediately stopped if a word line defect is detected, operation performance of a nonvolatile memory device can also be improved.

[0150] Summarizing the detailed description, those skilled in the art will appreciate that many variations and modifications can be made to the preferred embodiments without departing substantially from the principles of the present disclosure. Therefore, the preferred embodiments of the present invention disclosed are used only in a general and descriptive sense, and not for limiting purposes.

Claims

1. A storage device, comprising: A memory cell array, the memory cell array comprising a first memory cell disposed on a substrate and a second memory cell located above the first memory cell; a first word line connected to the first memory cell and a second word line connected to the second memory cell, the second word line being disposed above the first word line; a clock generator configured to generate a pump clock signal when the pump voltage is lower than a reference pump voltage; a voltage generator configured to generate the pumping voltage in response to the pumping clock signal, and to generate a first voltage and a second voltage greater than the first voltage based on the pumping voltage; as well as a word line defect detection circuit configured to monitor the number of pulses of the pump clock signal when the first voltage is applied to the first word line to detect a defect of the first word line, The voltage generator is configured to apply the second voltage to the second word line to program the second memory cell when the number of pulses of the pump clock signal is less than a reference value.

2. The storage device according to claim 1, wherein: The voltage generator is configured to apply the second voltage to the first word line to program the first memory cell after programming of the second memory cell is completed.

3. The storage device according to claim 1, wherein: The first word line includes a third word line and a fourth word line disposed above the third word line, The second word line includes a fifth word line and a sixth word line disposed above the fifth word line. Wherein, a first interval between the third word line and the fourth word line is different from a second interval between the fifth word line and the sixth word line.

4. The storage device according to claim 3, wherein: The first interval is smaller than the second interval.

5. The storage device according to claim 1, wherein: The word line defect detection circuit comprises: a counter configured to count the number of pulses of the pump clock signal; and A comparator is configured to compare the number of pulses of the pump clock signal with the reference value to determine whether the first word line has a defect.

6. The storage device according to claim 1, wherein: The voltage generator comprises: a determination signal generator configured to compare the pumping voltage with a reference pumping voltage to output a determination signal, The clock generator is configured to generate the pump clock signal based on the determination signal and a system clock signal.

7. The storage device according to claim 1, wherein: The word line defect detection circuit is configured to monitor the number of pulses of the pump clock signal after an erase operation on a memory block including the first memory cell and the second memory cell is completed.

8. A method for operating a storage device, the method comprising: Providing a memory cell array, the memory cell array comprising a first memory cell disposed on a substrate, a first word line connected to the first memory cell, a second memory cell disposed above the first memory cell, and a second word line disposed above the first word line and connected to the second memory cell; generating a pump clock signal when the pump voltage is lower than the reference pump voltage; generating the pumping voltage in response to the pumping clock signal, and generating a first voltage and a second voltage greater than the first voltage based on the pumping voltage; detecting a defect of the first word line by monitoring a first number of pulses of the pump clock signal when the first voltage is applied to the first word line; as well as When a first number of pulses of the pump clock signal is less than a first reference value, the second memory cell is programmed by applying the second voltage to the second word line.

9. The method according to claim 8, further comprising: After programming of the second memory cell is completed, the first memory cell is programmed by applying the second voltage to the first word line.

10. The method according to claim 8, further comprising: Before detecting a defect of the first word line, performing an erase operation on a memory block including the first memory cell and the second memory cell, When the erase operation on the storage block fails, the operation of detecting defects of the first word line is not performed, and when the erase operation on the storage block passes, the operation of detecting defects of the first word line is performed.

11. The method according to claim 8, wherein: Programming the second storage unit includes: A second number of pulses of the pump clock signal is monitored while the second voltage is applied to the second word line to detect a defect of the second word line.

12. The method according to claim 11, wherein: Programming the second storage unit further includes: When a second number of pulses of the pump clock signal is greater than or equal to a second reference value, the programming operation on the second memory cell is stopped.

13. A storage device, comprising: A memory cell array, the memory cell array comprising a first memory cell disposed on a substrate, a second memory cell disposed above the first memory cell, and a third memory cell disposed above the second memory cell; A first word line connected to the first memory cell, a second word line connected to the second memory cell, and a third word line connected to the third memory cell, wherein the second word line is arranged above the first word line, and the third word line is arranged above the second word line; a clock generator configured to generate a pump clock signal when the pump voltage is lower than a reference pump voltage; a voltage generator configured to generate the pumping voltage in response to the pumping clock signal, and to generate a first programming voltage and a second programming voltage greater than the first programming voltage based on the pumping voltage; as well as a word line defect detection circuit configured to monitor a first number of pulses of the pump clock signal to detect a defect of the first word line when the first programming voltage is applied to the first word line, wherein, when the first number of pulses of the pump clock signal is less than a first reference value, the word line defect detection circuit is configured to monitor a second number of pulses of the pump clock signal when the first programming voltage is applied to the second word line to detect a defect of the second word line, The voltage generator is configured to apply the second programming voltage to the third word line to program the third memory cell when the second number of pulses of the pump clock signal is less than the first reference value.

14. The storage device according to claim 13, wherein: The voltage generator is configured to apply the second program voltage to the second word line to program the second memory cell after programming of the third memory cell is completed.

15. The storage device according to claim 13, wherein: When a first number of pulses of the pump clock signal is greater than or equal to the first reference value, the storage device is configured such that a storage block including the first to third storage cells is designated as a bad block.

16. The storage device according to claim 13, wherein: The word line defect detection circuit is configured to monitor a third number of pulses of the pump clock signal to detect a defect of the third word line when the second program voltage is applied to the third word line.

17. The storage device according to claim 13, wherein: The memory device is configured such that an erase operation on a memory block including the first to third memory cells is completed before the word line defect detection circuit detects a defect of the first word line.

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