A mid-range test circuit for high output current products

Abstract

The present invention discloses a mid-test circuit for a high output current product, which includes a VEN and VIN comparison module, a current comparison module, and a current sampling module. The current sampling module is used to convert the output current into a smaller current value through the current mirror effect, and the current comparison module compares the reference current to feed back to the current sampling module to output a constant current value. The VEN and VIN comparison module is used to give a mid-test indication signal, so that the output current is reduced to a certain proportion of the original for mid-test. This solution can reduce the output current during mid-test without affecting the actual output high current, so as to adapt to the continuous working current range that the probe can withstand during mid-test for testing, and has more superior performance than traditional protection solutions.

Description

Technical Field

[0001] The invention relates to a mid-test circuit for a high output current product, which is a solution to the problem that excessive current during mid-test of a high output current product may easily cause probe damage or low test accuracy. Background Art

[0002] After the integrated circuit is taped out, in order to check the chip yield, the chip is generally tested at the wafer level. However, the test probe can generally only pass a small continuous current. When encountering a high output current, the probe will be damaged and the test cannot be performed. Or when the current is too large, it will introduce large long-line interference and parasitic voltage drop, causing inaccurate test accuracy. Summary of the invention

[0003] To solve the above problems, the present invention introduces a solution to the problem that excessive current during measurement of high output current products can easily cause probe damage or low test accuracy. The solution reduces the actual current limiting value to a certain proportion on the original basis for medium measurement, avoiding the problem of excessive current damaging the probe and low accuracy.

[0004] The technical solution of the present invention to solve the above problems includes the following modules:

[0005] VEN and VIN comparison module, current comparison module, current sampling module. The VEN and VIN comparison module is used to give the mid-measurement indication signal, and control the current comparison module to use the actual output current or a smaller output current for the sampling current for comparison; the current comparison module is used to compare the sampling current generated by the current sampling module with the reference current, and output feedback to the power tube to control the output current to be basically constant; the current sampling module is used to convert the output current into a smaller current value through the current mirror effect, which is used for comparison with the reference current. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 This is the schematic diagram of the VEN and VIN comparison module;

[0007] Figure 2 This is a schematic diagram of the current comparison module;

[0008] Figure 3 This is a schematic diagram of the current sampling module;

[0009] Figure 4 This is a schematic diagram of the output high current measurement solution;

[0010] Figure 5 This is the simulation waveform. DETAILED DESCRIPTION

[0011] In order to make the above technical contents, features and advantages of the present invention more understandable, the present invention will be further described in detail below.

[0012] Figure 1 It is a VEN and VIN comparison module, which is composed of a first PMOS tube PM1, a first NMOS tube NM1, and a first buffer BUF1. The gate of the first PMOS tube PM1 is connected to the gate of the first NMOS tube NM1 and is also connected to the power supply IN. The source of the first PMOS tube PM1 is connected to the enable input EN, the source of the first NMOS tube NM1 is grounded, the drain of the first PMOS tube PM1 is connected to the drain of the first NMOS tube NM1 and is also connected to the input end of the first buffer BUF1. The output Y1 is used to control the current comparison module to use the actual current limit value and the measured current limit value for the sampled current for comparison.

[0013] Figure 2 It is a current comparison module, which consists of a second PMOS tube PM2, a third PMOS tube PM3, a second NMOS tube NM2, a third NMOS tube NM3, a fourth NMOS tube NM4, and a fifth NMOS tube NM5. The gate of the second PMOS tube PM2 is connected to the output reference voltage of the external reference module. At this time, IdPM2 is the reference current. The source of the second PMOS tube PM2 is connected to the power supply, and the drain is connected to the drain of the second NMOS tube NM2; the source of the second NMOS tube NM2 is grounded, and the gate is connected to the gate of the fourth NMOS tube NM4, the gate and drain of the fifth NMOS tube NM5, and the sampling current provided by the current sampling module is connected, and the sampling current is mirrored to the fourth NMOS tube NM4 and the fifth NMOS tube NM5. Here, the sampling current is connected to

[0014] IdPM2 is a reference current comparison. The comparison result is output and connected to the gate of the third PMOS tube PM3, which is used to control the size of VdPM3 and output Y2 to feed back to the current sampling module. The gate of the third NMOS tube NM3 is connected to the output end of the first buffer BUF1 of the VEN and VIN comparison module, receives the instructions given by the VEN and VIN comparison module, and the drain is connected to the drain of the second PMOS tube PM2, the drain of the second NMOS tube NM2, and the drain of the third PMOS tube PM3. The sampling current compared with the reference current IdPM2 is selected as IdNM2 or the sum of IdNM2 and IdNM4. By adjusting the ratio of the width-to-length ratio of the fourth NMOS tube NM4 to the width-to-length ratio of the second NMOS tube NM2, the output current can be adjusted.

[0015] The ratio of the width to length ratio of the fourth NMOS tube NM4 to the width to length ratio of the second NMOS tube NM2 is 3. The source of the third NMOS tube NM3 is connected to the drain of the fourth NMOS tube NM4, and the source of the fourth NMOS tube NM4 and the source of the fifth NMOS tube NM5 are grounded.

[0016] Figure 3 The current sampling module is composed of a fourth PMOS tube PM4, a fifth PMOS tube PM5, a sixth PMOS tube PM6, and a first operational amplifier OP1. The fourth PMOS tube PM4 is a power tube, the fifth PMOS tube PM5 is a sampling tube, the gates of the power tube PM4 and the sampling tube PM5 are connected to the drain of the third PMOS tube PM3 of the current comparison module, and are used to receive the output feedback signal of the current comparison module and adjust the output current IOUT. The sources of the power tube PM4 and the sampling tube PM5 are connected to the power supply, the drain of the power tube PM4 is connected to the output port OUT and the negative input terminal of the first operational amplifier OP1, and the drain of the sampling tube PM5 is connected to the positive input terminal of the first operational amplifier OP1.

[0017] The input terminal and the source of the sixth PMOS tube PM6, the output of the first operational amplifier OP1 is connected to the gate of the sixth PMOS tube PM6, the sixth PMOS tube PM6 is controlled and fed back to the sampling tube PM5, that is, when VdPM5>VOUT, the output of the first operational amplifier OP1 is positive, the gate voltage of the sixth PMOS tube PM6 is controlled to increase, the sixth PMOS tube PM6 is not easy to conduct, so that the VdPM5 of the sampling tube PM5 is reduced, forming a negative feedback, and finally making VdPM5=VOUT, that is, by adjusting the width-to-length ratio of the sampling tube PM5 and the power tube PM4, the sampling tube PM5 can sample the output current of the power tube PM4 more accurately according to a certain ratio, and the output Y3 is transmitted to the fifth NMOS tube NM5 of the current comparison module. To complete the entire process of current sampling, current comparison and voltage comparison and control of output current.

[0018] Figure 4 For the output high current mid-measurement solution, it can be seen that the current sampling module completes the matching of the sampling tube and the power tube through negative feedback to form a sampling current. The sampling current is compared with the reference current of the reference voltage provided by the external current through the current mirror image, and the output is fed back to the power tube, forming a negative feedback as a whole, so that the output current is basically constant. When mid-measurement is required, the EN voltage is intentionally raised to turn on the PM1 tube, and the high voltage is output to the switch tube NM3 after rectification by the BUF, so that NM3 is turned on. At this time, the width-to-length ratio (W) of NM4 and NM2 is adjusted. NM4 / L NM4 ) / (W NM2 / L NM2 )=n, at this time INM4_d=nINM2_d, through the negative feedback loop, the final output current is made 1 / (n+1) of the original. This design can not only achieve a higher output current, but also improve reliability and accuracy during measurement.

[0019] Figure 5To simulate the waveform, add 5V to VIN. When VEN is increased from 5V to above 5V+VthPM1, the output current will become 1 / (n+1) of the original output.

[0020] The present invention provides a solution to the problem that excessive current during measurement of a high output current product may easily cause probe damage or low test accuracy. The advantage is that the protection solution can proportionally adjust the output current during measurement without affecting the high output current of the device itself, thereby achieving the purpose of accurate testing.

[0021] The content, advantages and working methods of the present invention have been disclosed above, however, the present invention described above is only briefly or only relates to a specific part of the present invention, and the features of the present invention may be more than those disclosed herein. Therefore, the protection scope of the present invention should not be limited to the content disclosed in the embodiments, but should include the combination of all the contents embodied in different parts, as well as various substitutions and modifications that do not deviate from the present invention, and are covered by the claims of the present invention.

Claims

1. A test circuit for a high output current product, characterized in that , including VEN and VIN comparison module, current comparison module, and current sampling module; wherein the VEN and VIN comparison module is used to give a mid-measurement indication signal, and control the current comparison module to use the actual output current or a smaller output current for the sampling current for comparison; the current comparison module is used to compare the sampling current generated by the current sampling module with the reference current, and output feedback to the power tube to control the output current to be in a constant state; the current sampling module is used to convert the output current into a smaller current value through the current mirror effect, which is used for comparison with the reference current; wherein, The VEN and VIN comparison module is composed of a first PMOS tube PM1, a first NMOS tube NM1, and a first buffer BUF1; the gate of the first PMOS tube PM1 is connected to the gate of the first NMOS tube NM1 and is connected to the power supply IN at the same time, the source of the first PMOS tube PM1 is connected to the enable input EN, the source of the first NMOS tube NM1 is grounded, the drain of the first PMOS tube PM1 is connected to the drain of the first NMOS tube NM1 and is connected to the input end of the first buffer BUF1 at the same time, the output end Y1 of the first buffer BUF1 is connected to the gate of the third NMOS tube NM3 in the current comparison module, and the output end Y1 of the first buffer BUF1 is used to control the current comparison module to use the actual current limit value and the measured current limit value for the sampled current for comparison; The current comparison module is composed of a second PMOS tube PM2, a third PMOS tube PM3, a second NMOS tube NM2, a third NMOS tube NM3, a fourth NMOS tube NM4, and a fifth NMOS tube NM5; the gate of the second PMOS tube PM2 is connected to the output reference voltage of the external reference module, at which time IdPM2 is the reference current, the source of the second PMOS tube PM2 is connected to the power supply, and the drain is connected to the drain of the second NMOS tube NM2; the source of the third PMOS tube PM3 is connected to the power supply; the source of the second NMOS tube NM2 is grounded, and the gate is connected to the gate of the fourth NMOS tube NM4, the gate and drain of the fifth NMOS tube NM5, and the sampling current provided by the current sampling module is connected and mirrored to the fourth NMOS tube NM4 and the fifth NMOS tube NM5. Here, the sampling current is compared with IdPM2 as the reference current, and the comparison result is output and connected to the gate of the third PMOS tube PM3 to control The size of VdPM3 is output and Y2 is fed back to the current sampling module; the gate of the third NMOS tube NM3 is connected to the output end of the first buffer BUF1 of the VEN and VIN comparison module, receives the instruction given by the VEN and VIN comparison module, and the drain is connected to the drain of the second PMOS tube PM2, the drain of the second NMOS tube NM2, and the drain of the third PMOS tube PM3, and the sampling current compared with the reference current IdPM2 is selected to be IdNM2 or the sum of IdNM2 and IdNM4. By adjusting the ratio of the width-to-length ratio of the fourth NMOS tube NM4 to the width-to-length ratio of the second NMOS tube NM2, the value of the output current can be adjusted, and the ratio of the width-to-length ratio of the fourth NMOS tube NM4 to the width-to-length ratio of the second NMOS tube NM2 is 3; the source of the third NMOS tube NM3 is connected to the drain of the fourth NMOS tube NM4, and the source of the fourth NMOS tube NM4 and the source of the fifth NMOS tube NM5 are grounded.

2. The intermediate test circuit of the high output current product according to claim 1 is characterized in that The current sampling module is composed of a fourth PMOS tube PM4, a fifth PMOS tube PM5, a sixth PMOS tube PM6, and a first operational amplifier OP1; wherein the fourth PMOS tube PM4 is a power tube, the fifth PMOS tube PM5 is a sampling tube, the gates of the power tube PM4 and the sampling tube PM5 are connected to the drain of the third PMOS tube PM3 of the current comparison module, and are used to receive the output feedback signal of the current comparison module and adjust the output current IOUT, the sources of the power tube PM4 and the sampling tube PM5 are connected to the power supply, the drain of the power tube PM4 is connected to the output port OUT and the negative input terminal of the first operational amplifier OP1, the drain of the sampling tube PM5 is connected to the positive input terminal of the first operational amplifier OP1 and the source of the sixth PMOS tube PM6, and the first operational amplifier OP1 is connected to the output port OUT. The output of P1 is connected to the gate of the sixth PMOS tube PM6, controls the sixth PMOS tube PM6 and feeds back to the sampling tube PM5, that is, when VdPM5>VOUT, the output of the first operational amplifier OP1 is positive, controls the gate voltage of the sixth PMOS tube PM6 to increase, and the sixth PMOS tube PM6 is not easily turned on, so that VdPM5 of the sampling tube PM5 is reduced, forming negative feedback, and finally making VdPM5=VOUT, that is, by adjusting the width-to-length ratio of the sampling tube PM5 and the power tube PM4, the sampling tube PM5 can accurately sample the output current of the power tube PM4 according to a certain ratio; the drain terminal Y3 of the sixth PMOS tube PM6 is connected to the gate and drain of the fifth NMOS tube NM5 in the current comparison module, so as to convert the sampled current into a sampled voltage output.

3. The intermediate test circuit of the high output current product according to claim 1 is characterized in that The current sampling module completes the matching of the sampling tube and the power tube through negative feedback to form a sampling current. The sampling current is compared with the reference current biased by the reference voltage provided by the external current through the current mirror image, and the output is fed back to the power tube, forming a negative feedback as a whole, so that the output current is basically constant. When the intermediate measurement is required, the EN voltage is intentionally raised to turn on the PM1 tube, and the high voltage is output to the switch tube NM3 after rectification by BUF, so that NM3 is turned on. At this time, the width-to-length ratio (W) of NM4 and NM2 is adjusted. NM4 / NM4 ) / (W NM2 / L NM2 )=n, at this time INM4_d=nINM2_d, through the negative feedback loop, the final output current is made to be 1 / (n+1) of the original.

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