Semiconductor structure

Abstract

Provided are a semiconductor structure and a method of forming the same. The semiconductor structure includes a gate structure, a source / drain structure, a first contact plug, and a first via plug. The gate structure is located above a fin structure. The source / drain structure is located in the fin structure and adjacent to the gate structure. The first contact plug is located above the source / drain structure. The first via plug is located above the first contact plug, and the first via plug includes a first group of Group IV elements.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor technology, and more particularly to semiconductor structures. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in integrated circuit materials and design have produced generations of integrated circuits, each generation having smaller and more complex circuits than the previous one. However, these advances have increased the complexity of processing and manufacturing integrated circuits, and similar developments are required in processing and manufacturing integrated circuits to achieve these advancements. In the history of integrated circuits, the functional density (i.e., the number of devices interconnected per chip area) has increased while the geometric size (i.e., the smallest component produced in the manufacturing process) has decreased.

[0003] Despite the breakthroughs in materials and manufacturing, miniaturizing planar devices such as metal-oxide-semiconductor field effect transistors (MOSFETs) remains challenging. To overcome these challenges, circuit designers have sought novel structures to provide improved performance, thus leading to the development of three-dimensional designs such as fin field effect transistors (FinFETs). A fin field effect transistor is fabricated with thin vertical "fins" (or fin structures) extending upward from a substrate. The channel of the fin field effect transistor is formed in this vertical fin. A gate is provided above the fin such that the gate controls the channel from multiple sides. The advantages of a fin field effect transistor may include reducing short-channel effects, reducing leakage, and increasing current.

[0004] However, as the feature size continues to shrink, the manufacturing process continues to become more difficult to perform. Therefore, it is a challenge to form reliable semiconductor structures with increasingly smaller sizes that include fin field effect transistors. Summary of the Invention

[0005] In some embodiments, a semiconductor structure is provided that includes a gate structure located above a fin structure; a source / drain structure located in the fin structure and adjacent to the gate structure; a first contact plug located above the source / drain structure; and a first via plug located above the first contact plug, wherein the first via plug includes a first group of group IV elements.

[0006] In some other embodiments, a semiconductor structure is provided, which includes a gate structure located above a fin structure; source / drain structures located in the fin structure and adjacent to the gate structure; a dielectric layer located above the gate structure and the source / drain structures; and via plugs penetrating the dielectric layer, wherein the via plugs include a first group of group-IV elements and the dielectric layer includes a second group of group-IV elements.

[0007] In some other embodiments, a method of forming a semiconductor structure is provided, the method including forming a gate structure above a fin structure; forming source / drain structures in the fin structure and adjacent to the gate structure; forming contact plugs above the source / drain structures; forming a dielectric layer above the contact plugs; forming an opening in the dielectric layer to expose the contact plugs; depositing a metal material to fill the opening; implanting a first group of group-IV elements into the metal material; and removing a portion of the metal material on the top surface of the dielectric layer to form via plugs above the contact plugs. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments of the present invention can be better understood according to the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to the standard practice in the industry, various components in the drawings are not necessarily drawn to scale. In fact, the dimensions of various components may be arbitrarily enlarged or reduced for clear illustration.

[0009] Figure 1 FIG. 12 is a three-dimensional view of an exemplary simplified fin field-effect transistor (FinFET) according to some embodiments.

[0010] FIGS. 2A-2I are cross-sectional schematic views of various stages of a process of forming a semiconductor structure along line A-A' according to some embodiments. Figure 1

[0011] LIST OF REFERENCE NUMERALS

[0012] 200 Substrate

[0013] 204 Fin structure

[0014] 205, 208, 263, 278A, 278B, 278C Top surface

[0015] 206 Isolation region

[0016] 207 First isolation region

[0017] 210, 243A, 243B, 261, 277A, 277B, 277C Bottom surface

[0018] 218, 218A, 218B, 218C Gate spacer

[0019] ​220, 220A, 220B Source / Drain Structure

[0020] 221 Contact Etch Stop Layer

[0021] 222, 226, 262 Dielectric Layer

[0022] 232A, 232B, 232C, 264A, 264B, 264C Opening

[0023] 233A, 233B, 233C, 265A, 265B, 265C Sidewall Surface

[0024] 240A, 240B, 240C Source / Drain Silicide Layer

[0025] 242A, 242B, 242C Adhesion Layer

[0026] 244A, 244B, 244C Contact Plug

[0027] 252, 252A, 252B, 252C Gate Dielectric Layer

[0028] 254, 254A, 254B, 254C Gate Electrode Layer

[0029] 255A, 255B, 255C Sidewall

[0030] 256, 256A, 256B, 256C Gate Structure

[0031] 260 Etch Stop Layer

[0032] 266 Metal Material

[0033] 270 Normal

[0034] 272 Implantation Process

[0035] 274 First Group of Group-IV Elements

[0036] 276A, 276B, 276C Through-Hole Plug

[0037] 284 Neck

[0038] 350A First Region

[0039] 350B Second Region

[0040] 350C Third Region

[0041] 500, 500A, 500B Fin Field-Effect Transistor

[0042] 500C Input / Output Device

[0043] 600 semiconductor structure

[0044] Angles θ1 and θ2 Detailed implementation manners

[0045] It should be understood that the following disclosure provides many different embodiments or examples for implementing different components of the provided subject matter. Specific examples of various components and their arrangements are described below to simplify the description of the disclosure. Of course, these are only examples and are not intended to limit the present invention. For example, the following disclosure describes forming a first component on or above a second component, which means that it includes embodiments where the formed first component and the second component are in direct contact, and also includes embodiments where additional components can be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. In addition, repeated reference symbols and / or words may be used in different examples in the disclosure. These repeated symbols or words are for the purpose of simplification and clarity and are not intended to limit the relationship between various embodiments and / or the described appearance structures.

[0046] Furthermore, for the convenience of describing the relationship between an element or component in the drawings and another element or component(s), spatial relative terms may be used, such as "under", "below", "lower part", "above", "upper part" and similar terms. In addition to the orientations shown in the drawings, spatial relative terms also cover different orientations during the use or operation of the device. The device can also be positioned otherwise (for example, rotated 90 degrees or in other orientations), and the descriptions of the spatial relative terms used can be interpreted accordingly.

[0047] Some embodiments of the present invention are described below. Additional operations can be provided before, during, and / or after the stages described in these embodiments. For different embodiments, some of the described stages can be replaced or eliminated. Additional components can be added to the semiconductor device structure. For different embodiments, some of the components described below can be replaced or eliminated. Although some embodiments are discussed with operations performed in a specific order, these operations can be performed in other logical orders.

[0048] The fin can be patterned by any suitable method. For example, the fin can be patterned by using one or more lithography processes, including double patterning or multiple patterning processes. Generally, double patterning or multiple patterning processes combine lithography and self-alignment processes to create patterns with smaller pitch. For example, the pattern has a smaller pitch than that obtainable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned by using a lithography process. Spacers are formed beside the patterned sacrificial layer by using a self-alignment process. Then, the sacrificial layer is removed, and the fin can then be patterned using the remaining spacers.

[0049] Figure 1 A three-dimensional (3D) view showing an example of a simplified fin field-effect transistor (FinFET) 500 according to some embodiments is presented. Regarding Figure 1 Other aspects not shown or described may be readily apparent from the following drawings and description. Each fin field-effect transistor 500 includes a portion of a fin structure 204 on a substrate 200. The fin structure 204 of the substrate 200 protrudes above a top surface 208 of an isolation region 206 (e.g., a shallow trench isolation structure) on the substrate 200. Additionally, the fin structure 204 may be formed between adjacent isolation regions 206. Each fin field-effect transistor 500 includes a gate structure 256 over the fin structure 204. The gate structure 256 may include a gate dielectric layer 252 and a gate electrode layer 254. The gate dielectric layer 252 may be disposed along sidewalls of the fin structure 204 and above a top surface of the fin structure 204, and the gate electrode layer 254 may be disposed above the gate dielectric layer 252. Gate spacer walls 218 may be disposed along sidewalls of the gate dielectric layer 252. Each fin field-effect transistor 500 includes source / drain structures 220 disposed in two side regions of the fin structure 204 relative to the gate dielectric layer 252 and the gate electrode layer 254. Figure 1 A reference cross-section along line A-A' is further shown, which is for the subsequent drawings. The cross-section along line A-A' may be, for example, a plane along a channel region in the fin structure 204 between the source / drain structures 220 on both sides.

[0050] For example, the source / drain structures 220 may be shared among various transistors. In some examples, the source / drain structures 220 may be connected or coupled to other fin field-effect transistors such that these fin field-effect transistors are implemented as one functional transistor. For example, if adjacent (e.g., opposite) source / drains are electrically connected, such as by coalescing regions through epitaxial growth, one functional transistor can be realized. In other examples, other configurations may implement other numbers of functional transistors.

[0051] Embodiments of the present invention provide a semiconductor structure and a method of forming the same. FIGS. 2A-2I are cross-sectional schematic views of various stages of a process of forming a semiconductor structure 600 along a line A-A' Figure 1 as shown. It should be noted that the cross-sectional schematic view of the semiconductor structure is taken along the length direction of the fin structure (e.g., fin structure 204) of the semiconductor structure (i.e., the channel length direction of the fin field-effect transistor).

[0052] In some embodiments, a gate replacement (post-gate) process is used to fabricate the semiconductor structure 600. For example, the semiconductor structure 600 includes fin field-effect transistors (FinFETs) (e.g., fin field-effect transistors 500A and 500B) or input / output (I / O) devices (e.g., input / output (I / O) device 500C).

[0053] As Figure 2A shown, the substrate 200 includes receiving fin structures 204. In some embodiments, the substrate 200 may be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, and may be doped (e.g., with P-type or N-type dopants) or undoped. The substrate 200 may be a wafer, such as a silicon wafer. Generally, a semiconductor-on-insulator substrate includes a semiconductor material layer formed on an insulating layer. For example, the insulating layer may be a buried oxide (BOX) layer, a silicon oxide layer, or the like. An insulating layer is provided on the substrate, and the substrate is generally a silicon substrate or a glass substrate, and other substrates, such as a multi-layer substrate or a gradient substrate, may also be used. In some embodiments, the semiconductor material of the substrate 200 may include silicon, germanium, compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), alloy semiconductors (including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP), or a combination of the foregoing.

[0054] In some embodiments, the substrate 200 has a first region 350A, a second region 350B, and a third region 350C. The second region 350B may be adjacent to the first region 350A, and the third region 350C is adjacent to the second region 350B. The first region 350A may be used to form N-type devices, such as N-type metal-oxide-semiconductor field-effect transistors (MOSFETs) (e.g., fin field-effect transistor 500A). The second region 350B may be used to form P-type devices, such as P-type metal-oxide-semiconductor field-effect transistors (MOSFETs) (e.g., fin field-effect transistor 500B). The third region 350C may be used to form input / output (I / O) devices (e.g., input / output device 500C). Thus, the first region 350A may be referred to as an N-type metal-oxide-semiconductor field-effect transistor (NMOS) region, the second region 350B may be referred to as a P-type metal-oxide-semiconductor field-effect transistor (PMOS) region, and the third region 350C may be referred to as an input / output device region.

[0055] In some embodiments, the fin structure 204 is formed by performing a patterning process on the substrate 200. The fin structure 204 may include a first isolation region 207 (e.g., a shallow trench isolation (STI) structure) filled in a first trench buried in the fin structure 204. In addition, the fin structure 204 is surrounded by a second trench (not shown) formed in the substrate 200 by a patterning process. A second isolation region (not shown) (e.g., a shallow trench isolation (STI) structure) may be formed on the bottom surface 210 of each trench. The lower portion of the fin structure 204 is surrounded by the second isolation region, and the upper portion of the fin structure 204 protrudes from the top surface 208 of each second isolation region.

[0056] After forming the isolation regions, a dummy gate structure (not shown) is formed above the top surface 205 of the fin structure 204. In addition, a hard mask layer is formed on the dummy gate structure. In some embodiments, the dummy gate structure covers the channel regions of the final fin field-effect transistors (e.g., fin field-effect transistors 500A and 500B) of the fin structure 204 individually. In addition, the dummy gate structures may be separated from each other by the first isolation region 207. In some embodiments, the dummy gate structure covers the top surface 205 and sidewalls of the fin structure 204 and extends above the isolation regions and the substrate 200 outside the fin structure 204. In some embodiments, each dummy gate structure includes a gate dielectric (not shown) and a gate electrode (not shown) formed above the gate dielectric.

[0057] After that, according to some embodiments, as Figure 2AAs shown, gate spacer walls 218A, 218B, and 218C are formed on both sidewalls of the dummy gate structure and above the fin structure 204. The gate spacer walls 218A, 218B, and 218C may include a single-layer structure or a multi-layer structure. The gate spacer walls 218A, 218B, and 218C may be made of a low dielectric constant (low-k) material (e.g., k < 5), such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, other suitable materials, or a combination of the foregoing. In some embodiments, the gate spacer walls 218A, 218B, and 218C are formed by a deposition process and a subsequent etching process. The deposition process may include a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a spin coating process, other applicable processes, or a combination of the foregoing. The etching process may include a dry etching process.

[0058] According to some embodiments, as Figure 2A shown, after the gate spacer walls 218A, 218B, and 218C are formed, source / drain structures 220A and 220B are formed in portions not covered by the dummy gate structure and the gate spacer walls 218A, 218B, and 218C. The source / drain structures 220A and 220B may be formed in the fin structure 204 and are adjacent to the gate spacer wall 218A and the gate spacer wall 218B. In addition, the source / drain structure 220A is separated from the source / drain structure 220B by a first isolation region 207.

[0059] In some embodiments, the source / drain structures 220A and 220B may include a strained material to apply stress to the channel region. For example, the source / drain structures 220A and 220B are formed of Ge, SiGe, InAs, InGaAs, InSb, GaAs, GaSb, InAlP, InP, or the like. In some embodiments, the lattice constants of the source / drain structures 220A and 220B are different from the lattice constant of the fin structure 204. In some embodiments, the source / drain structures 220A and 220B have a hexagonal shape as Figure 2A shown, but the embodiments of the present invention are not limited thereto. In some other embodiments, the source / drain structures 220A and 220B may be diamond-shaped, any other applicable shape, or a combination of the foregoing. In addition, the bottoms of the source / drain structures 220A and 220B may be located below the top surface 208 of each isolation structure surrounding the fin structure 204.

[0060] The source / drain structures 220A and 220B can be formed by an etching process or a subsequent filling process. An etching process is performed to form notches (not shown) adjacent to the gate spacer walls 218A and 218B and located in the fin structure 204. In some embodiments, the etching process is a dry etching process. In some embodiments, the filling process (not shown) is performed by filling the notches with one or more strained semiconductor materials to form the source / drain structures 220A and 220B. In some embodiments, the filling process includes an epitaxial process, such as a selective epitaxial growth (SEG) process, a chemical vapor deposition technique (such as vapor-phase epitaxy (VPE) and / or ultra-high vacuum chemical vapor deposition (UHV-CVD)), molecular beam epitaxy, or other applicable epitaxial processes.

[0061] According to some embodiments, as Figure 2A shown, after the source / drain structures 220A and 220B are formed, a contact etch stop layer (CESL) 221 is conformally deposited over the source / drain structures 220A and 220B and the gate spacer walls 218A, 218B, and 218C by a thin film deposition process. The contact etch stop layer 221 can serve as an etch stop layer for a subsequent etching process configured to form source / drain contact holes (not shown). In some embodiments, the contact etch stop layer 221 can be a single layer or multiple layers. The contact etch stop layer 221 can be made of silicon carbide (SiC), silicon nitride (SixNy), silicon carbonitride (SiCN), silicon oxynitride (SiOC), silicon oxynitride carbonitride (SiOCN), silicon dioxide (SiO2), or other applicable materials. In some embodiments, the contact etch stop layer 221 has a bilayer structure that includes forming a SiO2 layer on a SiC layer. Additionally, the SiC layer can be used as an adhesion layer to improve the adhesion between the underlying layer and the SiO2 layer. In some embodiments, the contact etch stop layer 221 is formed by a plasma enhanced chemical vapor deposition (PECVD) process, a low pressure chemical vapor deposition process, an atomic layer deposition (ALD) process, or other applicable processes.

[0062] According to some embodiments, as Figure 2AAs shown, after the contact etch stop layer 221 is formed, a dielectric layer 222 (e.g., the first inter-layer dielectric (ILD) layer) is formed over the fin structure 204, dummy gate structure, gate spacer walls 218A, 218B, and 218C, and source / drain structures 220A and 220B. The dielectric layer 222 is formed over the contact etch stop layer 221 and may fill the gaps between the dummy gate structures. In some embodiments, the dielectric layer 222 surrounds the dummy gate structures.

[0063] In some embodiments, a deposition process is performed to form the dielectric layer 222 over the contact etch stop layer 221. Thereafter, a planarization process is performed to make the top surfaces of the contact etch stop layer 221, dielectric layer 222, gate spacer walls 218A and 218B, and the dummy gate structure flush.

[0064] In some embodiments, dielectric layer 222 is made of a dielectric material such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), carbon-doped silicate glass, silicon nitride, or silicon oxynitride. In some embodiments, dielectric layer 222 is made of an extreme low-k (ELK) material having a dielectric constant (k) less than about 2.5. As the geometric dimensions are gradually reduced as the technology node progresses to 30 nm and above, the extreme low-k dielectric material is used to minimize the resistance capacitance (RC) delay of the device. In some embodiments, the extreme low-k dielectric material includes carbon-doped silicon oxide, amorphous fluorocarbon, parylene, bis-benzocyclobutenes (BCB), polytetrafluoroethylene (PTFE) (Teflon), or silicon oxycarbide polymer (SiOC). In some embodiments, the extreme low-k dielectric material includes a porous type of the existing dielectric material, such as hydrogen silsesquioxane (HSQ), porous methylsilsesquioxane (MSQ), porous polyarylether (PAE), porous SiLK, or porous silicon dioxide (SiO2). In some embodiments, the extreme low-k dielectric material is deposited by a plasma-enhanced chemical vapor deposition (PECVD) process or a spin coating process.

[0065] In some embodiments, the deposition process of dielectric layer 222 includes a plasma-enhanced chemical vapor deposition (PECVD) process, a low-pressure chemical vapor deposition process, an atomic layer deposition (ALD) process, a flowable chemical vapor deposition (FCVD) process, a spin coating process, or other applicable processes. In some embodiments, the planarization process includes a chemical mechanical polishing (CMP) process, a grinding process, an etching process, other applicable processes, or a combination of the foregoing.

[0066] According to some embodiments, as Figure 2AAs shown, after forming the dielectric layer 222, the gate structures 256A, 256B, and 256C are formed by a removal process, a deposition process, and a subsequent planarization process to replace the dummy gate structures. In some embodiments, the gate structure 256A surrounded by the gate spacer 218A includes a gate dielectric layer 252A and a gate electrode layer 254A above the gate dielectric layer 252A. Similarly, the gate structure 256B surrounded by the gate spacer 218B may include a gate dielectric layer 252B and a gate electrode layer 254B above the gate dielectric layer 252B. The gate structure 256C surrounded by the gate spacer 218C may include a gate dielectric layer 252C and a gate electrode layer 254C above the gate dielectric layer 252C. In some embodiments, the gate spacer 218A is located on the two sidewalls 255A of the gate structure 256A. The gate spacer 218B may be located on the two sidewalls 255B of the gate structure 256B. The gate spacer 218C may be located on the two sidewalls 255C of the gate structure 256C.

[0067] In some embodiments, the gate dielectric layers 252A, 252B, and 252C include a single layer or multiple layers. In some embodiments, the gate dielectric layers 252A, 252B, and 252C are U-shaped or rectangular. In some embodiments, the gate dielectric layers 252A, 252B, and 252C are formed of silicon oxide, silicon nitride, or a high-k dielectric material (k>7.0) (including metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb) or a combination of the foregoing. The formation method of the gate dielectric layers 252A, 252B, and 252C may include molecular beam deposition (MBD), atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), or similar methods.

[0068] In some embodiments, the gate electrode layers 254A, 254B, and 254C are made of a metal-containing material, such as TiN, TaN, TaC, Co, Ru, Al, a combination of the foregoing, or multiple layers of the foregoing, and may be formed by a deposition process, such as electroplating, electroless plating, or other suitable methods.

[0069] In some embodiments, a work function layer (not shown) may be formed in the gate structures 256A, 256B, and 256C. The work function layer may include an N-type work function layer or a P-type work function layer. The P-type work function layer may include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable P-type work function materials, or a combination of the foregoing. The N-type work function layer may include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable N-type work function materials, or a combination of the foregoing. In some embodiments, the work function layer in the gate structure 256A may include an N-type work function layer, while the gate structure 256B may include a P-type work function layer.

[0070] After that, according to some embodiments, as Figure 2A shown, a dielectric layer (e.g., a second interlayer dielectric (ILD) layer) 226 is formed over the dielectric layer 222 and the gate structures 256A, 256B, and 256C. For example, the dielectric layer 226 may be a flowable film formed by a flowable chemical vapor deposition method. In some embodiments, the dielectric layer 226 is formed of a dielectric material, such as phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, undoped silicate glass, or the like, and the dielectric layer 226 may be deposited by any suitable method, such as chemical vapor deposition and plasma-enhanced chemical vapor deposition.

[0071] According to some embodiments, as Figure 2B shown, after forming the dielectric layer 226, openings 232A, 232B, and 232C are formed in the dielectric layers 222 and 226 by a patterning process. In some embodiments, the patterning process may be performed to remove a portion of the dielectric layers 222 and 226 and the contact etch stop layer 221 to form the openings 232A, 232B, and 232C, and stop on the source / drain structures 220A and 220B and the gate structure 256C. Thus, the openings 232A, 232B, and 232C are formed to penetrate the dielectric layers 222 and 226 and the contact etch stop layer 221 to expose the source / drain structures 220A and 220B and the gate structure 256C. In some embodiments, the patterning process also removes a portion of the source / drain structures 220A and 220B. Thus, the lower portions of the openings 232A, 232B, and 232C are buried in the source / drain structures 220A and 220B.

[0072] In some embodiments, the patterning process of openings 232A, 232B, and 232C includes a lithography process and a subsequent etching process. The lithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning, and drying (e.g., hard baking). In some embodiments, the etching process is a dry etching process. In addition, the etching gas used for the etching process includes a fluorine-containing gas. In some embodiments, a mask layer (not shown) may be used in the patterning process. After forming openings 232A, 232B, and 232C, the mask layer can be removed by etching or any other suitable method.

[0073] After that, according to some embodiments, as Figure 2C shown, source / drain silicide layers 240A, 240B, and 240C are formed on source / drain structures 220A and 220B through a silicidation process. In some embodiments, the silicidation process includes a metal material deposition process and an annealing process carried out in sequence. In some embodiments, the deposition process of the silicidation process includes a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or other applicable processes. In some embodiments, the annealing process of the silicidation process is carried out in a temperature range of about 300 °C to about 800 °C. After the annealing process, the unreacted metal material is removed.

[0074] In some embodiments, source / drain silicide layers 240A, 240B, and 240C are composed of one or more cobalt silicides (e.g., CoSi, CoSi2, Co2Si, Co3Si, collectively referred to as "cobalt silicides"), titanium silicides (e.g., Ti5Si3, TiSi, TiSi2, TiSi3, Ti6Si4, collectively referred to as "titanium silicides"), nickel silicides (e.g., Ni3Si, Ni 31 Si 12 , Ni2Si, Ni3Si2, NiSi, NiSi2, collectively referred to as "nickel silicides"), copper silicides (Cu 17 Si3, Cu 56 Si 11 , Cu5Si, Cu 33 Si7, Cu4Si, Cu 19 Si6, Cu3Si, Cu 87 Si 13 , collectively referred to as "copper silicides"), tungsten silicides (W5Si3, WSi2, collectively referred to as "tungsten silicides"), molybdenum silicides (Mo3Si, Mo5Si3, MoSi2, collectively referred to as "molybdenum silicides").

[0075] After that, adhesion layers 242A, 242B, and 242C are formed to cover the sidewall surfaces of openings 232A, 232B, and 232C. According to some embodiments, asFigure 2C As shown, adhesive layers 242A, 242B, and 242C are formed to cover source / drain structures 220A and 220B and gate structure 256C in openings 232A, 232B, and 232C ( Figure 2B ). In addition, contact plugs 244A, 244B, and 244C are formed to fill openings 232A, 232B, and 232C. For example, contact plugs 244A and 244B can be formed to penetrate dielectric layers 222 and 226, and contact plug 244C can be formed to penetrate dielectric layer 226.

[0076] As Figure 2C shown, adhesive layer 242A is conformally formed over source / drain silicide layer 240A and serves as a liner for sidewall surface 233A and the bottom of opening 232A. Adhesive layer 242B is conformally formed over source / drain silicide layer 240B and serves as a liner for sidewall surface 233B and the bottom of opening 232B. Adhesive layer 242C is conformally formed over gate structure 256C and serves as a liner for sidewall surface 233C and the bottom of opening 232C. In addition, bottom surfaces 243A and 243B of adhesive layers 242A and 242B directly contact source / drain silicide layers 240A and 240B, respectively. Moreover, bottom surfaces 243A and 243B of adhesive layers 242A and 242B can be flush with or lower than the top surfaces of source / drain silicide layers 240A and 240B, respectively.

[0077] As Figure 2C shown, adhesive layers 242A, 242B, and 242C surround contact plugs 244A, 244B, and 244C, respectively. Dielectric layers 222 and 226 surround contact plugs 244A, 244B, and 244C. Dielectric layers 222 and 226 surround contact plugs 244A and 244B. Dielectric layer 226 surrounds contact plug 244C. In addition, contact plug 244A is formed over source / drain structure 220A. Contact plug 244B is formed over source / drain structure 220B. Contact plug 244C is formed over gate structure 256C. Moreover, contact plugs 244A and 244B can be electrically connected to source / drain structures 220A and 220B through adhesive layers 242A and 242B, respectively. Contact plug 244C can be electrically connected to gate structure 256C through adhesive layer 242C.

[0078] As Figure 2C shown, contact plugs 244A and 244B can serve as source / drain contact plugs. In addition, contact plug 244C can serve as a contact plug for final input / output device 500C.

[0079] In some embodiments, the adhesion layers 242A, 242B, and 242C and the contact plugs 244A, 244B, and 244C may be formed by a deposition process and a subsequent planarization process (e.g., chemical mechanical polishing). The adhesion layers 242A, 242B, and 242C may comprise an electrically conductive material such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or the like, and the adhesion layers 242A, 242B, and 242C may be formed by a chemical vapor deposition process such as plasma enhanced chemical vapor deposition (PECVD). However, other processes such as sputtering or metal organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), atomic layer deposition (ALD) may also be used. In some embodiments, the contact plugs 244A, 244B, and 244C may be formed of cobalt (Co). In some other embodiments, the contact plugs 244A, 244B, and 244C may be made of a conductive material such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or other applicable materials. The contact plugs 244A, 244B, and 244C may be formed by any suitable deposition method such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, plating (e.g., electroplating).

[0080] After that, according to some embodiments, as Figure 2D shown, an etching stop layer (ESL) 260 is formed on the dielectric layer 226. The etching stop layer 260 may be formed to cover the adhesion layers 242A, 242B, and 242C and the contact plugs 244A, 244B, and 244C. The etching stop layer 260 may be a single layer or multiple layers. The etching stop layer 260 is made of silicon carbide (SiC), silicon nitride (SixNy), silicon carbonitride (SiCN), silicon oxynitride (SiOC), silicon oxynitride carbonitride (SiOCN), silicon dioxide (SiO2), or other applicable materials. In some embodiments, the etching stop layer 260 has a bilayer structure, and the bilayer structure comprises a SiO2 layer formed on a SiC layer. In addition, the SiC layer may be used as an adhesion layer to improve the adhesion between the underlying layer and the SiO2 layer. In some embodiments, the etching stop layer 260 is formed by performing a plasma enhanced chemical vapor deposition (PECVD) process, a low pressure chemical vapor deposition process, an atomic layer deposition (ALD) process, or other applicable processes.

[0081] After that, according to some embodiments, as Figure 2DAs shown, a dielectric layer 262 (such as an inter-metal dielectric (IMD) layer) is formed over the contact plugs 244A, 244B, and 244C. In addition, the dielectric layer 262 may be formed to cover the etch stop layer 260. The dielectric layer 262 may be a single layer or multiple layers. In some embodiments, the dielectric layer 262 is made of silicon oxide. In some other embodiments, the dielectric layer 262 is made of undoped silicate glass (USG), fluorinated silicate glass (FSG), carbon-doped silicate glass, silicon nitride, or silicon oxynitride.

[0082] In some embodiments, the dielectric layer 262 includes an extremely low dielectric constant (ELK) dielectric layer. The extremely low dielectric constant dielectric layer is made of an extremely low dielectric constant dielectric material having a dielectric constant (k) less than about 2.5. The extremely low dielectric constant dielectric material may include carbon-doped silicon oxide, amorphous fluorocarbon, parylene, benzocyclobutene (BCB), polytetrafluoroethylene (PTFE) (Teflon), or silicon oxycarbon polymer (SiOC). In some embodiments, the extremely low dielectric constant dielectric material is made of a porous type of material of an existing dielectric material, such as hydrogen silsesquioxane (HSQ), porous methylsilsesquioxane (MSQ), porous polyaryl ether (PAE), porous SiLK, or porous silicon dioxide (SiO2). In some embodiments, the extremely low dielectric constant dielectric material is deposited by a plasma-enhanced chemical vapor deposition (PECVD) process or a spin coating process.

[0083] After that, according to some embodiments, as Figure 2E shown, openings 264A, 264B, and 264C are formed in the dielectric layer 262 through a patterning process to expose the contact plugs 244A, 244B, and 244C. The patterning process is performed to remove a portion of the dielectric layer 262 and the etch stop layer 260 and stop on the contact plugs 244A and 244B. Thus, the openings 264A and 264B can be formed to penetrate the dielectric layer 262 and the etch stop layer 260. In addition, the patterning process is performed to remove a portion of the dielectric layer 262 on the contact plug 244C. Thus, the opening 264C can be formed to penetrate the dielectric layer 262 and expose the contact plug 244C.

[0084] In some embodiments, the angle θ1 between the sidewall surfaces 265A, 265B, and 265C of the openings 264A, 264B, and 264C and the normal 270 of the top surface 263 of the dielectric layer 226 is about 15° to about 70°.

[0085] In some embodiments, the patterning process includes a lithography process and a subsequent etching process. The lithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning, and drying (e.g., hard baking). The etching process may include a dry etching process or a wet etching process. In some embodiments, the etching process is a dry etching process. Additionally, the etching gas used for the etching process includes a fluorine-containing gas. After forming the openings 264A, 264B, and 264C, the photoresist layer (not shown) may be removed by etching or any other suitable method.

[0086] After that, according to some embodiments, as Figure 2F shown, a metal material 266 is deposited over the dielectric layer 262 and fills the openings 264A, 264B, and 264C. Additionally, a top surface 263 of the dielectric layer 262 is covered by the metal material 266. In some embodiments, the metal material 266 is made of tungsten (W). In some other embodiments, the metal material 266 is made of cobalt (Co), titanium (Ti), aluminum (Al), copper (Cu), tantalum (Ta), platinum (Pt), molybdenum (Mo), silver (Ag), manganese (Mn), zirconium (Zr), ruthenium (Ru), or other applicable materials. In some embodiments, the metal material 266 is formed by any suitable deposition method, such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, or plating (e.g., electroplating).

[0087] After that, according to some embodiments, as Figure 2G shown, an implantation process 272 is performed to implant a first group of Group IV elements 274 into the metal material 266. Thus, after performing the implantation process 272, the metal material 266 may include the first group of Group IV elements 274. The first group of Group IV elements 274 may fill the spaces between the metal ions in the metal material 266. Additionally, the first group of Group IV elements 274 may react with the metal ions in the metal material 266 to form a first compound. In some embodiments, the first group of Group IV elements 274 includes carbon (C), silicon (Si), germanium (Ge), or a combination of the foregoing. For example, when the metal material 266 is tungsten (W), the first compound in the metal material 266 may include tungsten germanium (WGe), tungsten carbide (WC), tungsten disilicide (WSi2), or a combination of the foregoing. The first compound may increase the mechanical strength of the metal material 266.

[0088] In some embodiments, after performing the implantation process 272, a first group of Group-IV elements 274 is implanted into a dielectric layer 262 that contains (or is formed of) a second compound, such as silicon dioxide (SiO2). Thus, after performing the implantation process 272, the dielectric layer 262 may contain the first group of Group-IV elements 274 and a second group of Group-IV elements. The first group of Group-IV elements 274 may be the same as or different from the second group of Group-IV elements. For example, the first group of Group-IV elements 274 includes carbon (C), silicon (Si), or germanium (Ge), and the second group of Group-IV elements may include silicon (Si). In addition, the second group of Group-IV elements (such as silicon (Si)) is uniformly distributed in the dielectric layer 262. Furthermore, the first group of Group-IV elements 274 may react with the dielectric layer 262 to form a third compound. In some embodiments, the third compound may be the same as or different from the second compound. For example, the lattice constant of the third compound may be greater than or equal to the lattice constant of the second compound in the dielectric layer 262. For example, when the second compound is silicon dioxide (SiO2), the third compound may include carbon dioxide (CO2), germanium dioxide (GeO2), or a combination of the foregoing. In addition, after performing the implantation process 272, the dielectric layer 262 may be formed of carbon dioxide (CO2), germanium dioxide (GeO2), or a combination of the foregoing.

[0089] In some embodiments, after implanting the first group of Group-IV elements 274 into the metal material 266 (i.e., after performing the implantation process 272), the maximum concentration of the first group of Group-IV elements 274 in the metal material 266 is located at a position close to the top surface 263 of the dielectric layer 262. In some embodiments, the maximum concentration of the first group of Group-IV elements 274 in the metal material 266 may be located between the top surface 263 and the bottom surface 261 of the dielectric layer 262.

[0090] In some embodiments, after performing the implantation process 272, the maximum concentration of the first group of Group-IV elements 274 in the dielectric layer 262 is located at a position close to the top surface 263 of the dielectric layer 262.

[0091] In some embodiments, the implantation process 272 is performed with an implantation energy in the range of about 25 keV to about 40 keV. For example, when the thickness of the dielectric layer 262 is about The implantation energy of the implantation process 272 may be about 30 keV. In some embodiments, the implantation process 272 is performed with an incident implantation angle θ2 equal to the angle θ1. For example, the first group of Group-IV elements 274 may be implanted into the metal material by the implantation process 272 with an incident implantation angle θ2 in the range of about 15° to about 70°.

[0092] In some embodiments, the implantation process 272 is performed multiple times by rotating the substrate 200. Accordingly, different portions of the metal material 266 and / or the dielectric layer 262 can be implanted with the first group of Group IV elements 274 respectively. For example, the implantation process 272 is performed by rotating the substrate 200 by 90 degrees four times to reposition the substrate 200. Four different positions of the metal material 266 (or the dielectric layer 262) can be implanted with the first group of Group IV elements 274. During the implantation process 272, the first group of Group IV elements 274 can be evenly distributed in the metal material 266 and / or the dielectric layer 262 by rotating the substrate 200.

[0093] In some embodiments, a first compound (such as WGe, WC, or WSi2) in the metal material 266 can contribute to making the structure of the metal material 266 denser. Accordingly, the mechanical strength of the metal material 266 with the first group of Group IV elements 274 can be improved. In some embodiments, a second compound (such as GeO2) in the dielectric layer 262 can contribute to increasing the lattice constant of the dielectric layer 262. After the implantation process 272 is performed, the density of the dielectric layer 262 can be reduced. Accordingly, compressive stress can be generated between the metal material 266 and the dielectric layer 262 after the implantation process 272 is performed. In some embodiments, the maximum compressive stress can be generated at the interface between the metal material 266 and the dielectric layer 262 having the maximum concentration of the first group of Group IV elements 274.

[0094] After implanting the first group of Group IV elements 274 into the metal material 266 (i.e., after performing the implantation process 272), the metal material 266 in each of the openings 264A, 264B, and 264C changes from a tapered shape to a shape having an hourglass shape, as Figure 2H shown in the cross-sectional schematic view. In some embodiments, the metal material 266 in each of the openings 264A, 264B, and 264C has a narrow neck 284 at the position having the maximum concentration of the first group of Group IV elements 274.

[0095] In some embodiments, the difference between the mechanical strength of the metal material 266 and the mechanical strength of the dielectric layer 262 can be reduced. After performing the implantation process 272, the mechanical strengths of the metal material 266 and the dielectric layer 262 can be consistent.

[0096] Afterwards, according to some embodiments, as Figure 2I shown, the portions of the metal material 266 above the top surface 263 of the dielectric layer 262 are removed to form the via plugs 276A, 276B, and 276C. The via plugs 276A, 276B, and 276C can be formed above the contact plugs 244A, 244B, and 244C respectively.

[0097] A planarization process (e.g., chemical mechanical polishing (CMP)) can be performed to make the top surface of the metal material 266 flush with the top surface 263 of the dielectric layer 262. Thus, via plugs 276A, 276B, and 276C are formed to penetrate the dielectric layer 262 and the etch stop layer 260. The dielectric layer 262 surrounds the via plugs 276A, 276B, and 276C. The top surface 263 of the dielectric layer 262 can be flush with the top surfaces 278A, 278B, and 278C of the via plugs 276A, 276B, and 276C. In addition, the bottom surface 261 of the dielectric layer 262 can be located between the top surfaces 278A, 278B, and 278C and the bottom surfaces 277A, 277B, and 277C of the via plugs 276A, 276B, and 276C. Furthermore, the bottom surfaces 277A, 277B, and 277C of the via plugs 276A, 276B, and 276C are in direct contact with the contact plugs 244A, 244B, and 244C, respectively.

[0098] In some embodiments, the planarization process can remove a portion of the dielectric layer 262 from the top surface 263 of the dielectric layer 262. For example, the planarization process can remove Figure 2H a portion of the dielectric layer 262 as shown and a portion of the metal material 266 above or slightly below the neck 284 of the metal material 266 in each of the openings 264A, 264B, and 264C.

[0099] In some embodiments, the concentration of the first group of Group IV elements 274 in the via plugs 276A, 276B, and 276C gradually decreases from the top surfaces 278A, 278B, and 278C to the bottom surfaces 277A, 277B, and 277C of the via plugs 276A, 276B, and 276C. In addition, the concentration of the first group of Group IV elements 274 in the dielectric layer 262 gradually decreases from the top surface 263 to the bottom surface 261 of the dielectric layer 262. Furthermore, the concentration of the second group of Group IV elements (i.e., silicon) is uniform in the dielectric layer 262.

[0100] Since the compressive stress between the via plugs 276A, 276B, and 276C and the dielectric layer 262 can be induced by performing the implantation process 272, the via plugs 276A, 276B, and 276C and the dielectric layer 262 have consistent mechanical strength, so that cracks between the via plugs 276A, 276B, and 276C and the dielectric layer 262 can be sealed or eliminated. Therefore, the slurry for chemical mechanical polishing in the planarization process (e.g., chemical mechanical polishing process) does not attack the via plugs 276A, 276B, and 276C, and thus does not cause loss of the contact plugs 244A, 244B, and 244C.

[0101] After performing the foregoing processes, a fin field-effect transistor 500A is formed in the first region 350A, a fin field-effect transistor 500B is formed in the second region 350B, and an input / output (I / O) device 500C is formed in the third region 350C. Furthermore, according to some embodiments, as Figure 2I shown, a semiconductor structure 600 including a fin field-effect transistor 500A (e.g., an N-type fin field-effect transistor), a fin field-effect transistor 500B (e.g., a P-type fin field-effect transistor), and an input / output device 500C is formed.

[0102] In some embodiments, the semiconductor structure 600 includes via plugs 276A, 276B, and 276C doped with a first group of Group IV elements 274. The first group of Group IV elements 274 can fill the spaces between metal ions in the via plugs 276A, 276B, and 276C. The first group of Group IV elements 274 can react with the metal ions in the via plugs 276A, 276B, and 276C to form a first compound, and the first compound includes tungsten germanium (WGe), tungsten carbon (WC), tungsten silicon (WSi2). In some embodiments, each of the via plugs 276A, 276B, and 276C can include tungsten (W) and the first compound (e.g., tungsten germanium (WGe), tungsten carbon (WC), tungsten silicon (WSi2), or a combination of the foregoing). In some embodiments, the first group of Group IV elements 274 can be doped into a dielectric layer 262 including a second group of Group IV elements (e.g., silicon) (or including a second compound, e.g., silicon dioxide (SiO2)). The first group of Group IV elements 274 can react with the dielectric layer 262 to form a third compound, and the third compound includes carbon dioxide (CO2), silicon dioxide (SiO2), germanium dioxide (GeO2). The lattice constant of the dielectric layer 262 can be increased. Furthermore, the doped first group of Group IV elements 274 can induce compressive stress between the via plugs 276A, 276B, and 276C and the dielectric layer 262. Therefore, the mechanical strength of the via plugs 276A, 276B, and 276C can be improved. In addition, the mechanical strengths of the via plugs 276A, 276B, and 276C and the dielectric layer 262 can become consistent. Cracks occurring at the interface between the via plugs 276A, 276B, and 276C and the dielectric layer 262 can be sealed or eliminated. The via plugs 276A, 276B, and 276C doped with the first group of Group IV elements 274 can prevent the polishing slurry of chemical mechanical polishing from attacking the via plugs 276A, 276B, and 276C. Therefore, the problem of consumption of the contact plugs during the planarization process (e.g., the chemical mechanical polishing process of W) of the via plugs 276A, 276B, and 276C can be eliminated. The problem of increased contact plug resistance can be improved.

[0103] As described above, a semiconductor structure (e.g., semiconductor structure 600) includes via plugs (e.g., first via plugs 276A, 276B, and 276C) containing a first group of Group-IV elements (e.g., first group of Group-IV elements 274). The first group of Group-IV elements can react with the via plugs to form a first compound containing WGe, WC, or WSi2. In addition, a dielectric layer (e.g., dielectric layer 262) surrounding the via plugs can contain the first group of Group-IV elements and a second group of Group-IV elements (e.g., silicon). The first group of Group-IV elements can react with the dielectric layer to form a third compound containing CO2, SiO2, or GeO2. Thus, the structure of the via plugs can be dense. The via plugs and the dielectric layer can have consistent mechanical strength. The problem of consumption of contact plugs during the planarization process of the via plugs can be eliminated. The problem of increased contact plug resistance can be improved.

[0104] Embodiments of the present invention provide a semiconductor structure and a method of forming the same. The semiconductor structure includes a gate structure, source / drain structures, a first contact plug, and a first via plug. The first via plug is located above the first contact plug and contains a first group of Group-IV elements. The first group of Group-IV elements can fill the space in the via plug and react with the via plug to form a first compound, making the structure of the via plug denser. Thus, the problem of consumption of contact plugs during the planarization process (e.g., chemical mechanical polishing process of W) of the via plugs can be eliminated.

[0105] In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a gate structure, source / drain structures, a first contact plug, and a first via plug. The gate structure is located above a fin structure. The source / drain structures are located in the fin structure and adjacent to the gate structure. The first contact plug is located above the source / drain structures. The first via plug is located above the first contact plug, and the first via plug contains a first group of Group-IV elements.

[0106] In some other embodiments, the first via plug has a bottom surface contacting the first contact plug and a top surface opposite to the bottom surface, and the concentration of the first group of Group-IV elements in the first via plug gradually decreases from the top surface to the bottom surface of the first via plug.

[0107] In some other embodiments, the first group of Group-IV elements includes carbon (C), silicon (Si), or germanium (Ge).

[0108] In some other embodiments, the first via plug includes tungsten (W), tungsten germanium (WGe), tungsten carbon (WC), tungsten silicon (WSi2), or a combination of the foregoing.

[0109] In some other embodiments, the semiconductor structure further includes an etch stop layer located above the gate structure and the source / drain structure and surrounding the first via plug; and a dielectric layer located above the etch stop layer and surrounding the first via plug, wherein the dielectric layer includes a first group of Group-IV elements and a second group of Group-IV elements.

[0110] In some other embodiments, wherein the second group of Group-IV elements includes silicon (Si), and wherein the dielectric layer is formed of carbon dioxide (CO2), silicon dioxide (SiO2), germanium dioxide (GeO2), or a combination of the foregoing.

[0111] In some other embodiments, wherein the concentration of the first group of Group-IV elements in the dielectric layer gradually decreases from the top surface to the bottom surface of the dielectric layer, and wherein the concentration of the second group of Group-IV elements is uniform in the dielectric layer.

[0112] In some other embodiments, the semiconductor structure further includes gate sidewalls located above the fin structure and on the sidewall surfaces of the gate structure; a second contact plug located above the gate structure and spaced apart from the first contact plug; and a second via plug located above the second contact plug, wherein the second via plug includes a first group of Group-IV elements.

[0113] In some embodiments, a semiconductor structure is provided, the semiconductor structure including a gate structure, a source / drain structure, a dielectric layer, and a via plug. The gate structure is located above the fin structure. The source / drain structure is located in the fin structure and adjacent to the gate structure. The dielectric layer is located above the gate structure and the source / drain structure. The via plug penetrates the dielectric layer, the via plug includes a first group of Group-IV elements, and the dielectric layer includes a second group of Group-IV elements.

[0114] In some other embodiments, wherein the first group of Group-IV elements includes carbon (C), silicon (Si), or germanium (Ge), and the second group of Group-IV elements includes silicon (Si).

[0115] In some other embodiments, wherein the dielectric layer has a top surface aligned with the top surface of the via plug and a bottom surface between the top surface and the bottom surface of the via plug.

[0116] In some other embodiments, wherein the concentration of the first group of Group-IV elements in the via plug gradually decreases from the top surface to the bottom surface of the via plug, and the concentration of the second group of Group-IV elements is uniform in the dielectric layer.

[0117] In some other embodiments, wherein the dielectric layer includes a first group of Group-IV elements, and the concentration of the first group of Group-IV elements in the dielectric layer gradually decreases from the top surface to the bottom surface of the dielectric layer.

[0118] In some embodiments, a method of forming a semiconductor structure is provided. The method includes forming a gate structure over a fin structure. The method further includes forming source / drain structures in the fin structure and adjacent to the gate structure. The method further includes forming contact plugs over the source / drain structures. The method further includes forming a first dielectric layer over the contact plugs. The method further includes forming a first opening in the first dielectric layer to expose the contact plugs. The method further includes depositing a metal material to fill the first opening. The method further includes implanting a first group of group-IV elements into the metal material. The method further includes removing a portion of the metal material on the top surface of the first dielectric layer to form a via plug over the contact plug.

[0119] In some other embodiments, after implanting the first group of group-IV elements into the metal material, the maximum concentration of the first group of group-IV elements in the metal material is located at a position between the top surface and the bottom surface of the first dielectric layer.

[0120] In some other embodiments, after implanting the first group of group-IV elements into the metal material, the first group of group-IV elements and the metal material form a first compound.

[0121] In some other embodiments, the above method further includes implanting the first group of group-IV elements into the first dielectric layer containing a second compound to form a third compound.

[0122] In some other embodiments, the lattice constant of the third compound is greater than the lattice constant of the second compound in the first dielectric layer.

[0123] In some other embodiments, after implanting the first group of group-IV elements into the metal material, the metal material in the first opening is in a hourglass shape.

[0124] In some other embodiments, the metal material in the first opening has a narrow neck at the position of the first group of group-IV elements with the maximum concentration.

[0125] The foregoing text outlines the features of many embodiments, enabling those skilled in the art to better understand the embodiments of the present invention from various aspects. Those skilled in the art should understand that and can easily design or modify other processes and structures based on the embodiments of the present invention, and achieve the same purpose and / or the same advantages as the embodiments introduced herein. Those skilled in the art should also understand that these equivalent structures do not depart from the inventive concept and scope of the present invention. Various changes, substitutions, or modifications can be made to the embodiments of the present invention without departing from the inventive concept and scope of the present invention.

Claims

1. A semiconductor structure, comprising: A gate structure located above a fin structure; A source / drain structure located in the fin structure and adjacent to the gate structure; A first contact plug located above the source / drain structure; A first via plug located above the first contact plug; And A dielectric layer surrounding and directly contacting the first via plug, wherein the first via plug comprises a first group of Group IV elements and the dielectric layer comprises the first group of Group IV elements and a second group of Group IV elements, and wherein the concentration of the first group of Group IV elements in the dielectric layer gradually decreases from a top surface to a bottom surface of the dielectric layer.

2. The semiconductor structure according to claim 1, wherein the first via plug has a bottom surface contacting the first contact plug and a top surface opposite to the bottom surface, and the concentration of the first group of Group IV elements in the first via plug gradually decreases from the top surface to the bottom surface of the first via plug.

3. The semiconductor structure according to claim 1, wherein the first group of Group IV elements comprises carbon (C), silicon (Si), or germanium (Ge).

4. The semiconductor structure according to claim 2, wherein the first via plug comprises tungsten (W), tungsten germanium (WGe), tungsten carbon (WC), tungsten silicon (WSi2), or a combination of the foregoing.

5. The semiconductor structure according to claim 2, further comprising an etch stop layer located above the gate structure and the source / drain structure and surrounding the first via plug, wherein the dielectric layer is located above the etch stop layer.

6. The semiconductor structure according to claim 1, wherein the second group of Group IV elements comprises silicon (Si), and wherein the dielectric layer is formed of carbon dioxide (CO2), silicon dioxide (SiO2), germanium dioxide (GeO2), or a combination of the foregoing.

7. The semiconductor structure according to claim 1, wherein the concentration of the second group of Group IV elements is uniform in the dielectric layer.

8. The semiconductor structure according to claim 1, further comprising: A gate spacer located above the fin structure and on a sidewall surface of the gate structure; A second contact plug located above the gate structure and spaced apart from the first contact plug; And A second via plug located above the second contact plug, wherein the second via plug comprises the first group of Group IV elements.

9. A semiconductor structure, comprising: A gate structure located above a fin structure; A source / drain structure located in the fin structure and adjacent to the gate structure; A dielectric layer located above the gate structure and the source / drain structure; And A via plug penetrating the dielectric layer and directly contacting the dielectric layer, wherein the via plug comprises a first group of Group IV elements, and the dielectric layer comprises a second group of Group IV elements, a second compound, and a third compound of elements included in the second compound and the first group of Group IV elements, and wherein the concentration of the first group of Group IV elements in the dielectric layer gradually decreases from a top surface to a bottom surface of the dielectric layer.

10. A semiconductor structure, comprising: A fin structure located on a substrate; A gate structure spanning the fin structure; Multiple source / drain structures located in the fin structure and on opposite sides of the gate structure; A contact structure formed above the source / drain structures; An etch stop layer formed above the contact structure; A dielectric layer located above the etch stop layer; and A via plug penetrating the dielectric layer and the etch stop layer, wherein the via plug directly contacts the dielectric layer, wherein the via plug includes a first group of group-IV elements and a metal compound including the first group of group-IV elements, and wherein the concentration of the first group of group-IV elements in the dielectric layer gradually decreases from the top surface to the bottom surface of the dielectric layer.

11. A method of forming a semiconductor structure, comprising: Forming a gate structure above a fin structure; Forming a source / drain structure in the fin structure and adjacent to the gate structure; Forming a contact plug above the source / drain structure; Forming a dielectric layer above the contact plug; Forming an opening in the dielectric layer to expose the contact plug; Depositing a metal material to fill the opening and cover a top surface of the dielectric layer; Implanting a first group of group-IV elements into the metal material, and the dielectric layer is covered by the metal material; And Removing a portion of the metal material above the top surface of the dielectric layer to form a via plug above the contact plug.

12. The method of forming a semiconductor structure according to claim 11, wherein after the step of implanting the first group of group-IV elements into the metal material, the maximum concentration of the first group of group-IV elements in the metal material is located at a position between the top surface and the bottom surface of the dielectric layer.

13. The method of forming a semiconductor structure according to claim 11, wherein after the step of implanting the first group of group-IV elements into the metal material, the first group of group-IV elements and the metal material form a first compound.

14. The method of forming a semiconductor structure according to claim 11, further comprising implanting the first group of group-IV elements into the dielectric layer containing a second compound to form a third compound in the dielectric layer.

15. The method of forming a semiconductor structure according to claim 14, wherein the lattice constant of the third compound is greater than the lattice constant of the second compound in the dielectric layer.

16. The method of forming a semiconductor structure according to claim 14, after the step of implanting the first group of group-IV elements into the metal material, the metal material in the opening is in a hourglass shape.

17. The method of forming a semiconductor structure according to claim 16, wherein the metal material in the opening has a narrow neck at the position of the first group of group-IV elements having the maximum concentration.

18. A method of forming a semiconductor structure, comprising: Patterning a substrate to form a fin structure; Forming a gate structure above the fin structure; Forming a source / drain structure above the fin structure, wherein the source / drain structure is adjacent to the gate structure; Forming a contact plug above the source / drain structure; Forming a dielectric layer above the contact plug; Forming an opening in the dielectric layer to expose the contact plug; Filling the opening with a metal material; Perform an implantation process to reduce the compressive stress between the metal material and the dielectric layer, which is caused by an element implanted in the metal material and the dielectric layer, wherein the metal material covers a top surface of the dielectric layer; And After the step of performing the implantation process, perform a planarization process on the metal material until a top surface of the dielectric layer is exposed.

19. A method for forming a semiconductor structure, comprising: Form a gate structure over a fin structure; Form a source / drain structure in the fin structure, wherein the source / drain structure is adjacent to the gate structure; Form a contact plug on the source / drain structure; Form a dielectric layer on the contact plug; Form an opening in the dielectric layer to expose the contact plug; Deposit a metal material to fill the opening; Perform an implantation process to implant a first group of Group IV elements in the metal material and the dielectric layer, wherein after the implantation process, the difference in mechanical strength between the metal material and the metal strength of the dielectric layer is reduced; and Deposit the metal material directly over the dielectric layer, wherein the step of performing the implantation process includes implanting the first group of Group IV elements in the metal material and the dielectric layer located directly under the metal material.

20. The method for forming a semiconductor structure according to claim 19, wherein after the implantation process, the density of the dielectric layer is reduced.

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