Fin cut and fin trim isolation for advanced integrated circuit structure fabrication

Abstract

Fin cut and fin trim isolation for advanced integrated circuit structure fabrication are disclosed. Embodiments of the present disclosure are in the field of advanced integrated circuit structure fabrication, and in particular, 10 nanometer node and smaller integrated circuit structure fabrication and resulting structures. In an example, an integrated circuit structure includes a fin. A first isolation structure separates a first end of a first portion of the fin from a first end of a second portion of the fin, the first end of the first portion of the fin having a depth. A gate structure is over a top of the first portion of the fin and laterally adjacent to a sidewall of a region of the first portion of the fin. A second isolation structure is over a second end of the first portion of the fin, the second end of the first portion of the fin having a depth that is different than the depth of the first end of the first portion of the fin.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of U.S. Provisional Application No. 62 / 593,149, filed November 30, 2017, entitled “ADVANCED INTEGRATED CIRCUITSTRUCTURE FABRICATION,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments disclosed herein belong to the field of advanced integrated circuit structure manufacturing, and particularly to the field of 10-nanometer node and smaller integrated circuit structure manufacturing and the resulting structures. Background Technology

[0004] For decades, the scaling of features in integrated circuits has been a driving force behind the ever-evolving semiconductor industry. Scaling to increasingly smaller features enables greater functional unit density on the limited substrate surface of semiconductor chips. For example, shrinking transistor sizes allow for the incorporation of a larger number of memory or logic devices on a single chip, resulting in products with increased capacity. However, this drive for ever-increasing capacity is not without its challenges. The need to optimize the performance of each device becomes increasingly crucial.

[0005] The variability in conventional and currently known manufacturing processes may limit the possibility of extending them further to the 10-nanometer or sub-10-nanometer node range. Therefore, the manufacture of functional components required for future technology nodes may necessitate the introduction of new methods or the integration of new technologies into current manufacturing processes, or their replacement of current manufacturing processes. Attached Figure Description

[0006] Figure 1A This illustration shows a cross-sectional view of the initial structure of a hard mask material layer formed on an interlayer dielectric (ILD) layer after deposition but before patterning.

[0007] Figure 1B An example is shown after patterning the hard mask layer by bisecting the pitch. Figure 1A A cross-sectional view of the structure.

[0008] Figure 2A This is a schematic diagram of a pitch quartering method for manufacturing semiconductor fins according to an embodiment of the present disclosure.

[0009] Figure 2B A cross-sectional view of a semiconductor fin manufactured using a pitch quartering method according to an embodiment of the present disclosure is illustrated.

[0010] Figure 3A This is a schematic diagram of a fused fin pitch quartering method for manufacturing semiconductor fins according to an embodiment of the present disclosure.

[0011] Figure 3B A cross-sectional view of a semiconductor fin manufactured using a fused fin pitch quartering method according to an embodiment of the present disclosure is illustrated.

[0012] Figures 4A-4C This is a cross-sectional view illustrating various operations in a method of manufacturing a plurality of semiconductor fins according to embodiments of the present disclosure.

[0013] Figure 5A A cross-sectional view of a pair of semiconductor fins separated by a three-layer trench isolation structure is illustrated according to an embodiment of the present disclosure.

[0014] Figure 5B A cross-sectional view of another pair of semiconductor fins separated by another three-layer trench isolation structure according to another embodiment of the present disclosure is illustrated.

[0015] Figures 6A-6D Cross-sectional views illustrating various operations in the manufacture of a three-layer trench isolation structure according to embodiments of the present disclosure are shown.

[0016] Figures 7A-7E An angled three-dimensional cross-sectional view illustrates various operations in a method of manufacturing an integrated circuit structure according to embodiments of the present disclosure.

[0017] Figures 8A-8F Examples of various operations in a method for manufacturing an integrated circuit structure according to embodiments of the present disclosure are illustrated. Figure 7E A slightly projected cross-sectional view taken along the a-a' axis.

[0018] Figure 9A Examples of integrated circuit structures including permanent gate stacks and epitaxial source or drain regions according to embodiments of the present disclosure are illustrated. Figure 7E A slightly projected cross-sectional view taken along the a-a' axis.

[0019] Figure 9B Examples of integrated circuit structures including epitaxial source or drain regions and multilayer trench isolation structures according to embodiments of the present disclosure are illustrated. Figure 7E A cross-sectional view taken along the b-b' axis.

[0020] Figure 10 A cross-sectional view of an integrated circuit structure taken at the source or drain location according to an embodiment of the present disclosure is illustrated.

[0021] Figure 11A cross-sectional view of another integrated circuit structure taken at the source or drain location according to an embodiment of the present disclosure is illustrated.

[0022] Figure 12A-12D Examples of various operations in manufacturing an integrated circuit structure according to embodiments of the present disclosure are illustrated, and cross-sectional views are taken at the source or drain locations.

[0023] Figure 13A and 13B A plan view illustrating various operations in a patterning method having fins with multiple gate spacings for forming local isolation structures, according to embodiments of the present disclosure, is shown.

[0024] Figures 14A-14D A plan view illustrating various operations in a patterning method having fins with single gate spacing for forming a local isolation structure, according to another embodiment of the present disclosure, is shown.

[0025] Figure 15 A cross-sectional view of an integrated circuit structure with fins according to an embodiment of the present disclosure is illustrated, the fins having multiple gate spacings for local isolation.

[0026] Figure 16A A cross-sectional view of an integrated circuit structure with fins according to another embodiment of the present disclosure is illustrated, the fins having single gate spacing for local isolation.

[0027] Figure 16B A cross-sectional view illustrating an embodiment of the present disclosure is shown, in which a fin isolation structure may be formed in place of the gate electrode.

[0028] Figures 17A-17C Various depth possibilities for fin cuts manufactured using the fin trimming isolation method are illustrated according to embodiments of the present disclosure.

[0029] Figure 18 The plan view and the corresponding cross-sectional view taken along the a-a' axis illustrate possible options for the depth of a fin cut in a local location relative to a wider location, according to embodiments of the present disclosure.

[0030] Figure 19A and 19B Cross-sectional views illustrating various operations in a method for selecting the location of a fin tip stress source at a fin tip with a wide cut, according to embodiments of the present disclosure.

[0031] Figure 20A and 20B Cross-sectional views illustrating various operations in a method for selecting the location of a fin tip stress source at a fin tip with a partial cutout, according to embodiments of the present disclosure.

[0032] Figure 21A-21M Cross-sectional views illustrating various operations in a method of manufacturing an integrated circuit structure with differentiated fin-end dielectric plugs according to embodiments of the present disclosure are shown.

[0033] Figures 22A-22D illustrate exemplary structures of PMOS fin-end stress source dielectric plugs according to embodiments of the present disclosure.

[0034] Figure 23A A cross-sectional view of another semiconductor structure having fin-end stress-induced features according to another embodiment of the present disclosure is illustrated.

[0035] Figure 23B A cross-sectional view of another semiconductor structure having fin-end stress-induced features according to another embodiment of the present disclosure is illustrated.

[0036] Figure 24A An angled view of a fin with uniaxial tensile stress according to an embodiment of the present disclosure is shown.

[0037] Figure 24B An angled view of a fin with uniaxial compressive stress according to an embodiment of the present disclosure is shown.

[0038] Figure 25A and 25B A plan view illustrating various operations in a method of patterning a fin having a single gate spacing for forming a local isolation structure in a selected gate line cut-out location, according to embodiments of the present disclosure.

[0039] Figures 26A-26C Cross-sectional views illustrating various possibilities for dielectric plugs according to embodiments of the present disclosure are shown, the dielectric plugs being used for Figure 25B Poly cuts and fin trimming isolation (FTI) locations in various regions of the structure, as well as poly cut locations only.

[0040] Figure 27A A plan view and a corresponding cross-sectional view of an integrated circuit structure having a gate line cutout according to an embodiment of the present disclosure are illustrated, the gate line cutout having a dielectric plug extending into a dielectric spacer portion of the gate line.

[0041] Figure 27B A plan view and a corresponding cross-sectional view of an integrated circuit structure having a gate line cutout according to another embodiment of the present disclosure are illustrated, the gate line cutout having a dielectric plug extending beyond the dielectric spacer of the gate line.

[0042] Figures 28A-28FCross-sectional views illustrating various operations in a method of manufacturing an integrated circuit structure having a gate line cutout with a dielectric plug according to another embodiment of the present disclosure are shown, the dielectric plug having an upper portion extending beyond a dielectric spacer portion of the gate line and a lower portion extending into the dielectric spacer portion of the gate line.

[0043] Figures 29A-29C A plan view and a corresponding cross-sectional view of an integrated circuit structure having residual dummy gate material at a portion of the bottom of a permanent gate stack, according to an embodiment of the present disclosure, are illustrated.

[0044] Figures 30A-30D Cross-sectional views illustrating various operations in a method of manufacturing an integrated circuit structure having residual dummy gate material at a portion of the bottom of a permanent gate stack, according to another embodiment of the present disclosure.

[0045] Figure 31A A cross-sectional view of a semiconductor device having a ferroelectric or antiferroelectric gate dielectric structure according to an embodiment of the present disclosure is illustrated.

[0046] Figure 31B A cross-sectional view of another semiconductor device having a ferroelectric or antiferroelectric gate dielectric structure according to another embodiment of the present disclosure is illustrated.

[0047] Figure 32A A plan view of a plurality of gate lines over a pair of semiconductor fins is illustrated according to an embodiment of the present disclosure.

[0048] Figure 32B Examples of embodiments according to this disclosure are illustrated along... Figure 32A A cross-sectional view taken along the a-a' axis.

[0049] Figure 33A Cross-sectional views of a pair of NMOS devices having a differential voltage threshold based on modulation doping and a pair of PMOS devices having a differential voltage threshold based on modulation doping, according to embodiments of the present disclosure, are illustrated.

[0050] Figure 33B A cross-sectional view is illustrated for a pair of NMOS devices having differentiated voltage thresholds based on differentiated gate electrode structures and a pair of PMOS devices having differentiated voltage thresholds based on differentiated gate electrode structures, according to another embodiment of the present disclosure.

[0051] Figure 34A Cross-sectional views of a group of three NMOS devices having a differentiated voltage threshold based on a differentiated gate electrode structure and modulation doping, and a group of three PMOS devices having a differentiated voltage threshold based on a differentiated gate electrode structure and modulation doping, according to embodiments of the present disclosure, are illustrated.

[0052] Figure 34B Cross-sectional views of a group of three NMOS devices having a differentiated voltage threshold based on a differentiated gate electrode structure and modulation doping, and a group of three PMOS devices having a differentiated voltage threshold based on a differentiated gate electrode structure and modulation doping, according to another embodiment of the present disclosure, are illustrated.

[0053] Figures 35A-35D Cross-sectional views illustrating various operations in a method for manufacturing an NMOS device having a differentiated voltage threshold based on a differentiated gate electrode structure, according to another embodiment of the present disclosure.

[0054] Figures 36A-36D Cross-sectional views illustrating various operations in a method for manufacturing a PMOS device having a differentiated voltage threshold based on a differentiated gate electrode structure, according to another embodiment of the present disclosure.

[0055] Figure 37 A cross-sectional view of an integrated circuit structure having a P / N junction according to an embodiment of the present disclosure is illustrated.

[0056] Figures 38A-38H Cross-sectional views illustrate various operations in a method for fabricating an integrated circuit structure using a double-metal gate-instead-of-gate process according to embodiments of the present disclosure.

[0057] Figures 39A-39H Cross-sectional views illustrating various operations in a method of manufacturing a dual-silicide-based integrated circuit according to embodiments of the present disclosure are shown.

[0058] Figure 40A A cross-sectional view of an integrated circuit structure having trench contacts for an NMOS device is illustrated according to an embodiment of the present disclosure.

[0059] Figure 40B A cross-sectional view of an integrated circuit structure having trench contacts for a PMOS device is illustrated according to another embodiment of the present disclosure.

[0060] Figure 41A A cross-sectional view of a semiconductor device having conductive contacts in the source or drain region according to an embodiment of the present disclosure is illustrated.

[0061] Figure 41B A cross-sectional view of another semiconductor device having conductive contacts on a raised source or drain region is illustrated according to an embodiment of the present disclosure.

[0062] Figure 42 A plan view of a plurality of gate lines over a pair of semiconductor fins is illustrated according to an embodiment of the present disclosure.

[0063] Figures 43A-43C Examples of various operations in a method for manufacturing an integrated circuit structure according to embodiments of the present disclosure are illustrated. Figure 42 A cross-sectional view taken along the a-a' axis.

[0064] Figure 44 Examples of integrated circuit structures according to embodiments of the present disclosure are illustrated. Figure 42 A cross-sectional view taken along the b-b' axis.

[0065] Figure 45A and 45B Plan view and corresponding cross-sectional view of an integrated circuit structure including a trench contact plug having a hard mask material thereon, according to embodiments of the present disclosure, are illustrated respectively.

[0066] Figures 46A-46D Cross-sectional views illustrating various operations in a method of manufacturing an integrated circuit structure including trench contact plugs having hard mask material thereon, according to embodiments of the present disclosure.

[0067] Figure 47A A plan view of a semiconductor device having a gate contact disposed on an inactive portion of the gate electrode is shown. Figure 47B A cross-sectional view of a nonplanar semiconductor device having a gate contact disposed on an inactive portion of the gate electrode is illustrated.

[0068] Figure 48A A plan view of a semiconductor device having a gate contact via disposed on an effective portion of a gate electrode, according to an embodiment of the present disclosure, is illustrated. Figure 48B A cross-sectional view of a non-planar semiconductor device having a gate contact via disposed on an effective portion of a gate electrode, according to an embodiment of the present disclosure, is illustrated.

[0069] Figures 49A-49D Cross-sectional views illustrating various operations in a method of manufacturing a semiconductor structure having a gate contact structure deployed on an effective portion of the gate, according to embodiments of the present disclosure.

[0070] Figure 50 A plan view and a corresponding cross-sectional view of an integrated circuit structure having trench contacts including superimposed insulating capping layers according to an embodiment of the present disclosure are illustrated.

[0071] Figures 51A-51F Cross-sectional views of various integrated circuit structures according to embodiments of the present disclosure are illustrated, each having a trench contact including a superimposed insulating capping layer and a gate stack including a superimposed insulating capping layer.

[0072] Figure 52AA plan view of another semiconductor device having a gate contact via disposed on an effective portion of the gate, according to another embodiment of the present disclosure, is illustrated.

[0073] Figure 52B A plan view of another semiconductor device having a trench contact via with a pair of coupled trench contacts is shown according to another embodiment of the present disclosure.

[0074] Figures 53A-53E Cross-sectional views illustrating various operations in a method of manufacturing an integrated circuit structure having a gate stack containing superimposed insulating capping layers, according to embodiments of the present disclosure, are shown.

[0075] Figure 54 This is a schematic diagram of a pitch quartering method for manufacturing trenches for interconnect structures according to embodiments of the present disclosure.

[0076] Figure 55A A cross-sectional view of a metallization layer manufactured using a pitch quadrature scheme according to an embodiment of the present disclosure is illustrated.

[0077] Figure 55B A cross-sectional view is shown above a metallization layer manufactured using a pitch bisection scheme over a metallization layer manufactured using a pitch quadrature scheme, according to an embodiment of the present disclosure.

[0078] Figure 56A A cross-sectional view of an integrated circuit structure having a metallization layer composed of different metal lines above a metallization layer composed of one type of metal lines, according to an embodiment of the present disclosure, is illustrated.

[0079] Figure 56B A cross-sectional view of an integrated circuit structure having a metallization layer composed of different metal lines coupled to a metallization layer composed of one type of metal lines, according to an embodiment of the present disclosure, is illustrated.

[0080] Figures 57A-57C Cross-sectional views of various interconnects arranged with various gaskets and conductive capping structures according to embodiments of the present disclosure are illustrated.

[0081] Figure 58 A cross-sectional view of an integrated circuit structure according to an embodiment of the present disclosure is shown, having four metallization layers with different metallization layers and pitches above two metallization layers with one metallization layer and a small pitch.

[0082] Figures 59A-59D Cross-sectional views illustrating various interconnect and via arrangements having a bottom conductive layer according to embodiments of the present disclosure are shown.

[0083] Figure 60A-60DA cross-sectional view illustrating a structural arrangement of recessed line morphology for a BEOL metallization layer according to an embodiment of the present disclosure is shown.

[0084] Figures 61A-61D A cross-sectional view illustrating a structural arrangement of a stepped line morphology for a BEOL metallization layer according to an embodiment of the present disclosure is shown.

[0085] Figure 62A A plan view of a metallization layer according to an embodiment of the present disclosure and a corresponding cross-sectional view taken along the a-a' axis of the plan view of the metallization layer are illustrated.

[0086] Figure 62B A cross-sectional view of a wire end or plug according to an embodiment of the present disclosure is illustrated.

[0087] Figure 62C Another cross-sectional view of a wire end or plug according to an embodiment of the present disclosure is illustrated.

[0088] Figures 63A-63F Plan views and corresponding cross-sectional views illustrating various operations in a plug end-channel processing scheme according to embodiments of the present disclosure are shown.

[0089] Figure 64A A cross-sectional view of a wire plug having a seam, according to an embodiment of the present disclosure, is illustrated.

[0090] Figure 64B A cross-sectional view illustrating a metallization layer stack including a wire plug at the lower metal wire location according to an embodiment of the present disclosure is shown.

[0091] Figure 65 A first view illustrating the cell layout for a memory cell is shown.

[0092] Figure 66 A first view illustrating a cell layout for a memory cell with internal node jumpers according to an embodiment of the present disclosure is shown.

[0093] Figure 67 A second view illustrating the cell layout for memory cells is shown.

[0094] Figure 68 A second view illustrating a cell layout for a memory cell with internal node jumpers according to an embodiment of the present disclosure is shown.

[0095] Figure 69 A third view illustrating the cell layout for a memory cell is shown.

[0096] Figure 70 A third view illustrating a cell layout for a memory cell with internal node jumpers according to an embodiment of the present disclosure is shown.

[0097] Figure 71A and 71B Bit cell layouts and schematic illustrations for a six-transistor (6T) static random access memory (SRAM) according to embodiments of the present disclosure are shown respectively.

[0098] Figure 72 Cross-sectional views illustrating two different layouts for the same standard cell according to embodiments of the present disclosure are shown.

[0099] Figure 73 Plan views illustrating four different cell arrangements for indicating even (E) or odd (O) names according to embodiments of the present disclosure are shown.

[0100] Figure 74 A plan view of a block-level aggregated grid according to an embodiment of the present disclosure is illustrated.

[0101] Figure 75 Exemplary acceptable (passable) layouts based on standard units with different versions are illustrated according to embodiments of the present disclosure.

[0102] Figure 76 An exemplary unacceptable (failing) layout based on standard units with different versions is illustrated according to embodiments of the present disclosure.

[0103] Figure 77 Another exemplary acceptable (passable) layout based on standard units with different versions is illustrated according to embodiments of the present disclosure.

[0104] Figure 78 A partially cut plan view and a corresponding cross-sectional view of a fin-based thin-film resistor structure according to an embodiment of the present disclosure are illustrated, wherein the cross-sectional view is cut along the a-a' axis of the partially cut plan view.

[0105] Figures 79-83 Plan views and corresponding cross-sectional views illustrating various operations in a method for manufacturing a fin-based thin-film resistor structure according to embodiments of the present disclosure are shown.

[0106] Figure 84 A plan view of a fin-based thin-film resistor structure according to an embodiment of the present disclosure is shown, having various exemplary positions for anode or cathode electrode contacts.

[0107] Figure 85A-85D Plan views illustrating various fin geometries for manufacturing fin-based precision resistors according to embodiments of the present disclosure are shown.

[0108] Figure 86A cross-sectional view of a photolithographic mask structure according to an embodiment of the present disclosure is illustrated.

[0109] Figure 87 A computing device according to one embodiment of the present disclosure is illustrated.

[0110] Figure 88 An intermediary layer including one or more embodiments of the present disclosure is illustrated.

[0111] Figure 89 An isometric view illustrating an IC or a mobile computing platform comprising one or more features described herein, manufactured according to one or more processes described herein, according to embodiments of the present disclosure.

[0112] Figure 90 A cross-sectional view of a die mounted in a flip-chip manner according to an embodiment of the present disclosure is illustrated. Detailed Implementation

[0113] Advanced integrated circuit fabrication techniques are described. Numerous specific details, such as particular integration and material organization methods (regimes), are set forth in the following description to provide a thorough understanding of embodiments of this disclosure. It will be apparent to those skilled in the art that embodiments of this disclosure can be practiced without these specific details. In other instances, well-known features such as integrated circuit design layouts have not been described in detail to avoid unnecessarily obscuring embodiments of this disclosure. Furthermore, it should be understood that the various embodiments illustrated in the accompanying drawings are illustrative representations and are not necessarily drawn to scale.

[0114] The following detailed description is illustrative in nature only and is not intended to limit the embodiments of this subject matter or the application and use of such embodiments. As used herein, the word "exemplary" means "serving as an example, instance, or illustration." Any implementation described herein as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, it is not intended to be bound by any express or implied theory presented in the foregoing technical field, background art, summary of the invention, or the following detailed description.

[0115] This specification includes references to "one embodiment" or "embodiment". The appearance of the phrase "in one embodiment" or "in an embodiment" does not necessarily refer to the same embodiment. Specific features, structures, or characteristics may be combined in any suitable manner in accordance with this disclosure.

[0116] Terminology. The following paragraphs provide definitions or context for the terms that appear in this disclosure (including the appended claims).

[0117] "Comprising": This term is open-ended. As used in the appended claims, this term does not exclude additional structures or operations.

[0118] "Configured to": Various units or components may be described or claimed as being "configured to" perform one or more tasks. In such a context, "configured to" is used to imply a structure by indicating that the unit or component includes a structure that performs that one or more tasks during operation. Accordingly, even when the unit or component is not currently in operation (e.g., not turned on or inactive), the specified unit or component may be said to be configured to perform the task. The statement that a unit or circuit or component is "configured to" perform one or more tasks is expressly intended not to invoke paragraph 6 of 35 U.S.SC §112 against that unit or component.

[0119] "First", "second", etc.: As used in this article, these terms are used as labels for the nouns that follow them and do not imply any kind of ordering (e.g., spatial, temporal, logical, etc.).

[0120] "Coupling" – The following description refers to elements, nodes, or features being "coupled" together. As used herein, unless explicitly stated otherwise, "coupling" means that one element, node, or feature is directly or indirectly connected to (or directly or indirectly linked to) another element, node, or feature, and not necessarily in a mechanical way.

[0121] Additionally, certain terms may be used in the following description for reference only, and such terms are therefore not intended to be limiting. For example, terms such as “up,” “down,” “above,” and “below” refer to orientations in the referenced figures. Terms such as “front,” “rear,” “back,” “side,” “outer,” and “inner” describe the orientation or position, or both, of the parts of the component in a consistent but arbitrary frame of reference, which is clarified by referring to the text describing the component under discussion and the associated figures. Such terms may include words specifically mentioned above, their derivatives, and words with similar meanings.

[0122] "Inhibition"—as used herein—is used to describe reducing or minimizing an effect. When a component or feature is described as inhibiting an action, movement, or condition, it can completely prevent that result or consequence or future state. Additionally, "inhibition" can also refer to reducing or mitigating a consequence, performance, or effect that would otherwise have occurred. Therefore, when a component, element, or feature is described as inhibiting a result or state, it is not necessary to completely prevent or eliminate that result or state.

[0123] The embodiments described herein may relate to front-end process (FEOL) semiconductor processing and structure. FEOL is the first part of integrated circuit (IC) fabrication, in which various devices (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or layer. FEOL generally encompasses any process up to (but not including) the deposition of metal interconnect layers. After the final FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

[0124] The embodiments described herein may relate to back-end process (BEOL) semiconductor processing and structures. BEOL is the second part of IC manufacturing, where wiring (e.g., one or more metallization layers) on the wafer is used to interconnect various devices (e.g., transistors, capacitors, resistors, etc.). BEOL includes contacts, insulating layers (dielectrics), metal layers, and bonding areas for chip-to-package connections. During the manufacturing phase of the BEOL, contacts (pads), interconnect wires, vias, and dielectric structures are formed. For modern IC processes, more than 10 metal layers can be added to the BEOL.

[0125] The embodiments described below can be applied to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. In particular, although an exemplary processing scheme can be illustrated using an FEOL processing scenario, such a method can also be applied to BEOL processing. Similarly, although an exemplary processing scheme can be illustrated using a BEOL processing scenario, such a method can also be applied to FEOL processing.

[0126] Pitch segmentation and patterning schemes can be implemented to enable the embodiments described herein, or pitch segmentation and patterning schemes can be included as part of the embodiments described herein. Pitch segmentation patterning typically refers to pitch bisection, pitch quartering, etc. Pitch segmentation schemes can be applied to FEOL processing, BEOL processing, or both FEOL (device) and BEOL (metallization) processing. According to one or more embodiments described herein, optical lithography is first performed to print unidirectional lines (e.g., strictly unidirectional or predominantly unidirectional) in a predefined pitch. Then, pitch segmentation is performed as a technique for increasing line density.

[0127] In embodiments, the term "grid structure" used for fins, gate lines, metal lines, ILD lines, or hard mask lines is used herein to refer to a grid structure with a tight pitch. In one such embodiment, the tight pitch cannot be directly achieved by the chosen lithography. For example, a pattern based on the chosen lithography can be formed first, but the pitch can be bisected by using spacer mask patterning, as is known in the art. Furthermore, the original pitch can be quartered by a second round of spacer mask patterning. Thus, the grid-like pattern described herein can have metal lines, ILD lines, or hard mask lines spaced at a generally uniform pitch and having a generally uniform width. For example, in some embodiments, the pitch variation will be within 10% and the width variation will be within 10%, and in some embodiments, the pitch variation will be within 5% and the width variation will be within 5%. Patterning can be fabricated by pitch bisecting, pitch quartering, or other pitch segmentation methods. In embodiments, the grid is not necessarily single-pitch.

[0128] In the first embodiment, the pitch can be bisected to double the linear density of the manufactured grid structure. Figure 1A This illustration shows a cross-sectional view of the initial structure of a hard mask material layer formed on an interlayer dielectric (ILD) layer after deposition but before patterning. Figure 1B An example is shown after patterning the hard mask layer by bisecting the pitch. Figure 1A A cross-sectional view of the structure.

[0129] refer to Figure 1A The initial structure 100 has a hard mask material layer 104 formed on an interlayer dielectric (ILD) layer 102. A patterned mask 106 is deposited on the hard mask material layer 104. The patterned mask 106 has spacers 108 formed on the hard mask material layer 104 along its feature (line) sidewalls.

[0130] refer to Figure 1B The hard mask material layer 104 is patterned using a pitch bisection method. Specifically, the patterned mask 106 is first removed. The resulting spacer 108 has a pattern with double the density, or half the pitch or features of the mask 106. The pattern of the spacer 108 is transferred to the hard mask material layer 104 by, for example, an etching process to form a patterned hard mask 110, as... Figure 1B As depicted in the figure. In one such embodiment, the patterned hard mask 110 is formed with a lattice pattern having unidirectional lines. The lattice pattern of the patterned hard mask 110 can be a closely pitched lattice structure. For example, a closely pitched structure may not be directly achievable using the selected photolithography technique. Furthermore, although not shown, the original pitch can be quartered by patterning a second spacer mask. Therefore, Figure 1B The grid-like pattern of the patterned hard mask 110 can have hard mask lines spaced at a constant pitch and having a constant width relative to each other. The achieved dimensions can be much smaller than the critical dimensions of the photolithography technique employed.

[0131] Therefore, for front-end process (FEOL) or back-end process (BEOL) or both integrated solutions, photolithography and etching processes can be used to pattern the blanket film, which may involve, for example, double patterning based on spacers (SBDP) or pitch bisection, or quadruple patterning based on spacers (SBQP) or pitch quartering. It should be understood that other pitch segmentation methods can also be implemented. In any case, in an embodiment, a grid-like layout can be fabricated using a selected photolithography method such as 193nm immersion lithography (193i). Pitch segmentation can be implemented to increase the line density in the grid-like layout by a factor of n. A grid-like layout formed using 193i lithography plus a pitch segmentation of "n" times can be designated as 193i+P / n pitch segmentation. In one such embodiment, 193nm immersion scaling can be extended for many generations using cost-effective pitch segmentation.

[0132] In the manufacture of integrated circuit devices, as device dimensions continue to shrink, multi-gate transistors, such as tri-gate transistors, are becoming increasingly popular. Tri-gate transistors are typically fabricated on bulk silicon substrates or silicon-on-insulator (SiI) structures. In some cases, bulk silicon substrates are preferred due to their lower cost and compatibility with existing high-yield bulk silicon substrate infrastructures.

[0133] However, scaling multi-gate transistors has not been without its challenges. As the size of the basic building blocks of these microelectronic circuits decreases and the absolute number of basic building blocks manufactured in a given area increases, the constraints on the semiconductor processes used to manufacture these building blocks have become unbearable.

[0134] According to one or more embodiments of this disclosure, a pitch quadrature method is implemented for patterning semiconductor layers to form semiconductor fins. In one or more embodiments, a fused fin pitch quadrature method is implemented.

[0135] Figure 2A This is a schematic diagram of a pitch quadrature method 200 for manufacturing semiconductor fins according to an embodiment of the present disclosure. Figure 2B A cross-sectional view of a semiconductor fin manufactured using a pitch quartering method according to an embodiment of the present disclosure is illustrated.

[0136] refer to Figure 2AIn operation (a), a photoresist layer (PR) is patterned to form photoresist feature 202. Standard photolithography techniques such as 193 immersion lithography can be used to pattern the photoresist feature 202. In operation (b), the photoresist feature 202 is used to pattern a material layer, such as an insulating or dielectric hard mask layer, to form a first backbone (BB1) feature 204. A first spacer (SP1) feature 206 is then formed adjacent to the sidewalls of the first backbone feature 204. In operation (c), the first backbone feature 204 is removed, leaving only the first spacer feature 206. Before or during the removal of the first backbone feature 204, the first spacer feature 206 can be thinned to form a thinned first spacer feature 206', as shown below. Figure 2A As depicted. The thinning can be performed before (as depicted) or after the removal of BB1 (feature 204), depending on the required spacing and size for feature BB2 (208, described below). At operation (d), a material layer, such as an insulating or dielectric hard mask layer, is patterned using the first spacer feature 206 or a thinned first spacer feature 206' to form the second pillar (BB2) feature 208. The second spacer (SP2) feature 210 is then formed adjacent to the sidewalls of the second pillar feature 208. At operation (e), the second pillar feature 208 is removed, leaving only the second spacer feature 210. The remaining second spacer feature 210 can then be used to pattern a semiconductor layer to provide a plurality of semiconductor fins with a pitched quadrature dimension relative to the initial patterned photoresist feature 202. For example, refer to... Figure 2B The second spacer feature 210 is used as a mask for patterning (e.g., dry or plasma etching patterning) to form a plurality of semiconductor fins 250, such as silicon fins formed from bulk silicon layers. Figure 2B In the example, the plurality of semiconductor fins 250 always have essentially the same pitch and spacing.

[0137] The key takeaway is that the spacing between the initially patterned photoresist features can be modified to alter the structural outcome of the pitch-quadrant process. In the example, Figure 3A This is a schematic diagram of a fused fin pitch quadrature method 300 for manufacturing semiconductor fins according to an embodiment of the present disclosure. Figure 3B A cross-sectional view of a semiconductor fin manufactured using a fused fin pitch quartering method according to an embodiment of the present disclosure is illustrated.

[0138] refer to Figure 3AAt operation (a), a photoresist layer (PR) is patterned to form photoresist feature 302. Standard lithography techniques such as 193 immersion lithography can be used, but the photoresist feature 302 is patterned at intervals that may ultimately interfere with the design rules required to produce a uniform, multiple-pitch pattern (e.g., referred to as sub-design rule intervals). At operation (b), a material layer, such as an insulating or dielectric hard mask layer, is patterned using the photoresist feature 302 to form a first pillar (BB1) feature 304. A first spacer (SP1) feature 306 is then formed adjacent to the sidewalls of the first pillar feature 304. However, with… Figure 2A Compared to the illustrated scheme, as a result of the denser photoresist features 302, some of the adjacent first spacer features 306 are fused spacer features. At operation (c), the first pillar features 304 are removed to leave only the first spacer features 306. Before or after removing the first pillar features 304, some of the first spacer features 306 can be thinned to form thinned first spacer features 306', as shown below. Figure 3A As depicted in the diagram. At operation (d), a material layer, such as an insulating or dielectric hard mask layer, is patterned using a first spacer feature 306 and a thinned first spacer feature 306' to form a second pillar (BB2) feature 308. A second spacer (SP2) feature 310 is then formed adjacent to the sidewall of the second pillar feature 308. However, in locations where the BB2 feature 308 is a fused feature, such as in… Figure 3A At the central BB2 feature 308, no second spacer is formed. At operation (e), the second pillar feature 308 is removed to leave only the second spacer feature 310. The remaining second spacer feature 310 can then be used to pattern a semiconductor layer to provide a plurality of semiconductor fins with a pitched quadrature size relative to the initial patterned photoresist feature 302.

[0139] As an example, see reference Figure 3B The second spacer feature 310 is used as a mask for patterning (e.g., dry or plasma etching patterning) to form multiple semiconductor fins 350, such as silicon fins formed from bulk silicon layers. However, in Figure 3B In the example, the plurality of semiconductor fins 350 have varying pitch and spacing. Such a fused fin spacing patterning method can be implemented to essentially eliminate the presence of fins in certain locations within the pattern of the plurality of fins. Therefore, fusing the first spacing feature 306 in certain locations allows for the generation of eight fins based on two first pillar features 304 (which typically generate eight fins, as with...). Figure 2A and 2B(As described in association) to manufacture six or four fins. In one example, the fins in the plate have a closer pitch than would typically be allowed by producing fins at a uniform pitch and then cutting off unwanted fins, but the latter method can still be implemented according to the embodiments described herein.

[0140] In an exemplary embodiment, reference is made to Figure 3B The integrated circuit structure includes a first plurality of semiconductor fins 352 having the longest dimension along a first direction (y, entering the page). Adjacent semiconductor fins 353 of the first plurality of semiconductor fins 352 are spaced apart by a first amount (S11) in a second direction (x) orthogonal to the first direction y. A second plurality of semiconductor fins 354 have the longest dimension along the first direction y. Adjacent semiconductor fins 355 of the second plurality of semiconductor fins 354 are spaced apart by a first amount (S1) in the second direction. The closest semiconductor fins 356 and 357 belonging to the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354, respectively, are spaced apart by a second amount (S2) in the second direction x. In one embodiment, the second amount S2 is greater than the first amount S1 but less than twice the first amount S1. In another embodiment, the second amount S2 is greater than twice the first amount S1.

[0141] In one embodiment, the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354 comprise silicon. In one embodiment, the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354 are continuous with an underlying single-crystal silicon substrate. In one embodiment, each semiconductor fin in the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354 has a sidewall that tapers outwardly from the top to the bottom along a second direction x. In one embodiment, the first plurality of semiconductor fins 352 has exactly five semiconductor fins, and the second plurality of semiconductor fins 354 has exactly five semiconductor fins.

[0142] In another exemplary embodiment, reference is made to Figure 3A and 3BA method for manufacturing an integrated circuit structure includes forming a first primary pillar feature 304 (BB1 on the left) and a second primary pillar feature 304 (BB1 on the right). The sidewalls adjacent to the first primary pillar feature 304 (BB1 on the left) and the second primary pillar feature 304 (BB1 on the right) form a primary spacer structure 306. The primary spacer structure 306 between the first primary pillar feature 304 (BB1 on the left) and the second primary pillar feature 304 (BB1 on the right) is fused. The first primary pillar feature (BB1 on the left) and the second primary pillar feature (BB1 on the right) are removed, and first, second, third, and fourth secondary pillar features 308 are provided. The second and third secondary pillar features (e.g., a central pair of secondary pillar features 308) are fused. The sidewalls adjacent to the first, second, third, and fourth secondary pillar features 308 form a secondary spacer structure 310. The first, second, third, and fourth secondary pillar features 308 are then removed. Then, the semiconductor material is patterned with secondary spacer structures 310 to form semiconductor fins 350 in the semiconductor material.

[0143] In one embodiment, the first primary pillar structure 304 (BB1 on the left) and the second primary pillar structure 304 (BB1 on the right) are patterned with a sub-design rule spacing between the first primary pillar structure and the second primary pillar structure. In one embodiment, the semiconductor material comprises silicon. In one embodiment, each semiconductor fin in the semiconductor fin 350 has a sidewall that tapers outward from the top to the bottom of the semiconductor fin along a second direction x. In one embodiment, the semiconductor fin 350 is continuous with the underlying monocrystalline silicon substrate. In one embodiment, the semiconductor material patterned with a secondary spacing structure 310 includes forming a first plurality of semiconductor fins 352 having the longest dimension along a first direction y, wherein adjacent semiconductor fins in the first plurality of semiconductor fins 352 are spaced apart from each other by a first amount S1 in the second direction x, which is orthogonal to the first direction y. A second plurality of semiconductor fins 354 are formed to have the longest dimension along the first direction y, wherein adjacent semiconductor fins in the second plurality of semiconductor fins 354 are spaced apart from each other by a first amount S1 in the second direction x. The closest semiconductor fins 356 and 357 belonging to the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354, respectively, are spaced apart from each other by a second number S2 in the second direction x. In an embodiment, the second number S2 is greater than the first number S1. In one such embodiment, the second number S2 is less than twice the first number S1. In another such embodiment, the second number S2 is greater than twice the first number S1 but less than three times it. In an embodiment, the first plurality of semiconductor fins 352 have exactly five semiconductor fins, and the second plurality of semiconductor fins 254 have exactly five semiconductor fins, as... Figure 3B As depicted in the text.

[0144] On the other hand, it's important to understand that during fin trimming as an alternative to fin fusion, fins can be trimmed (removed) either during hard mask patterning or by physically removing the fins. As an example of the latter method, Figures 4A-4C This is a cross-sectional view illustrating various operations in a method of manufacturing a plurality of semiconductor fins according to embodiments of the present disclosure.

[0145] refer to Figure 4A A patterned hard mask layer 402 is formed on a semiconductor layer 404, such as a bulk single-crystal silicon layer. (See reference) Figure 4B Then, fins 406 are formed in semiconductor layer 404 by, for example, a dry etching or plasma etching process. (Reference) Figure 4C Selected fins 406 are removed using processes such as masking and etching. In the example shown, one of the fins 406 is removed, leaving a residual fin root 408, such as... Figure 4C As depicted in the text. In this "fin finishing process," the hard mask 402 is patterned as a whole to provide a grid structure without removing or modifying individual features. The fin group is not modified until after the fins have been manufactured.

[0146] In another aspect, a multilayer trench isolation region, which may be referred to as a shallow trench isolation (STI) structure, can be formed between semiconductor fins. In an embodiment, a multilayer STI structure is formed between silicon fins formed in a bulk silicon substrate to define sub-fin regions of the silicon fins.

[0147] Using bulk silicon for fins or tri-gate based transistors can be desirable. However, there is a concern that the region below the effective silicon fin portion of the device (e.g., the gate-controlled region or HSi) (the sub-fin) may be weakened or uncontrolled by the gate. Consequently, if the source or drain region is at or below the HSi point, leakage paths may exist through this sub-fin region. Therefore, leakage paths in the sub-fin region should be controlled for proper device operation.

[0148] One approach to solving the above problem involves using it to heavily dope the sub-fin region (e.g., more than 2E18 / cm). 3 A much larger trap injection operation cuts off leakage in the sub-fins but also results in significant doping in the fins. Adding halogen injectors further increases fin doping, causing the tips of the wire fins to be doped at high levels (e.g., greater than about 1E18 / cm). 3 ).

[0149] Another approach involves doping via sub-fin doping, rather than delivering the same level of doping to the HSi portion of the fin. The process can involve selectively doping the sub-fin regions of a tri-gate or FinFET transistor fabricated on a bulk silicon wafer, for example, by outward diffusion of tri-gate doped glass sub-fins. For instance, selectively doping the sub-fin regions of a tri-gate or FinFET transistor can mitigate sub-fin leakage while keeping the fin doping low. Incorporating solid-state doping sources (e.g., p-type and n-type doped oxides, nitrides, or carbides) into the transistor fabrication process—after being recessed from the fin sidewalls—delivers well doping to the sub-fin regions while keeping the fin body relatively undoped.

[0150] Therefore, the process scheme may include the use of a solid source dopant layer (e.g., boron-doped oxide) deposited on the fin after fin etching. Later, after trench filling and polishing, the doped layer is recessed along with the trench fill material to define the fin height (HSi) for the device. This operation removes the doped layer from the fin sidewalls above HSi. Thus, the doped layer is present only along the fin sidewalls in the sub-fin region, ensuring precise control of doping distribution. After driven annealing, the high doping is confined to the sub-fin region, allowing for a rapid transition to low doping in the adjacent fin region above HSi (which forms the channel region of the transistor). Generally, borosilicate glass (BSG) is implemented for NMOS fin doping, while phosphorus silicate glass (PSG) or arsenic silicate glass (AsSG) layers are implemented for PMOS fin doping. In one example, such a P-type solid dopant source is a BSG layer with a boron concentration in the range of approximately 0.1–10 mass percentages. In another example, such an N-type solid-state dopant source is a PSG layer or an AsSG layer having a phosphorus or arsenic concentration in the range of approximately 0.1–10 by mass percentage, respectively. A silicon nitride capping layer may be included on the doped layer, and then a silicon dioxide or silicon oxide filling material may be included on the silicon nitride capping layer.

[0151] According to another embodiment of this disclosure, sub-fin leakage is sufficiently low for relatively thin fins (e.g., fins with a width of less than about 20 nanometers) where an undoped or lightly doped silicon oxide or silicon dioxide film is formed directly adjacent to the fin, a silicon nitride layer is formed on the undoped or lightly doped silicon oxide or silicon dioxide film, and a silicon dioxide or silicon oxide filler material is included on the silicon nitride capping layer. It should be understood that doping, such as halogen doping, in the sub-fin region can also be achieved using this structure.

[0152] Figure 5A A cross-sectional view of a pair of semiconductor fins separated by a three-layer trench isolation structure is illustrated according to an embodiment of the present disclosure.

[0153] refer to Figure 5AThe integrated circuit structure includes a fin 502, such as a silicon fin. The fin 502 has a lower fin portion (sub-fin) 502A and an upper fin portion 502B (H). Si The first insulating layer 504 is directly located on the sidewall of the lower fin portion 502A of the fin 502. The second insulating layer 506 is directly located on the first insulating layer 504, which is directly located on the sidewall of the lower fin portion 502A of the fin 502. The dielectric filling material 508 is laterally directly adjacent to the second insulating layer 506, which is directly located on the first insulating layer 504, which is directly located on the sidewall of the lower fin portion 502A of the fin 502.

[0154] In an embodiment, the first insulating layer 504 is an undoped insulating layer comprising silicon and oxygen, such as silicon oxide or silicon dioxide. In an embodiment, the first insulating layer 504 comprises silicon and oxygen and does not have other atomic species with an atomic concentration greater than 1E15 atoms per cubic centimeter. In an embodiment, the first insulating layer 504 has a thickness in the range of 0.5-2 nanometers.

[0155] In an embodiment, the second insulating layer 506 comprises silicon and nitrogen, such as a silicon nitride insulating layer with a stoichiometric Si3N4, a silicon-rich silicon nitride insulating layer, or a silicon-poor silicon nitride insulating layer. In an embodiment, the second insulating layer 506 has a thickness in the range of 2-5 nanometers.

[0156] In an embodiment, the dielectric filling material 508 comprises silicon and oxygen, such as a silicon oxide or silicon dioxide insulating layer. In an embodiment, a gate electrode is ultimately formed on top of the upper fin portion 502B of the fin 502 and laterally adjacent to the sidewall of the upper fin portion 502B of the fin 502.

[0157] It is important to understand that during processing, the upper fin portion of the semiconductor fin may be eroded or consumed. Furthermore, the trench isolation structure between the fins may also be eroded into a non-planar morphology, or may be formed into a non-planar fabricated top morphology. As an example, Figure 5B A cross-sectional view of another pair of semiconductor fins separated by another three-layer trench isolation structure according to another embodiment of the present disclosure is illustrated.

[0158] refer to Figure 5BThe integrated circuit structure includes a first fin 552, such as a silicon fin. The first fin 552 has a lower fin portion 552A and an upper fin portion 552B, and a shoulder feature 554 in the region between the lower fin portion 552A and the upper fin portion 552B. A second fin 562, such as a second silicon fin, has a lower fin portion 562A and an upper fin portion 562B, and a shoulder feature 564 in the region between the lower fin portion 562A and the upper fin portion 562B. A first insulating layer 574 is directly on the sidewall of the lower fin portion 552A of the first fin 552 and directly on the sidewall of the lower fin portion 562A of the second fin 562. The first insulating layer 574 has a first end portion 574A that is substantially coplanar with the shoulder feature 554 of the first fin 552, and the first insulating layer 574 further has a second end portion 574B that is substantially coplanar with the shoulder feature 564 of the second fin 562. The second insulating layer 576 is directly on the first insulating layer 574, which is directly on the sidewall of the lower fin portion 552A of the first fin 552 and directly on the sidewall of the lower fin portion 562A of the second fin 562.

[0159] The dielectric filling material 578 is laterally adjacent to the second insulating layer 576, which is directly on the first insulating layer 574. The first insulating layer 574 is directly on the sidewall of the lower fin portion 552A of the first fin 552 and directly on the sidewall of the lower fin portion 562A of the second fin 562. In an embodiment, the dielectric filling material 578 has an upper surface 578A, wherein a portion of the upper surface 578A of the dielectric filling material 578 is lower than at least one of the shoulder features 554 of the first fin 552 and lower than at least one of the shoulder features 564 of the second fin 562, such as... Figure 5B As depicted in the text.

[0160] In an embodiment, the first insulating layer 574 is an undoped insulating layer comprising silicon and oxygen, such as silicon oxide or silicon dioxide. In an embodiment, the first insulating layer 574 comprises silicon and oxygen and does not have other atomic species with an atomic concentration greater than 1E15 atoms per cubic centimeter. In an embodiment, the first insulating layer 574 has a thickness in the range of 0.5-2 nanometers.

[0161] In an embodiment, the second insulating layer 576 comprises silicon and nitrogen, such as a silicon nitride insulating layer with a stoichiometric Si3N4, a silicon-rich silicon nitride insulating layer, or a silicon-poor silicon nitride insulating layer. In an embodiment, the second insulating layer 576 has a thickness in the range of 2-5 nanometers.

[0162] In one embodiment, the dielectric filling material 578 comprises silicon and oxygen, such as a silicon oxide or silicon dioxide insulating layer. In another embodiment, a gate electrode is ultimately formed on top of the upper fin portion 552B of the first fin 552 and laterally adjacent to the sidewall of the upper fin portion 552B of the first fin 552, and on top of the upper fin portion 562B of the second fin 562 and laterally adjacent to the sidewall of the upper fin portion 562B of the second fin 562. This gate electrode is further formed on the dielectric filling material 578 between the first fin 552 and the second fin 562.

[0163] Figures 6A-6D Cross-sectional views illustrating various operations in the manufacture of a three-layer trench isolation structure according to embodiments of the present disclosure are shown.

[0164] refer to Figure 6A A method for manufacturing an integrated circuit structure includes forming a fin 602, such as a silicon fin. A first insulating layer 604 is formed directly on the fin 602, and the first insulating layer 604 is conformally fitted to the fin 602, such as... Figure 6B As depicted in the text. In an embodiment, the first insulating layer 604 comprises silicon and oxygen, and does not have other atomic species with an atomic concentration greater than 1E15 atoms per cubic centimeter.

[0165] refer to Figure 6C A second insulating layer 606 is formed directly on the first insulating layer 604, and the second insulating layer 606 is conformally fitted to the first insulating layer 604. In an embodiment, the second insulating layer 606 comprises silicon and nitrogen. A dielectric filling material 608 is formed directly on the second insulating layer 606, such as... Figure 6D As depicted in the text.

[0166] In an embodiment, the method further involves recessing the dielectric filling material 608, the first insulating layer 604, and the second insulating layer 606 to provide an exposed upper fin portion 602A (e.g., such as...). Figure 5A and 5B The upper fin portion (502B, 552B, or 562B) of fin 602. The resulting structure can be as follows: Figure 5A Or as described in 5B. In one embodiment, recessing the dielectric filler 608, the first insulating layer 604, and the second insulating layer 606 involves using a wet etching process. In another embodiment, recessing the dielectric filler 608, the first insulating layer 604, and the second insulating layer 606 involves using a plasma etching or dry etching process.

[0167] In one embodiment, a chemical vapor deposition process is used to form the first insulating layer 604. In another embodiment, a chemical vapor deposition process is used to form the second insulating layer 606. In yet another embodiment, a spin-on process is used to form the dielectric filler material 608. In one such embodiment, the dielectric filler material 608 is a spin-on material and is exposed to vapor treatment, for example, before or after a recess etching process, to provide a cured material comprising silicon and oxygen. In yet another embodiment, a gate electrode is ultimately formed on top of the upper fin portion of the fin 602 and laterally adjacent to the sidewall of the upper fin portion of the fin 602.

[0168] On the other hand, gate sidewall spacer material can be retained over certain trench isolation regions as protection against trench isolation region erosion during subsequent processing operations. For example, Figures 7A-7E An angled three-dimensional cross-sectional view illustrates various operations in a method of manufacturing an integrated circuit structure according to embodiments of the present disclosure.

[0169] refer to Figure 7A A method of manufacturing an integrated circuit structure includes forming a fin 702, such as a silicon fin. The fin 702 has a lower fin portion 702A and an upper fin portion 702B. An insulating structure 704 is formed on the sidewall directly adjacent to the lower fin portion 702A of the fin 702. A gate structure 706 is formed over the upper fin portion 702B and over the insulating structure 704. In an embodiment, the gate structure is a reserved location or a dummy gate structure, which includes a sacrificial gate dielectric layer 706A, a sacrificial gate 706B, and a hard mask 706C. A dielectric material 708 is formed conformally to the upper fin portion 702B of the fin 702, conformally to the gate structure 706, and conformally to the insulating structure 704.

[0170] refer to Figure 7B A hard mask material 710 is formed on top of the dielectric material 708. In an embodiment, the hard mask material 710 is a carbon-based hard mask material formed using a spin coating process.

[0171] refer to Figure 7C The hard mask material 710 is recessed to form a recessed hard mask material 712, exposing a portion of the dielectric material 708 conformally to the upper fin portion 702B of the fin 702 and conformally to the gate structure 706. The recessed hard mask material 712 covers a portion of the dielectric material 708 conformally to the insulating structure 704. In one embodiment, a wet etching process is used to recess the hard mask material 710. In another embodiment, an ashing, dry etching, or plasma etching process is used to recess the hard mask material 710.

[0172] refer to Figure 7DAnisotropic etching of dielectric material 708 is used to form patterned dielectric material 714 (such as dielectric spacer 714A) along the sidewall of gate structure 706, along part of the sidewall of upper fin portion 702B of fin 702, and on insulating structure 704.

[0173] refer to Figure 7E ,from Figure 7D The recessed hard mask material 712 is removed from the structure. In an embodiment, the gate structure 706 is a dummy gate structure, and subsequent processing includes replacing the gate structure 706 with a permanent gate dielectric and a gate electrode stack. In an embodiment, further processing includes forming embedded source or drain structures on opposite sides of the gate structure 706, as described in more detail below.

[0174] Refer again Figure 7E In an embodiment, the integrated circuit structure 700 includes a first fin (702 on the left), such as a first silicon fin, having a lower fin portion 702A and an upper fin portion 702B. The integrated circuit structure further includes a second fin (702 on the right), such as a second silicon fin, having a lower fin portion 702A and an upper fin portion 702B. An insulating structure 704 directly abuts the sidewall of the lower fin portion 702A of the first fin and directly abuts the sidewall of the lower fin portion 702A of the second fin. A gate electrode 706 is located on the upper fin portion 702B of the first fin (702 on the left), on the upper fin portion 702B of the second fin (702 on the right), and on a first portion 704 of the insulating structure 704. A first dielectric spacer 714A is located along the sidewall of the upper fin portion 702B of the first fin (702 on the left), and a second dielectric spacer 702C is located along the sidewall of the upper fin portion 702B of the second fin (702 on the right). The second dielectric spacer 714C is continuous with the first dielectric spacer 714B above the second part 704B of the insulating structure 704 between the first fin (702 on the left) and the second fin (702 on the right).

[0175] In the embodiments, the first and second dielectric spacers 714B and 714C comprise silicon and nitrogen, such as silicon nitride material with a stoichiometric Si3N4, silicon-rich silicon nitride material, or silicon-poor silicon nitride material.

[0176] In an embodiment, the integrated circuit structure 700 further includes an embedded source or drain structure on opposite sides of the gate electrode 706. The embedded source or drain structure has a bottom surface below the top surfaces of the first and second dielectric spacers 714B and 714C along the sidewalls of the upper fin portions 702B of the first and second fins 702, and the source or drain structure has a top surface above the top surfaces of the first and second dielectric spacers 714B and 714C along the sidewalls of the upper fin portions 702B of the first and second fins 702, as described below. Figure 9B As described. In an embodiment, the insulating structure 704 includes a first insulating layer, a second insulating layer directly on the first insulating layer, and a dielectric filling material directly laterally on the second insulating layer, as also described below. Figure 9B As described.

[0177] Figures 8A-8F Examples of various operations in a method for manufacturing an integrated circuit structure according to embodiments of the present disclosure are illustrated. Figure 7E A slightly projected cross-sectional view taken along the a-a' axis.

[0178] refer to Figure 8A Methods for manufacturing integrated circuit structures include forming fins 702, such as silicon fins. Fin 702 has a lower fin portion (in... Figure 8A (Not visible in the image) and the upper fin portion 702B. An insulating structure 704 is formed on the sidewall of the lower fin portion 702A directly adjacent to the fin 702. A pair of gate structures 706 are formed on the upper fin portion 702B and on the insulating structure 704. It should be understood that in Figures 8A-8F The view shown is slightly projected to show a portion of the insulating structure and gate structure 706 in front of the upper fin portion 702B (outside the page), where the upper fin portion extends slightly into the page. In an embodiment, the gate structure 706 is a reserved location or dummy gate structure that includes a sacrificial gate dielectric layer 706A, a sacrificial gate 706B, and a hard mask 706C.

[0179] refer to Figure 8B Its corresponding connection Figure 7A The described process involves forming a dielectric material 708 conformally with the upper fin portion 702B of the fin 702, conformally with the gate structure 706, and conformally with the exposed portion of the insulating structure 704.

[0180] refer to Figure 8C Its corresponding connection Figure 7B The described process involves forming a hard mask material 710 on a dielectric material 708. In an embodiment, the hard mask material 710 is a carbon-based hard mask material formed using a spin coating process.

[0181] refer to Figure 8D Its corresponding connection Figure 7C The described process involves recessing the hard mask material 710 to form a recessed hard mask material 712 and exposing a portion of the dielectric material 708 conformally to the upper fin portion 702B of the fin 702 and conformally to the gate structure 706. The recessed hard mask material 712 covers a portion of the dielectric material 708 conformally to the insulating structure 704. In one embodiment, a wet etching process is used to recess the hard mask material 710. In another embodiment, an ashing, dry etching, or plasma etching process is used to recess the hard mask material 710.

[0182] refer to Figure 8E Its corresponding connection Figure 7D The described process involves anisotropically etching dielectric material 708 to form a patterned dielectric material 714 along the sidewall of gate structure 706 (as part 714A), along part of the sidewall of the upper fin portion 702B of fin 702, and on insulating structure 704.

[0183] refer to Figure 8F Its corresponding connection Figure 7E The described process operation, from Figure 8E The recessed hard mask material 712 is removed from the structure. In an embodiment, the gate structure 706 is a dummy gate structure, and subsequent processing includes replacing the gate structure 706 with a permanent gate dielectric and a gate electrode stack. In an embodiment, further processing includes forming embedded source or drain structures on opposite sides of the gate structure 706, as described in more detail below.

[0184] Refer again Figure 8F In an embodiment, the integrated circuit structure 700 includes a fin 702, such as a silicon fin, which has a lower fin portion (in... Figure 8F (Not visible in the middle) and upper fin portion 702B. Insulating structure 704 is directly adjacent to the sidewall of the lower fin portion of fin 702. First gate electrode (left side 706) is above upper fin portion 702B and above the first portion 704A of insulating structure 704. Second gate electrode (right side 706) is above upper fin portion 702B and above the second portion 704A' of insulating structure 704. First dielectric spacer (right side 714A of left side 706) is along the sidewall of first gate electrode (left side 706), and second dielectric spacer (left side 714A of right side 706) is along the sidewall of second gate electrode (right side 706). The second dielectric spacer is continuous with the first dielectric spacer on the third portion 704A'' of insulating structure 704 between first gate electrode (left side 706) and second gate electrode (right side 706).

[0185] Figure 9A Examples of integrated circuit structures including permanent gate stacks and epitaxial source or drain regions according to embodiments of the present disclosure are illustrated. Figure 7E A slightly projected cross-sectional view taken along the a-a' axis. Figure 9B Examples of integrated circuit structures including epitaxial source or drain regions and multilayer trench isolation structures according to embodiments of the present disclosure are illustrated. Figure 7E A cross-sectional view taken along the b-b' axis.

[0186] refer to Figure 9A and 9B In an embodiment, the integrated circuit structure includes an embedded source or drain structure 910 on opposite sides of the gate electrode 706. The embedded source or drain structure 910 has a bottom surface 910A along the sidewall of the upper fin portion 702B of the first and second fins 702, below the top surface 990 of the first and second dielectric spacers 714B and 714C. The embedded source or drain structure 910 has a top surface 910B along the sidewall of the upper fin portion 702B of the first and second fins 702, above the top surface of the first and second dielectric spacers 714B and 714C.

[0187] In an embodiment, the gate stack 706 is a permanent gate stack 920. In one such embodiment, the permanent gate stack 920 includes a gate dielectric layer 922, a first gate layer 924 such as a work function gate layer, and a gate fill material 926, such as... Figure 9A As depicted in the figure. In one embodiment, the permanent gate structure 920 is formed on a residual polysilicon portion 930 over an insulating structure 704, which may be a remnant of an alternative gate process involving a sacrificial polysilicon gate electrode.

[0188] In one embodiment, the insulating structure 704 includes a first insulating layer 902, a second insulating layer 904 directly on the first insulating layer 902, and a dielectric filling material 906 directly laterally on the second insulating layer 904. In one embodiment, the first insulating layer 902 is an undoped insulating layer comprising silicon and oxygen. In one embodiment, the second insulating layer 904 comprises silicon and nitrogen. In one embodiment, the dielectric filling material 906 comprises silicon and oxygen.

[0189] In another aspect, the epitaxial embedded source or drain region is implemented as a source or drain structure for a semiconductor fin. As an example, Figure 10 A cross-sectional view of an integrated circuit structure taken at the source or drain location according to an embodiment of the present disclosure is illustrated.

[0190] refer to Figure 10The integrated circuit structure 1000 includes P-type devices, such as P-type metal-oxide-semiconductor (PMOS) devices. The integrated circuit structure 1000 also includes N-type devices, such as N-type metal-oxide-semiconductor (NMOS) devices.

[0191] Figure 10 The PMOS device includes a first plurality of semiconductor fins 1002, such as silicon fins formed from a bulk silicon substrate 1001. At the source or drain location, the upper portion of the fins 1002 has been removed, and the same or different semiconductor materials are grown to form source or drain structures 1004. It should be understood that in a cross-sectional view taken from either side of the gate electrode, the source or drain structures 1004 will appear identical; for example, they will appear substantially the same on the source side as on the drain side. In an embodiment, as depicted, the source or drain structure 1004 has a portion below the upper surface of the insulating structure 1006 and a portion above the upper surface. In an embodiment, as depicted, the source or drain structure 1004 is strongly faceted. In an embodiment, conductive contacts 1008 are formed on the source or drain structure 1004. However, in one such embodiment, the strong facet miniaturization and relatively wide growth of the source or drain structure 1004 at least partially inhibits good coverage by the conductive contact portion 1008.

[0192] Figure 10 The NMOS device includes a second plurality of semiconductor fins 1052, such as silicon fins formed from a bulk silicon substrate 1001. At the source or drain location, the upper portion of the fins 1052 has been removed, and the same or different semiconductor materials are grown to form source or drain structures 1054. It should be understood that the source or drain structures 1054 will appear identical in a cross-sectional view taken from either side of the gate electrode; for example, they will appear substantially the same on the source side as on the drain side. In an embodiment, as depicted, the source or drain structure 1054 has a portion below the upper surface of the insulating structure 1006 and a portion above the upper surface. In an embodiment, as depicted, the source or drain structure 1054 is weakly areaified relative to the source or drain structure 1004. In an embodiment, conductive contacts 1058 are formed on the source or drain structure 1054. In one such embodiment, the relatively weak facetization of the source or drain structure 1054 (as compared to the source or drain structure 1004) and the resulting relatively narrow growth enhance the good coverage by the conductive contact 1058.

[0193] The shape of the source or drain structure of a PMOS device can be altered to increase the contact area with the superimposed contact. For example, Figure 11 A cross-sectional view of another integrated circuit structure taken at the source or drain location according to an embodiment of the present disclosure is illustrated.

[0194] refer to Figure 11 The integrated circuit structure 1100 includes a P-type semiconductor (e.g., PMOS) device. The PMOS device includes a first fin 1102, such as a silicon fin. A first epitaxial source or drain structure 1104 is embedded in the first fin 1102. In one embodiment, although not depicted, the first epitaxial source or drain structure 1104 is located on a first side of a first gate electrode (which may be formed on an upper fin portion such as a channel portion of the fin 1102), and a second epitaxial source or drain structure is embedded in the first fin 1102 on a second side of such a first gate electrode opposite to the first side. In an embodiment, the first epitaxial source or drain structure 1104 and the second epitaxial source or drain structure comprise silicon and germanium and have a profile 1105. In one embodiment, this profile is a matchstick-shaped profile, such as... Figure 11 As depicted in the diagram, the first conductive electrode 1108 is located on the first epitaxial source or drain structure 1104.

[0195] Refer again Figure 11 In one embodiment, the integrated circuit structure 1100 further includes an N-type semiconductor (e.g., NMOS) device. The NMOS device includes a second fin 1152, such as a silicon fin. A third epitaxial source or drain structure 1154 is embedded in the second fin 1152. In one embodiment, although not depicted, the third epitaxial source or drain structure 1154 is located on a first side of a second gate electrode (which may be formed over an upper fin portion such as a channel portion of the fin 1152), and a fourth epitaxial source or drain structure is embedded in the second fin 1152 on a second side of such a second gate electrode opposite to the first side. In one embodiment, the third epitaxial source or drain structure 1154 and the fourth epitaxial source or drain structure comprise silicon and have substantially the same outline as the outline 1105 of the first epitaxial source or drain structure 1104 and the second epitaxial source or drain structure. A second conductive electrode 1158 is located above the third epitaxial source or drain structure 1154.

[0196] In one embodiment, the first epitaxial source or drain structure 1104 is weakly surface-formed. In another embodiment, the first epitaxial source or drain structure 1104 has a height of approximately 50 nanometers and a width in the range of 30-35 nanometers. In one such embodiment, the third epitaxial source or drain structure 1154 has a height of approximately 50 nanometers and a width in the range of 30-35 nanometers.

[0197] In one embodiment, the first epitaxial source or drain structure 1104 gradually varies in germanium concentration from approximately 20% at the bottom 1104A of the first epitaxial source or drain structure 1104 to approximately 45% at the top 1104B of the first epitaxial source or drain structure 1104. In another embodiment, the first epitaxial source or drain structure 1104 is doped with boron atoms. In one such embodiment, the third epitaxial source or drain structure 1154 is doped with phosphorus or arsenic atoms.

[0198] Figure 12A-12D Examples of various operations in manufacturing an integrated circuit structure according to embodiments of the present disclosure are illustrated, and cross-sectional views are taken at the source or drain locations.

[0199] refer to Figure 12A A method of manufacturing an integrated circuit structure includes forming fins, such as silicon fins formed from a silicon substrate 1201. Fin 1202 has a lower fin portion 1202A and an upper fin portion 1202B. In an embodiment, although not depicted, a gate electrode is formed over a portion of the upper fin portion 1202B at a location where it enters the page. Such a gate electrode has a first side opposite a second side, and defines source or drain locations on said first and second sides. For example, for illustrative purposes, a cut is made at one of the source or drain locations on one of the sides of the gate electrode for... Figure 12A-12D The cross-sectional position of the view.

[0200] refer to Figure 12B This causes the source or drain position of fin 1202 to be recessed to form a recessed fin portion 1206. The recessed source or drain position of fin 1202 can be located on one side of the gate electrode and on the second side of the gate electrode. (See reference) Figure 12A and 12B In both embodiments, a dielectric spacer 1204 is formed along a portion of the sidewall of the fin 1202, for example, on one side of the gate structure. In one such embodiment, recessing the fin 1202 involves recessing the fin 1202 below the top surface 1204A of the dielectric spacer 1204.

[0201] refer to Figure 12C For example, an epitaxial source or drain structure 1208 is formed on the recessed fin 1206, and thus the epitaxial source or drain structure 1208 can be formed on one side of the gate electrode. In one such embodiment, a second epitaxial source or drain structure is formed on a second portion of the recessed fin 1206 on a second side of such a gate electrode. In an embodiment, the epitaxial source or drain structure 1208 comprises silicon and germanium and has a matchstick-shaped profile, such as... Figure 12CAs depicted in the figure. In an embodiment, a dielectric spacer 1204 is included, and it is the lower portion 1208A along the sidewall of the epitaxial source or drain structure 1208, as depicted.

[0202] refer to Figure 12D A conductive electrode 1210 is formed on the epitaxial source or drain structure 1208. In one embodiment, the conductive electrode 1210 includes a conductive barrier layer 1210A and a conductive filler material 1210B. In one embodiment, the conductive electrode 1210 follows the contour of the epitaxial source or drain structure 1208 as depicted. In other embodiments, the upper portion of the epitaxial source or drain structure 1208 is etched during the fabrication of the conductive electrode 1210.

[0203] In another aspect, fin trimming isolation (FTI) and a single-gate spacing for the isolated fins are described. Non-planar transistors utilizing fins of semiconductor material protruding from the substrate surface employ gate electrodes (i.e., dual-gate, tri-gate, nanowire transistors) surrounding two, three, or even all sides of the fin. Source and drain regions are then typically formed in the fin on either side of the gate electrode, or formed as regrowth portions of the fin. To isolate the source or drain region of a first non-planar transistor from the source or drain region of an adjacent second non-planar transistor, a gap or spacing can be formed between two adjacent fins. Such isolation gaps generally require some form of masked etching. Once isolated, gate stacks are then patterned over the individual fins, again typically using some form of masked etching (e.g., line etching or aperture etching, depending on the specific implementation).

[0204] A potential problem with the aforementioned fin isolation technology is that the gate does not automatically align with the tip of the fin, and the alignment of the gate stack pattern with the semiconductor fin pattern depends on the superposition of these two patterns. Consequently, photolithographic superposition tolerances are added to the dimensional determination of the semiconductor fins and isolation gaps, where the fins need to have a relatively large length and the isolation gaps are larger than they would otherwise be for a given transistor functionality level. Device architectures and fabrication techniques that reduce such over-dimensional determinations thus offer highly advantageous improvements in transistor density.

[0205] Another potential problem with the fin isolation technique described above is that the stress in the semiconductor fins desired for improved carrier mobility may be lost from the channel region of the transistor, where excessive fin surface stress is released during fabrication, thus allowing fin strain relaxation. Device architectures and fabrication techniques that maintain high levels of desired fin stress therefore offer advantageous improvements in nonplanar transistor performance.

[0206] According to embodiments of this disclosure, through-gate fin isolation architectures and techniques are described herein. In the exemplary embodiments illustrated, non-planar transistors in a microelectronic device, such as an integrated circuit (IC), are isolated from each other in a manner that aligns themselves to the gate electrode of the transistor. While embodiments of this disclosure are applicable to virtually any IC employing non-planar transistors, exemplary ICs include, but are not limited to: microprocessor cores including logic and memory (SRAM) portions, RFICs (e.g., wireless ICs including digital baseband and analog front-end modules), and power ICs.

[0207] In embodiments, isolation regions are used to electrically isolate the ends of adjacent semiconductor fins from each other, and the isolation regions are positioned relative to the gate electrode using only a single patterned mask stage. In embodiments, a single mask is used to form multiple sacrificial reserved location strips with a fixed pitch. A first subset of the reserved location strips defines the location or size of the isolation region, while a second subset defines the location or size of the gate electrode. In some embodiments, the first subset of the reserved location strips is removed, and isolation notches are made in the semiconductor fins within the openings obtained by removing the first subset, ultimately replacing the second subset of the reserved location strips with a non-sacrificial gate electrode stack. Because a subset of reserved locations for gate electrode replacement is used to form the isolation region, this method and the resulting architecture are referred to herein as “through-gate” isolation. One or more through-gate isolations described herein can, for example, enable higher transistor densities and higher levels of favorable transistor channel stress.

[0208] By utilizing isolation defined after the placement or definition of the gate electrode, a higher transistor density can be achieved because the fin isolation size can be determined and positioned perfectly on-pitch with respect to the gate electrode, such that both the gate electrode and the isolation region are integer multiples of the minimum feature pitch of a single masking level. In another embodiment where the semiconductor fin has a lattice mismatch with the substrate on which the fin is placed, a greater degree of strain is maintained by defining isolation after the placement or definition of the gate electrode. For such embodiments, other features of the transistor formed before defining the fin tip (such as the gate electrode and any added source or drain material) help to mechanically maintain fin strain after the isolation notch is formed in the fin.

[0209] To provide further context, transistor scaling can benefit from denser packing of cells within a chip. Currently, most cells are separated from their neighboring cells by two or more dummy gates with buried fins. The cells are isolated by etching fins beneath these two or more dummy gates, which connect one cell to another. Scaling can be significantly beneficial if the number of dummy gates separating neighboring cells can be reduced from two or more to one. As explained above, one solution requires two or more dummy gates. The fins beneath these two or more dummy gates are etched during fin patterning. A potential problem with such a method is that the dummy gates consume space on the chip that can be used for cells. In embodiments, the method described herein makes it possible to separate neighboring cells using only a single dummy gate.

[0210] In this embodiment, the fin trimming isolation method is implemented as a self-aligned patterning scheme. Here, the fins beneath a single gate are etched away. Therefore, adjacent cells can be separated by a single dummy gate. Advantages of such a method can include saving on-chip space and allowing for more computational power for a given area. This method can also allow fin trimming to be performed at sub-fin pitch distances.

[0211] Figure 13A and 13B A plan view illustrating various operations in a patterning method having fins with multiple gate spacings for forming local isolation structures, according to embodiments of the present disclosure, is shown.

[0212] refer to Figure 13A The diagram shows a plurality of fins 1302 having a length along a first direction 1304. A grid 1306 is shown along a second direction 1308 orthogonal to the first direction 1304, with spacings 1307 therebetween, the grid 1306 defining locations for the eventual formation of a plurality of gate lines.

[0213] refer to Figure 13B A portion of the plurality of fins 1302 is cut (e.g., removed by an etching process) to leave fins 1310 with cutouts 1312 therein. The isolation structure ultimately formed in the cutouts 1312 therefore has a size larger than a single gate line, for example, having the size of three gate lines 1306. Thus, the gate structure ultimately formed along the location of the gate lines 1306 will be formed at least partially on top of the isolation structure in the cutouts 1312. Therefore, the cutouts 1312 are relatively wide fin cutouts.

[0214] Figures 14A-14D A plan view illustrating various operations in a patterning method having fins with single gate spacing for forming a local isolation structure, according to another embodiment of the present disclosure, is shown.

[0215] refer to Figure 14A A method of manufacturing an integrated circuit structure includes forming a plurality of fins 1402, each of the plurality of fins 1402 having a longest dimension along a first direction 1404. A plurality of gate structures 1406 are placed above the plurality of fins 1402, each of the gate structures 1406 having a longest dimension along a second direction 1408 orthogonal to the first direction 1404. In an embodiment, the gate structure 1406 is, for example, a sacrificial gate line or a dummy gate line made of polysilicon. In one embodiment, the plurality of fins 1402 are silicon fins and are continuous with a portion of an underlying silicon substrate.

[0216] refer to Figure 14B A dielectric material structure 1410 is formed between adjacent gate structures 1406 in a plurality of gate structures 1406.

[0217] refer to Figure 14C A portion 1412 of one of the plurality of gate structures 1406 is removed to expose a portion 1414 of each of the plurality of fins 1402. In an embodiment, removing a portion 1412 of one of the plurality of gate structures 1406 involves using a photolithographic window 1416 that is wider than the width 1418 of that portion 1412 of the plurality of gate structures 1406.

[0218] refer to Figure 14D The exposed portion 1414 of each of the plurality of fins 1402 is removed to form a cut-out region 1420. In an embodiment, a dry or plasma etching process is used to remove the exposed portion 1414 of each of the plurality of fins 1402. In an embodiment, removing the exposed portion 1414 of each of the plurality of fins 1402 involves etching to a depth smaller than the height of the plurality of fins 1402. In one such embodiment, this depth is greater than the depth of the source or drain regions in the plurality of fins 1402. In an embodiment, this depth is greater than the depth of the effective portion of the plurality of fins 1402 to provide an isolation margin. In an embodiment, the exposed portion 1414 of each of the plurality of fins 1402 is removed without etching or substantially without etching the source or drain regions (such as epitaxial source or drain regions) of the plurality of fins 1402. In one such embodiment, the exposed portion 1414 of each of the plurality of fins 1402 is removed without lateral etching or substantially without lateral etching of the source or drain regions (such as epitaxial source or drain regions) of the plurality of fins 1402.

[0219] In one embodiment, the cut-out region 1420 is ultimately filled with an insulating layer at the location of the removed portion 1414 of each of the plurality of fins 1402. Exemplary insulating layer, or "aggregate cut-out," or "plug" structures are described below. However, in other embodiments, the cut-out region 1420 is only partially filled with an insulating layer, and then a conductive structure is formed within the insulating layer. This conductive structure can serve as a local interconnect. In another embodiment, before filling the cut-out region 1420 with an insulating layer or with an insulating layer that accommodates the local interconnect structure, dopant can be injected or delivered through a solid source dopant layer across the cut-out region 1420 to the partially cut portion of one or more fins.

[0220] Figure 15 A cross-sectional view of an integrated circuit structure with fins according to an embodiment of the present disclosure is illustrated, the fins having multiple gate spacings for local isolation.

[0221] refer to Figure 15 The silicon fin 1502 has a first fin portion 1504 laterally adjacent to the second fin portion 1506. This is achieved through a relatively wide cutout 1508 (such as a contact). Figure 13A and 13B The first fin portion 1504 and the second fin portion 1506 are separated by a relatively wide cutout 1508 having a width X. A dielectric filler material 1510 is formed in the relatively wide cutout 1508, and the dielectric filler material 1510 electrically isolates the first fin portion 1504 and the second fin portion 1506. A plurality of gate lines 1512 are on the silicon fin 1502, each of which may include a gate dielectric and a gate electrode stack 1514, a dielectric capping layer 1516, and a sidewall spacer 1518. Two gate lines (the two gate lines 1512 on the left) occupy the relatively wide cutout 1508, and thus, the first fin portion 1504 and the second fin portion 1506 are effectively separated by two dummy gates or invalid gates.

[0222] In contrast, fin sections can be separated by a single gate spacing. As an example, Figure 16A A cross-sectional view of an integrated circuit structure with fins according to another embodiment of the present disclosure is illustrated, the fins having single gate spacing for local isolation.

[0223] refer to Figure 16A The silicon fin 1602 has a first fin portion 1604 laterally adjacent to the second fin portion 1606. This is achieved through a relatively narrow cutout 1608 (such as a contact). Figures 14A-14D (As described) The first fin portion 1604 is separated from the second fin portion 1606, and the relatively narrow cut 1608 has a width Y, where Y is less than... Figure 15The X. A dielectric filler 1610 is formed in the relatively narrow cut 1608, and the dielectric filler 1610 electrically isolates the first fin portion 1604 from the second fin portion 1606. A plurality of gate lines 1612 are on the silicon fin 1602, each of which may include a gate dielectric and gate electrode stack 1614, a dielectric capping layer 1616, and a sidewall spacer 1618. The dielectric filler 1610 occupies the position previously occupied by a single gate line, thereby separating the first fin portion 1604 from the second fin portion 1606 by a single "plugged" gate line. In one embodiment, residual spacer material 1620 is retained on the sidewall at the location of the removed gate line portion, as depicted. It should be understood that other regions of fin 1602 can be isolated from each other by two or more invalid gate lines (region 1622 with three invalid gate lines) made by an earlier, wider fin cutting process, as described below.

[0224] Refer again Figure 16A The integrated circuit structure 1600 includes a fin 1602, such as a silicon fin. The fin 1602 has a longest dimension along a first direction 1650. An isolation structure 1610 separates a first upper portion 1604 of the fin 1602 from a second upper portion 1606 of the fin 1602 along the first direction 1650. The isolation structure 1610 has a center 1611 along the first direction 1650.

[0225] A first gate structure 1612A is located above a first upper portion 1604 of fin 1602. The first gate structure 1612A has its longest dimension along a second direction 1652 (e.g., in the middle of a page) orthogonal to a first direction 1650. The center 1613A of the first gate structure 1612A is spaced from the center 1611 of the isolation structure 1610 by a pitch along the first direction 1650. A second gate structure 1612B is located above the first upper portion 1604 of fin. The second gate structure 1612B has its longest dimension along the second direction 1652. The center 1613B of the second gate structure 1612B is spaced from the center 1613A of the first gate structure 1612A by this pitch along the first direction 1650. A third gate structure 1612C is located above a second upper portion 1606 of fin 1602. The third gate structure 1612C has its longest dimension along the second direction 1652. The center 1613C of the third gate structure 1612C is spaced apart from the center 1611 of the isolation structure 1610 by the pitch along the first direction 1650. In an embodiment, the isolation structure 1610 has a top that is substantially coplanar with the top of the first gate structure 1612A, the top of the second gate structure 1612B, and the top of the third gate structure 1612C, as depicted.

[0226] In an embodiment, each of the first gate structure 1612A, the second gate structure 1612B, and the third gate structure 1612C includes a gate electrode 1660 on and between the sidewalls of the high-k gate dielectric layer 1662, as illustrated with respect to the exemplary third gate structure 1612C. In one such embodiment, each of the first gate structure 1612A, the second gate structure 1612B, and the third gate structure 1612C further includes an insulating cap 1616 on the gate electrode 1660 and on the sidewall of the high-k gate dielectric layer 1662.

[0227] In one embodiment, the integrated circuit structure 1600 further includes a first epitaxial semiconductor region 1664A on a first upper portion 1604 of the fin 1602 between the first gate structure 1612A and the isolation structure 1610. A second epitaxial semiconductor region 1664B is located on the first upper portion 1604 of the fin 1602 between the first gate structure 1612A and the second gate structure 1612B. A third epitaxial semiconductor region 1664C is located on a second upper portion 1606 of the fin 1602 between the third gate structure 1612C and the isolation structure 1610. In one embodiment, the first, second, and third epitaxial semiconductor regions 1664A, 1664B, and 1664C comprise silicon and germanium. In another embodiment, the first, second, and third epitaxial semiconductor regions 1664A, 1664B, and 1664C comprise silicon.

[0228] In one embodiment, the isolation structure 1610 induces stress on a first upper portion 1604 and a second upper portion 1606 of the fin 1602. In one embodiment, the stress is compressive stress. In another embodiment, the stress is tensile stress. In other embodiments, the isolation structure 1610 is a partially filled insulating layer, in which a conductive structure is then formed. This conductive structure can serve as a local interconnect. In one embodiment, before forming the isolation structure 1610 with an insulating layer or with an insulating layer that accommodates the local interconnect structure, dopant is implanted or delivered to the locally cut portions of the one or more fins via a solid source dopant layer.

[0229] On the other hand, it should be understood that an isolation structure such as the aforementioned isolation structure 1610 can be formed in place of an effective gate electrode at a local location or a wider location of the fin cut. Additionally, the depth of such local or wider locations of the fin cut can be formed to vary relative to each other within the fin. In the first example, Figure 16B A cross-sectional view illustrating an embodiment of the present disclosure is shown, in which a fin isolation structure may be formed in place of the gate electrode.

[0230] refer to Figure 16BA fin 1680, such as a silicon fin, is formed above and continuous with a substrate 1682. The fin 1680 has a fin tip or a wide fin cutout 1684, which may be formed, for example, during fin patterning as described above in the fin trimming end pass method. The fin 1680 also has a partial cutout 1686, in which a portion of the fin 1680 is removed, for example, using a fin trimming isolation method, in which a dielectric plug is used instead of a dummy gate as described above. An effective gate electrode 1688 is formed on the fin, and for illustrative purposes, the effective gate electrode 1688 is shown slightly in front of the fin 1680, which is in the background, with the dashed line indicating the area covered from the front view. A dielectric plug 1690 may be formed at the fin tip or the wide fin cutout 1684 instead of using an effective gate at these locations. Furthermore or alternatively, a dielectric plug 1692 may be formed at the partial cutout 1686 instead of using an effective gate at these locations. It should be understood that an epitaxial source or drain region 1694 is also shown at the location of fin 1680 between the effective gate electrode 1688 and plug 1690 or 1692. Additionally, in an embodiment, the surface roughness of the fin tip at the partial notch 1686 is rougher than that of the fin tip at the location of the wider notch, such as... Figure 16B As depicted in the text.

[0231] Figures 17A-17C Various depth possibilities for fin cuts manufactured using the fin trimming isolation method are illustrated according to embodiments of the present disclosure.

[0232] refer to Figure 17A Semiconductor fins 1700, such as silicon fins, are formed above and continuous with the underlying substrate 1702. The fin 1700 has a lower fin portion 1700A and an upper fin portion 1700B, defined by an insulating structure 1704 relative to the height of the fin 1700. A partial fin isolation notch 1706A separates the fin 1700 into a first fin portion 1710 and a second fin portion 1712. Figure 17A In the example, as shown along the a-a' axis, the depth of the local fin isolation cut 1706A is the entire depth from fin 1700 to substrate 1702.

[0233] refer to Figure 17B In the second example, as shown along the a-a' axis, the depth of the local fin isolation cut 1706B is greater than the entire depth from the fin 1700 to the substrate 1702. That is, the cut 1706B extends into the underlying substrate 1702.

[0234] refer to Figure 17C In the third example, as shown along the a-a' axis, the depth of the local fin isolation cut 1706C is smaller than the entire depth of the fin 1700, but deeper than the upper surface of the isolation structure 1704. (See again...) Figure 17C In the fourth example, as shown along the a-a' axis, the depth of the local fin isolation cut 1706D is smaller than the entire depth of the fin 1700 and is at a level that is approximately coplanar with the upper surface of the isolation structure 1704.

[0235] Figure 18 The plan view and the corresponding cross-sectional view taken along the a-a' axis illustrate possible options for the depth of a fin cut in a local location relative to a wider location, according to embodiments of the present disclosure.

[0236] refer to Figure 18 First and second semiconductor fins 1800 and 1802, such as silicon fins, have upper fin portions 1800B and 1802B extending over an insulating structure 1804. Both fins 1800 and 1802 have fin tips or wide fin cutouts 1806, which may be formed during fin patterning, such as in the fin trimming end-pass method described above. Both fins 1800 and 1802 also have partial cutouts 1808, where a portion of fin 1800 or 1802 is removed, for example, using a fin trimming isolation method, in which a dielectric plug is replaced with a dummy gate as described above. In embodiments, the surface roughness of the tips of fins 1800 and 1802 at partial cutout 1808 is rougher than that at the fin tips at location 1806, such as... Figure 18 As depicted in the text.

[0237] refer to Figure 18 In the cross-sectional view, the lower fin portions 1800A and 1802A are visible below the height of the insulating structure 1804. Also seen in this cross-sectional view is the residual portion 1810 of the fin, which was removed during the final fin trimming process prior to the formation of the insulating structure 1804, as described above. Although shown as protruding above the substrate, the residual portion 1810 may also be at the substrate level or into the substrate, as depicted by the additional exemplary wide cut depth 1820. It should be understood that the wide cut 1806 for fins 1800 and 1802 may also be at the level described for cut depth 1820, an example of which is depicted. The partial cut 1808 may have a corresponding cut for... Figures 17A-17C An exemplary depth is described, as depicted.

[0238] Common Reference Figure 16A , 16BAccording to embodiments of the present disclosure, 17A-17C and 18, an integrated circuit structure includes a silicon-containing fin having a top and sidewalls, wherein the top has a longest dimension along a first direction. A first isolation structure spaced a first end of a first portion of the fin from a first end of a second portion of the fin along the first direction. The first isolation structure has a width along the first direction. The first end of the first portion of the fin has a surface roughness. A gate structure includes a gate electrode on top of the fin and laterally adjacent to the sidewalls of a region of the first portion of the fin. The gate structure has a width along the first direction and its center is spaced from the center of the first isolation structure by a pitch along the first direction. A second isolation structure is located on a second end of the first portion of the fin, the second end opposite the first end. The second isolation structure has a width along the first direction, and the second end of the first portion of the fin has a smaller surface roughness than the surface roughness of the first end of the first portion of the fin. The center of the second isolation structure is spaced from the center of the gate structure by a pitch along the first direction.

[0239] In one embodiment, the first end of the first portion of the fin has a serrated morphology, such as... Figure 16B As depicted in [the text]. In one embodiment, a first epitaxial semiconductor region is located on a first portion of the fin between the gate structure and the first isolation structure. A second epitaxial semiconductor region is located on a first portion of the fin between the gate structure and the second isolation structure. In one embodiment, the first and second epitaxial semiconductor regions have widths along a second direction orthogonal to the first direction, and the width along the second direction is wider than the width along the second direction of the first portion of the fin below the gate structure, for example, as described in [the text]. Figure 11 and 12D The extensional features described have more than in Figure 11 and 12D The fins on which they grow are wider in the view shown. In one embodiment, the gate structure further includes a high-k dielectric layer between the gate electrode and the first portion of the fin and along the sidewall of the gate electrode.

[0240] Common Reference Figure 16A , 16BAccording to another embodiment of this disclosure, 17A-17C and 18, an integrated circuit structure includes a silicon-containing fin having a top and sidewalls, wherein the top has a longest dimension along one direction. A first isolation structure spaced along this direction a first end of a first portion of the fin from a first end of a second portion of the fin. The first end of the first portion of the fin has a depth. A gate structure includes a gate electrode above the top of the fin and laterally adjacent to the sidewalls of a region of the first portion of the fin. A second isolation structure is located above a second end of the first portion of the fin, the second end being opposite the first end. The second end of the first portion of the fin has a depth different from the depth of the first end of the first portion of the fin.

[0241] In one embodiment, the depth of the second end of the first portion of the fin is less than the depth of the first end of the first portion of the fin. In another embodiment, the depth of the second end of the first portion of the fin is greater than the depth of the first end of the first portion of the fin. In one embodiment, the first isolation structure has a width along this direction, and the gate structure has a width along this direction. The second isolation structure has a width along this direction. In one embodiment, the center of the gate structure is spaced apart from the center of the first isolation structure by a pitch along this direction, and the center of the second isolation structure is spaced apart from the center of the gate structure by a pitch along this direction.

[0242] Common Reference Figure 16A , 16B According to another embodiment of this disclosure, 17A-17C and 18, the integrated circuit structure includes a first fin comprising silicon, the first fin having a top and sidewalls, wherein the top has a longest dimension along a certain direction, and a discontinuity along that direction separates a first end of a first portion of the first fin from a first end of a second portion of the fin. The first portion of the first fin has a second end opposite to the first end, and the first end of the first portion of the fin has a depth. The integrated circuit structure also includes a second fin comprising silicon, the second fin having a top and sidewalls, wherein the top has a longest dimension along the direction. The integrated circuit structure also includes a remaining or residual fin portion between the first fin and the second fin. The residual fin portion has a top and sidewalls, wherein the top has a longest dimension along the direction, and the depth of the top is not coplanar with the depth of the first end of the first portion of the fin.

[0243] In one embodiment, the depth of the first end of the first portion of the fin is lower than the top of the remaining or residual fin portion. In one embodiment, the second end of the first portion of the fin has a depth coplanar with the depth of the first end of the first portion of the fin. In one embodiment, the second end of the first portion of the fin has a depth lower than the depth of the first end of the first portion of the fin. In one embodiment, the second end of the first portion of the fin has a depth higher than the depth of the first end of the first portion of the fin. In one embodiment, the depth of the first end of the first portion of the fin is higher than the top of the remaining or residual fin portion. In one embodiment, the second end of the first portion of the fin has a depth coplanar with the depth of the first end of the first portion of the fin. In one embodiment, the second end of the first portion of the fin has a depth lower than the depth of the first end of the first portion of the fin. In one embodiment, the second end of the first portion of the fin has a depth higher than the depth of the first end of the first portion of the fin. In one embodiment, the second end of the first portion of the fin has a depth coplanar with the top of the residual fin portion. In one embodiment, the second end of the first portion of the fin has a depth lower than the top of the residual fin portion. In one embodiment, the second end of the first portion of the fin has a depth higher than the top of the residual fin portion.

[0244] In another embodiment, dielectric plugs formed at the locations of partial or wide fin cuts can be used to provide specific stress to the fin or fin portion. In such an embodiment, the dielectric plug can be referred to as a fin end stress source.

[0245] One or more embodiments relate to the fabrication of fin-based semiconductor devices. Performance improvements for such devices can be achieved via channel stress induced from the polymer plug-in filling process. Embodiments may include inducing mechanical stress in the channel of a metal-oxide-semiconductor field-effect transistor (MOSFET) using material properties during the polymer plug-in filling process. As a result, the induced stress can improve the transistor's mobility and drive current. Furthermore, the plug-in filling method described herein can allow the elimination of any seams or voids formed during deposition.

[0246] To provide context, manipulating the unique material properties of the plug filler adjacent to the fins can induce stress within the channel. According to one or more embodiments, by adjusting the composition, deposition, and post-processing conditions of the plug filler material, the stress in the channel is modulated to benefit both NMOS and PMOS transistors. Furthermore, such plugs can reside deeper in the fin substrate compared to other common stress-generating techniques such as epitaxial sources or drains. The properties of the plug filler used to achieve this effect also eliminate seams or voids during deposition and mitigate certain defect modes during the process.

[0247] To provide further context, there is currently no intentional stress engineering for the gate (polymerized) plug. Unfortunately, stress enhancement from conventional stress sources tends to decrease as the device pitch shrinks, such as epitaxial source or drain, dummy polymerized gate removal, stress pads, etc. To address one or more of the above problems, according to one or more embodiments of this disclosure, additional stress sources are incorporated into the transistor structure. Another potential benefit of utilizing such a process is the elimination of seams or voids within the plug that may be common in other chemical vapor deposition methods.

[0248] Figure 19A and 19B Cross-sectional views illustrating various operations in a method for selecting the location of a fin tip stress source at a fin tip with a wide cut, according to embodiments of the present disclosure (e.g., as part of a fin trimming end-stage process as described above).

[0249] refer to Figure 19A A fin 1900, such as a silicon fin, is formed above and continuous with the substrate 1902. The fin 1900 has a fin tip or wide fin cutout 1904, which may be formed, for example, during fin patterning in the aforementioned fin trimming process. An effective gate electrode location 1906 and a dummy gate electrode location 1908 are formed on the fin 1900, and for illustrative purposes, the effective gate electrode location 1906 and the dummy gate electrode location 1908 are shown slightly in front of the fin 1900, with the fin 1900 in the background, where dashed lines indicate areas covered from the front view. It should be understood that an epitaxial source or drain region 1910 is also shown on the fin 1900 at a location between the gate locations 1906 and 1908. Additionally, an interlayer dielectric material 1912 is included on the fin 1900 at a location between the gate locations 1906 and 1908.

[0250] refer to Figure 19B The gate pre-reserved location structure or dummy gate location 1908 is removed, thereby exposing the fin tip or wide fin cutout 1904. This removal creates an opening 1920, at which a dielectric plug, such as a fin tip stress source dielectric plug, can eventually be formed.

[0251] Figure 20A and 20B Cross-sectional views illustrating various operations in a method for selecting the location of a fin tip stress source at a fin tip with a partial cut, according to embodiments of the present disclosure (e.g., as part of a fin trimming isolation process as described above).

[0252] refer to Figure 20AFins 2000, such as silicon fins, are formed above and continuous with the substrate 2002. The fin 2000 has a partial notch 2004, in which a portion of the fin 2000 is removed, for example, using a fin trimming isolation method, in which a dummy gate is removed and the fin is etched at the partial location as described above. An effective gate electrode location 2006 and a dummy gate electrode location 2008 are formed on the fin 2000, and for illustrative purposes, the effective gate electrode location 2006 and the dummy gate electrode location 2008 are shown slightly in front of the fin 2000, while the fin 2000 is in the background, where dashed lines indicate areas covered from the front view. It should be understood that an epitaxial source or drain region 2010 is also shown at a location on the fin 2000 between gate locations 2006 and 2008. Additionally, an interlayer dielectric material 2012 is included at a location on the fin 2000 between gate locations 2006 and 2008.

[0253] refer to Figure 20B The gate pre-reserved location structure or dummy gate electrode location 2008 is removed, thereby exposing the fin tip with a local cutout 2004. This removal creates an opening 2020, at which a dielectric plug, such as a fin tip stress source dielectric plug, can ultimately be formed.

[0254] Figure 21A-21M Cross-sectional views illustrating various operations in a method of manufacturing an integrated circuit structure with differentiated fin-end dielectric plugs according to embodiments of the present disclosure are shown.

[0255] refer to Figure 21A The initial structure 2100 includes an NMOS region and a PMOS region. The NMOS region of the initial structure 2100 includes a first fin 2102, such as a first silicon fin, which is formed above and continuous with the substrate 2104. The first fin 2102 has a fin tip 2106, which may be formed by a partial or wide fin cutout. A first effective gate electrode location 2108 and a first dummy gate electrode location 2110 are formed on the first fin 2102, and for illustrative purposes, the first effective gate electrode location 2108 and the first dummy gate electrode location 2110 are shown slightly in front of the first fin 2102, while the first fin 2102 is in the background, where dashed lines indicate areas covered from the front view. An epitaxial N-type source or drain region 2112, such as an epitaxial silicon source or drain structure, is also shown at a location on the first fin 2102 between the gate locations 2108 and 2110. Additionally, an interlayer dielectric material 2114 is included at a location of the first fin 2102 between gate positions 2108 and 2110.

[0256] The PMOS region of the initial structure 2100 includes a second fin 2122, such as a second silicon fin, which is formed above and continuous with the substrate 2104. The second fin 2122 has a fin tip 2126, which may be formed by a partial or wide fin cutout. A second active gate electrode location 2128 and a second dummy gate electrode location 2130 are formed above the second fin 2122, and for illustrative purposes, the second active gate electrode location 2128 and the second dummy gate electrode location 2130 are shown slightly in front of the second fin 2122, while the second fin 2122 is in the background, where dashed lines indicate areas covered from the front view. An epitaxial P-type source or drain region 2132, such as an epitaxial silicon-germanium source or drain structure, is also shown at a location on the second fin 2122 between the gate locations 2128 and 2130. Additionally, an interlayer dielectric material 2134 is included at a location of the second fin 2122 between gate positions 2128 and 2130.

[0257] refer to Figure 21B The first and second dummy gate electrodes at positions 2110 and 2130 are removed, respectively. Once removed, the fin tip 2106 of the first fin 2102 and the fin tip 2126 of the second fin 2122 are exposed. This removal also creates openings 2116 and 2136, respectively, at which dielectric plugs, such as fin tip stress source dielectric plugs, can ultimately be formed.

[0258] refer to Figure 21C ,and Figure 21B The material pad 2140 is conformally formed in a structure. In an embodiment, the material pad comprises silicon and nitrogen, such as a silicon nitride material pad.

[0259] refer to Figure 21D ,exist Figure 21C A protective canopy 2142 is formed on its structure, such as a metal nitride layer.

[0260] refer to Figure 21E ,exist Figure 21D A hard mask material 2144, such as a carbon-based hard mask material, is formed on top of the structure. A photomask or mask stack 2146 is formed on top of the hard mask material 2144.

[0261] refer to Figure 21F ,from Figure 21E In the structure, a portion of the hard mask material 2144 and a portion of the protective crown layer 2142 in the PMOS region are removed. The photolithography mask or mask stack 2146 is also removed.

[0262] refer to Figure 21G ,and Figure 21FThe second material liner 2148 is conformally formed in the structure. In an embodiment, the second material liner comprises silicon and nitrogen, such as a second silicon nitride material liner. In an embodiment, the second material liner 2148 has different stress states to modulate the stress in the exposed plug.

[0263] refer to Figure 21H ,exist Figure 21G A second hard mask material 2150, such as a second carbon-based hard mask material, is formed on the structure, and then the second hard mask material 2150 is recessed within the opening 2136 of the PMOS region of the structure.

[0264] refer to Figure 21I ,from Figure 21H The structure is etched to remove the second material pad 2148 from the NMOS region and to recess the second material pad 2148 in the PMOS region of the structure.

[0265] refer to Figure 21J ,from Figure 21I The hard mask material 2144, the protective canopy 2142, and the second hard mask material 2150 are removed from the structure. Compared with the opening 2136, this removal leaves two different filling structures for the opening 2116.

[0266] refer to Figure 21K ,exist Figure 21J An insulating filler material 2152 is formed in the openings 2116 and 2136 of the structure and then planarized. In an embodiment, the insulating filler material 2152 is a flowable oxide material, such as flowable silicon oxide or silicon dioxide.

[0267] refer to Figure 21L ,exist Figure 21K The openings 2116 and 2136 of the structure allow the insulating filler material 2152 to be recessed to form a recessed insulating filler material 2154. In an embodiment, a vapor oxidation process is performed as part of or after the recessing process to solidify the recessed insulating filler material 2154. In one such embodiment, the recessed insulating filler material 2154 shrinks, thereby inducing tensile stress on fins 2102 and 2122. However, there is relatively less tensile stress-inducing material in the PMOS region than in the NOMS region.

[0268] refer to Figure 21M The third material, gasket 2156, is located in Figure 21LAbove the structure. In an embodiment, the third material pad 2156 comprises silicon and nitrogen, such as a third silicon nitride material pad. In an embodiment, the third material pad 2156 prevents the recessed insulating filler 2154 from being etched away during subsequent source or drain contact etching.

[0269] Figures 22A-22D illustrate exemplary structures of PMOS fin-end stress source dielectric plugs according to embodiments of the present disclosure.

[0270] Referring to Figure 22A, the opening 2136 in the PMOS region of structure 2100 includes a material pad 2140 along the sidewall of the opening 2136. A second material pad 2148 is conformal to the lower portion of the material pad 2140, but recessed relative to the upper portion of the material pad 2140. A recessed insulating filler material 2154 is located within the second material pad 2148 and has an upper surface coplanar with the upper surface of the second material pad 2148. A third material pad 2156 is located within the upper portion of the material pad 2140 and is located on the upper surface of the insulating filler material 2154 and on the upper surface of the second material pad 2148. The third material pad 2156 has a seam 2157, for example, as an artifact in the deposition process for forming the third material pad 2156.

[0271] Referring to Figure 22B, the opening 2136 in the PMOS region of structure 2100 includes a material pad 2140 along the sidewall of the opening 2136. A second material pad 2148 is conformal to the lower portion of the material pad 2140, but recessed relative to the upper portion of the material pad 2140. A recessed insulating filler material 2154 is located within the second material pad 2148 and has an upper surface coplanar with the upper surface of the second material pad 2148. A third material pad 2156 is located within the upper portion of the material pad 2140 and is located on the upper surface of the insulating filler material 2154 and on the upper surface of the second material pad 2148. The third material pad 2156 has no seams.

[0272] Referring to FIG22C, the opening 2136 in the PMOS region of structure 2100 includes a material pad 2140 along the sidewall of the opening 2136. A second material pad 2148 conforms to the lower portion of the material pad 2140 but is recessed relative to the upper portion of the material pad 2140. A recessed insulating filler material 2154 is within and above the second material pad 2148 and has an upper surface higher than the upper surface of the second material pad 2148. A third material pad 2156 is within the upper portion of the material pad 2140 and is on the upper surface of the insulating filler material 2154. The third material pad 2156 is shown without seams, but in other embodiments, the third material pad 2156 has seams.

[0273] refer to Figure 22D The opening 2136 in the PMOS region of structure 2100 includes a material pad 2140 along the sidewall of the opening 2136. A second material pad 2148 is conformal to the lower portion of the material pad 2140, but is recessed relative to the upper portion of the material pad 2140. A recessed insulating filler 2154 is within the second material pad 2148 and has an upper surface recessed below the upper surface of the second material pad 2148. A third material pad 2156 is within the upper portion of the material pad 2140 and is located on the upper surface of the insulating filler 2154 and on the upper surface of the second material pad 2148. The third material pad 2156 is shown without a seam, but in other embodiments, the third material pad 2156 has a seam.

[0274] Common Reference Figure 19A , 19B According to embodiments of the present disclosure, 20A, 20B, 21A-21M, and 22A-22D, the integrated circuit structure includes a fin, such as silicon, having a top and sidewalls. The top has a longest dimension along a direction. A first isolation structure is located above a first end of the fin. A gate structure includes a gate electrode located above the top of the fin and laterally adjacent to the sidewalls of a region of the fin. The gate structure is spaced apart from the first isolation structure along this direction. A second isolation structure is located above a second end of the fin, opposite to the first end. The second isolation structure is spaced apart from the gate structure along this direction. Both the first and second isolation structures include a first dielectric material (e.g., material pad 2140) laterally surrounding a recessed second dielectric material (e.g., a second material pad 2148) that is different from the first dielectric material. The recessed second dielectric material laterally surrounds at least a portion of a third dielectric material (e.g., a recessed insulating filler material 2154) that is different from the first and second dielectric materials.

[0275] In one embodiment, both the first and second isolation structures further include a fourth dielectric material (e.g., a third material pad 2156) laterally surrounded by the upper portion of the first dielectric material, the fourth dielectric material being on the upper surface of the third dielectric material. In one such embodiment, the fourth dielectric material is further on the upper surface of the second dielectric material. In another such embodiment, the fourth dielectric material has a nearly vertical central seam. In yet another such embodiment, the fourth dielectric material has no seam.

[0276] In one embodiment, the third dielectric material has an upper surface coplanar with the upper surface of the second dielectric material. In one embodiment, the third dielectric material has an upper surface lower than the upper surface of the second dielectric material. In one embodiment, the third dielectric material has an upper surface higher than the upper surface of the second dielectric material, and the third dielectric material further lies above the upper surface of the second dielectric material. In one embodiment, the first and second isolation structures induce compressive stress on the fin. In such an embodiment, the gate electrode is a P-type gate electrode.

[0277] In one embodiment, the first isolation structure has a width along the direction, the gate structure has a width along the direction, and the second isolation structure has a width along the direction. In such an embodiment, the center of the gate structure is spaced apart from the center of the first isolation structure by a pitch along the direction, and the center of the second isolation structure is spaced apart from the center of the gate structure by the same pitch along the direction. In one embodiment, both the first and second isolation structures are located in corresponding trenches in an interlayer dielectric layer.

[0278] In one such embodiment, a first source or drain region is located between the gate structure and the first isolation structure. A second source or drain region is located between the gate structure and the second isolation structure. In one such embodiment, the first and second source or drain regions are embedded source or drain regions comprising silicon and germanium. In one such embodiment, the gate structure further includes a high-k dielectric layer between the gate electrode and the fin and along the sidewall of the gate electrode.

[0279] In another respect, the depth of each dielectric plug can vary within a semiconductor structure or within an architecture formed on a common substrate. As an example, Figure 23A A cross-sectional view illustrating another semiconductor structure having fin-tip stress-induced features according to another embodiment of the present disclosure is shown. Reference Figure 23A This includes a shallow dielectric plug 2308A along with a pair of deep dielectric plugs 2308B and 2308C. In one such embodiment, as depicted, the shallow dielectric plug 2308A is at a depth approximately equal to the depth of the semiconductor fin 2302 within the substrate 2304, while the pair of deep dielectric plugs 2308B and 2308C are at a depth less than the depth of the semiconductor fin 2302 within the substrate 2304.

[0280] Refer again Figure 23AThis arrangement allows for stress amplification in fin trimming isolation (FTI) devices within trenches etched deeper into the substrate 2304 to provide isolation between adjacent fins 2302. This approach can be used to increase the density of transistors on the chip. In an embodiment, the stress effect induced by plug filling on the transistor is amplified in the FTI transistor because stress transfer occurs in both the fin and the substrate or well beneath the transistor.

[0281] In another respect, the width or amount of the tensile stress-induced oxide layer included in the dielectric plug can vary within the semiconductor structure or within an architecture formed on a common substrate, depending, for example, on whether the device is a PMOS or NMOS device. As an example, Figure 23B A cross-sectional view illustrating another semiconductor structure having fin-tip stress-induced features according to another embodiment of the present disclosure is shown. Reference Figure 23B In a particular embodiment, the NMOS device includes a relatively larger tensile stress-induced oxide layer 2350 than the corresponding PMOS device.

[0282] Refer again Figure 23B In embodiments, the plug fill is differentiated to induce appropriate stress in NMOS and PMOS devices. For example, NMOS plugs 2308D and 2308E have a larger volume and a wider tensile stress-induced oxide layer 2350 than PMOS plugs 2308F and 2308G. The plug fill can be patterned to induce different stresses in NMOS and PMOS devices. For example, photolithographic patterning can be used to open up a PMOS device (e.g., widening the dielectric plug trench for a PMOS device), where different fill options can be implemented to differentiate the plug fill in NMOS versus PMOS devices. In an exemplary embodiment, reducing the volume of the flowable oxide in the plug on a PMOS device can reduce the induced tensile stress. In one such embodiment, compressive stress can dominate, for example, by applying compressive stress to the source and drain regions. In other embodiments, the use of different plug pads or different fill materials provides adjustable stress control.

[0283] As described above, it is important to understand that the polymer plug stress effect can benefit both NMOS transistors (e.g., channel tensile stress) and PMOS transistors (e.g., channel compressive stress). According to embodiments of this disclosure, the semiconductor fin is a uniaxially stressed semiconductor fin. Tensile stress or compressive stress can be used to uniaxially stress the uniaxially stressed semiconductor fin. For example, Figure 24A An angled view of a fin with uniaxial tensile stress according to one or more embodiments of the present disclosure is illustrated, while Figure 24BAn angled view of a fin having uniaxial compressive stress according to one or more embodiments of the present disclosure is illustrated.

[0284] refer to Figure 24A The semiconductor fin 2400 has discrete channel regions (C) disposed therein. A source region (S) and a drain region (D) are disposed on either side of the channel region (C) in the semiconductor fin 2400. The discrete channel regions of the semiconductor fin 2400 have a current flow direction from the source region (S) to the drain region (D) along the direction of uniaxial tensile stress (arrows pointing away from each other and toward ends 2402 and 2404).

[0285] refer to Figure 24B The semiconductor fin 2450 has discrete channel regions (C) disposed therein. A source region (S) and a drain region (D) are disposed on either side of the channel region (C) in the semiconductor fin 2450. The discrete channel regions of the semiconductor fin 2450 have a current flow direction from the source region (S) to the drain region (D) along the direction of uniaxial compressive stress (pointing to each other and indicated by arrows from ends 2452 and 2454). Therefore, the embodiments described herein can be implemented to improve transistor mobility and drive current, thereby allowing for faster execution of circuits and chips.

[0286] In another aspect, a relationship may exist between the location of the gate line cut (polymer cut) and the location of the fin trimming isolation (FTI) local fin cut. In one embodiment, the FTI local fin cut is made only at the locations where the polymer cut is made. However, in such an embodiment, it is not necessary to make an FTI cut at every location where the polymer cut is made.

[0287] Figure 25A and 25B A plan view illustrating various operations in a method of patterning a fin having a single gate spacing for forming a local isolation structure in a selected gate line cut-out location, according to embodiments of the present disclosure.

[0288] refer to Figure 25A A method of manufacturing an integrated circuit structure includes forming a plurality of fins 2502, each of the plurality of fins 2502 having a longest dimension along a first direction 2504. A plurality of gate structures 2506 are placed above the plurality of fins 2502, each of the gate structures 2506 having a longest dimension along a second direction 2508 orthogonal to the first direction 2504. In an embodiment, the gate structure 2506 is, for example, a sacrificial gate line or a dummy gate line made of polysilicon. In one embodiment, the plurality of fins 2502 are silicon fins and are continuous with a portion of an underlying silicon substrate.

[0289] Refer again Figure 25AA dielectric material structure 2510 is formed between adjacent gate structures in the plurality of gate structures 2506. Portions 2512 and 2513 of two of the plurality of gate structures 2506 are removed to expose a portion of each of the plurality of fins 2502. In an embodiment, removing portions 2512 and 2513 of the two gate structures 2506 involves using a photolithographic window wider than the width of each of portions 2512 and 2513 of the gate structures 2506. The exposed portion of each of the plurality of fins 2502 at location 2512 is removed to form a notch region 2520. In an embodiment, a dry or plasma etching process is used to remove the exposed portion of each of the plurality of fins 2502. However, the exposed portion of each of the plurality of fins 2502 at location 2513 is masked to avoid removal. In an embodiment, regions 2512 / 2520 represent both a polymer notch and an FTI partial fin notch. However, location 2513 only represents a polymer notch.

[0290] refer to Figure 25B The locations 2512 / 2520 of the polymer cut and the FTI partial fin cut, as well as the location 2513 of the polymer cut, are filled with an insulating structure 2530, such as a dielectric plug. Exemplary insulating structures, or "polymer cut" or "plug" structures, are described below.

[0291] Figures 26A-26C Cross-sectional views illustrating various possibilities for dielectric plugs according to embodiments of the present disclosure, the dielectric plugs being used for Figure 25B The location of the aggregated incisions and FTI local fin incisions in various regions of the structure, as well as the location of aggregated incisions only.

[0292] refer to Figure 26A along Figure 25B The a-a' axis of the structure shows a cross-sectional view of portion 2600A of the dielectric plug 2530 at position 2513. Portion 2600A of the dielectric plug 2530 is shown on the uncut fin 2502 and between the dielectric material structures 2510.

[0293] refer to Figure 26B along Figure 25B The b-b' axis of the structure shows a cross-sectional view of portion 2600B of the dielectric plug 2530 at position 2512. Portion 2600B of the dielectric plug 2530 is shown at the cut-out fin position 2520 and between the dielectric material structures 2510.

[0294] refer to Figure 26C along Figure 25BThe c-c' axis of the structure shows a cross-sectional view of a portion 2600C of the dielectric plug 2530 at location 2512. The portion 2600C of the dielectric plug 2530 is shown as being on the trench isolation structure 2602 between the fins 2502 and between the dielectric material structures 2510. In an embodiment, as described above, the trench isolation structure 2602 includes a first insulating layer 2602A, a second insulating layer 2602B, and an insulating filler material 2602C on the second insulating layer 2602B.

[0295] Referring to common references to 25A, 25B, and 26A-26C, according to embodiments of the present disclosure, a method of manufacturing an integrated circuit structure includes forming a plurality of fins, each of the plurality of fins being along a first direction. A plurality of gate structures are formed over the plurality of fins, each of the gate structures being along a second direction orthogonal to the first direction. A dielectric material structure is formed between adjacent gate structures in the plurality of gate structures. A portion of a first gate structure in the plurality of gate structures is removed to expose a first portion of each of the plurality of fins. A portion of a second gate structure in the plurality of gate structures is removed to expose a second portion of each of the plurality of fins. The exposed first portion of each of the plurality of fins is removed, but the exposed second portion of each of the plurality of fins is not removed. A first insulating structure is formed at the location of the removed first portion of the plurality of fins. A second insulating structure is formed at the location of the removed portion of the second gate structure in the plurality of gate structures.

[0296] In one embodiment, removing portions of the first and second gate structures of the plurality of gate structures involves using photolithographic windows wider than the width of each of the portions of the first and second gate structures. In one embodiment, removing the exposed first portion of each of the plurality of fins involves etching to a depth smaller than the height of the plurality of fins. In such an embodiment, this depth is greater than the depth of the source or drain regions of the plurality of fins. In one embodiment, the plurality of fins comprises silicon and is continuous with a portion of a silicon substrate.

[0297] Common Reference Figure 16A , 25AAccording to another embodiment of this disclosure, 25B and 26A-26C, the integrated circuit structure includes a silicon-containing fin having a longest dimension along a first direction. An isolation structure is located above the upper portion of the fin, having a center along the first direction. A first gate structure is located above the upper portion of the fin, having a longest dimension along a second direction orthogonal to the first direction. The center of the first gate structure is spaced apart from the center of the isolation structure by a pitch along the first direction. A second gate structure is located above the upper portion of the fin, having a longest dimension along the second direction. The center of the second gate structure is spaced apart from the center of the first gate structure by the pitch along the first direction. A third gate structure is located above the upper portion of the fin, opposite the side of the isolation structure of the first and second gate structures, having a longest dimension along the second direction. The center of the third gate structure is spaced apart from the center of the isolation structure by the pitch along the first direction.

[0298] In one embodiment, each of the first gate structure, the second gate structure, and the third gate structure includes a gate electrode on and between the sidewalls of the high-k gate dielectric layer. In such an embodiment, each of the first gate structure, the second gate structure, and the third gate structure further includes an insulating cap on the gate electrode and on the sidewalls of the high-k gate dielectric layer.

[0299] In one embodiment, a first epitaxial semiconductor region is located on the upper part of the fin between the first gate structure and the isolation structure. A second epitaxial semiconductor region is located on the upper part of the fin between the first gate structure and the second gate structure. A third epitaxial semiconductor region is located on the upper part of the fin between the third gate structure and the isolation structure. In one such embodiment, the first, second, and third epitaxial semiconductor regions comprise silicon and germanium. In another such embodiment, the first, second, and third epitaxial semiconductor regions comprise silicon.

[0300] Common Reference Figure 16A , 25AAccording to another embodiment of this disclosure, 25B and 26A-26C, an integrated circuit structure includes a shallow trench isolation (STI) structure between a pair of semiconductor fins, the STI structure having a longest dimension along a first direction. An isolation structure is located on the STI structure, the isolation structure having a center along the first direction. A first gate structure is located on the STI structure, the first gate structure having a longest dimension along a second direction orthogonal to the first direction. The center of the first gate structure is spaced apart from the center of the isolation structure by a pitch along the first direction. A second gate structure is located on the STI structure, the second gate structure having a longest dimension along the second direction. The center of the second gate structure is spaced apart from the center of the first gate structure by a pitch along the first direction. A third gate structure is located on the STI structure opposite the side of the isolation structure of the first and second gate structures, the third gate structure having a longest dimension along the second direction. The center of the third gate structure is spaced apart from the center of the isolation structure by a pitch along the first direction.

[0301] In one embodiment, each of the first gate structure, the second gate structure, and the third gate structure includes a gate electrode on and between the sidewalls of the high-k gate dielectric layer. In such an embodiment, each of the first gate structure, the second gate structure, and the third gate structure further includes an insulating cap on the gate electrode and on the sidewall of the high-k gate dielectric layer. In one embodiment, the pair of semiconductor fins is a pair of silicon fins.

[0302] On the other hand, whether the aggregated cut is together with the FTI partial fin cut or only the aggregated cut, the insulating structure or dielectric plug used to fill the cut position can extend laterally into the dielectric spacer of the corresponding cut gate line, or even extend beyond the dielectric spacer of the corresponding cut gate line.

[0303] In the first example, where the shape of the grooved contact portion is unaffected by the polymer-cut dielectric plug, Figure 27A A plan view and a corresponding cross-sectional view of an integrated circuit structure having a gate line cutout according to an embodiment of the present disclosure are illustrated, the gate line cutout having a dielectric plug extending into a dielectric spacer portion of the gate line.

[0304] refer to Figure 27AThe integrated circuit structure 2700A includes a first silicon fin 2702 having the longest dimension along a first direction 2703. A second silicon fin 2704 has the longest dimension along the first direction 2703. An insulating material 2706 is located between the first silicon fin 2702 and the second silicon fin 2704. A gate line 2708 is located above the first silicon fin 2702 and above the second silicon fin 2704 along a second direction 2709, which is orthogonal to the first direction 2703. The gate line 2708 has a first side 2708A and a second side 2708B, and has a first end 2708C and a second end 2708D. The gate line 2708 has an interruption 2710 on the insulating material 2706 between the first end 2708C and the second end 2708D. The interruption 2710 is filled with a dielectric plug 2712.

[0305] The trench contact 2714 is located on the first side 2708A of the gate line 2708, along the second direction 2709, over the first silicon fin 2702 and the second silicon fin 2704. The trench contact 2714 is continuous over the insulating material 2706 at a position 2715 laterally adjacent to the dielectric plug 2712. A dielectric spacer 2716 is laterally located between the trench contact 2714 and the first side 2708A of the gate line 2708. The dielectric spacer 2716 is continuous along the first side 2708A of the gate line 2708 and the dielectric plug 2712. The dielectric spacer 2716 has a width (W2) laterally adjacent to the dielectric plug 2712, which is thinner than the width (W1) laterally adjacent to the first side 2708A of the gate line 2708.

[0306] In one embodiment, the second trench contact 2718 is located on the second side 2708B of the gate line 2708, over the first silicon fin 2702 and the second silicon fin 2704 along the second direction 2709. The second trench contact 2718 is continuous over the insulating material 2706 at a position 2719 laterally adjacent to the dielectric plug 2712. In such an embodiment, the second dielectric spacer 2720 is laterally located between the second trench contact 2718 and the second side 2708B of the gate line 2708. The second dielectric spacer 2720 is continuous along the second side 2708B of the gate line 2708 and the dielectric plug 2712. The second dielectric spacer has a width laterally adjacent to the dielectric plug 2712 that is thinner than the width laterally adjacent to the second side 2708B of the gate line 2708.

[0307] In one embodiment, gate line 2708 includes a high-k gate dielectric layer 2722, a gate electrode 2724, and a dielectric capping layer 2726. In one embodiment, dielectric plug 2712 comprises the same material as dielectric spacer 2714, but is separate from dielectric spacer 2714. In one embodiment, dielectric plug 2712 comprises a different material than dielectric spacer 2714.

[0308] In the second example, where the shape of the grooved contact portion is affected by the polymer-cut dielectric plug, Figure 27B A plan view and a corresponding cross-sectional view of an integrated circuit structure having a gate line cutout according to another embodiment of the present disclosure are illustrated, the gate line cutout having a dielectric plug extending beyond the dielectric spacer of the gate line.

[0309] refer to Figure 27B The integrated circuit structure 2700B includes a first silicon fin 2752 having the longest dimension along a first direction 2753. A second silicon fin 2754 has the longest dimension along the first direction 2753. An insulating material 2756 is located between the first silicon fin 2752 and the second silicon fin 2754. A gate line 2758 is located above the first silicon fin 2752 and above the second silicon fin 2754 along a second direction 2759, which is orthogonal to the first direction 2753. The gate line 2758 has a first side 2758A and a second side 2758B, and has a first end 2758C and a second end 2758D. The gate line 2758 has an interruption 2760 on the insulating material 2756 between the first end 2758C and the second end 2758D of the gate line 2758. The interruption 2760 is filled with a dielectric plug 2762.

[0310] The trench contact 2764 is located on the first silicon fin 2752 and the second silicon fin 2754 along the second direction 2759 at the first side 2758A of the gate line 2758. The trench contact 2764 is continuous on the insulating material 2756 at a position 2765 laterally adjacent to the dielectric plug 2762. The dielectric spacer 2766 is laterally located between the trench contact 2764 and the first side 2758A of the gate line 2758. The dielectric spacer 2766 is along the first side 2758A of the gate line 2758, but not along the dielectric plug 2762, thus resulting in a discontinuous dielectric spacer 2766. The trench contact 2764 has a width (W1) laterally adjacent to the dielectric plug 2762, which is thinner than the width (W2) laterally adjacent to the dielectric spacer 2766.

[0311] In one embodiment, the second trench contact 2768 is located on the second side 2758B of the gate line 2758, along a second direction 2759, over the first silicon fin 2752 and the second silicon fin 2754. The second trench contact 2768 is continuous over the insulating material 2756 at a position 2769 laterally adjacent to the dielectric plug 2762. In such an embodiment, the second dielectric spacer 2770 is laterally located between the second trench contact 2768 and the second side 2758B of the gate line 2758. The second dielectric spacer 2770 is along the second side 2758B of the gate line 2758, but not along the dielectric plug 2762, thus resulting in a discontinuous dielectric spacer 2770. The second trench contact 2768 has a width laterally adjacent to the dielectric plug 2762, which is thinner than the width laterally adjacent to the second dielectric spacer 2770.

[0312] In one embodiment, gate line 2758 includes a high-k gate dielectric layer 2772, a gate electrode 2774, and a dielectric capping layer 2776. In one embodiment, dielectric plug 2762 comprises the same material as dielectric spacer 2764, but is separate from dielectric spacer 2764. In one embodiment, dielectric plug 2762 comprises a different material than dielectric spacer 2764.

[0313] In the third example, where the dielectric plug used for the polymerization notch location gradually tapers from the top to the bottom of the plug, Figures 28A-28F Cross-sectional views illustrating various operations in a method of manufacturing an integrated circuit structure having a gate line cutout with a dielectric plug according to another embodiment of the present disclosure are shown, the dielectric plug having an upper portion extending beyond a dielectric spacer portion of the gate line and a lower portion extending into the dielectric spacer portion of the gate line.

[0314] refer to Figure 28A A plurality of gate lines 2802 are formed on top of structure 2804, such as on trench isolation structures between semiconductor fins. In one embodiment, each of the gate lines 2802 is a sacrificial or dummy gate line, for example having a dummy gate electrode 2806 and a dielectric cap 2808. Such a sacrificial or dummy gate line may later be replaced in a gate replacement process, such as after dielectric plug formation described below. Dielectric spacers 2810 run along the sidewalls of the gate lines 2802. A dielectric material 2812, such as an interlayer dielectric layer, is present between the gate lines 2802. A mask 2814 is formed and photolithographically patterned to expose a portion of one of the gate lines 2802.

[0315] refer to Figure 28BWith mask 2814 in place, the central gate line 2802 is removed using an etching process. Then, mask 2814 is removed. In one embodiment, the etching process erodes a portion of the dielectric spacer 2810 of the removed gate line 2802, thereby forming a reduced dielectric spacer 2816. Additionally, the upper portion of the dielectric material 2812 exposed by mask 2814 is etched during the etching process, thereby forming an etched dielectric material portion 2818. In a particular embodiment, residual dummy gate material 2820, such as residual polysilicon, is retained in the structure as an article of an incomplete etching process.

[0316] refer to Figure 28C ,exist Figure 28B A hard mask 2822 is formed on top of the structure. The hard mask 2822 can be combined with... Figure 28B The upper part of the structure conforms to the structure, and in particular conforms to the eroded dielectric material portion 2818.

[0317] refer to Figure 28D For example, an etching process can be used to remove residual dummy gate material 2820, which can be chemically similar to the etching process used to remove the central gate line in gate line 2802. In an embodiment, during the removal of residual dummy gate material 2820, a hard mask 2822 protects the etched dielectric material portion 2818 from further erosion.

[0318] refer to Figure 28E Remove hard mask 2822. In one embodiment, hard mask 2822 is removed without or substantially without further erosion of the eroded dielectric material portion 2818.

[0319] refer to Figure 28F ,exist Figure 28E A dielectric plug 2830 is formed in the opening of the structure. The upper part of the dielectric plug 2830 is above the eroded dielectric material portion 2818, for example, effectively extending beyond the original spacer portion 2810. The lower part of the dielectric plug 2830 is adjacent to the reduced dielectric spacer portion 2816, for example, effectively entering into the original spacer portion 2810 but not exceeding it. As a result, the dielectric plug 2830 has the following characteristics: Figure 28F The gradually tapering outline is depicted in the image. It should be understood that the dielectric plug 2830 can be manufactured using the materials and processes described above for other polymer cutouts or FTI plugs or fin end stress sources.

[0320] In another aspect, a portion of the reserved gate structure or dummy gate structure can be retained above the trench isolation region beneath the permanent gate structure, serving as protection against erosion of the trench isolation region during the gate replacement process. For example, Figures 29A-29CA plan view and a corresponding cross-sectional view of an integrated circuit structure having residual dummy gate material at a portion of the bottom of a permanent gate stack, according to an embodiment of the present disclosure, are illustrated.

[0321] refer to Figures 29A-29C The integrated circuit structure includes a fin 2902, such as a silicon fin, protruding from a semiconductor substrate 2904. The fin 2902 has a lower fin portion 2902B and an upper fin portion 2902A. The upper fin portion 2902A has a top 2902C and a sidewall 2902D. An isolation structure 2906 surrounds the lower fin portion 2902B. The isolation structure 2906 includes an insulating material 2906C having a top surface 2907. A semiconductor material 2908 is located on a portion of the top surface 2907 of the insulating material 2906C. The semiconductor material 2908 is spaced apart from the fin 2902.

[0322] A gate dielectric layer 2910 is situated above the top 2902C of the upper fin portion 2902A and laterally adjacent to the sidewall 2902D of the upper fin portion 2902A. The gate dielectric layer 2910 is further situated on a semiconductor material 2908 on the portion of the top surface 2907 of the insulating material 2906C. An intermediate additional gate dielectric layer 2911, such as an oxide portion of the fin 2902, may be situated between the gate dielectric layer 2910 and the top 2902C of the upper fin portion 2902A and laterally adjacent to the sidewall 2902D of the upper fin portion 2902A. A gate electrode 2912 is situated above the gate dielectric layer 2910 above the top 2902C of the upper fin portion 2902A and laterally adjacent to the sidewall 2902D of the upper fin portion 2902A. The gate electrode 2912 is further situated on the gate dielectric layer 2910 on the semiconductor material 2908 on the portion of the top surface 2907 of the insulating material 2906C. A first source or drain region 2916 is adjacent to a first side of the gate electrode 2912, and a second source or drain region 2918 is adjacent to a second side of the gate electrode 2912, the second side being opposite to the first side. In an embodiment, an example of which has been described above, the isolation structure 2906 includes a first insulating layer 2906A, a second insulating layer 2906B, and an insulating material 2906C.

[0323] In one embodiment, the semiconductor material 2908 on the portion of the top surface 2907 of the insulating material 2906C is or comprises polycrystalline silicon. In one embodiment, the top surface 2907 of the insulating material 2906C has a recess, and is depicted therein, and the semiconductor material 2908 is located in the recess. In one embodiment, the isolation structure 2906 includes a second insulating material (2906A or 2906B or both 2906A and 2906B) along the bottom and sidewalls of the insulating material 2906C. In such an embodiment, the portion of the second insulating material (2906A or 2906B or both 2906A and 2906B) along the sidewalls of the insulating material 2906C has a top surface above the highest surface of the insulating material 2906C, as depicted. In one embodiment, the top surface of the second insulating material (2906A or 2906B or both 2906A and 2906B) is higher than or coplanar with the highest surface of the semiconductor material 2908.

[0324] In one embodiment, the semiconductor material 2908 on the portion of the top surface 2907 of the insulating material 2906C does not extend beyond the gate dielectric layer 2910. That is, from a plan view perspective, the position of the semiconductor material 2908 is confined to the area covered by the gate stack 2912 / 2910. In one embodiment, a first dielectric spacer 2920 extends along a first side of the gate electrode 2912. A second dielectric spacer 2922 extends along a second side of the gate electrode 2912. In such an embodiment, the gate dielectric layer 2910 further extends along the sidewalls of the first dielectric spacer 2920 and the second dielectric spacer 2922, as shown below. Figure 29B As depicted in the text.

[0325] In one embodiment, the gate electrode 2912 includes a conformal conductive layer 2912A (e.g., a work function layer). In one such embodiment, the work function layer 2912A includes titanium and nitrogen. In another embodiment, the work function layer 2912A includes titanium, aluminum, carbon, and nitrogen. In one embodiment, the gate electrode 2912 further includes a conductive filler metal layer 2912B over the work function layer 2912A. In one such embodiment, the conductive filler metal layer 2912B includes tungsten. In a particular embodiment, the conductive filler metal layer 2912B includes 95 or greater atomic percent tungsten and 0.1 to 2 atomic percent fluorine. In one embodiment, an insulating cap 2924 is on the gate electrode 2912 and may extend over the gate dielectric layer 2910, such as... Figure 29B As depicted in the text.

[0326] Figures 30A-30DCross-sectional views illustrating various operations in a method of fabricating an integrated circuit structure having residual dummy gate material at a portion of the bottom of a permanent gate stack, according to another embodiment of this disclosure. This view shows along... Figure 29C It is part of the a-a' axis of the structure.

[0327] refer to Figure 30A A method for manufacturing an integrated circuit structure includes forming a fin 3000 from a semiconductor substrate 3002. The fin 3000 has a lower fin portion 3000A and an upper fin portion 3000B. The upper fin portion 3000B has a top 3000C and a sidewall 3000D. An isolation structure 3004 surrounds the lower fin portion 3000A. The isolation structure 3004 includes an insulating material 3004C having a top surface 3005. A reserved position gate electrode 3006 is located above the top 3000C of the upper fin portion 3000B and laterally abuts the sidewall 3000D of the upper fin portion 3000B. The reserved position gate electrode 3006 comprises a semiconductor material.

[0328] Although not from Figure 30A The perspective of the description (but in Figure 29C (The location is shown in the figure), but a first source or drain region may be formed adjacent to the first side of the reserved position gate electrode 3006, and a second source or drain region may be formed adjacent to the second side of the reserved position gate electrode 3006, the second side being opposite to the first side. Additionally, a gate dielectric spacer may be formed along the sidewall of the reserved position gate electrode 3006, and an interlayer dielectric (ILD) layer may be formed laterally adjacent to the reserved position gate electrode 3006.

[0329] In one embodiment, the reserved position gate electrode 3006 is or comprises polysilicon. In one embodiment, the top surface 3005 of the insulating material 3004C of the isolation structure 3004 has a recess, as depicted. A portion of the reserved position gate electrode 3006 is located in this recess. In one embodiment, the isolation structure 3004 includes a second insulating material (3004A or 3004B, or both 3004A and 3004B) along the bottom and sidewalls of the insulating material 3004C, as depicted. In one such embodiment, a portion of the second insulating material (3004A or 3004B, or both 3004A and 3004B) along the sidewalls of the insulating material 3004C has a top surface above at least a portion of the top surface 3005 of the insulating material 3004C. In one embodiment, the top surface of the second insulating material (3004A or 3004B, or both 3004A and 3004B) is higher than the lowest surface of a portion of the reserved position gate electrode 3006.

[0330] refer to Figure 30BFrom the top 3000C and sidewall 3000D of the upper fin portion 3000B, for example along Figure 30A The reserved position gate electrode 3006 is etched in direction 3008. This etching process can be referred to as a gate replacement process. In an embodiment, the etching or gate replacement process is incomplete, leaving a portion 3012 of the reserved position gate electrode 3006 on at least a portion of the top surface 3005 of the insulating material 3004C of the isolation structure 3004.

[0331] refer to Figure 30A and 30B In both embodiments, the oxide portion 3010 of the upper fin portion 3000B formed before the formation of the reserved position gate electrode 3006 is retained during the etching process, as depicted. However, in another embodiment, the reserved position gate dielectric layer is formed before the formation of the reserved position gate electrode 3006, and the reserved position gate dielectric layer is removed after etching the reserved position gate electrode.

[0332] refer to Figure 30C A gate dielectric layer 3014 is formed on the top 3000C of the upper fin portion 3000B and laterally adjacent to the sidewall 3000D of the upper fin portion 3000B. In one embodiment, the gate dielectric layer 3014 is formed on the oxide portion 3010 of the upper fin portion 3000B above the top 3000C of the upper fin portion 3000B and laterally adjacent to the sidewall 3000D of the upper fin portion 3000B, as depicted. In another embodiment, if the oxide portion 3010 of the upper fin portion 3000B is removed after etching the reserved position gate electrode, the gate dielectric layer 3014 is formed directly on the upper fin portion 3000B above the top 3000C of the upper fin portion 3000B and laterally adjacent to the sidewall 3000D of the upper fin portion 3000B. In any case, in the embodiment, a gate dielectric layer 3014 is further formed on a portion 3012 of the reserved position gate electrode 3006 located on the portion of the top surface 3005 of the insulating material 3004C of the isolation structure 3004.

[0333] refer to Figure 30D A permanent gate electrode 3016 is formed on the gate dielectric layer 3014 above the top 3000C of the upper fin portion 3000B and laterally adjacent to the sidewall 3000D of the upper fin portion 3000B. The permanent gate electrode 3016 is further positioned on the gate dielectric layer 3014 on the portion 3012 of the reserved gate electrode 3006 located on the top surface 3005 of the insulating material 3004C.

[0334] In one embodiment, forming a permanent gate electrode 3016 includes forming a work function layer 3016A. In one such embodiment, the work function layer 3016A comprises titanium and nitrogen. In another such embodiment, the work function layer 3016A comprises titanium, aluminum, carbon, and nitrogen. In one embodiment, forming a permanent gate electrode 3016 further includes forming a conductive filler metal layer 3016B, which is formed over the work function layer 3016A. In one such embodiment, forming the conductive filler metal layer 3016B includes forming a tungsten-containing film using atomic layer deposition (ALD) utilizing a tungsten hexafluoride (WF6) precursor. In an embodiment, an insulating gate capping layer 3018 is formed on the permanent gate electrode 3016.

[0335] In another aspect, some embodiments of this disclosure include an amorphous high-k layer in the gate dielectric structure for the gate electrode. In other embodiments, the gate dielectric structure for the gate electrode includes a partially or fully crystalline high-k layer. In one embodiment that includes a partially or fully crystalline high-k layer, the gate dielectric structure is a ferroelectric (FE) gate dielectric structure. In another embodiment that includes a partially or fully crystalline high-k layer, the gate dielectric structure is an antiferroelectric (AFE) gate dielectric structure.

[0336] In the embodiments, methods are described herein for increasing the charge in the device channel and improving subthreshold behavior by employing ferroelectric or antiferroelectric gate oxides. Ferroelectric and antiferroelectric gate oxides can increase the channel charge for higher currents and can also achieve steeper turn-on behavior.

[0337] To provide context, hafnium or zirconium (Hf or Zr)-based ferroelectric and antiferroelectric (FE or AFE) materials are typically much thinner than ferroelectric materials such as lead zirconate titanate (PZT), and thus can be compatible with highly scalable logic technologies. FE or AFE materials have two characteristics that improve the performance of logic transistors: (1) higher charge in the channel achieved by FE or AFE polarization, and (2) steeper turn-on behavior attributed to sharp FE or AFE transitions. Such properties can improve transistor performance by increasing current and reducing subthreshold swing (SS).

[0338] Figure 31A A cross-sectional view of a semiconductor device having a ferroelectric or antiferroelectric gate dielectric structure according to an embodiment of the present disclosure is illustrated.

[0339] refer to Figure 31AThe integrated circuit structure 3100 includes a gate structure 3102 above a substrate 3104. In one embodiment, the gate structure 3102 is above or on a semiconductor channel structure 3106 comprising a single-crystal material such as single-crystal silicon. The gate structure 3102 includes a gate dielectric over the semiconductor channel structure 3106 and a gate electrode over the gate dielectric structure. The gate dielectric includes a ferroelectric or antiferroelectric polycrystalline material layer 3102A. The gate electrode has a conductive layer 3102B on the ferroelectric or antiferroelectric polycrystalline material layer 3102A. The conductive layer 3102B includes a metal and may be a barrier layer, a work function layer, or a template layer that enhances the crystallinity of the FE or AFE layer. One or more gate fill layers 3102C are on or above the conductive layer 3102B. A source region 3108 and a drain region 3110 are on opposite sides of the gate structure 3102. Source or drain contact 3112 is electrically connected to source region 3108 and drain region 3110 at position 3149, and is spaced apart from gate structure 3102 by one or both of interlayer dielectric layer 3114 or gate dielectric spacer 3116. Figure 31A In the example, source region 3108 and drain region 3110 are regions of substrate 3104. In an embodiment, source or drain contact 3112 includes a barrier layer 3112A and a conductive trench filler material 3112B. In one embodiment, a ferroelectric or antiferroelectric polycrystalline material layer 3102A extends along dielectric spacer 3116, such as... Figure 31A As depicted in the text.

[0340] In embodiments, and where applicable throughout this disclosure, the ferroelectric or antiferroelectric polycrystalline material layer 3102A is a ferroelectric polycrystalline material layer. In one embodiment, the ferroelectric polycrystalline material layer is an oxide comprising Zr and Hf, wherein the Zr:Hf ratio is 50:50 or greater than Zr. The ferroelectric effect can increase with increasing orthorhombic crystallinity. In one embodiment, the ferroelectric polycrystalline material layer has at least 80% orthorhombic crystallinity.

[0341] In embodiments, and where applicable throughout this disclosure, the ferroelectric or antiferroelectric polycrystalline material layer 3102A is an antiferroelectric polycrystalline material layer. In one embodiment, the antiferroelectric polycrystalline material layer is an oxide comprising Zr and Hf, wherein the Zr:Hf ratio is 80:20 or greater than Zr, and even up to 100% Zr, i.e., ZrO2. In one embodiment, the antiferroelectric polycrystalline material layer has at least 80% tetragonal crystallinity.

[0342] In embodiments, and throughout the scope of this disclosure, the gate dielectric of the gate stack 3102 further includes an amorphous dielectric layer 3103, such as a native silicon oxide layer, a high-k dielectric (HfOx, Al2O3, etc.), or a combination of oxide and high-k, between the ferroelectric or antiferroelectric polycrystalline material layer 3102A and the semiconductor channel structure 3106. In embodiments, and throughout the scope of this disclosure, the ferroelectric or antiferroelectric polycrystalline material layer 3102A has a thickness in the range of 1 nanometer to 8 nanometers. In embodiments, and throughout the scope of this disclosure, the ferroelectric or antiferroelectric polycrystalline material layer 3102A has a grain size in the range of approximately 20 nanometers or more.

[0343] In one embodiment, after depositing a ferroelectric or antiferroelectric polycrystalline material layer 3102A, for example by atomic layer deposition (ALD), a layer comprising a metal (e.g., layer 3102B, such as 5-10 nanometers of titanium nitride, tantalum nitride, or tungsten) is formed on the ferroelectric or antiferroelectric polycrystalline material layer 3102A. Annealing is then performed. In one embodiment, annealing is performed for a duration ranging from 1 millisecond to 30 minutes. In another embodiment, annealing is performed at a temperature ranging from 500 to 1100 degrees Celsius.

[0344] Figure 31B A cross-sectional view of another semiconductor device having a ferroelectric or antiferroelectric gate dielectric structure according to another embodiment of the present disclosure is illustrated.

[0345] refer to Figure 31BThe integrated circuit structure 3150 includes a gate structure 3152 above a substrate 3154. In one embodiment, the gate structure 3152 is above or on a semiconductor channel structure 3156 comprising a single-crystal material such as single-crystal silicon. The gate structure 3152 includes a gate dielectric over the semiconductor channel structure 3156 and a gate electrode over the gate dielectric structure. The gate dielectric includes a ferroelectric or antiferroelectric polycrystalline material layer 3152A and may further include an amorphous oxide layer 3153. The gate electrode has a conductive layer 3152B on the ferroelectric or antiferroelectric polycrystalline material layer 3152A. The conductive layer 3152B includes a metal and may be a barrier layer or a work function layer. One or more gate fill layers 3152C are on or above the conductive layer 3152B. Raised source regions 3158 and raised drain regions 3160, such as regions of semiconductor material different from that of the semiconductor channel structure 3156, are on opposite sides of the gate structure 3152. Source or drain contact 3162 is electrically connected at location 3199 to source region 3158 and drain region 3160, and is spaced apart from gate structure 3152 by one or both of interlayer dielectric layer 3164 and gate dielectric spacer 3166. In an embodiment, source or drain contact 3162 includes barrier layer 3162A and conductive trench filler 3162B. In one embodiment, ferroelectric or antiferroelectric polycrystalline material layer 3152A extends along dielectric spacer 3166, such as... Figure 31B As depicted in the text.

[0346] Figure 32A A plan view of a plurality of gate lines over a pair of semiconductor fins is illustrated according to another embodiment of the present disclosure.

[0347] refer to Figure 32A A plurality of active gate lines 3204 are formed on a plurality of semiconductor fins 3200. Dummy gate lines 3206 are located at the ends of the plurality of semiconductor fins 3200. The spacing 3208 between the gate lines 3204 / 3206 is a location where trench contacts can be located to provide conductive contacts to source or drain regions such as source or drain regions 3251, 3252, 3253, and 3254. In embodiments, the pattern of the plurality of gate lines 3204 / 3206 or the pattern of the plurality of semiconductor fins 3200 is described as a grid structure. In one embodiment, the grid pattern comprises a pattern of a plurality of semiconductor fins 3200 spaced at a constant pitch and having a constant width, or a plurality of gate lines 3204 / 3206, or both.

[0348] Figure 32B Examples of embodiments according to this disclosure are illustrated along... Figure 32A A cross-sectional view taken along the a-a' axis.

[0349] refer to Figure 32B A plurality of effective gate lines 3264 are formed on semiconductor fins 3262, which are formed above substrate 3260. Dummy gate lines 3266 are located at the ends of semiconductor fins 3262. A dielectric layer 3270 is located outside the dummy gate lines 3266. Trench contact material 3297 is located between the effective gate lines 3264 and between the dummy gate lines 3266 and the effective gate lines 3264. Embedded source or drain structures 3268 are located in semiconductor fins 3262, between the effective gate lines 3264, and between the dummy gate lines 3266 and the effective gate lines 3264.

[0350] The effective gate line 3264 includes a gate dielectric structure 3272, a work function gate electrode portion 3274, a filled gate electrode portion 3276, and a gate electrode capping layer 3278. A dielectric spacer 3280 is lining the sidewalls of the effective gate line 3264 and the dummy gate line 3266. In one embodiment, the gate dielectric structure 3272 includes a ferroelectric or antiferroelectric polycrystalline material layer 3298. In one embodiment, the gate dielectric structure 3272 further includes an amorphous oxide layer 3299.

[0351] On the other hand, devices with the same conductivity type—e.g., N-type or P-type—can have differentiated gate electrode stacks for the same conductivity type. However, for comparison purposes, devices with the same conductivity type can have differentiated voltage thresholds (VT) based on modulation doping.

[0352] Figure 33A Cross-sectional views of a pair of NMOS devices having a differential voltage threshold based on modulation doping and a pair of PMOS devices having a differential voltage threshold based on modulation doping, according to embodiments of the present disclosure, are illustrated.

[0353] refer to Figure 33AA first NMOS device 3302 is adjacent to a second NMOS device 3304 over a semiconductor active region 3300, such as over a silicon fin or substrate. Both the first NMOS device 3302 and the second NMOS device 3304 include a gate dielectric layer 3306, a first gate electrode conductive layer 3308 such as a work function layer, and a gate electrode conductive fill 3310. In an embodiment, the first gate electrode conductive layer 3308 of the first NMOS device 3302 and the second NMOS device 3304 have the same material and the same thickness, and thus have the same work function. However, the first NMOS device 3302 has a lower VT than the second NMOS device 3304. In one such embodiment, the first NMOS device 3302 is referred to as a "standard VT" device, and the second NMOS device 3304 is referred to as a "high VT" device. In an embodiment, differentiated VT is achieved by using modulation or differentiated implant doping at region 3312 of the first NMOS device 3302 and the second NMOS device 3304.

[0354] Refer again Figure 33A A first PMOS device 3322 is adjacent to a second PMOS device 3324 over a semiconductor active region 3320, such as over a silicon fin or substrate. Both the first PMOS device 3322 and the second PMOS device 3324 include a gate dielectric layer 3326, a first gate electrode conductive layer 3328 such as a work function layer, and a gate electrode conductive fill 3330. In an embodiment, the first gate electrode conductive layer 3328 of the first PMOS device 3322 and the second PMOS device 3324 have the same material and the same thickness, and thus have the same work function. However, the first PMOS device 3322 has a higher VT than the second PMOS device 3324. In one such embodiment, the first PMOS device 3322 is referred to as a "standard VT" device, and the second PMOS device 3324 is referred to as a "low VT" device. In an embodiment, differentiated VT is achieved by using modulation or differentiated implant doping in region 3332 of the first PMOS device 3322 and the second PMOS device 3324.

[0355] and Figure 33A compared to, Figure 33B A cross-sectional view is illustrated for a pair of NMOS devices having differentiated voltage thresholds based on differentiated gate electrode structures and a pair of PMOS devices having differentiated voltage thresholds based on differentiated gate electrode structures, according to another embodiment of the present disclosure.

[0356] refer to Figure 33BA first NMOS device 3352 is adjacent to a second NMOS device 3354 over a semiconductor active region 3350, such as over a silicon fin or substrate. Both the first NMOS device 3352 and the second NMOS device 3354 include a gate dielectric layer 3356. However, the first NMOS device 3352 and the second NMOS device 3354 have structurally different gate electrode stacks. Specifically, the first NMOS device 3352 includes a first gate electrode conductive layer 3358, such as a first work function layer, and a gate electrode conductive fill 3360. The second NMOS device 3354 includes a second gate electrode conductive layer 3359, such as a second work function layer, a first gate electrode conductive layer 3358, and a gate electrode conductive fill 3360. The first NMOS device 3352 has a lower VT than the second NMOS device 3354. In such an embodiment, the first NMOS device 3352 is referred to as a "standard VT" device, and the second NMOS device 3354 is referred to as a "high VT" device. In one embodiment, differentiated VT is achieved by using differentiated gate stacks for devices of the same conductivity type.

[0357] Refer again Figure 33B A first PMOS device 3372 is adjacent to a second PMOS device 3374 over a semiconductor active region 3370, such as on a silicon fin or substrate. Both the first PMOS device 3372 and the second PMOS device 3374 include a gate dielectric layer 3376. However, the first PMOS device 3372 and the second PMOS device 3374 have structurally different gate electrode stacks. Specifically, the first PMOS device 3372 includes a gate electrode conductive layer 3378A of a first thickness, such as a work function layer, and a gate electrode conductive fill 3380. The second PMOS device 3374 includes a gate electrode conductive layer 3378B of a second thickness and a gate electrode conductive fill 3380. In one embodiment, the gate electrode conductive layers 3378A and 3378B have the same configuration, but the thickness of the gate electrode conductive layer 3378B (the second thickness) is greater than the thickness of the gate electrode conductive layer 3378A (the first thickness). The first PMOS device 3372 has a higher VT than the second PMOS device 3374. In one such embodiment, the first PMOS device 3372 is referred to as a "standard VT" device, and the second PMOS device 3374 is referred to as a "low VT" device. In this embodiment, the differentiated VT is achieved by using differentiated gate stacks for devices of the same conductivity type.

[0358] Refer again Figure 33BAccording to embodiments of this disclosure, the integrated circuit structure includes a fin (e.g., a silicon fin, such as 3350). It should be understood that the fin has a top (as shown) and sidewalls (inside and outside the page). A gate dielectric layer 3356 is situated above the top of the fin and laterally adjacent to the sidewalls of the fin. An N-type gate electrode of device 3354 is situated above the gate dielectric layer 3356 above the top of the fin and laterally adjacent to the sidewalls of the fin. The N-type gate electrode includes a P-type metal layer 3359 on the gate dielectric layer 3356 and an N-type metal layer 3358 on the P-type metal layer 3359. As will be understood, a first N-type source or drain region may be adjacent to a first side of the gate electrode (e.g., inside the page), and a second N-type source or drain region may be adjacent to a second side of the gate electrode (e.g., outside the page), the second side being opposite to the first side.

[0359] In one embodiment, the P-type metal layer 3359 comprises titanium and nitrogen, and the N-type metal layer 3358 comprises titanium, aluminum, carbon, and nitrogen. In one embodiment, the P-type metal layer 3359 has a thickness in the range of 2-12 angstroms, and in a particular embodiment, the P-type metal layer 3359 has a thickness in the range of 2-4 angstroms. In one embodiment, the N-type gate electrode further comprises a conductive filler metal layer 3360 on the N-type metal layer 3358. In one such embodiment, the conductive filler metal layer 3360 comprises tungsten. In a particular embodiment, the conductive filler metal layer 3360 comprises 95 or greater atomic percent tungsten and 0.1 to 2 atomic percent fluorine.

[0360] Refer again Figure 33B According to another embodiment of this disclosure, the integrated circuit structure includes a first N-type device 3352 having a voltage threshold (VT), the first N-type device 3352 having a first gate dielectric layer 3356 and a first N-type metal layer 3358 on the first gate dielectric layer 3356. It also includes a second N-type device 3354 having a voltage threshold (VT), the second N-type device 3354 having a second gate dielectric layer 3356, a P-type metal layer 3359 on the second gate dielectric layer 3356, and a second N-type metal layer 3358 on the P-type metal layer 3359.

[0361] In one embodiment, the VT of the second N-type device 3354 is higher than the VT of the first N-type device 3352. In one embodiment, the first N-type metal layer 3358 and the second N-type metal layer 3358 have the same configuration. In one embodiment, the first N-type metal layer 3358 and the second N-type metal layer 3358 have the same thickness. In one embodiment, the N-type metal layer 3358 comprises titanium, aluminum, carbon, and nitrogen, and the P-type metal layer 3359 comprises titanium and nitrogen.

[0362] Refer again Figure 33B According to embodiments of this disclosure, the integrated circuit structure includes a first P-type device 3372 having a voltage threshold (VT). The first P-type device 3372 has a first gate dielectric layer 3376 and a first P-type metal layer 3378A on the first gate dielectric layer 3376. The first P-type metal layer 3378A has a thickness. The system also includes a second P-type device 3374 having a voltage threshold (VT). The second P-type device 3374 has a second gate dielectric layer 3376 and a second P-type metal layer 3378B on the second gate dielectric layer 3376. The second P-type metal layer 3378B has a thickness greater than that of the first P-type metal layer 3378A.

[0363] In one embodiment, the VT of the second P-type device 3374 is lower than the VT of the first P-type device 3372. In one embodiment, the first P-type metal layer 3378A and the second P-type metal layer 3378B have the same configuration. In one embodiment, both the first P-type metal layer 3378A and the second P-type metal layer 3378B comprise titanium and nitrogen. In one embodiment, the thickness of the first P-type metal layer 3378A is less than the work function saturation thickness of the material of the first P-type metal layer 3378A. In one embodiment, although not depicted, the second P-type metal layer 3378B comprises a first metal film (e.g., from a second deposition) on a second metal film (e.g., from a first deposition), and a seam is formed between the first metal film and the second metal film.

[0364] Refer again Figure 33B According to another embodiment of this disclosure, the integrated circuit structure includes a first N-type device 3352, which has a first gate dielectric layer 3356 and a first N-type metal layer 3358 on the first gate dielectric layer 3356. A second N-type device 3354 has a second gate dielectric layer 3356, a first P-type metal layer 3359 on the second gate dielectric layer 3356, and a second N-type metal layer 3358 on the first P-type metal layer 3359. A first P-type device 3372 has a third gate dielectric layer 3376 and a second P-type gate layer 3378A on the third gate dielectric layer 3376. The second P-type metal layer 3378A has a thickness. The second P-type device 3374 has a fourth gate dielectric layer 3376 and a third P-type gate layer 3378B on the fourth gate dielectric layer 3376. The third P-type metal layer 3378B has a thickness greater than that of the second P-type metal layer 3378A.

[0365] In one embodiment, a first N-type device 3352 has a voltage threshold (VT), a second N-type device 3354 has a voltage threshold (VT), and the VT of the second N-type device 3354 is lower than the VT of the first N-type device 3352. In one embodiment, a first P-type device 3372 has a voltage threshold (VT), a second P-type device 3374 has a voltage threshold (VT), and the VT of the second P-type device 3374 is lower than the VT of the first P-type device 3372. In one embodiment, a third P-type metal layer 3378B includes a first metal film on a second metal film and a seam between the first metal film and the second metal film.

[0366] It is important to understand that more than two types of VT devices for the same conductivity type can be included in the same structure, such as on the same die. In the first example, Figure 34A Cross-sectional views of a group of three NMOS devices having a differentiated voltage threshold based on a differentiated gate electrode structure and modulation doping, and a group of three PMOS devices having a differentiated voltage threshold based on a differentiated gate electrode structure and modulation doping, according to embodiments of the present disclosure, are illustrated.

[0367] refer to Figure 34AA first NMOS device 3402 is adjacent to a second NMOS device 3404 and a third NMOS device 3403 on a semiconductor active region 3400, such as on a silicon fin or substrate. The first NMOS device 3402, the second NMOS device 3404, and the third NMOS device 3403 include a gate dielectric layer 3406. The first NMOS device 3402 and the third NMOS device 3403 have gate electrode stacks that are structurally identical or similar. However, the second NMOS device 3404 has a gate electrode stack that is structurally different from that of the first NMOS device 3402 and the third NMOS device 3403. Specifically, the first NMOS device 3402 and the third NMOS device 3403 include a first gate electrode conductive layer 3408, such as a first work function layer, and a gate electrode conductive fill 3410. The second NMOS device 3404 includes a second gate electrode conductive layer 3409, such as a second work function layer, a first gate electrode conductive layer 3408, and a gate electrode conductive fill 3410. The first NMOS device 3402 has a lower VT than the second NMOS device 3404. In one such embodiment, the first NMOS device 3402 is referred to as a "standard VT" device, and the second NMOS device 3404 is referred to as a "high VT" device. In this embodiment, the differentiated VT is achieved by using differentiated gate stacking for devices of the same conductivity type. In this embodiment, the third NMOS device 3403 has a different VT than the first NMOS device 3402 and the second NMOS device 3404, even though the gate electrode structure of the third NMOS device 3403 is the same as the gate electrode structure of the first NMOS device 3402. In one embodiment, the VT of the third NMOS device 3403 is between that of the first NMOS device 3402 and the second NMOS device 3404. In this embodiment, the differentiated VT between the third NMOS device 3403 and the first NMOS device 3402 is achieved by using modulation or differentiated implant doping at region 3412 of the third NMOS device 3403. In one such embodiment, the third N-type device 3403 has a channel region containing a dopant concentration different from that of the channel region of the first N-type device 3402.

[0368] Refer again Figure 34AA first PMOS device 3422 is adjacent to a second PMOS device 3424 and a third PMOS device 3423 on a semiconductor active region 3420, such as on a silicon fin or substrate. The first PMOS device 3422, the second PMOS device 3424, and the third PMOS device 3423 include a gate dielectric layer 3426. The first PMOS device 3422 and the third PMOS device 3423 have gate electrode stacks that are structurally identical or similar. However, the second PMOS device 3424 has a gate electrode stack that is structurally different from that of the first PMOS device 3422 and the third PMOS device 3423. Specifically, the first PMOS device 3422 and the third PMOS device 3423 include a gate electrode conductive layer 3428A of a first thickness, such as a work function layer, and a gate electrode conductive fill 3430. The second PMOS device 3424 includes a gate electrode conductive layer 3428B of a second thickness and a gate electrode conductive fill 3430. In one embodiment, gate electrode conductive layer 3428A and gate electrode conductive layer 3428B have the same configuration, but the thickness of gate electrode conductive layer 3428B (second thickness) is greater than the thickness of gate electrode conductive layer 3428A (first thickness). In another embodiment, the first PMOS device 3422 has a higher VT than the second PMOS device 3424. In such an embodiment, the first PMOS device 3422 is referred to as a "standard VT" device, and the second PMOS device 3424 is referred to as a "low VT" device. In another embodiment, differentiated VT is achieved by using differentiated gate stacks for devices of the same conductivity type. In another embodiment, the third PMOS device 3423 has a different VT than the first PMOS device 3422 and the second PMOS device 3424, even though the gate electrode structure of the third PMOS device 3423 is the same as the gate electrode structure of the first PMOS device 3422. In one embodiment, the VT of the third PMOS device 3423 is between the VT of the first PMOS device 3422 and the second PMOS device 3424. In an embodiment, the differentiation VT between the third PMOS device 3423 and the first PMOS device 3422 is achieved by using modulation or differential implantation doping in region 3432 of the third PMOS device 3423. In one such embodiment, the third P-type device 3423 has a channel region containing a dopant concentration different from that of the channel region of the first P-type device 3422.

[0369] In the second example, Figure 34B Cross-sectional views of a group of three NMOS devices having a differentiated voltage threshold based on a differentiated gate electrode structure and modulation doping, and a group of three PMOS devices having a differentiated voltage threshold based on a differentiated gate electrode structure and modulation doping, according to another embodiment of the present disclosure, are illustrated.

[0370] refer to Figure 34B A first NMOS device 3452 is adjacent to a second NMOS device 3454 and a third NMOS device 3453 on a semiconductor active region 3450, such as on a silicon fin or substrate. The first NMOS device 3452, the second NMOS device 3454, and the third NMOS device 3453 include a gate dielectric layer 3456. The second NMOS device 3454 and the third NMOS device 3453 have gate electrode stacks that are structurally identical or similar. However, the first NMOS device 3452 has a gate electrode stack that is structurally different from that of the second NMOS device 3454 and the third NMOS device 3453. Specifically, the first NMOS device 3452 includes a first gate electrode conductive layer 3458, such as a first work function layer, and a gate electrode conductive fill 3460. The second NMOS device 3454 and the third NMOS device 3453 include a second gate electrode conductive layer 3459, such as a second work function layer, a first gate electrode conductive layer 3458, and a gate electrode conductive fill 3460. The first NMOS device 3452 has a lower VT than the second NMOS device 3454. In one such embodiment, the first NMOS device 3452 is referred to as a "standard VT" device, and the second NMOS device 3454 is referred to as a "high VT" device. In this embodiment, the differentiated VT is achieved by using differentiated gate stacking for devices of the same conductivity type. In this embodiment, the third NMOS device 3453 has a different VT than the first NMOS device 3452 and the second NMOS device 3454, even though the gate electrode structure of the third NMOS device 3453 is the same as the gate electrode structure of the second NMOS device 3454. In one embodiment, the VT of the third NMOS device 3453 is between the VT of the first NMOS device 3452 and the second NMOS device 3454. In this embodiment, the differentiated VT between the third NMOS device 3453 and the second NMOS device 3454 is achieved by using modulation or differentiated implant doping at region 3462 of the third NMOS device 3453. In one such embodiment, the third N-type device 3453 has a channel region containing a dopant concentration different from that of the channel region of the second N-type device 3454.

[0371] Refer again Figure 34BA first PMOS device 3472 is adjacent to a second PMOS device 3474 and a third PMOS device 3473 on a semiconductor active region 3470, such as on a silicon fin or substrate. The first PMOS device 3472, the second PMOS device 3474, and the third PMOS device 3473 include a gate dielectric layer 3476. The second PMOS device 3474 and the third PMOS device 3473 have gate electrode stacks that are structurally identical or similar. However, the first PMOS device 3472 has a gate electrode stack that is structurally different from that of the second PMOS device 3474 and the third PMOS device 3473. Specifically, the first PMOS device 3472 includes a gate electrode conductive layer 3478A of a first thickness, such as a work function layer, and a gate electrode conductive fill 3480. The second PMOS device 3474 and the third PMOS device 3473 include a gate electrode conductive layer 3478B of a second thickness and a gate electrode conductive fill 3480. In one embodiment, gate electrode conductive layer 3478A and gate electrode conductive layer 3478B have the same configuration, but the thickness of gate electrode conductive layer 3478B (second thickness) is greater than the thickness of gate electrode conductive layer 3478A (first thickness). In another embodiment, the first PMOS device 3472 has a higher VT than the second PMOS device 3474. In such an embodiment, the first PMOS device 3472 is referred to as a "standard VT" device, and the second PMOS device 3474 is referred to as a "low VT" device. In another embodiment, differentiated VT is achieved by using differentiated gate stacks for devices of the same conductivity type. In another embodiment, the third PMOS device 3473 has a different VT than the first PMOS device 3472 and the second PMOS device 3474, even though the gate electrode structure of the third PMOS device 3473 is the same as the gate electrode structure of the second PMOS device 3474. In one embodiment, the VT of the third PMOS device 3473 is between the VT of the first PMOS device 3472 and the second PMOS device 3474. In one embodiment, the differentiation VT between the third PMOS device 3473 and the first PMOS device 3472 is achieved by using modulation or differential implantation doping in region 3482 of the third PMOS device 3473. In one such embodiment, the third P-type device 3473 has a channel region containing a dopant concentration different from that of the channel region of the second P-type device 3474.

[0372] Figures 35A-35D Cross-sectional views illustrating various operations in a method for manufacturing an NMOS device having a differentiated voltage threshold based on a differentiated gate electrode structure, according to another embodiment of the present disclosure.

[0373] refer to Figure 35AThe “Standard VT NMOS” region (STD VT NMOS) and the “High VT NMOS” region (HIGH VT NMOS) are shown as branching on a common substrate. The method of fabricating the integrated circuit structure includes forming a gate dielectric layer 3506 on a first semiconductor fin 3502 and a second semiconductor fin 3504, such as on the first and second silicon fins. A P-type metal layer 3508 is formed on the gate dielectric layer 3506 on the first semiconductor fin 3502 and the second semiconductor fin 3504.

[0374] refer to Figure 35B A portion of the P-type metal layer 3508 is removed from the gate dielectric layer 3506 above the first semiconductor fin 3502, but a portion 3509 of the P-type metal layer 3508 remains on the gate dielectric layer 3506 above the second semiconductor fin 3504.

[0375] refer to Figure 35C An N-type metal layer 3510 is formed on a portion 3509 of the P-type metal layer on the gate dielectric layer 3506 above the first semiconductor fin 3502 and on the gate dielectric layer 3506 above the second semiconductor fin 3504. In an embodiment, subsequent processing includes forming a first N-type device having a voltage threshold (VT) on the first semiconductor fin 3502 and forming a second N-type device having a voltage threshold (VT) on the second semiconductor fin 3504, wherein the VT of the second N-type device is higher than the VT of the first N-type device.

[0376] refer to Figure 35D In one embodiment, a conductive filler metal layer 3512 is formed on the N-type metal layer 3510. In one such embodiment, forming the conductive filler metal layer 3512 includes forming a tungsten-containing film using atomic layer deposition (ALD) with tungsten hexafluoride (WF6) precursor.

[0377] Figures 36A-36D Cross-sectional views illustrating various operations in a method for manufacturing a PMOS device having a differentiated voltage threshold based on a differentiated gate electrode structure, according to another embodiment of the present disclosure.

[0378] refer to Figure 36A The “Standard VT PMOS” region (STD VT PMOS) and the “Low VT PMOS” region (LOW VT PMOS) are shown as branching on a common substrate. The method of fabricating the integrated circuit structure includes forming a gate dielectric layer 3606 on a first semiconductor fin 3602 and a second semiconductor fin 3604, such as on the first and second silicon fins. A first P-type metal layer 3608 is formed on the gate dielectric layer 3606 on the first semiconductor fin 3602 and the second semiconductor fin 3604.

[0379] refer to Figure 36B A portion of the first P-type metal layer 3608 is removed from the gate dielectric layer 3606 above the first semiconductor fin 3602, but a portion 3609 of the first P-type metal layer 3608 remains on the gate dielectric layer 3606 above the second semiconductor fin 3604.

[0380] refer to Figure 36C A second P-type metal layer 3610 is formed on a portion 3609 of the first P-type metal layer on the gate dielectric layer 3606 above the first semiconductor fin 3602 and on the gate dielectric layer 3606 above the second semiconductor fin 3604. In an embodiment, subsequent processing includes forming a first P-type device having a voltage threshold (VT) on the first semiconductor fin 3602 and forming a second P-type device having a voltage threshold (VT) on the second semiconductor fin 3604, wherein the VT of the second P-type device is lower than the VT of the first P-type device.

[0381] In one embodiment, the first P-type metal layer 3608 and the second P-type metal layer 3610 have the same configuration. In one embodiment, the first P-type metal layer 3608 and the second P-type metal layer 3610 have the same thickness. In one embodiment, the first P-type metal layer 3608 and the second P-type metal layer 3610 have the same thickness and the same configuration. In one embodiment, a seam 3611 is located between the first P-type metal layer 3608 and the second P-type metal layer 3610, as depicted.

[0382] refer to Figure 36D In one embodiment, a conductive filler metal layer 3612 is formed over the P-type metal layer 3610. In one such embodiment, forming the conductive filler metal layer 3612 includes forming a tungsten-containing film using atomic layer deposition (ALD) with a tungsten hexafluoride (WF6) precursor. In one embodiment, an N-type metal layer 3614 is formed on the P-type metal layer 3610 prior to forming the conductive filler metal layer 3612, as depicted. In one such embodiment, the N-type metal layer 3614 is an article of manufacture of a bimetallic gate alternative processing scheme.

[0383] In another aspect, a metal gate structure for a complementary metal-oxide-semiconductor (CMOS) semiconductor device is described. In the example, Figure 37 A cross-sectional view of an integrated circuit structure having a P / N junction according to an embodiment of the present disclosure is illustrated.

[0384] refer to Figure 37The integrated circuit structure 3700 includes a semiconductor substrate 3702 having an N-well region 3704 and a P-well region 3708. The N-well region 3704 has a first semiconductor fin 3706 projecting therefrom, and the P-well region 3708 has a second semiconductor fin 3710 projecting therefrom. The first semiconductor fin 3706 and the second semiconductor fin 3710 are spaced apart. The N-well region 3704 is directly adjacent to the P-well region 3708 in the semiconductor substrate 3702. A trench isolation structure 3712 is on the semiconductor substrate 3702, outside and between the first semiconductor fin 3706 and the second semiconductor fin 3710. The first semiconductor fin 3706 and the second semiconductor fin 3710 extend above the trench isolation structure 3712.

[0385] A gate dielectric layer 3714 is located on the first semiconductor fin 3706 and the second semiconductor fin 3710, and on the trench isolation structure 3712. The gate dielectric layer 3714 is continuous between the first semiconductor fin 3706 and the second semiconductor fin 3710. A conductive layer 3716 is located on the gate dielectric layer 3714, which is located on the first semiconductor fin 3706 but not on the second semiconductor fin 3710. In one embodiment, the conductive layer 3716 comprises titanium, nitrogen, and oxygen. A p-type metal gate layer 3718 is located on the conductive layer 3716, which is located on the first semiconductor fin 3706 but not on the second semiconductor fin 3710. The p-type metal gate layer 3718 is also located on a portion, but not all, of the trench isolation structure 3712 between the first semiconductor fin 3706 and the second semiconductor fin 3710. An n-type metal gate layer 3720 is located on the second semiconductor fin 3710, on the trench isolation structure 3712 between the first semiconductor fin 3706 and the second semiconductor fin 3710, and on the p-type metal gate layer 3718.

[0386] In one embodiment, an interlayer dielectric (ILD) layer 3722 is situated above a trench isolation structure 3712 on the exterior of the first semiconductor fin 3706 and the second semiconductor fin 3710. The ILD layer 3722 has an opening 3724 that exposes the first semiconductor fin 3706 and the second semiconductor fin 3710. In one such embodiment, a conductive layer 3716, a p-type metal gate layer 3718, and an n-type metal gate layer 3720 are further formed along the sidewall 3726 of the opening 3724, as depicted. In a particular embodiment, the conductive layer 3716 has a top surface 3717 along the sidewall 3726 of the opening 3724, which is below the top surface 3719 of the p-type gate metal layer 3718 and the top surface 3721 of the n-type metal gate layer 3720 along the sidewall 3726 of the opening 3724, as depicted.

[0387] In one embodiment, the p-type metal gate layer 3718 comprises titanium and nitrogen. In one embodiment, the n-type metal gate layer 3720 comprises titanium and aluminum. In one embodiment, a conductive fill metal layer 3730 is situated above the n-type metal gate layer 3720, as depicted. In one such embodiment, the conductive fill metal layer 3730 comprises tungsten. In a particular embodiment, the conductive fill metal layer 3730 comprises 95 or greater atomic percent tungsten and 0.1 to 2 atomic percent fluorine. In one embodiment, the gate dielectric layer 3714 has a layer comprising hafnium and oxygen. In one embodiment, a thermal oxide layer or chemical oxide layer 3732 is situated between the upper portions of the first semiconductor fin 3706 and the second semiconductor fin 3710, as depicted. In one embodiment, the semiconductor substrate 3702 is a bulk silicon semiconductor substrate.

[0388] For reference only. Figure 37 On the right-hand side, according to embodiments of the present disclosure, the integrated circuit structure includes a semiconductor substrate 3702, which includes an N-well region 3704 having a semiconductor fin 3706 projecting therefrom. A trench isolation structure 3712 is located on the semiconductor substrate 3702 surrounding the semiconductor fin 3706. The semiconductor fin 3706 extends over the trench isolation structure 3712. A gate dielectric layer 3714 is on the semiconductor fin 3706. A conductive layer 3716 is on the gate dielectric layer 3714 on the semiconductor fin 3706. In one embodiment, the conductive layer 3716 comprises titanium, nitrogen, and oxygen. A P-type metal gate layer 3718 is on the conductive layer 3716 on the semiconductor fin 3706.

[0389] In one embodiment, an interlayer dielectric (ILD) layer 3722 is located above a trench isolation structure 3712. The ILD layer has an opening that exposes a semiconductor fin 3706. A conductive layer 3716 and a P-type metal gate layer 3718 are further formed along the sidewall of the opening. In one such embodiment, the conductive layer 3716 has a top surface along the sidewall of the opening, which is below the top surface of the P-type metal gate layer 3718 along the sidewall of the opening. In one embodiment, the P-type metal gate layer 3718 is on the conductive layer 3716. In one embodiment, the P-type metal gate layer 3718 comprises titanium and nitrogen. In one embodiment, a conductive fill metal layer 3730 is located above the P-type metal gate layer 3718. In one such embodiment, the conductive fill metal layer 3730 comprises tungsten. In a particular such embodiment, the conductive fill metal layer 3730 is composed of 95 or greater atomic percent tungsten and 0.1 to 2 atomic percent fluorine. In one embodiment, a gate dielectric layer 3714 comprises a layer containing hafnium and oxygen.

[0390] Figures 38A-38HCross-sectional views illustrate various operations in a method for fabricating an integrated circuit structure using a double-metal gate replacement gate process flow according to embodiments of the present disclosure.

[0391] The reference shows the NMOS (N-type) and PMOS (P-type) regions. Figure 38A A method of manufacturing an integrated circuit structure includes forming an interlayer dielectric (ILD) layer 3802 over a substrate 3800 and over a first semiconductor fin 3804 and a second semiconductor fin 3806. An opening 3808 is formed in the ILD layer 3802, exposing the first semiconductor fin 3804 and the second semiconductor fin 3806. In one embodiment, the opening 3808 is formed by removing a gate reservation or dummy gate structure initially located over the first semiconductor fin 3804 and the second semiconductor fin 3806.

[0392] A gate dielectric layer 3810 is formed in the opening 3808 and over the first semiconductor fin 3804 and the second semiconductor fin 3806, and on a portion of the trench isolation structure 3812 located between the first semiconductor fin 3804 and the second semiconductor fin 3806. In one embodiment, the gate dielectric layer 3810 is formed on a thermal oxide or chemical oxide layer 3811, such as a silicon oxide or silicon dioxide layer, which is formed on the first semiconductor fin 3804 and the second semiconductor fin 3806, as depicted. In another embodiment, the gate dielectric layer 3810 is formed directly on the first semiconductor fin 3804 and the second semiconductor fin 3806.

[0393] A conductive layer 3814 is formed on the gate dielectric layer 3810 formed on the first semiconductor fin 3804 and the second semiconductor fin 3806. In one embodiment, the conductive layer 3814 comprises titanium, nitrogen, and oxygen. A p-type metal gate layer 3816 is formed on the conductive layer 3814 formed on the first semiconductor fin 3804 and the second semiconductor fin 3806.

[0394] refer to Figure 38B A dielectric etch stop layer 3818 is formed on the p-type metal gate layer 3816. In one embodiment, the dielectric etch stop layer 3818 includes a first silicon oxide layer (e.g., SiO2), an aluminum oxide layer (e.g., Al2O3) on the first silicon oxide layer, and a second silicon oxide layer (e.g., SiO2) on the aluminum oxide layer.

[0395] refer to Figure 38C ,exist Figure 38B A mask 3820 is formed on top of the structure. The mask 3820 covers the PMOS region and exposes the NMOS region.

[0396] refer to Figure 38D The dielectric etch stop layer 3818, the p-type metal gate layer 3816, and the conductive layer 3814 are patterned to provide a patterned dielectric etch stop layer 3819 and a patterned p-type metal gate layer 3817 on the patterned conductive layer 3815 above the first semiconductor fin 3804 but not above the second semiconductor fin 3806. In an embodiment, the conductive layer 3814 protects the second semiconductor fin 3806 during patterning.

[0397] refer to Figure 38E ,from Figure 38D Remove mask 3820 from the structure. (Reference) Figure 38F ,from Figure 38E The patterned dielectric etch stop layer 3819 is removed from the structure.

[0398] refer to Figure 38G An n-type metal gate layer 3822 is formed on the second semiconductor fin 3806, on the portion of the trench isolation structure 3812 between the first semiconductor fin 3804 and the second semiconductor fin 3806, and on the patterned p-type metal gate layer 3817. In an embodiment, a patterned conductive layer 3815, a patterned p-type metal gate layer 3817, and an n-type metal gate layer 3822 are further formed along the sidewall 3824 of the opening 3808. In one such embodiment, the patterned conductive layer 3815 has a top surface along the sidewall 3824 of the opening 3808, which is below the top surfaces of the patterned p-type gate metal layer 3817 and the n-type metal gate layer 3822 along the sidewall 3824 of the opening 3808.

[0399] refer to Figure 38H A conductive fill metal layer 3826 is formed on top of the n-type metal gate layer 3822. In one embodiment, the conductive fill metal layer 3826 is formed by depositing a tungsten-containing film using atomic layer deposition (ALD) with tungsten hexafluoride (WF6) precursor.

[0400] In another aspect, a double silicide structure for complementary metal-oxide-semiconductor (CMOS) semiconductor devices is described. As an exemplary process flow, Figures 39A-39H Cross-sectional views illustrating various operations in a method of manufacturing a dual-silicide-based integrated circuit according to embodiments of the present disclosure are shown.

[0401] refer to Figure 39AThe NMOS and PMOS regions are shown as branching on a common substrate. A method of fabricating the integrated circuit structure includes forming a first gate structure 3902 on a first fin 3904, such as a first silicon fin, which may include dielectric sidewall spacers 3903. A second gate structure 3952 is formed on a second fin 3954, such as a second silicon fin, which may include dielectric sidewall spacers 3953. An insulating material 3906 is formed on the first fin 3904 adjacent to the first gate structure 3902 and on the second fin 3954 adjacent to the second gate structure 3952. In one embodiment, the insulating material 3906 is a sacrificial material and serves as a mask in the double silicide process.

[0402] refer to Figure 39B A first portion of the insulating material 3906 is removed from the first fin 3904 but not from the second fin 3954 to expose a first source or drain region 3908 and a second source or drain region 3910 of the first fin 3904 adjacent to the first gate structure 3902. In an embodiment, the first source or drain region 3908 and the second source or drain region 3910 are epitaxial regions formed within a recessed portion of the first fin 3904, as depicted. In one such embodiment, the first source or drain region 3908 and the second source or drain region 3910 comprise silicon and germanium.

[0403] refer to Figure 39C A first metal silicide layer 3912 is formed on the first source or drain region 3908 and the second source or drain region 3910 of the first fin 3904. In one embodiment, the first metal silicide layer 3912 is formed by the following steps: Figure 39B The process involves depositing a layer of nickel and platinum on the structure, annealing the layer of nickel and platinum, and removing unreacted portions of the layer of nickel and platinum.

[0404] refer to Figure 39D After forming the first metal silicide layer 3912, a second portion of the insulating material 3906 is removed from the second fin 3954 to expose the third source or drain region 3958 and the fourth source or drain region 3960 of the second fin 3954 adjacent to the second gate structure 3952. In one embodiment, the third source or drain region 3958 and the fourth source or drain region 3960 are formed within the second fin 3954, such as within a second silicon fin, as depicted. However, in another embodiment, the third source or drain region 3958 and the fourth source or drain region 3960 are epitaxial regions formed within a recessed portion of the second fin 3954. In one such embodiment, the third source or drain region 3958 and the fourth source or drain region 3960 comprise silicon.

[0405] refer to Figure 39E ,exist Figure 39D Structurally, a first metal layer 3914 is formed on the first source or drain region 3908, the second source or drain region 3910, the third source or drain region 3958, and the fourth source or drain region 3960. Then, a second metal silicide layer 3962 is formed on the third source or drain region 3958 and the fourth source or drain region 3960 of the second fin 3954. The second metal silicide layer 3962 is formed from the first metal layer 3914, for example, using an annealing process. In an embodiment, the second metal silicide layer 3962 is structurally different from the first metal silicide layer 3912. In one embodiment, the first metal layer 3914 is or includes a titanium layer. In one embodiment, the first metal layer 3914 is formed as a conformal metal layer, for example, with... Figure 39D The open grooves are conformal, as depicted.

[0406] refer to Figure 39F In one embodiment, the first metal layer 3914 is recessed to form a U-shaped metal layer 3916 over each of the first source or drain region 3908, the second source or drain region 3910, the third source or drain region 3958, and the fourth source or drain region 3960.

[0407] refer to Figure 39G In the embodiments, in Figure 39F A second metal layer 3918 is formed on the U-shaped metal layer 3916. In an embodiment, the second metal layer 3918 is constructed differently from the U-shaped metal layer 3916.

[0408] refer to Figure 39H In the embodiments, in Figure 39G A third metal layer 3920 is formed on the second metal layer 3918 of the structure. In an embodiment, the third metal layer 3920 has the same structure as the U-shaped metal layer 3916.

[0409] Refer again Figure 39H According to embodiments of this disclosure, an integrated circuit structure 3900 includes a P-type semiconductor device (PMOS) above a substrate. The P-type semiconductor device includes a first fin 3904, such as a first silicon fin. It should be understood that the first fin has a top (shown as 3904A) and sidewalls (e.g., entering and exiting the page). A first gate electrode 3902 is included over the top 3904A of the first fin 3904 and laterally adjacent to the sidewalls of the first fin 3904, and also includes a first gate electrode over the first gate dielectric layer over the top 3904A of the first fin 3904 and laterally adjacent to the sidewalls of the first fin 3904. The first gate electrode 3902 has a first side 3902A and a second side 3902B opposite to the first side 3902A.

[0410] The first and second semiconductor source or drain regions 3908 and 3910 are respectively adjacent to the first side 3902A and the second side 3902B of the first gate electrode 3902. The first and second trench contact structures 3930 and 3932 are respectively above the first and second semiconductor source or drain regions 3908 and 3910, adjacent to the first side 3902A and the second side 3902B of the first gate electrode 3902. The first metal silicide layer 3912 is respectively directly between the first and second trench contact structures 3930 and 3932 and the first and second semiconductor source or drain regions 3908 and 3910.

[0411] The integrated circuit structure 3900 includes an N-type semiconductor device (NMOS) above a substrate. The N-type semiconductor device includes a second fin 3954, such as a second silicon fin. It should be understood that the second fin has a top (shown as 3954A) and sidewalls (e.g., entering and exiting the page). A second gate electrode 3952 is included on the top 3954A of the second fin 3954 and laterally adjacent to the sidewalls of the second fin 3954, and also includes a second gate electrode on the second gate dielectric layer above the top 3954A of the second fin 3954 and laterally adjacent to the sidewalls of the second fin 3954. The second gate electrode 3952 has a first side 3952A and a second side 3952B opposite to the first side 3952A.

[0412] The third and fourth semiconductor source or drain regions 3958 and 3960 are respectively adjacent to the first side 3952A and the second side 3952B of the second gate electrode 3952. The third and fourth trench contact structures 3970 and 3972 are respectively located above the third and fourth semiconductor source or drain regions 3958 and 3960, adjacent to the first side 3952A and the second side 3952B of the second gate electrode 3952. The second metal silicide layer 3962 is directly between the third and fourth trench contact structures 3970 and 3972 and the third and fourth semiconductor source or drain regions 3958 and 3960. In an embodiment, the first metal silicide layer 3912 includes at least one metal type not included in the second metal silicide layer 3962.

[0413] In one embodiment, the second metal silicide layer 3962 comprises titanium and silicon. The first metal silicide layer 3912 comprises nickel, platinum, and silicon. In one embodiment, the first metal silicide layer 3912 further comprises germanium. In one embodiment, the first metal silicide layer 3912 further comprises titanium, for example, as incorporated into the first metal silicide layer 3912 during subsequent formation of the second metal silicide layer 3962 with the first metal layer 3914. In one such embodiment, the silicide layer already formed on the PMOS source or drain region is further modified by an annealing process for forming a silicide region on the NMOS source or drain region. This can result in a silicide layer having a fractional percentage of all silicide metal on the PMOS source or drain region. However, in other embodiments, such a silicide layer already formed on the PMOS source or drain region is not modified, or is substantially not modified, by an annealing process for forming a silicide region on the NMOS source or drain region.

[0414] In one embodiment, the first and second semiconductor source or drain regions 3908 and 3910 are first and second embedded semiconductor source or drain regions comprising silicon and germanium. In one such embodiment, the third and fourth semiconductor source or drain regions 3958 and 3960 are third and fourth embedded semiconductor source or drain regions comprising silicon. In another embodiment, the third and fourth semiconductor source or drain regions 3958 and 3960 are formed in a fin 3954 instead of an embedded epitaxial region.

[0415] In one embodiment, the first, second, third, and fourth trench contact structures 3930, 3932, 3970, and 3972 all include a U-shaped metal layer 3916 and a T-shaped metal layer 3918 above and over the entire U-shaped metal layer 3916. In one embodiment, the U-shaped metal layer 3916 includes titanium, and the T-shaped metal layer 3918 includes cobalt. In one embodiment, the first, second, third, and fourth trench contact structures 3930, 3932, 3970, and 3972 all further include a third metal layer 3920 on the T-shaped metal layer 3918. In one embodiment, the third metal layer 3920 and the U-shaped metal layer 3916 have the same configuration. In a particular embodiment, the third metal layer 3920 and the U-shaped metal layer include titanium, and the T-shaped metal layer 3918 includes cobalt.

[0416] In another aspect, trench contact structures, for example, for the source or drain regions, are described. In the example, Figure 40A A cross-sectional view of an integrated circuit structure having trench contacts for an NMOS device is illustrated according to an embodiment of the present disclosure. Figure 40BA cross-sectional view of an integrated circuit structure having trench contacts for a PMOS device is illustrated according to another embodiment of the present disclosure.

[0417] refer to Figure 40A The integrated circuit structure 4000 includes a fin 4002, such as a silicon fin. A gate dielectric layer 4004 is on the fin 4002. A gate electrode 4006 is on the gate dielectric layer 4004. In an embodiment, the gate electrode 4006 includes a conformal conductive layer 4008 and a conductive fill 4010. In an embodiment, a dielectric cap 4012 is on the gate electrode 4006 and on the gate dielectric layer 4004. The gate electrode has a first side 4006A and a second side 4006B opposite to the first side 4006A. A dielectric spacer 4013 is along the sidewall of the gate electrode 4006. In one embodiment, the gate dielectric layer 4004 is further located between a first dielectric spacer 4013 and the first side 4006A of the gate electrode 4006, and between a second dielectric spacer 4013 and the second side 4006B of the gate electrode 4006, as depicted. In the embodiments, although not depicted, a thin oxide layer such as a thermal or chemical silicon oxide or silicon dioxide layer is present between the fin 4002 and the gate dielectric layer 4004.

[0418] The first and second semiconductor source or drain regions 4014 and 4016 are respectively adjacent to the first side 4006A and the second side 4006B of the gate electrode 4006. In one embodiment, the first and second semiconductor source or drain regions 4014 and 4016 are in the fin 4002, as depicted. However, in another embodiment, the first and second semiconductor source or drain regions 4014 and 4016 are embedded epitaxial regions formed in the recess of the fin 4002.

[0419] The first and second trench contact structures 4018 and 4020 are respectively located above the first and second semiconductor source or drain regions 4014 and 4016, adjacent to the first side 4006A and the second side 4006B of the gate electrode 4006. Both the first and second trench contact structures 4018 and 4020 include a U-shaped metal layer 4022 and a T-shaped metal layer 4024 above and over the entire U-shaped metal layer 4022. In one embodiment, the U-shaped metal layer 4022 and the T-shaped metal layer 4024 differ in configuration. In one such embodiment, the U-shaped metal layer 4022 comprises titanium, and the T-shaped metal layer 4024 comprises cobalt. In one embodiment, both the first and second trench contact structures 4018 and 4020 further include a third metal layer 4026 on the T-shaped metal layer 4024. In one such embodiment, the third metal layer 4026 and the U-shaped metal layer 4022 have the same configuration. In a particular embodiment, the third metal layer 4026 and the U-shaped metal layer 4022 comprise titanium, and the T-shaped metal layer 4024 comprises cobalt.

[0420] A first trench contact via 4028 is electrically connected to a first trench contact portion 4018. In a particular embodiment, the first trench contact via 4028 is on and coupled to a third metal layer 4026 of the first trench contact portion 4018. The first trench contact via 4028 further lies on and contacts a portion of one of the dielectric spacers 4013, and also lies on and contacts a portion of the dielectric cap 4012. A second trench contact via 4030 is electrically connected to a second trench contact portion 4020. In a particular embodiment, the second trench contact via 4030 lies on and is coupled to the third metal layer 4026 of the second trench contact portion 4020. The second trench contact via 4030 further lies on and contacts a portion of the other dielectric spacer 4013, and also lies on and contacts another portion of the dielectric cap 4012.

[0421] In one embodiment, a metal silicide layer 4032 is positioned directly between the first and second trench contact structures 4018 and 4020 and the first and second semiconductor source or drain regions 4014 and 4016, respectively. In one embodiment, the metal silicide layer 4032 comprises titanium and silicon. In a particular embodiment, the first and second semiconductor source or drain regions 4014 and 4016 are first and second N-type semiconductor source or drain regions.

[0422] refer to Figure 40BThe integrated circuit structure 4050 includes a fin 4052, such as a silicon fin. A gate dielectric layer 4054 is on the fin 4052. A gate electrode 4056 is on the gate dielectric layer 4054. In an embodiment, the gate electrode 4056 includes a conformal conductive layer 4058 and a conductive fill 4060. In an embodiment, an insulating cap 4062 is on the gate electrode 4056 and on the gate dielectric layer 4054. The gate electrode has a first side 4056A and a second side 4056B opposite to the first side 4056A. A dielectric spacer 4063 is along the sidewall of the gate electrode 4056. In one embodiment, the gate dielectric layer 4054 is further located between a first dielectric spacer 4063 and the first side 4056A of the gate electrode 4056, and between a second dielectric spacer 4063 and the second side 4056B of the gate electrode 4056, as depicted. In the embodiments, although not depicted, a thin oxide layer such as a thermal or chemical silicon oxide or silicon dioxide layer is present between the fin 4052 and the gate dielectric layer 4054.

[0423] The first and second semiconductor source or drain regions 4064 and 4066 are respectively adjacent to the first side 4056A and the second side 4056B of the gate electrode 4056. In one embodiment, the first and second semiconductor source or drain regions 4064 and 4066 are embedded epitaxial regions formed in the recesses 4065 and 4067 of the fin 4052, as depicted. However, in another embodiment, the first and second semiconductor source or drain regions 4064 and 4066 are in the fin 4052.

[0424] The first and second trench contact structures 4068 and 4070 are respectively located above the first and second semiconductor source or drain regions 4064 and 4066, adjacent to the first side 4056A and the second side 4056B of the gate electrode 4056. Both the first and second trench contact structures 4068 and 4070 include a U-shaped metal layer 4072 and a T-shaped metal layer 4074 above and over the entire U-shaped metal layer 4072. In one embodiment, the U-shaped metal layer 4072 and the T-shaped metal layer 4074 differ in configuration. In one such embodiment, the U-shaped metal layer 4072 comprises titanium, and the T-shaped metal layer 4074 comprises cobalt. In one embodiment, both the first and second trench contact structures 4068 and 4070 further include a third metal layer 4076 on the T-shaped metal layer 4074. In one such embodiment, the third metal layer 4076 and the U-shaped metal layer 4072 have the same configuration. In a particular embodiment, the third metal layer 4076 and the U-shaped metal layer 4072 comprise titanium, and the T-shaped metal layer 4074 comprises cobalt.

[0425] A first trench contact via 4078 is electrically connected to a first trench contact portion 4068. In a particular embodiment, the first trench contact via 4078 is on and coupled to a third metal layer 4076 of the first trench contact portion 4068. The first trench contact via 4078 further lies on and contacts a portion of one of the dielectric spacers 4063, and also lies on and contacts a portion of the dielectric cap 4062. A second trench contact via 4080 is electrically connected to a second trench contact portion 4070. In a particular embodiment, the second trench contact via 4080 lies on and is coupled to the third metal layer 4076 of the second trench contact portion 4070. The second trench contact via 4080 further lies on and contacts a portion of the other dielectric spacer 4063, and also lies on and contacts another portion of the dielectric cap 4062.

[0426] In one embodiment, a metal silicide layer 4082 is directly between the first and second trench contact structures 4068 and 4070 and the first and second semiconductor source or drain regions 4064 and 4066, respectively. In one embodiment, the metal silicide layer 4082 comprises nickel, platinum, and silicon. In a particular embodiment, the first and second semiconductor source or drain regions 4064 and 4066 are first and second P-type semiconductor source or drain regions. In one embodiment, the metal silicide layer 4082 further comprises germanium. In one embodiment, the metal silicide layer 4082 further comprises titanium.

[0427] One or more embodiments described herein relate to the use of metal chemical vapor deposition for wrap-around semiconductor contacts. The embodiments may be applicable to or include one or more of the following: chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), conductive contact fabrication, or thin films.

[0428] Specific embodiments may include fabricating titanium or similar metal-containing layers using low-temperature (e.g., below 500 degrees Celsius, or in the range of 400-500 degrees Celsius) chemical vapor deposition of the contact metal to provide conformal source or drain contacts. Achieving such conformal source or drain contacts can improve the performance of three-dimensional (3D) transistor complementary metal-oxide-semiconductor (CMOS).

[0429] To provide context, sputtering can be used to deposit metal onto a semiconductor contact layer. Sputtering is a line-of-sight process and may not be well-suited for 3D transistor fabrication. Known sputtering solutions result in poor or incomplete metal-semiconductor junctions on the device contact surface at an angle relative to the incident deposition.

[0430] According to one or more embodiments of this disclosure, a low-temperature chemical vapor deposition process is implemented to fabricate contact metals to provide conformality in three dimensions and maximize the contact area of ​​the metal-semiconductor junction. The resulting larger contact area can reduce the resistance of the junction. Embodiments may include deposition on a semiconductor surface having an uneven topography, wherein the topography of the region refers to the surface shape and features themselves, and the uneven topography includes uneven surface shapes and features or portions of surface shapes and features, i.e., surface shapes and features that are not completely flat.

[0431] The embodiments described herein may include fabricating a surround contact structure. In one such embodiment, the use of pure metal conformally deposited onto the source-drain contact of a transistor via chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, or plasma-enhanced atomic layer deposition is described. Such conformal deposition can be used to increase the usable area of ​​the metal-semiconductor contact and reduce resistance, thereby improving the performance of the transistor device. In the embodiment, the relatively low deposition temperature results in a minimized resistance per unit area of ​​the junction.

[0432] It should be understood that a wide variety of integrated circuit structures can be fabricated using integration schemes involving metal layer deposition processes as described herein. According to embodiments of this disclosure, a method of fabricating an integrated circuit structure includes providing a substrate having features thereon in a chemical vapor deposition (CVD) chamber having an RF source. The method further includes reacting titanium tetrachloride (TiCl4) with hydrogen (H2) to form a titanium (Ti) layer on the features of the substrate.

[0433] In an embodiment, the titanium layer has a total atomic composition comprising 98% or more titanium and 0.5-2% chlorine. In alternative embodiments, a similar process is used to produce high-purity metal-containing layers of zinc (Zr), hafnium (Hf), tantalum (Ta), niobium (Nb), or vanadium (V). In an embodiment, there is a relatively small variation in film thickness; for example, in an embodiment, all coverage is greater than 50% and nominally 70% or greater (i.e., a thickness variation of 30% or less). In an embodiment, the thickness is measurably thicker on silicon (Si) or silicon germanium (SiGe) than on other surfaces because Si or SiGe reacts during deposition and accelerates the uptake of Ti. In an embodiment, the film composition includes about 0.5% Cl (or less than 1% Cl) as an impurity, while substantially no other observed impurities. In an embodiment, the deposition process enables the realization of metal coverage on non-visual surfaces, such as surfaces hidden by sputtering deposition lines of sight. The embodiments described herein can be implemented to improve transistor device driving by reducing the external resistance of the current driven through the source and drain contacts.

[0434] According to embodiments of this disclosure, the substrate is characterized by exposing source or drain contact trenches of a semiconductor source or drain structure. A titanium layer (or other high-purity metal-containing layer) is used as a conductive contact layer for the semiconductor source or drain structure. (See below for further details.) Figure 41A , 41B Exemplary embodiments of such implementations are described in 42, 43A-43C and 44.

[0435] Figure 41A A cross-sectional view of a semiconductor device having conductive contacts in the source or drain region according to an embodiment of the present disclosure is illustrated.

[0436] refer to Figure 41A The semiconductor structure 4100 includes a gate structure 4102 above the substrate 4104. The gate structure 4102 includes a gate dielectric layer 4102A, a work function layer 4102B, and a gate fill 4102C. A source region 4108 and a drain region 4110 are located on opposite sides of the gate structure 4102. A source or drain contact 4112 is electrically connected to the source region 4108 and the drain region 4110, and is spaced apart from the gate structure 4102 by one or both of an interlayer dielectric layer 4114 or a gate dielectric spacer 4116. The source region 4108 and the drain region 4110 are regions of the substrate 4104.

[0437] In an embodiment, the source or drain contact 4112 includes a high-purity metal-containing layer 4112A and a conductive trench filler material 4112B, as described above. In one embodiment, the high-purity metal-containing layer 4112A has a total atomic composition comprising 98% or more titanium. In such an embodiment, the total atomic composition of the high-purity metal-containing layer 4112A further comprises 0.5-2% chlorine. In an embodiment, the high-purity metal-containing layer 4112A has a thickness variation of 30% or less. In an embodiment, the conductive trench filler material 4112B is composed of a conductive metal, such as, but not limited to, Cu, Al, W, or alloys thereof.

[0438] Figure 41B A cross-sectional view of another semiconductor device having conductive contacts on a raised source or drain region is illustrated according to an embodiment of the present disclosure.

[0439] refer to Figure 41BThe semiconductor structure 4150 includes a gate structure 4152 above the substrate 4154. The gate structure 4152 includes a gate dielectric layer 4152A, a work function layer 4152B, and a gate fill 4152C. A source region 4158 and a drain region 4160 are located on opposite sides of the gate structure 4152. A source or drain contact 4162 is electrically connected to the source region 4158 and the drain region 4160, and is spaced apart from the gate structure 4152 by one or both of an interlayer dielectric layer 4164 and a gate dielectric spacer 4166. The source region 4158 and the drain region 4160 are epitaxial or embedded material regions formed in etched areas of the substrate 4154. As depicted, in this embodiment, the source region 4158 and the drain region 4160 are protruding source and drain regions. In a particular embodiment, the protruding source and drain regions are protruding silicon source and drain regions or protruding silicon-germanium source and drain regions.

[0440] In an embodiment, the source or drain contact 4162 includes a high-purity metal-containing layer 4162A and a conductive trench filler material 4162B, as described above. In one embodiment, the high-purity metal-containing layer 4162A has a total atomic composition comprising 98% or more titanium. In such an embodiment, the total atomic composition of the high-purity metal-containing layer 4162A further comprises 0.5-2% chlorine. In an embodiment, the high-purity metal-containing layer 4162A has a thickness variation of 30% or less. In an embodiment, the conductive trench filler material 4162B is composed of a conductive metal, such as, but not limited to, Cu, Al, W, or alloys thereof.

[0441] Therefore, in the embodiments, common references are made. Figure 41A and 41B The integrated circuit structure includes surface features (source or drain contact trenches exposing semiconductor source or drain structures). A high-purity metal-containing layer 4112A or 4162A is applied to the surface of the source or drain contact trench. It should be understood that the contact formation process may involve consuming the exposed silicon or germanium or silicon-germanium material in the source or drain region. Such consumption can degrade device performance. In contrast, according to embodiments of this disclosure, the surface (4149 or 4199) of the semiconductor source (4108 or 4158) or drain (4110 or 4160) structure below the source or drain contact trench is not eroded or consumed, or substantially not eroded or consumed. In one such embodiment, this lack of consumption or erosion results from the low-temperature deposition of a high-purity metal-containing contact layer.

[0442] Figure 42 A plan view of a plurality of gate lines over a pair of semiconductor fins according to an embodiment of the present disclosure is illustrated.

[0443] refer to Figure 42 Multiple effective gate lines 4204 are formed on multiple semiconductor fins 4200. Dummy gate lines 4206 are located at the ends of the multiple semiconductor fins 4200. The spacing 4208 between gate lines 4204 / 4206 is a location where trench contacts can be formed as conductive contacts to source or drain regions such as source or drain regions 4251, 4252, 4253, and 4254.

[0444] Figures 43A-43C Examples of various operations in a method for manufacturing an integrated circuit structure according to embodiments of the present disclosure are illustrated. Figure 42 A cross-sectional view taken along the a-a' axis.

[0445] refer to Figure 43A A plurality of effective gate lines 4304 are formed on semiconductor fins 4302, which are formed above substrate 4300. Dummy gate lines 4306 are located at the ends of semiconductor fins 4302. A dielectric layer 4310 is located between the effective gate lines 4304, between the dummy gate lines 4306 and the effective gate lines 4304, and outside the dummy gate lines 4306. An embedded source or drain structure 4308 is located in semiconductor fins 4302, between the effective gate lines 4304, and between the dummy gate lines 4306 and the effective gate lines 4304. The effective gate lines 4304 include a gate dielectric layer 4312, a work function gate electrode portion 4314, a filled gate electrode portion 4316, and a gate electrode capping layer 4318. Dielectric spacers 4320 are lined within the sidewalls of the effective gate lines 4304 and the dummy gate lines 4306.

[0446] refer to Figure 43B Removing portions of the dielectric layer 4310 between the effective gate lines 4304 and between the dummy gate line 4306 and the effective gate line 4304 provides an opening 4330 at the location where a trench contact is to be formed. Removing portions of the dielectric layer 4310 between the effective gate lines 4304 and between the dummy gate line 4306 and the effective gate line 4304 may result in erosion of the embedded source or drain structure 4308 to provide an eroded embedded source or drain structure 4332, which may have an upper saddle-shaped morphology, such as... Figure 43B As depicted in the text.

[0447] refer to Figure 43C Trench contacts 4334 are formed in the openings 4330 between the effective gate lines 4304 and between the dummy gate line 4306 and the effective gate line 4304. Each of the trench contacts 4334 may include a metal contact layer 4336 and a conductive filler material 4338.

[0448] Figure 44 Examples of integrated circuit structures according to embodiments of the present disclosure are illustrated. Figure 42 A cross-sectional view taken along the b-b' axis.

[0449] refer to Figure 44 Fin 4402 is depicted above substrate 4404. The lower portion of fin 4402 is surrounded by trench isolation material 4404. The upper portion of fin 4402 has been removed to allow for the growth of embedded source and drain structures 4406. Trench contacts 4408 are formed in openings in dielectric layer 4410, exposing the embedded source and drain structures 4406. The trench contacts include a metal-containing contact layer 4412 and a conductive filler material 4414. It should be understood that, according to an embodiment, the metal-containing contact layer 4412 extends to the top of the trench contact 4408, as... Figure 44 As depicted in the diagram. However, in another embodiment, the metal contact layer 4412 does not extend to the top of the trench contact portion 4408, but is slightly recessed within the trench contact portion 4408, for example, similar to... Figure 43C The depiction of the metal-containing contact layer 4336 in the image.

[0450] Therefore, common reference Figure 42 , 43A-43C and 44, according to embodiments of the present disclosure, an integrated circuit structure includes semiconductor fins (4200, 4302, 4402) above a substrate (4300, 4400). The semiconductor fins (4200, 4302, 4402) have a top and sidewalls. A gate electrode (4204, 4304) is located above the top of the semiconductor fins (4200, 4302, 4402) and adjacent to a portion of the sidewall of the semiconductor fins (4200, 4302, 4402). The gate electrode (4204, 4304) defines a channel region in the semiconductor fins (4200, 4302, 4402). The first semiconductor source or drain structure (4251, 4332, 4406) is located at the first end of the channel region on the first side of the gate electrode (4204, 4304), and the first semiconductor source or drain structure (4251, 4332, 4406) has a non-planar morphology. The second semiconductor source or drain structure (4252, 4332, 4406) is located at the second end of the channel region on the second side of the gate electrode (4204, 4304), the second end being opposite to the first end, and the second side being opposite to the first side. The second semiconductor source or drain structure (4252, 4332, 4406) also has a non-planar morphology. Metal contact materials (4336, 4412) are applied directly to the first semiconductor source or drain structure (4251, 4332, 4406) and directly to the second semiconductor source or drain structure (4252, 4332, 4406). The metal contact material (4336, 4412) conforms to the uneven topography of the first semiconductor source or drain structure (4251, 4332, 4406) and also conforms to the uneven topography of the second semiconductor source or drain structure (4252, 4332, 4406).

[0451] In embodiments, the metal-containing contact materials (4336, 4412) have a total atomic composition comprising 95% or more of a single metal species. In one such embodiment, the metal-containing contact materials (4336, 4412) have a total atomic composition comprising 98% or more of titanium. In a particular such embodiment, the total atomic composition of the metal-containing contact materials (4336, 4412) further comprises 0.5-2% chlorine. In embodiments, the metal-containing contact materials (4336, 4412) have a thickness variation of 30% or less along the uneven morphology of the first semiconductor source or drain structure (4251, 4332, 4406) and along the uneven morphology of the second semiconductor source or drain structure (4252, 4332, 4406).

[0452] In the embodiments, both the uneven topography of the first semiconductor source or drain structure (4251, 4332, 4406) and the uneven topography of the second semiconductor source or drain structure (4252, 4332, 4406) include a convex central portion and a lower side portion, for example, as... Figure 44 As depicted in the figure. In the embodiment, both the uneven topography of the first semiconductor source or drain structure (4251, 4332, 4406) and the uneven topography of the second semiconductor source or drain structure (4252, 4332, 4406) include saddle-shaped portions, for example, as shown in the figure. Figure 43C As depicted in the text.

[0453] In an embodiment, both the first semiconductor source or drain structure (4251, 4332, 4406) and the second semiconductor source or drain structure (4252, 4332, 4406) comprise silicon. In another embodiment, both the first semiconductor source or drain structure (4251, 4332, 4406) and the second semiconductor source or drain structure (4252, 4332, 4406) further comprise germanium, for example, in the form of silicon-germanium.

[0454] In one embodiment, the metal-containing contact material (4336, 4412) directly on the first semiconductor source or drain structure (4251, 4332, 4406) further extends along the sidewall of a trench in the dielectric layer (4320, 4410) above the first semiconductor source or drain structure (4251, 4332, 4406), the trench exposing a portion of the first semiconductor source or drain structure (4251, 4332, 4406). In one such embodiment, the thickness of the metal-containing contact material (4336) along the sidewall of the trench decreases from 4336A at the first semiconductor source or drain structure (4332) towards a position (4336B) above the first semiconductor source or drain structure (4332), in Figure 43C Examples are illustrated below. In one embodiment, conductive filler materials (4338, 4414) are applied to the metal-containing contact materials (4336, 4412) within the trench, as shown below. Figure 43C and 44 As depicted in the text.

[0455] In an embodiment, the integrated circuit structure further includes a second semiconductor fin having a top and sidewalls (e.g., Figure 42The upper fins are 4200, 4302, and 4402. Gate electrodes (4204, 4304) are further positioned above the top of the second semiconductor fin and adjacent to a portion of the sidewall of the second semiconductor fin, defining a channel region in the second semiconductor fin. A third semiconductor source or drain structure (4253, 4332, 4406) is located at a first end of the channel region of the second semiconductor fin on a first side of the gate electrode (4204, 4304), and the third semiconductor source or drain structure has a non-planar topography. A fourth semiconductor source or drain structure (4254, 4332, 4406) is located at a second end of the channel region of the second semiconductor fin on a second side of the gate electrode (4204, 4304), the second end being opposite to the first end, and the fourth semiconductor source or drain structure (4254, 4332, 4406) also has a non-planar topography. The metal contact materials (4336, 4412) are directly on the third semiconductor source or drain structure (4253, 4332, 4406) and directly on the fourth semiconductor source or drain structure (4254, 4332, 4406). The metal contact materials (4336, 4412) conform to the non-flat topography of the third semiconductor source or drain structure (4253, 4332, 4406) and conform to the non-flat topography of the fourth semiconductor source or drain structure (4254, 4332, 4406). In the embodiment, the metal contact material (4336, 4412) is continuous between the first semiconductor source or drain structure (4251, 4332, 4406 on the left) and the third semiconductor source or drain structure (4253, 4332, 4406 on the right), and is continuous between the second semiconductor source or drain structure (4252) and the fourth semiconductor source or drain structure (4254).

[0456] In another aspect, a hard mask material is used to preserve (inhibit erosion) and can remain on top of the dielectric material at the location where the conductive trench contact is interrupted (e.g., at the contact plug location). For example, Figure 45A and 45B Plan view and corresponding cross-sectional view of an integrated circuit structure including a trench contact plug having a hard mask material thereon, according to embodiments of the present disclosure, are illustrated respectively.

[0457] refer to Figure 45A and 45BIn this embodiment, the integrated circuit structure 4500 includes a fin 4502A, such as a silicon fin. A plurality of gate structures 4506 are situated above the fin 4502A. Each gate structure in the gate structure 4506 is aligned along a direction 4508 orthogonal to the fin 4502A and has a pair of dielectric sidewall spacers 4510. A trench contact structure 4512 is situated above the fin 4502A and directly between the dielectric sidewall spacers 4510 of the first pair of gate structures 4506A / 4506B in the gate structure 4506. A contact plug 4514B is situated above the fin 4502A and directly between the dielectric sidewall spacers 4510 of the second pair of gate structures 4506B / 4506C in the gate structure 4506. The contact plug 4514B includes a lower dielectric material 4516 and an upper hard mask material 4518.

[0458] In an embodiment, the lower dielectric material 4516 of the contact plug 4516B comprises silicon and oxygen, such as silicon oxide or silicon dioxide. The upper hard mask material 4518 of the contact plug 4516B comprises silicon and nitrogen, such as silicon nitride, silicon-rich nitride, or silicon-poor nitride.

[0459] In one embodiment, the trench contact structure 4512 includes a lower conductive structure 4520 and a dielectric cap 4522 on the lower conductive structure 4520. In one embodiment, the dielectric cap 4522 of the trench contact structure 4512 has an upper surface that is coplanar with the upper surface of the upper hard mask material 4518 of the contact plug 4514B, as depicted.

[0460] In one embodiment, each of the plurality of gate structures 4506 includes a gate electrode 4524 on a gate dielectric layer 4526. A dielectric cap 4528 is on the gate electrode 4524. In one embodiment, the dielectric cap 4528 of each of the plurality of gate structures 4506 has an upper surface coplanar with the upper surface of the upper hard mask material 4518 of the contact plug 4514B, as depicted. In one embodiment, although not depicted, a thin oxide layer such as a thermally or chemically oxidized silicon or silicon dioxide layer is present between the fin 4502A and the gate dielectric layer 4526.

[0461] Refer again Figure 45A and 45BIn an embodiment, the integrated circuit structure 4500 includes a plurality of fins 4502, such as a plurality of silicon fins. Each of the plurality of fins 4502 is along a first direction 4504. A plurality of gate structures 4506 are on the plurality of fins 4502. Each of the plurality of gate structures 4506 is along a second direction 4508 orthogonal to the first direction 4504. Each of the plurality of gate structures 4506 has a pair of dielectric sidewall spacers 4510. A trench contact structure 4512 is on a first fin 4502A of the plurality of fins 4502 and directly between the dielectric sidewall spacers 4510 of the pair of gate structures in the gate structure 4506. A contact plug 4514A is on a second fin 4502B of the plurality of fins 4502 and directly between the dielectric sidewall spacers 4510 of the pair of gate structures in the gate structure 4506. Similar to the cross-sectional view of contact plug 4514B, contact plug 4514A includes a lower dielectric material 4516 and an upper hard mask material 4518.

[0462] In an embodiment, the lower dielectric material 4516 of the contact plug 4516A comprises silicon and oxygen, such as silicon oxide or silicon dioxide. The upper hard mask material 4518 of the contact plug 4516A comprises silicon and nitrogen, such as silicon nitride, silicon-rich nitride, or silicon-poor nitride.

[0463] In one embodiment, the trench contact structure 4512 includes a lower conductive structure 4520 and a dielectric cap 4522 on the lower conductive structure 4520. In one embodiment, the dielectric cap 4522 of the trench contact structure 4512 has an upper surface that is coplanar with the upper surface of the upper hard mask material 4518 of the contact plug 4514A or 4514B, as depicted.

[0464] In an embodiment, each of the plurality of gate structures 4506 includes a gate electrode 4524 on a gate dielectric layer 4526. A dielectric cap 4528 is on the gate electrode 4524. In one embodiment, the dielectric cap 4528 of each of the plurality of gate structures 4506 has an upper surface coplanar with the upper surface of the upper hard mask material 4518 of the contact plugs 4514A or 4514B, as depicted. In an embodiment, although not depicted, a thin oxide layer such as a thermally or chemically oxidized silicon or silicon dioxide layer is present between the fin 4502A and the gate dielectric layer 4526.

[0465] One or more embodiments of this disclosure relate to a gate-aligned contact process. Such a process can be implemented to form a contact structure for use in semiconductor structure fabrication (e.g., for integrated circuit fabrication). In embodiments, a contact pattern is formed to align with an existing gate pattern. In contrast, other methods typically involve an additional photolithography process, in which selective contact etching is combined to tightly align the photolithographic contact pattern to an existing gate pattern. For example, another process may include patterning a polymer (gate) lattice, wherein the contacts and contact plugs are patterned separately.

[0466] According to one or more embodiments described herein, a contact formation method involves forming a contact pattern that is substantially perfectly aligned with an existing gate pattern while eliminating the use of photolithography operations with extremely tight registration budgets. In one such embodiment, the method enables the generation of contact openings using inherently highly selective wet etching (e.g., compared to dry etching or plasma etching). In embodiments, the contact pattern is formed by utilizing an existing gate pattern in conjunction with contact plug photolithography operations. In one such embodiment, the method enables the elimination of the need for critical photolithography operations that would otherwise be required to generate the contact pattern, as used in other methods. In embodiments, the trench contact grid is not patterned separately, but rather formed between aggregated (gate) lines. For example, in one such embodiment, the trench contact grid is formed after gate grid patterning but before gate grid dicing.

[0467] Figures 46A-46D Cross-sectional views illustrating various operations in a method of manufacturing an integrated circuit structure having trench contact plugs having hard mask material thereon, according to embodiments of the present disclosure.

[0468] refer to Figure 46A A method of manufacturing an integrated circuit structure includes forming a plurality of fins, each of the plurality of fins 4602 being along a first direction 4604. Each of the plurality of fins 4602 may include a diffusion region 4606. A plurality of gate structures 4608 are formed on the plurality of fins. Each of the plurality of gate structures 4608 is along a second direction 4610 orthogonal to the first direction 4604 (e.g., direction 4610 entering into and exiting the page). A sacrificial material structure 4612 is formed between a first pair of gate structures 4608. A contact plug 4614 is formed between a second pair of gate structures 4608. The contact plug includes a lower dielectric material 4616. A hard mask material 4618 is on the lower dielectric material 4616.

[0469] In an embodiment, the gate structure 4608 includes a sacrificial gate stack or a dummy gate stack and a dielectric spacer 4609. The sacrificial gate stack or dummy gate stack may be made of polysilicon or silicon nitride pillars or some other sacrificial material, which may be referred to as a gate dummy material.

[0470] refer to Figure 46B ,from Figure 46A The structure removes the sacrificial material structure 4612 to form an opening 4620 between the first pair of gate structures 4608.

[0471] refer to Figure 46C A trench contact structure 4622 is formed in the opening 4620 between the first pair of gate structures 4608. Additionally, in an embodiment, as part of forming the trench contact structure 4622, a trench contact structure 4622 is formed in the opening 4620 between the first pair of gate structures 4608. Figure 46A and 46B The hard mask 4618 is planarized. The final contact plug 4614' includes a lower dielectric material 4616 and an upper hard mask material 4624 formed from the hard mask material 4618.

[0472] In an embodiment, the lower dielectric material 4616 of each of the contact plugs 4614' comprises silicon and oxygen, and the upper hard mask material 4624 of each of the contact plugs 4614' comprises silicon and nitrogen. In an embodiment, each of the trench contact structures 4622 includes a lower conductive structure 4626 and a dielectric cap 4628 on the lower conductive structure 4626. In one embodiment, the dielectric cap 4628 of the trench contact structure 4622 has an upper surface coplanar with the upper surface of the upper hard mask material 4624 of the contact plug 4614'.

[0473] refer to Figure 46D In the alternative gate process, the sacrificial gate stack or dummy gate stack of the alternative gate structure 4608 is replaced. In such an approach, dummy gate materials such as polysilicon or silicon nitride pillar materials are removed and replaced with permanent gate electrode materials. In one such embodiment, a permanent gate dielectric layer is also formed during the process, as opposed to that carried out from earlier processes.

[0474] Therefore, the permanent gate structure 4630 includes a permanent gate dielectric layer 4632 and a permanent gate electrode layer or stack 4634. Additionally, in embodiments, the top portion of the permanent gate structure 4630 is removed, for example, by an etching process, and replaced with a dielectric cap 4636. In embodiments, the dielectric cap 4636 of each gate structure in the permanent gate structure 4630 has an upper surface coplanar with the upper surface of the upper hard mask material 4624 of the contact plug 4614'.

[0475] Refer again Figures 46A-46DIn one embodiment, a replacement gate process is performed after the trench contact structure 4622 is formed, as depicted. However, according to other embodiments, the replacement gate process is performed before the trench contact structure 4622 is formed.

[0476] In another aspect, a contact structure and process on the effective gate (COAG) are described. One or more embodiments of this disclosure relate to a semiconductor structure or device having one or more gate contact structures (e.g., as gate contact vias) disposed over an effective portion of the gate electrode of a semiconductor structure or device. One or more embodiments of this disclosure relate to a method of manufacturing a semiconductor structure or device having one or more gate contact structures formed over an effective portion of the gate electrode of a semiconductor structure or device. The methods described herein can be used to reduce the standard cell area by enabling gate contact formation over an effective gate region. In one or more embodiments, the gate contact structure manufactured for contacting the gate electrode is a self-aligned via structure.

[0477] In techniques where space and layout constraints are slightly relaxed compared to current-generation technologies, contacts to the gate structure can be fabricated by forming a contact portion that is part of the gate electrode deployed above the isolation region. As an example, Figure 47A A plan view of a semiconductor device having a gate contact disposed on an inactive portion of the gate electrode is shown.

[0478] refer to Figure 47A The semiconductor structure or device 4700A includes a diffused or active region 4704 disposed in a substrate 4702 and within an isolation region 4706. One or more gate lines (also called aggregate lines), such as gate lines 4708A, 4708B, and 4708C, are disposed over the diffused or active region 4704 and over a portion of the isolation region 4706. Source or drain contacts (also called trench contacts), such as contacts 4710A and 4710B, are disposed over the source and drain regions of the semiconductor structure or device 4700A. Trench contact vias 4712A and 4712B provide contacts to trench contacts 4710A and 4710B, respectively. A separate gate contact 4714 and a superimposed gate contact via 4716 provide contacts to gate line 4708B. Compared to the source or drain trench contacts 4710A or 4710B, from a plan view perspective, the gate contact 4714 is positioned above the isolation region 4706 but not above the diffusion or active region 4704. Furthermore, neither the gate contact 4714 nor the gate contact via 4716 is positioned between the source or drain trench contacts 4710A and 4710B.

[0479] Figure 47BA cross-sectional view of a non-planar semiconductor device having a gate contact disposed over an inactive portion of the gate electrode is illustrated. (Reference) Figure 47B Semiconductor structures or devices 4700B (e.g., Figure 47A The non-planar version of device 4700A includes a non-planar diffused or active region 4704C (e.g., a fin structure) formed from substrate 4702 and within isolation region 4706. A gate line 4708B is deployed over the non-planar diffused or active region 4704B and over a portion of isolation region 4706. As shown, gate line 4708B includes a gate electrode 4750 and a gate dielectric layer 4752 together with a dielectric capping layer 4754. From this view, gate contact 4714 and superimposed gate contact via 4716, as well as superimposed metal interconnect 4760, are also visible, all deployed within an interlayer dielectric stack or layer 4770. Also from... Figure 47B From the perspective of the viewpoint, the gate contact 4714 is deployed on the isolation region 4706 but not on the non-planar diffusion or active region 4704B.

[0480] Refer again Figure 47A and 47B The semiconductor structures or devices 4700A and 4700B are arranged with gate contacts placed over isolation regions. Such arrangements waste layout space. However, placing gate contacts over active regions would require extremely tight registration budgets, or the gate size would have to be increased to provide sufficient space for the gate contacts to land. Furthermore, historically, contacting the gate over diffusion regions has been avoided due to the risk of drilling through other gate materials (e.g., polysilicon) and contacting the underlying active regions. One or more embodiments described herein address these problems by providing a feasible method for fabricating contact structures that contact portions of the gate electrode formed over diffusion or active regions.

[0481] As an example, Figure 48A A plan view of a semiconductor device having a gate contact via disposed on an effective portion of a gate electrode, according to an embodiment of the present disclosure, is illustrated. Reference Figure 48AThe semiconductor structure or device 4800A includes a diffused or active region 4804 disposed in a substrate 4802 and within an isolation region 4806. One or more gate lines, such as gate lines 4808A, 4808B, and 4808C, are disposed over the diffused or active region 4804 and a portion of the isolation region 4806. Source or drain trench contacts, such as trench contacts 4810A and 4810B, are disposed over the source and drain regions of the semiconductor structure or device 4800A. Trench contact vias 4812A and 4812B provide contacts to trench contacts 4810A and 4810B, respectively. A gate contact via 4816 without an intervening separate gate contact layer provides a contact to gate line 4808B. Figure 47A In contrast, from the perspective of a plan view, the gate contact 4816 is deployed above the diffusion or active region 4804 and between the source or drain contacts 4810A and 4810B.

[0482] Figure 48B A cross-sectional view of a non-planar semiconductor device having a gate contact via disposed over an effective portion of the gate electrode, according to an embodiment of the present disclosure, is illustrated. Reference Figure 48B Semiconductor structures or devices 4800B (e.g., Figure 48A The non-planar version of device 4800A includes a non-planar diffused or active region 4804B (e.g., a fin structure) formed from substrate 4802 and within isolation region 4806. A gate line 4808B is deployed over the non-planar diffused or active region 4804B and over a portion of isolation region 4806. As shown, gate line 4808B includes a gate electrode 4850 and a gate dielectric layer 4852 together with a dielectric capping layer 4854. A gate contact via 4816 and a superimposed metal interconnect 4860 are also visible from this view, both deployed within an interlayer dielectric stack or layer 4870. Also from... Figure 48B From the perspective of the viewpoint, the gate contact via 4816 is deployed on the non-planar diffusion or active region 4804B.

[0483] Therefore, refer to again Figure 48A and 48B In this embodiment, trench contact vias 4812A and 4812B and gate contact via 4816 are formed in the same layer and are substantially coplanar. Figure 47A and 47B In contrast, the contact to the gate line will additionally include an additional gate contact layer, for example, whose orientation may be perpendicular to the corresponding gate line. However, in the connection... Figure 48A and 48BIn the described structures(s), structures 4800A and 4800B are fabricated such that contacts directly from the metal interconnect layer can land on the active gate portion without short-circuiting to adjacent source or drain regions. In embodiments, such an arrangement provides a significant area reduction in the circuit layout by eliminating the need to extend the transistor gate over the isolation to form a reliable contact. As used throughout, in embodiments, the reference to the active portion of the gate refers to the portion of the gate line or structure that is deployed above the active or diffused region of the underlying substrate (from a planar view). In embodiments, the reference to the inactive portion of the gate refers to the portion of the gate line or structure that is deployed above the isolation region of the underlying substrate (from a planar view).

[0484] In one embodiment, the semiconductor structure or device 4800 is a non-planar device, such as, but not limited to, a finned FET or a tri-gate device. In such an embodiment, the corresponding semiconductor channel region is constituted by and formed within a three-dimensional body. In one such embodiment, the gate electrode stacks of gate lines 4808A-4808C surround at least the top surface and a pair of sidewalls of the three-dimensional body. In another embodiment, at least the channel region is fabricated as a discrete three-dimensional body, such as in a gate-wound device. In one such embodiment, the gate electrode stacks of gate lines 4808A-4808C each completely surround the channel region.

[0485] More generally, one or more embodiments relate to a method for directly landing gate contact vias on the effective transistor gate and a structure formed by directly landing gate contact vias on the effective transistor gate. Such a method eliminates the need for extending gate lines over isolation for contact purposes. Such a method also eliminates the need for a gate contact (GCN) layer for guiding signals from the gate lines or structure. In embodiments, the elimination of these features is achieved by recessing the contact metal in the trench contact (TCN) and introducing an additional dielectric material (e.g., TILA) during the process. This additional dielectric material is included as a trench contact dielectric capping layer, having different etch characteristics than the gate dielectric material capping layer (e.g., GILA) already used for trench contact alignment in the gate alignment contact process (GAP) treatment.

[0486] As an example manufacturing solution Figures 49A-49D Cross-sectional views illustrating various operations in a method of manufacturing a semiconductor structure having a gate contact structure deployed on an effective portion of the gate, according to embodiments of the present disclosure.

[0487] refer to Figure 49AA semiconductor structure 4900 is provided after the trench contact (TCN) is formed. It should be understood that this particular arrangement of structure 4900 is for illustrative purposes only, and a wide variety of possible arrangements may benefit from embodiments of the disclosure described herein. Semiconductor structure 4900 includes one or more gate stack structures, such as gate stack structures 4908A-4908E deployed over substrate 4902. The gate stack structure may include a gate dielectric layer and a gate electrode. Trench contacts—such as contacts to a diffusion region of substrate 4902, such as trench contacts 4910A-4910C—are also included in structure 4900 and spaced apart from gate stack structures 4908A-4908E by dielectric spacers 4920. An insulating capping layer 4922 may be deployed on gate stack structures 4908A-4908E (e.g., GILA), as well as... Figure 49A As depicted in [the text]. As also [it is described in the text]. Figure 49A As depicted, contact-blocking regions or "contact plugs" made of interlayer dielectric material, such as region 4923, can be included in the regions where contact formation is to be prevented.

[0488] In one embodiment, providing structure 4900 involves forming a contact pattern that is substantially perfectly aligned with an existing gate pattern while eliminating the use of photolithography operations with extremely tight registration budgets. In one such embodiment, the method enables the generation of contact openings using inherently highly selective wet etching (e.g., compared to dry etching or plasma etching). In another embodiment, the contact pattern is formed by utilizing an existing gate pattern in conjunction with contact plug photolithography operations. In yet another embodiment, the method eliminates the need for critical photolithography operations that would otherwise be necessary to generate the contact pattern, as in other methods. In yet another embodiment, the trench contact grid is not patterned separately, but rather formed between the aggregated (gate) lines. For example, in one such embodiment, the trench contact grid is formed after gate grid patterning but before gate grid dicing.

[0489] Furthermore, gate stack structures 4908A-4908E can be fabricated using an alternative gate process. In such an approach, dummy gate materials, such as polysilicon or silicon nitride pillar materials, can be removed and replaced with permanent gate electrode materials. In one such embodiment, a permanent gate dielectric layer is also formed during the process, as opposed to that carried out from earlier processes. In embodiments, the dummy gate is removed by a dry etching or wet etching process. In one embodiment, the dummy gate is made of polysilicon or amorphous silicon and is removed using a dry etching process including SF6. In another embodiment, the dummy gate is made of polysilicon or amorphous silicon and is removed using a wet etching process including hydrated NH4OH or tetramethylammonium hydroxide. In one embodiment, the dummy gate is made of silicon nitride and is removed using a wet etching process including hydrated phosphoric acid.

[0490] In embodiments, one or more methods described herein essentially envision a combination of dummy gate and substituted gate processes with dummy contact and substituted contact processes to achieve structure 4900. In one such embodiment, a substituted contact process is performed after the substituted gate process to allow high-temperature annealing of at least a portion of the permanent gate stack. For example, in a particular such embodiment, annealing is performed on at least a portion of the permanent gate structure at a temperature greater than about 600 degrees Celsius, for example, after the formation of the gate dielectric layer. Annealing is performed before the formation of permanent contacts.

[0491] refer to Figure 49B Within the spacer 4920, the trench contacts 4910A-4910C of structure 4900 are recessed to provide recessed trench contacts 4911A-4911C, which have a height lower than the top surface of the spacer 4920 and the insulating capping layer 4922. An insulating capping layer 4924 (e.g., TILA) is then formed on the recessed trench contacts 4911A-4911C. According to embodiments of this disclosure, the insulating capping layer 4924 on the recessed trench contacts 4911A-4911C is made of a material having different etch characteristics than the insulating capping layer 4922 on the gate stack structures 4908A-4908E. As will be seen in subsequent processing operations, this difference can be used to selectively etch one of 4922 / 4924 from the other.

[0492] The trench contacts 4910A-4910C can be recessed through a selective process for the materials of the spacers 4920 and the insulating capping layer 4922. For example, in one embodiment, the trench contacts 4910A-4910C are recessed through an etching process such as a wet etching process or a dry etching process. The insulating capping layer 4924 can be formed through a process adapted to provide a conformal and sealing layer over the exposed portions of the trench contacts 4910A-4910C. For example, in one embodiment, the insulating capping layer 4924 is formed as a conformal layer over the entire structure through a chemical vapor deposition (CVD) process. The conformal layer is then planarized, for example, through chemical mechanical polishing (CMP), to provide the insulating capping layer 4924 material only over the trench contacts 4910A-4910C and the re-exposed spacers 4920 and the insulating capping layer 4922.

[0493] Regarding the suitable material composition for the insulating capping layers 4922 / 4924, in one embodiment, one of the pair 4922 / 4924 is composed of silicon oxide and the other of silicon nitride. In another embodiment, one of the pair 4922 / 4924 is composed of silicon oxide and the other of silicon carbide. In another embodiment, one of the pair 4922 / 4924 is composed of silicon oxide and the other of silicon carbide. In another embodiment, one of the pair 4922 / 4924 is composed of silicon nitride and the other of silicon carbide. In another embodiment, one of the pair 4922 / 4924 is composed of silicon nitride and the other of silicon carbide. In another embodiment, one of the pair 4922 / 4924 is composed of silicon carbide and the other of silicon carbide.

[0494] refer to Figure 49C The interlayer dielectric (ILD) 4930 and hard mask 4932 are stacked and patterned to provide, for example, in Figure 49B The patterned metal (0) groove 4934 above the structure.

[0495] The interlayer dielectric (ILD) 4930 can be constructed from a material suitable for electrically isolating the metallic features ultimately formed therein while maintaining a robust structure between the front-end and back-end processes. Furthermore, in embodiments, the configuration of ILD 4930 is selected to align with the via etching selectivity used for patterning the trench contact dielectric capping layer, as detailed below. Figure 49DAs described in more detail. In one embodiment, the ILD 4930 is composed of one or more layers of silicon oxide or one or more layers of carbon-doped oxide (CDO) material. However, in other embodiments, the ILD 4930 has a bilayer configuration, wherein the top portion is composed of a different material than the bottom portion below the ILD 4930. The hard mask layer 4932 may be composed of a material suitable for serving as a subsequent sacrificial layer. For example, in one embodiment, the hard mask layer 4932 is substantially composed of carbon, for example, as a cross-linked organic polymer layer. In other embodiments, silicon nitride or carbon-doped silicon nitride is used as the hard mask 4932. The stack of interlayer dielectric (ILD) 4930 and hard mask 4932 can be patterned by photolithography and etching processes.

[0496] refer to Figure 49D Through-hole openings 4936 (e.g., VCT) are formed in the interlayer dielectric (ILD) 4930, extending from the metal (0) trench 4934 to one or more of the recessed trench contacts 4911A-4911C. For example, in Figure 49D In this embodiment, via openings are formed to expose recessed trench contacts 4911A and 4911C. Forming via opening 4936 includes etching corresponding portions of interlayer dielectric (ILD) 4930 and corresponding insulating capping layer 4924. In one such embodiment, a portion of insulating capping layer 4922 is exposed during patterning of interlayer dielectric (ILD) 4930 (e.g., the portion of insulating capping layer 4922 above gate stack structures 4908B and 4908E). In this embodiment, insulating capping layer 4924 is selectively etched relative to insulating capping layer 4922 (i.e., without significantly etching or affecting insulating capping layer 4922) to form via opening 4936.

[0497] In one embodiment, the via opening pattern is ultimately transferred to the insulating cap 4924 (i.e., the trench contact insulating cap) via an etching process that does not etch the insulating cap 4922 (i.e., the gate insulating cap). The insulating cap 4924 (TILA) can be composed of any or a combination thereof, including: silicon oxide, silicon nitride, silicon carbide, carbon-doped silicon nitride, carbon-doped silicon oxide, amorphous silicon, various metal oxides and silicates, including zirconium oxide, hafnium oxide, lanthanum oxide, or combinations thereof. This layer can be deposited using any of the following techniques: CVD, ALD, PECVD, PVD, HDP, assisted CVD, and low-temperature CVD. Corresponding plasma dry etching has been developed as a combination of chemical and physical sputtering mechanisms. Simultaneous polymer deposition can be used to control material removal rate, etching profile, and film selectivity. Dry etching is typically performed using a gas mixture comprising NF3, CHF3, C4F8, HBr, and O2, usually at pressures ranging from 30 to 100 millitors and plasma biases of 50 to 1000 watts. Dry etching can be designed to achieve significant etch selectivity between the capping 4924 (TILA) and 4922 (GILA) layers to minimize the loss of the 4922 (GILA) layer during dry etching of the 4924 (TILA) layer used to form contacts to the source and drain regions of the transistor.

[0498] Refer again Figure 49D It is important to understand that a similar method can be used to create the via opening pattern that is ultimately transferred to the insulating cap 4922 (i.e., the trench contact insulating cap) by an etching process that does not etch the insulating cap 4924 (i.e., the gate insulating cap).

[0499] To further illustrate the concept of contact on effective gate (COAG) technology, Figure 50 A plan view and a corresponding cross-sectional view of an integrated circuit structure having trench contacts including superimposed insulating capping layers according to an embodiment of the present disclosure are illustrated.

[0500] refer to Figure 50 The integrated circuit structure 5000 includes a gate line 5004 above a semiconductor substrate or fin 5002, such as a silicon fin. The gate line 5004 includes a gate stack 5005 (e.g., including a gate dielectric layer or stack and a gate electrode on the gate dielectric layer or stack) and a gate insulating capping layer 5006 on the gate stack 5005. Dielectric spacers 5008 run along the sidewalls of the gate stack 5005, and in an embodiment, along the sidewalls of the gate insulating capping layer 5006, as depicted.

[0501] The trench contact portion 5010 is adjacent to the sidewall of the gate line 5004, wherein the dielectric spacer portion 5008 is between the gate line 5004 and the trench contact portion 5010. Each trench contact portion in the trench contact portion 5010 includes a conductive contact structure 5011 and a trench contact portion insulating capping layer 5012 on the conductive contact structure 5011.

[0502] Refer again Figure 50 A gate contact via 5014 is formed in the opening of the gate insulating capping layer 5006, and the gate contact via 5014 electrically contacts the gate stack 5005. In an embodiment, the gate contact via 5014 electrically contacts the gate stack 5005 at a location on the semiconductor substrate or fin 5002 and laterally between the trench contacts 5010, as depicted. In such an embodiment, the trench contact insulating capping layer 5012 on the conductive contact structure 5011 prevents gate-to-source or gate-to-drain short circuits through the gate contact via 5014.

[0503] Refer again Figure 50 A trench contact via 5016 is formed in the opening of the trench contact insulating capping layer 5012, and the trench contact via 5016 electrically contacts the corresponding conductive contact structure 5011. In an embodiment, the trench contact via 5016 electrically contacts the corresponding conductive contact structure 5011 at a location on the semiconductor substrate or fin 5002 and laterally adjacent to the gate stack 5005 of the gate line 5004, as depicted. In such an embodiment, the gate insulating capping layer 5006 on the gate stack 5005 prevents source-to-gate or drain-to-gate short circuits through the trench contact via 5016.

[0504] The key takeaway is that it is possible to create dissimilar structural relationships between the insulating gate capping layer and the insulating trench contact capping layer. As an example, Figures 51A-51F Cross-sectional views of various integrated circuit structures according to embodiments of the present disclosure are illustrated, each having a trench contact including a superimposed insulating capping layer and a gate stack including a superimposed insulating capping layer.

[0505] refer to Figure 51A , 51BLike 51C, integrated circuit structures 5100A, 5100B, and 5100C each include a fin 5102, such as a silicon fin. Although depicted in cross-sectional view, it is to be understood that the fin 5102 has a top 5102A and sidewalls (inside the page and outside the page of the view shown). First and second gate dielectric layers 5104 and 5106 are above the top 5102A of the fin 5102 and laterally adjacent to the sidewalls of the fin 5102. First and second gate electrodes 5108 and 5110 are above the first and second gate dielectric layers 5104 and 5106, respectively, which are above the top 5102A of the fin 5102 and laterally adjacent to the sidewalls of the fin 5102. The first and second gate electrodes 5108 and 5110 each include a conformal conductive layer 5109A, such as a work function setting layer, and a conductive filler material 5109B above the conformal conductive layer 5109A. Both the first and second gate electrodes 5108 and 5110 have a first side 5112 and a second side 5114 opposite to the first side 5112. The first and second gate electrodes 5108 and 5110 also each have an insulating cap 5116 having a top surface 5118.

[0506] The first dielectric spacer 5120 is adjacent to the first side 5112 of the first gate electrode 5108. The second dielectric spacer 5122 is adjacent to the second side 5114 of the second gate electrode 5110. The semiconductor source or drain region 5124 is adjacent to the first and second dielectric spacers 5120 and 5122. The trench contact structure 5126 is above the semiconductor source or drain region 5124 and adjacent to the first and second dielectric spacers 5120 and 5122.

[0507] The trench contact structure 5126 includes an insulating cap 5128 on the conductive structure 5130. The insulating cap 5128 of the trench contact structure 5126 has a top surface 5129 that is substantially coplanar with the top surface 5118 of the insulating caps 5116 of the first and second gate electrodes 5108 and 5110. In one embodiment, the insulating cap 5128 of the trench contact structure 5126 extends laterally into recesses 5132 in the first and second dielectric spacers 5120 and 5122. In such an embodiment, the insulating cap 5128 of the trench contact structure 5126 is suspended above the conductive structure 5130 of the trench contact structure 5126. However, in other embodiments, the insulating cap 5128 of the trench contact structure 5126 does not extend laterally into the recesses 5132 in the first and second dielectric spacers 5120 and 5122, and therefore is not suspended above the conductive structure 5130 of the trench contact structure 5126.

[0508] It is important to understand that the conductive structure 5130 of the trench contact structure 5126 does not have to be rectangular, such as... Figures 51A-51CAs depicted in the diagram. For example, the conductive structure 5130 of the trench contact structure 5126 can have a similar conductive structure to that used in... Figure 51A The cross-sectional geometry of the conductive structure 5130A illustrated in the projection, or the same cross-sectional geometry.

[0509] In one embodiment, the insulating cap 5128 of the trench contact structure 5126 has a different configuration than the insulating cap 5116 of the first and second gate electrodes 5108 and 5110. In one such embodiment, the insulating cap 5128 of the trench contact structure 5126 comprises a carbide material, such as silicon carbide. The insulating cap 5116 of the first and second gate electrodes 5108 and 5110 comprises a nitride material, such as silicon nitride.

[0510] In the embodiment, both the insulating caps 5116 of the first and second gate electrodes 5108 and 5110 have a bottom surface 5117A below the bottom surface 5128A of the insulating cap 5128 of the trench contact structure 5126, as shown. Figure 51A As depicted in the diagram. In another embodiment, the insulating caps 5116 of the first and second gate electrodes 5108 and 5110 both have a bottom surface 5117B that is substantially coplanar with the bottom surface 5128B of the insulating cap 5128 of the trench contact structure 5126, as shown in the diagram. Figure 51B As depicted in the diagram. In another embodiment, both the insulating caps 5116 of the first and second gate electrodes 5108 and 5110 have a bottom surface 5117C above the bottom surface 5128C of the insulating cap 5128 of the trench contact structure 5126, as shown in the diagram. Figure 51C As depicted in the text.

[0511] In one embodiment, the conductive structure 5130 of the trench contact structure 5128 includes a U-shaped metal layer 5134, a T-shaped metal layer 5136 over and above the entire U-shaped metal layer 5134, and a third metal layer 5138 on the T-shaped metal layer 5136. An insulating cap 5128 of the trench contact structure 5126 rests on the third metal layer 5138. In one such embodiment, the third metal layer 5138 and the U-shaped metal layer 5134 comprise titanium, and the T-shaped metal layer 5136 comprises cobalt. In a particular such embodiment, the T-shaped metal layer 5136 further comprises carbon.

[0512] In one embodiment, the metal silicide layer 5140 is directly between the conductive structure 5130 of the trench contact structure 5126 and the semiconductor source or drain region 5124. In one such embodiment, the metal silicide layer 5140 comprises titanium and silicon. In a particular such embodiment, the semiconductor source or drain region 5124 is an N-type semiconductor source or drain region. In another embodiment, the metal silicide layer 5140 comprises nickel, platinum, and silicon. In a particular such embodiment, the semiconductor source or drain region 5124 is a P-type semiconductor source or drain region. In yet another particular such embodiment, the metal silicide layer further comprises germanium.

[0513] In the embodiment, reference Figure 51D A conductive via 5150 is located on a portion of the first gate electrode 5108 above the top 5102A of the fin 5102 and is electrically connected to that portion. The conductive via 5150 is situated in an opening 5152 within the insulating cap 5116 of the first gate electrode 5108. In one such embodiment, the conductive via 5150 is located on a portion of the insulating cap 5128 of the trench contact structure 5126 but is not electrically connected to the conductive structure 5130 of the trench contact structure 5126. In a particular such embodiment, the conductive via 5150 is located in an eroded portion 5154 of the insulating cap 5128 of the trench contact structure 5126.

[0514] In the embodiment, reference Figure 51E A conductive via 5160 is located on a portion of the trench contact structure 5126 and is electrically connected to that portion. The conductive via is situated in an opening 5162 of the insulating cap 5128 of the trench contact structure 5126. In one such embodiment, the conductive via 5160 is located on a portion of the insulating cap 5116 of the first and second gate electrodes 5108 and 5110 but is not electrically connected to the first and second gate electrodes 5108 and 5110. In a particular such embodiment, the conductive via 5160 is located in an eroded portion 5164 of the insulating cap 5116 of the first and second gate electrodes 5108 and 5110.

[0515] Refer again Figure 51E In this embodiment, the conductive via 5160 is connected to... Figure 51D A second conductive via with the same structure as the conductive via 5150. In one such embodiment, such a second conductive via 5160 is isolated from the conductive via 5150. In another such embodiment, such a second conductive via 5160 is fused with the conductive via 5150 to form an electrically short-circuit contact 5170, such as... Figure 51F As depicted in the text.

[0516] The methods and structures described herein enable the fabrication of other structures or devices that are impossible or difficult to manufacture using other methods. In the first example, Figure 52A A plan view of another semiconductor device having a gate contact via disposed on an effective portion of the gate, according to another embodiment of the present disclosure, is illustrated. (See reference...) Figure 52A The semiconductor structure or device 5200 includes a plurality of gate structures 5208...

Claims

1. An integrated circuit structure, comprising: A silicon-containing fin having a top and sidewalls, wherein the top has the longest dimension along a first direction; A first isolation structure that separates a first end of a first portion of the fin from a first end of a second portion of the fin along a first direction, the first isolation structure having a width along the first direction, and the first end of the first portion of the fin having a surface roughness; A gate structure including a gate electrode on top of the first portion of the fin and laterally adjacent to the sidewall of a region of the first portion of the fin, wherein the gate structure has a width along a first direction, and wherein the center of the gate structure is spaced apart from the center of the first isolation structure by a pitch along the first direction. as well as A second isolation structure is provided above the second end of the first portion of the fin, the second end being opposite to the first end. The second isolation structure has the width along the first direction, and the second end of the first portion of the fin has a surface roughness smaller than that of the first end of the first portion of the fin. The center of the second isolation structure is spaced apart from the center of the gate structure by the pitch along the first direction.

2. The integrated circuit structure according to claim 1, wherein, The first end of the first portion of the fin has a serrated shape.

3. The integrated circuit structure according to claim 1, further comprising: A first epitaxial semiconductor region on the first portion of the fin, between the gate structure and the first isolation structure; as well as A second epitaxial semiconductor region on the first portion of the fin, between the gate structure and the second isolation structure.

4. The integrated circuit structure according to claim 3, wherein, The first and second epitaxial semiconductor regions have widths along a second direction orthogonal to the first direction, and the width along the second direction is wider than the width along the second direction of the first portion of the fin below the gate structure.

5. The integrated circuit structure according to claim 1, wherein the gate structure further includes a high-k dielectric layer between the gate electrode and the first portion of the fin and along the sidewall of the gate electrode.

6. An integrated circuit structure, comprising: A silicon-containing fin having a top and sidewalls, wherein the top has the longest dimension along one direction; A first isolation structure that separates a first end of a first portion of the fin from a first end of a second portion of the fin along the said direction, the first end of the first portion of the fin having a surface roughness and a depth; A gate structure including a gate electrode on top of the first part of the fin and laterally adjacent to the sidewall of a region of the first part of the fin; as well as A second isolation structure above the second end of the first portion of the fin, the second end being opposite to the first end, the second end of the first portion of the fin having a surface roughness less than that of the first end of the first portion of the fin, and the second end of the first portion of the fin having a depth different from that of the first end of the first portion of the fin.

7. The integrated circuit structure according to claim 6, wherein, The depth of the second end of the first portion of the fin is less than the depth of the first end of the first portion of the fin.

8. The integrated circuit structure according to claim 6, wherein, The depth of the second end of the first portion of the fin is greater than the depth of the first end of the first portion of the fin.

9. The integrated circuit structure of claim 6, wherein the first isolation structure has a width along the direction, wherein the gate structure has the width along the direction, and wherein the second isolation structure has the width along the direction.

10. The integrated circuit structure of claim 6, wherein the center of the gate structure is spaced apart from the center of the first isolation structure by a pitch along the direction, and wherein the center of the second isolation structure is spaced apart from the center of the gate structure by the pitch along the direction.

11. An integrated circuit structure, comprising: A first fin comprising silicon has a top and sidewalls, wherein the top has a longest dimension along a direction, and wherein an interruption along the direction separates a first end of a first portion of the first fin from a first end of a second portion of the fin, the first portion of the first fin having a second end opposite to the first end, the first end of the first portion of the fin having a surface roughness and a depth, and the second end of the first portion of the fin having a surface roughness smaller than the surface roughness of the first end of the first portion of the fin; A second fin comprising silicon, the second fin having a top and sidewalls, wherein the top has the longest dimension along the direction; as well as The residual fin portion between the first fin and the second fin has a top and sidewalls, wherein the top has the longest dimension along the direction, and the depth of the top is not coplanar with that of the first end of the first portion of the fin.

12. The integrated circuit structure according to claim 11, wherein, The depth of the first end of the first portion of the fin is lower than the top of the remaining fin portion.

13. The integrated circuit structure according to claim 12, wherein, The second end of the first portion of the fin has a depth coplanar with the depth of the first end of the first portion of the fin.

14. The integrated circuit structure according to claim 12, wherein, The second end of the first portion of the fin has a depth lower than the depth of the first end of the first portion of the fin.

15. The integrated circuit structure according to claim 12, wherein, The second end of the first portion of the fin has a depth higher than the depth of the first end of the first portion of the fin.

16. The integrated circuit structure according to claim 11, wherein, The depth of the first end of the first portion of the fin is higher than the top of the remaining fin portion.

17. The integrated circuit structure according to claim 16, wherein, The second end of the first portion of the fin has a depth coplanar with the depth of the first end of the first portion of the fin.

18. The integrated circuit structure according to claim 16, wherein, The second end of the first portion of the fin has a depth lower than the depth of the first end of the first portion of the fin.

19. The integrated circuit structure according to claim 16, wherein, The second end of the first portion of the fin has a depth higher than the depth of the first end of the first portion of the fin.

20. The integrated circuit structure according to claim 11, wherein, The second end of the first portion of the fin has a depth that is coplanar with the top of the residual fin portion.

21. The integrated circuit structure according to claim 11, wherein, The second end of the first portion of the fin has a depth lower than the top of the remaining fin portion.

22. The integrated circuit structure according to claim 11, wherein, The second end of the first portion of the fin has a depth higher than the top of the remaining fin portion.

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