Non-volatile memory using interconnect terminals with reduced pin count

Abstract

A first signal may be received from a memory device at a first interconnect terminal of the plurality of interconnect terminals via a serial communication interface, the first signal indicating that the memory device includes a NAND-type memory device. A determination may be made as to whether a second signal indicating that the NAND-type memory device is initialized has been received from the memory device at a second interconnect terminal of the plurality of interconnect terminals. In response to determining that a second signal indicating that the NAND-type memory device is initialized has been received from the memory device, an operation associated with the NAND-type memory device may be performed at the second interconnect terminal and the third interconnect terminal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0001] Figure 1A A processing system having a NAND memory controller for controlling a NAND type memory device through a serial communication interface is shown according to an embodiment of the present disclosure.

[0002] Figure 1B is a block diagram of components having multiple transceivers that may be used within a serial communication interface to communicate with a NAND memory device in accordance with an embodiment of the present disclosure.

[0003] Figure 2 An example of initializing a NAND type memory device having a reduced number of interconnection terminals according to an embodiment of the present disclosure is shown.

[0004] Figure 3 An example of performing a read operation on a NAND-type memory device having a reduced number of interconnect terminals according to some embodiments of the present disclosure is shown.

[0005] Figure 4 An example of performing a write operation on a NAND memory cell of a NAND-type memory device having a reduced number of interconnection terminals according to an embodiment of the present disclosure is shown.

[0006] Figure 5 is a flow chart of an example method of performing operations on a NAND-type memory device having a reduced number of interconnect terminals according to an embodiment of the present disclosure.

[0007] Figure 6 is a flowchart of an example method for performing an operation on a determined NAND device based on a received signal according to another embodiment of the present disclosure.

[0008] Figure 7 A system on chip (SOC) design having a NAND memory controller with serial interface logic according to one embodiment is shown.

[0009] Figure 8 A block diagram of a computing system having a NAND memory controller with serial interface logic is shown in accordance with certain embodiments. DETAILED DESCRIPTION

[0010] Embodiments described herein relate to a NAND-type non-volatile memory (NVM) controller that communicates with a NVM (e.g., flash memory) via a serial interface. Flash memory is an electronic non-volatile computer storage medium that can be electrically erased and reprogrammed. The flash memory can be a NAND-type or NOR-type flash memory. Embodiments described herein relate to a NAND memory controller having a serial interface logic that communicates with a NAND flash memory via a serial interface. The NAND flash memory can be coupled to a processing device via a serial peripheral interface (SPI) bus, which includes a hardware logic circuit coupled to the processing device and a plurality of interconnection terminals of the flash memory. The SPI bus can operate using a master-slave architecture, in which a single master device has ownership of the SPI bus, allowing the master device to drive the SPI bus. A signal of data can be provided between a processing device and the flash memory via the interconnection terminals of the SPI bus. The signal can be driven to a high value (e.g., a value of 1) or a low value (e.g., a value of 0) to represent a single bit of data. The signal can switch between a high value and a low value over time to represent a sequence of bits corresponding to data transmitted by a processing device and / or a flash memory.

[0011] As mentioned above, one type of flash memory is NOR flash memory. In a NOR flash memory device, one end of each cell of the memory device is connected to a ground line, and the other end is connected to a bit line to form a storage transistor. The NOR flash memory device can be coupled to the SPI bus via multiple interconnect terminals. For example, the NOR flash memory can be coupled to the SPI via 5 interconnect terminals. However, for a given capacity, NOR flash memory has a relatively large chip area, making the memory per bit of NOR flash memory less cost-effective than other types of memory. In addition, as new platforms increase the amount of data to be stored in the flash memory of the system, the larger chip area per bit of NOR flash memory may become a design constraint.

[0012] Another type of flash memory is NAND flash memory. In a NAND-type memory device, several storage transistors are connected in series instead of the single storage transistor configuration of NOR flash memory. This results in a NAND-type memory device having a smaller chip area per bit of memory than NOR flash memory. However, the configuration of the NAND-type memory device makes the operations performed by the NAND-type memory device more complicated than NOR flash memory, which previously increased the number of interconnection terminals coupled to the NAND-type memory device for driving operations associated with the NAND-type memory device. Existing solutions using NAND-type memory devices may have a greater number of interconnection terminals than NOR flash memory. For example, a NAND-type memory device may have up to 32 interconnection terminals compared to NOR flash memory, which may have 5 interconnection terminals. The increased number of interconnection terminals used to drive the NAND-type memory device may make the integration of the NAND flash memory into the processing device cumbersome and inefficient. For example, all flash memory access operations of the processing device may have to be rewritten to support operations performed on a NAND-type memory device including a greater number of interconnection terminals, which is cumbersome, time-consuming and error-prone.

[0013] As disclosed herein, the devices, systems and methods provide a system including a NAND-type memory device having a reduced number of interconnection terminals. The reduced number of interconnection terminals can permit the use of NAND-type memory devices in systems previously configured to NOR flash memory without changing the hardware (e.g., SPI bus) or flash memory access operations of the system. NAND-type memory devices with a reduced number of interconnection terminals can increase the amount of data storage available on the flash memory of the system without increasing the chip area of ​​the flash memory, thereby improving the performance of the system. In addition, NAND-type memory devices with a reduced number of interconnection terminals can reduce the number of flash memory access operations that need to be rewritten to support the NAND-type memory device, thereby further improving the performance of the system. As described above, an embodiment of a NVM controller having serial interface logic is also described herein, which operates with a NAND-type memory device through a serial interface for various memory operations, as described herein.

[0014] In one embodiment, a processing device of the system can be coupled to a NAND-type memory device via an SPI bus having five interconnection terminals. A first interconnection terminal of the SPI bus can send a signal from the NAND-type memory device to the processing device, the signal indicating that the memory device is a NAND-type memory device. For example, when the memory device is a NAND-type memory device, the NAND-type memory device can drive the signal on the first terminal to a high value (e.g., a value of 1). The processing device can then receive a signal with a high value, indicating that the memory device includes a NAND-type memory device. Alternatively, the processing device can receive a signal with a low value, indicating that the memory device does not include a NAND-type memory device.

[0015] After receiving the signal indicating that the memory device is a NAND-type memory device, the processing device may monitor the second signal on the second interconnect terminal of the SPI bus to determine whether the NAND-type memory device has been initialized. The NAND-type memory device may have an initial delay (up to 1 millisecond) before initialization. Therefore, any instructions provided to the NAND-type memory device before initialization may not be received by the NAND-type memory device. While monitoring the second signal, the processing device may determine that the NAND-type memory device is initialized. For example, once the NAND-type memory device has been initialized, the NAND-type memory device may drive the second signal to a high value, indicating that the NAND-type memory device is initialized. Alternatively, the second signal having a low value may indicate that the NAND-type memory device is not initialized.

[0016] Once the second signal has been sent by the NAND-type memory device to the processing device at the second interconnect terminal, the second interconnect terminal can be used as an input / output (IO) terminal for transmitting data between the processing device and the NAND-type memory device. For example, after the NAND-type memory device drives the second signal on the second interconnect terminal to a value of 1 to indicate that the NAND-type memory device is initialized, the second interconnect terminal can be used to send a signal including a low value (e.g., a value of 0) and a high value (e.g., a value of 1), the low value and the high value corresponding to data associated with the operation. After the processing device determines that the NAND-type memory device is initialized, the processing device can perform operations associated with the NAND-type memory device at the second interconnect terminal and the third interconnect terminal of the SPI bus.

[0017] Figure 1AA processing system 100 with a NAND memory controller 115 is shown according to an embodiment of the present disclosure, and the NAND memory controller 115 is used to control a NAND-type memory device 125 through a serial communication interface 112. The processing system 100 may generally be referred to as a "processor" or "CPU". The "processor" or "CPU" here should refer to a device capable of executing instructions that encode arithmetic, logic, or I / O operations. In an illustrative example, the processor may include an arithmetic logic unit (ALU), a control unit, and a plurality of registers. On the other hand, the processor may include one or more processing cores, and thus may be a single-core processor that is generally capable of processing a single instruction pipeline, or a multi-core processor that can process multiple instruction pipelines simultaneously. On the other hand, the processor may be implemented as a single integrated circuit, two or more integrated circuits, or may be a component of a multi-chip module (e.g., where each microprocessor die is included in a single integrated circuit package and therefore shares a single socket).

[0018] like Figure 1A As shown, a processing system (hereinafter referred to as "system") 100 may include various components. In one embodiment, the processing system 100 may include one or more processing cores 102, which are coupled to a processor bus 104, which transmits data signals between the processing cores 102 and other components in the system 100.

[0019] Processing core 102 can execute instructions of processing system 100. Processing core includes but is not limited to pre-fetch logic for obtaining instructions, decoding logic for decoding instructions, execution logic for executing instructions, etc. Processing core 102 can be used with a computing system on a single integrated circuit (IC) chip of a computing system. One embodiment of a computing system on a chip may include a processor and a memory. The memory of one such system is flash memory. The flash memory can be located on the same chip as the processor and other system components. In addition, other logic blocks such as a memory controller or a graphics controller can also be located on the system on a chip. Instructions can include but are not limited to pre-fetch logic for obtaining instructions, decoding logic for decoding instructions, execution logic for executing instructions, etc. In one embodiment, the sample computing system can execute a version of an operating system, embedded software, and / or a graphical user interface. Therefore, the embodiments of the present disclosure are not limited to any specific combination of hardware circuits and software.

[0020] The system 100 also includes a system logic chip 110 coupled to the processor bus 104 and a platform system memory (hereinafter referred to as "memory") 120 such as a random access memory (SRAM) or a dynamic random access memory (DRAM). The system 100 also includes a NAND memory 125 for persistent storage of data. The system logic chip 110 in the illustrated embodiment is a platform controller hub (PCH) 110. The PCH 110 may include a NAND memory controller 115, which includes serial interface logic for managing the transmission and reception of data from the NAND memory 125 via a serial communication interface (e.g., SPI bus 112). The PCH 110 may communicate with the NAND memory 125 via the SPI bus 112. The processing core 102 may communicate with the PCH 110 via the processor bus 104. In one embodiment, the processing core 102 may include a clock generation circuit 106 for generating a timing signal to be provided to a memory device (e.g., memory 120) via the PCH 110. In some embodiments, the PCH 110 may be coupled to a NAND-type memory device 125 via an SPI bus 112. In other embodiments, the PCH 110 may be coupled to a plurality of memory agents 130a-130n via an inter-processor communication channel such as a peripheral controller interconnect (PCI) bus 106. As described above, the PCI bus is a parallel synchronous computer bus used to connect physical devices, which may be in the form of integrated circuits suitable for mounting on the motherboard itself (referred to as planar devices in the PCI specification) or in the form of expansion cards suitable for mounting in slots on the motherboard. Examples of PCI cards used in personal computers and servers include: network cards, sound cards, modems, USB ports, TV tuner cards, and disk controllers.

[0021] Figure 1B 1 is a block diagram of an assembly 152 having multiple transceiver pairs 150 that may be used within a serial communication interface to communicate with a NAND memory device 162 according to an embodiment of the present disclosure. The assembly 152 includes a hardware state machine 156, multiple transceivers 154, a sample and hold circuit 158, and a data buffer 160.

[0022] The transceiver 150 may be coupled to lines 184, 186, 188, 190, and 192 at a plurality of interconnect terminals 174, 176, 178, 180, and 182, respectively. The NAND memory device 162 includes a plurality of transceivers 164, which are similarly connected to the lines 184, 186, 188, 190, and 192, respectively. The transceivers 154 and 164 coupled via the transmission lines (184-192) constitute a serial interface. In one embodiment, the serial interface may be Figure 1A SPI bus 112.

[0023] The hardware state machine 156 can switch between states based on signals received through the line, as described in more detail below. The data sent or received at the component 152 can be stored in the data buffer 160. The data received from the NAND memory device 162 at the component 152 can be sampled by the sampling and holding circuit 158. The sampling and holding circuit 158 ​​and the data buffer 160 can be implemented in various configurations to receive, buffer, and convert the data received through the serial interface to a parallel format from a serial format. For example, the data buffer 160 can be a shift register that shifts each bit and outputs a digital value when the shift register has shifted a certain number of bits. Similarly, the data received or sent from the component 152 at the NAND memory device 162 can be sampled by the sampling and holding circuit 168. The sampling and holding circuit 168 and the data buffer 170 can be implemented in various configurations to receive, buffer, and convert the data received from the component 152 through the serial interface from a parallel format.

[0024] The signals transmitted and received via the lines 184, 186, 188, 190, 192 will be discussed in more detail below. In the illustrated embodiment, the transceiver at the component 152 and the transceiver at the NAND memory device 162 can be considered as a transceiver pair. Each of the transceiver pairs can include a pair of one of the transceivers 154a-154e and one of the transceivers 164a-164e for each of the lines 184, 186, 188, 190, 192. Thus, the component 152 can include transmission logic for transmitting data to the NAND memory device 162 and reception logic for receiving data from the NAND memory device 162.

[0025] In one embodiment, component 152 may correspond to Figure 1A The NAND memory controller 115 of the PCH 110 is a part of the PCH 110. Alternatively, the component 152 can be a stand-alone NAND memory controller. In other embodiments, the component 152 can be integrated into other circuits of a processor, a system on a chip (SoC), or other integrated circuits.

[0026] Return to reference Figure 1B , the NAND memory device 162 may include transmission logic for transmitting data to the component 152 (e.g., a NAND memory controller) and reception logic for receiving data from the component 152. In one embodiment, the NAND memory device 162 may correspond to Figure 1ANAND memory device 125. Although the present embodiment shows a transceiver pair for each of lines 184-192, in other embodiments, alternative configurations of transceiver pairs may be used. For example, a first transceiver pair may be coupled to lines 184, 186, while a second transceiver pair may be coupled to lines 188, 190, 192. It should also be noted that component 152 may include one or more transmitters and one or more receivers as separate circuits that may be switched or multiplexed to share lines 184-192.

[0027] Component 152 and / or NAND memory device 162 may also include a hardware state machine 156 to monitor signals on lines 184, 186, 188, 190, 192 and control Figure 1B 162. The component 152 and / or the NAND memory device 162 may include a sample and hold circuit 158, 168 for measuring a signal received on lines 184, 186, 188, 190, 192 at a particular point in time. For example, the high and low values ​​of the signal may represent a series of bits. The sample and hold circuit 158, 168 may generate a digital output value based on the series of bits. The component 152 and / or the NAND memory device 162 may include a data buffer 160, 170 for storing the output of the sample and hold circuit 158, 168. The device 162 may also include a plurality of NAND memory cells 172a-n to store data associated with the data signal received via lines 190, 192.

[0028] Figure 2 An example of initializing a NAND type memory device 200 with a reduced number of interconnect terminals according to an embodiment of the present disclosure is shown. The diagram includes lines 184, 186, 188, 190, 192, which can be connected to the SPI bus via Figure 1B The plurality of interconnected terminals 174, 176, 178, 180, 182 of the processor 184 correspond to signals transmitted between the processor 184 and the NAND-type memory device. In some embodiments, the transmitted signal may be a control signal. In other embodiments, the signal may be a data signal. Line 184 may correspond to a NAND enable pin strip. The NAND enable pin strip may send a signal from the memory device to the processor 184, indicating that the memory device comprises a NAND-type memory device. For example, the NAND-type memory device may drive the signal on the NAND enable pin strip to a high value (e.g., a value of 1), indicating that the memory device comprises a NAND-type memory device. The processor 184 may then receive a signal on the NAND enable pin strip indicating that the memory device comprises a NAND-type memory device.

[0029] Line 186 may correspond to Figure 1AThe timing signal generated by the clock generation circuit 106 of the processing device 100 may be driven alternately between a high value (e.g., a value of 1) and a low value (e.g., a value of 0) on the clock generation circuit 106, which is provided to the NAND-type memory device at line 186 via the SPI bus. Line 188 may correspond to a chip select line, which is used as a control line to select a chip (e.g., a NAND-type memory device) connected to the SPI bus. In one embodiment, when the processing device is not performing an operation associated with the NAND-type memory device, the processing device may drive the signal on the chip select line to a high value. Alternatively, when the processing device is performing an operation associated with the NAND-type memory device, the processing device may drive the signal on the chip select line to a low value.

[0030] Line 190 may correspond to an input / output line (e.g., IO1). In some embodiments, once the NAND memory device is initialized, the NAND memory device may drive the signal on line 190 to a high value for a period of time. After the processing device has received a signal indicating that the NAND memory is initialized, line 190 may transmit a data signal between the NAND memory device and the processing device. Line 192 may correspond to other input / output lines (e.g., other IOs). Other IOs may transmit data signals between the NAND memory device and the processing device. Although other IOs are shown as single lines (e.g., line 192), in other embodiments, other IOs may include multiple lines. For example, in the current illustration, the NAND memory device may operate in a single IO mode and have 2 IO lines (e.g., lines 190 and 192) for sending data signals, resulting in a total of 5 interconnection lines. However, in another embodiment, the NAND memory device may operate in a quad IO mode and have 4 IO lines for transmitting data signals, resulting in a total of 7 lines coupled to 7 interconnection terminals.

[0031] Operations to initialize a NAND-type memory device may begin at 202, where the NAND-type memory device drives a signal on line 184 (e.g., a NAND enable pin strip) to a high value. The signal on line 184 may indicate to the processing device that the memory device is a NAND-type memory device. Upon receiving a signal on line 184 indicating that the memory device is a NAND-type memory device, the processing device may begin monitoring a signal on line 190 (e.g., IO1) to determine whether the NAND-type memory device is initialized. At 204, after the NAND-type memory device has been initialized, the NAND-type memory device may drive the signal on line 190 to a high value for a period of time. In some embodiments, after the NAND-type memory device has driven the signal to a high value for a period of time, it may drive the signal back to a low value.

[0032] At 206, after receiving a signal on line 190 from the NAND-type memory device indicating that the NAND-type memory device is initialized, the processing device may drive a signal on line 188 (e.g., chip select) to a low value to indicate that the processing device is performing an operation associated with the NAND-type memory device. Subsequently, at 208, the processing device may send an instruction to the NAND-type memory device to perform the operation. In one embodiment, the operation may correspond to a read operation, and the NAND-type memory device may send data signals corresponding to data stored on the NAND-type memory device to the processing device at lines 190 and 192. In another embodiment, the operation may correspond to a write operation, and the processing device may send a data signal corresponding to data to be stored on the NAND-type memory device. Further details regarding read operations and write operations will be discussed in more detail below.

[0033] Figure 3 An example of performing a read operation 300 on a NAND-type memory device having a reduced number of interconnect terminals according to some embodiments of the present disclosure is shown. Figure 2 After the initialization operations discussed in Figure 1B A read control signal 302 indicating that a read operation is to be performed is sent to the NAND type memory device via the SPI bus at terminals 180 and 182 of the NAND type memory. The read control signal 302 may also indicate specific data stored on the NAND type memory device to be provided by the read operation. In some embodiments, once the read control signal 302 is provided to the NAND type memory device, the NAND type memory device may be controlled by the SPI bus at 304. Figure 1B The hardware state machine 156 transfers ownership of the SPI bus from the processing device to the NAND-type memory device (block 2).

[0034] After the NAND-type memory device has received the read control signal 302, there may be a waiting period 306 as the NAND-type memory device identifies data associated with the read operation stored on the NAND-type memory device and prepares the data to be sent to the processing device. During the waiting period 306, the NAND-type memory device may drive the signal on line 190 to a low value to indicate that the NAND-type memory device is not ready to provide the data associated with the read operation to the processing device. Once the NAND-type memory device identifies the data associated with the read operation, at 308 the NAND-type memory device may drive the signal on line 190 to a high value for a period of time to provide a second read control signal indicating that the NAND-type memory device is ready to provide the data to the processing device. After driving the signal on line 190 to a high value, the NAND-type memory device may send a data signal 310 corresponding to the data associated with the read operation to the processing device at terminals 190 and 192. After providing the data to the processing device, the NAND-type memory device may drive the signal on line 190 to a low value to indicate that the NAND-type memory device is no longer initialized. The processing device may then drive the signal on line 188 to a high value at 312, indicating that the processing device is not performing operations associated with the NAND-type memory device. Once the NAND-type memory device is subsequently initialized and ready to perform subsequent operations, the NAND-type memory device may drive the signal on line 190 to a high value to indicate that the NAND-type memory device is initialized and can perform subsequent operations.

[0035] Figure 4 An example of performing a write operation 400 on a NAND-type memory device having a reduced number of interconnect terminals according to an embodiment of the present disclosure is shown. Figure 2 After the initialization operation discussed in Figure 1B The write control signal 402 indicating that a write operation is to be performed is sent to the NAND type memory device at the terminals 180 and 182 of the NAND type memory device. In some embodiments, once the write control signal 402 is provided to the NAND type memory device, the NAND type memory device can be controlled by the controller 404. Figure 1B The hardware state machine 156 transfers ownership of the SPI bus from the processing device to the NAND-type memory device (block 2).

[0036] After the NAND-type memory device has received the write operation command, there may be a wait period 406 until the NAND-type memory device is ready to receive data associated with the write operation. During the wait period 406, the NAND-type memory device may drive the signal on line 190 to a low value to indicate that the NAND-type memory device is not ready to receive data associated with the write operation. Once the NAND-type memory device is ready to receive data associated with the write operation, the NAND-type memory device may drive the signal on line 190 to a high value for a period of time at 408 to provide a second write control signal indicating that the NAND-type memory device is ready to receive data from the processing device. After the NAND-type memory device drives the signal on line 190 to a high value, the processing device may Figure 1B The processing device may then drive the signal on line 188 to a high value at 412 to indicate that the processing device is no longer performing operations associated with the NAND-type memory device. Once the NAND-type memory device is subsequently initialized and ready to perform subsequent operations, the NAND-type memory device may drive the signal on line 190 to a high value to indicate that the NAND-type memory device is initialized and can perform subsequent operations.

[0037] Figure 5 is a flow chart of an example method 500 for performing operations on a NAND-type memory device having a reduced number of interconnect terminals. The method 500 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 500 may be performed by Figure 1A The PCH 110 is executed by the NAND memory controller 115 .

[0038] The method 500 may begin by a processing device receiving a first signal from a memory device at a first interconnect terminal of a plurality of interconnect terminals via a serial communication interface (block 510), the first signal indicating that the memory device comprises a NAND-type memory device. Figure 2The signal on line 1 of may be driven high to indicate that the memory device comprises a NAND-type memory device and received by the processing device via the SPI bus at terminal 174. After receiving the signal indicating that the memory device comprises a NAND-type memory device, the processing device may determine whether a second signal indicating that the NAND-type memory device has been initialized has been received from the memory device at the second interconnect terminal (block 520). For example, the memory device may Figure 2 The signal on line 190 of the processing device is driven high for a period of time to indicate that the NAND-type memory device is initialized. The processing device can then receive the signal on line 190 at 180. Once the processing device determines that a second signal has been received from the memory device indicating that the NAND-type memory device is initialized, the processing device can perform operations associated with the NAND-type memory device at the second interconnect terminal and the third interconnect terminal (block 530). For example, the processing device can perform operations associated with the NAND-type memory device at terminals 180 and 182.

[0039] In one embodiment, the operation may be as follows Figure 3 In another embodiment, the operation may be as follows: Figure 4 In some embodiments, once the NAND-type memory device is initialized, the processing device may queue multiple operations for sequential execution. For example, before the initialization of the NAND-type memory device, 2 read operations and 1 write operation may be queued. Therefore, after the NAND-type memory device is initialized, 2 read operations and 1 write operation may be performed in sequence. In other embodiments, the processing device may receive a signal at the second interconnect terminal indicating that an operation associated with the NAND-type memory device has been performed. For example, after the NAND-type memory device completes a write operation, the NAND-type memory device may send a signal on line 4 indicating that the write operation has been completed to the processing device.

[0040] Figure 6 is a flow chart of an example method 600 for performing an operation on a determined NAND device based on a received signal. The method 600 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 600 may be performed by Figure 1A The PCH 110 is executed by the NAND memory controller 115 .

[0041] Method 600 may begin by a processing device receiving a first signal at a first interconnect terminal (block 610). For example, the processing device may Figure 1BThe processing device may determine that the memory device comprises a NAND-type memory device based on the first signal. For example, if the signal received on line 184 has a high value, the processing device may determine that the memory device comprises a NAND-type memory device. The processing device may receive a second signal at a second interconnect terminal (block 630). For example, the processing device may determine that the memory device comprises a NAND-type memory device. Figure 1B Upon receiving the second signal, the processing device may determine based on the second signal that the NAND-type memory device is initialized (block 640). For example, the memory device may Figure 2 The signal on line 190 of the NAND type memory device is driven high for a period of time to indicate that the NAND type memory device is initialized. Once the processing device determines that the NAND type memory device is initialized, the processing device may perform operations associated with the NAND type memory device at the second interconnect terminal and the third interconnect terminal (block 650). For example, the processing device may Figure 1B Operations associated with NAND type memory devices are performed at terminals 180 and 182 of the memory. In one embodiment, the operations may be as follows: Figure 3 In another embodiment, the operation may be as follows: Figure 4 The write operations discussed in .

[0042] Figure 7 A computer system 700 with multiple interconnects is shown according to one embodiment. The system 700 includes a processor 705 and a system memory 710 coupled to a controller hub 715. The processor 705 includes any processing element, such as a microprocessor, a main processor, an embedded processor, a coprocessor, or other processor. The processor 705 is coupled to the controller hub 715 via a front side bus (FSB) 706. In one embodiment, the FSB 706 is a serial point-to-point interconnect as described below. In another embodiment, the FSB 706 (e.g., a link) includes a serial differential interconnect architecture that conforms to different interconnect standards. In one embodiment, the controller hub 715 may include Figure 1A NAND memory controller 115.

[0043] System memory 710 includes any memory device, such as random access memory (RAM), non-volatile (NV) memory, or other memory accessible to devices in system 700. System memory 710 is coupled to controller hub 715 through memory interface 716. Examples of memory interfaces include double data rate (DDR) memory interfaces, dual channel DDR memory interfaces, and dynamic RAM (DRAM) memory interfaces.

[0044] In one embodiment, controller hub 715 is a root hub, root complex or root controller. Examples of controller hub 715 include chipsets, memory controller hubs (MCH), north bridges, interconnect controller hubs (ICH), south bridges and root controllers / hubs. Typically, the term chipset refers to two physically separate controller hubs, i.e., a memory controller hub (MCH) coupled to an interconnect controller hub (ICH). Note that current systems typically include an MCH integrated with processor 705, and controller 715 communicates with I / O devices in a similar manner to that described below. In some embodiments, peer-to-peer routing is optionally supported through a root complex (e.g., controller 715).

[0045] Here, controller hub 715 is coupled to switch / bridge 720 via serial link 719. Input / output modules 717 and 721 (also referred to as interfaces / ports 717 and 721) include / implement a layered protocol stack to provide communication between controller hub 715 and switch 720. In one embodiment, multiple devices can be coupled to switch 720.

[0046] The switch / bridge 720 routes packets / messages from the device 725 from upstream (i.e., upward hierarchically) toward the root complex to the controller hub 715 and from downstream, i.e., from hierarchically away from the root controller downward from the processor 705 or the system memory 710 to the device 725. In one embodiment, the switch 720 is referred to as a logical component of multiple virtual PCI to PCI bridge devices (bridge devices that communicate according to the PCI protocol). The device 725 includes any internal or external device or component to be coupled to the electronic system, such as I / O devices, network interface controllers (NICs), add-in cards, audio processors, network processors, hard drives, storage devices, CD / DVD ROMs, monitors, printers, mice, keyboards, routers, portable storage devices, FireWire devices, Universal Serial Bus (USB) devices, scanners, and other input / output devices. Typically in In the terminology, such devices are referred to as endpoints. Although not specifically shown, device 725 may include to PCI / PCI-X bridge to support devices communicating according to legacy protocols, PCI protocols, etc. Endpoint devices that communicate using the standard are generally classified as legacy devices, or Root Composite Integration Endpoint (RCiEP).

[0047] The graphics accelerator 730 is also coupled to the controller hub 715 via a serial link 732. In one embodiment, the graphics accelerator 730 is coupled to the MCH, which is coupled to the ICH. The switch 720, and therefore the I / O device 725, is then coupled to the ICH. The I / O modules 731 and 718 are also used to implement a layered protocol stack to communicate between the graphics accelerator 730 and the controller hub 715. Similar to the MCH discussion above, the graphics controller or graphics accelerator 730 itself can be integrated into the processor 705.

[0048] I / O device 725 includes interface 726, and switch / bridge 720 includes interface 722. Interface 726 is coupled to interface 722 via serial link 723.

[0049] In one embodiment, the WLAN unit and The unit's short-range wireless engine can be based on The protocol is coupled to the processor 705 via an interconnect, according to Protocols such as fast Specification Base Specification Version 4.0 (Base Specification Version 4.0 Version 0.3, published on February 19, 2014, etc.), or other such protocols, such as the Serial Data Input / Output (SDIO) standard. Of course, the actual physical connection between these peripheral devices, which may be configured on one or more add-in cards, may be through an NGFF connector suitable for the motherboard. Using the WLAN unit, it is possible to implement a protocol in accordance with the given Institute of Electrical and Electronics Engineers (IEEE) 802.11 standard Communication, through the use of Technical units can be In another embodiment, the units may communicate with the processor 705 via, for example, a USB link or a Universal Asynchronous Receiver Transmitter (UART) link.

[0050] Next turn Figure 8 , depicting an embodiment of a system on chip (SOC) design according to the present disclosure. As a specific illustrative example, the SOC 800 is included in a user equipment (UE). In one embodiment, a UE refers to any device that an end user wants to use to communicate, such as a handheld phone, a smart phone, a tablet, an ultra-thin notebook, a notebook with a broadband adapter, or any other similar communication device. A UE is often connected to a base station or node, which in essence may correspond to a mobile station (MS) in a GSM network.

[0051] Here, SOC 800 includes two cores - 806 and 807. Similar to the above discussion, cores 806 and 807 may conform to an instruction set architecture, such as based on Architecture Core TM , Advanced Micro Devices, Inc. (AMD) processors, MIPS-based processors, ARM-based processor designs, or their customers, and their licensees or adopters. Cores 806 and 807 are coupled to a cache controller 808, which is associated with a bus interface unit 809 and L2 cache 804 to communicate with other portions of system 800. Interconnect 810 includes an on-chip interconnect, such as IOSF, AMBA, or other interconnect, as described above, which potentially implements one or more aspects of the described disclosure.

[0052] The interface 810 provides a communication channel to other components, such as a subscriber identity module (SIM) 830 for interfacing with a SIM card, a boot ROM 835 for holding boot code for execution by the cores 806 and 807 to initialize and boot the SOC 800, an SDRAM controller 840 for interfacing with an external memory (e.g., DRAM 860), a flash controller 845 for interfacing with a non-volatile memory (e.g., flash 865), a peripheral controller 850 (e.g., a serial peripheral interface) for interfacing with peripheral devices, a video codec 820 and a video interface 825 for displaying and receiving input (e.g., touch-enabled input), a GPU 815 for performing graphics-related calculations, etc. In one embodiment, the flash controller 845 may include Figure 1A NAND memory controller 115. Any of these interfaces may incorporate aspects of the present disclosure described herein.

[0053] In addition, the system shows peripheral devices for communication, such as module 870, 3G modem 875, GPS 885 and 885. Note that, as mentioned above, the UE includes a radio for communication. As a result, these peripheral communication modules are not all necessary. However, in the UE, some form of radio for external communication will be included.

[0054] The following examples relate to other embodiments.

[0055] Example 1 is a processing device, comprising: a hardware logic circuit for implementing a hardware state machine; and a plurality of interconnect terminals coupled to the hardware logic circuit, the hardware logic circuit being used to: receive a first signal from a memory device via a first interconnect terminal among the plurality of interconnect terminals indicating that the memory device includes a NAND memory cell; determine whether a second signal has been received from the memory device via a second interconnect terminal among the plurality of interconnect terminals, the second signal indicating that the NAND memory cell is initialized; and in response to determining that the second signal indicating that the NAND memory cell is initialized has been received from the memory device, perform an operation associated with the NAND memory cell via a second interconnect terminal and a third interconnect terminal among the plurality of interconnect terminals.

[0056] In Example 2, the subject matter of Example 1 further includes: a clock generation circuit coupled to a fourth interconnect terminal among the plurality of interconnect terminals, the clock generation circuit being used to generate a timing signal to be provided to the memory device via the fourth interconnect terminal among the plurality of interconnect terminals.

[0057] In Example 3, the subject matter of any of Examples 1-2, wherein, to perform an operation associated with a NAND memory cell, the hardware logic circuit is used to: send an instruction corresponding to a read operation to the NAND memory cell via the second interconnect terminal and the third interconnect terminal; receive a third signal from the NAND memory cell via the second interconnect terminal, the third signal indicating that the NAND memory cell is ready to provide data associated with the read operation; and receive data associated with the read operation from the NAND memory cell via the second interconnect terminal and the third interconnect terminal.

[0058] In Example 4, the subject matter of any of Examples 1-3, wherein, to perform an operation associated with a NAND memory cell, the hardware logic circuit is used to: send an instruction corresponding to a write operation to the NAND memory cell via the second interconnect terminal and the third interconnect terminal; receive a third signal from the NAND memory cell via the second interconnect terminal, the third signal indicating that the NAND memory cell is ready to receive data associated with the write operation; and provide the data associated with the write operation to the NAND memory cell via the second interconnect terminal and the third interconnect terminal.

[0059] In Example 5, the subject matter of any of Examples 1-4 further includes a data buffer operably coupled to the plurality of interconnect terminals to store a bit sequence associated with the operation.

[0060] In Example 6, the subject matter of any of Examples 1-5, wherein the hardware logic circuit is further for: receiving a third signal from the memory device via a second interconnect terminal of the plurality of interconnect terminals indicating that the NAND memory cell is not initialized.

[0061] In Example 7, the subject matter of any of Examples 1-6, wherein the plurality of interconnect terminals is less than 7 interconnect terminals.

[0062] Example 8 is a system comprising: a processing device comprising a plurality of interconnect terminals; and a memory device comprising a NAND memory cell operably coupled to the processing device via the plurality of interconnect terminals, wherein the NAND memory cell sends a signal to the processing device via the plurality of interconnect terminals, the processing device being configured to: receive a first signal via a first interconnect terminal among the plurality of interconnect terminals; determine based on the first signal that the memory device comprises a NAND memory cell; receive a second signal via a second interconnect terminal among the plurality of interconnect terminals; determine based on the second signal that the NAND memory cell is initialized; and perform operations associated with the NAND memory cell via a second interconnect terminal and a third interconnect terminal among the plurality of interconnect terminals.

[0063] In Example 9, the subject matter of Example 8, wherein a second interconnect terminal of the plurality of interconnect terminals comprises a dual purpose input-output terminal.

[0064] In Example 10, the subject matter of any of Examples 8-9, wherein a third interconnect terminal of the plurality of interconnect terminals comprises an input-output terminal for providing or receiving a signal from the memory device.

[0065] In Example 11, the subject matter of any of Examples 8-10 further includes a hardware state machine to monitor signals sent from the memory device via the plurality of interconnect terminals.

[0066] In Example 12, the subject matter of any of Examples 8-11, wherein, to perform an operation associated with a NAND memory cell, the processing device is used to: send an instruction corresponding to a read operation to the NAND memory cell via the second interconnect terminal and the third interconnect terminal; receive a third signal from the NAND memory cell via the second interconnect terminal, the third signal indicating that the NAND memory cell is ready to provide data associated with the read operation; and receive data associated with the read operation from the NAND memory cell via the second interconnect terminal and the third interconnect terminal.

[0067] In Example 13, the subject matter of any of Examples 8-12, wherein, to perform an operation associated with a NAND memory cell, the processing device is used to: send an instruction corresponding to a write operation to the NAND memory cell via the second interconnect terminal and the third interconnect terminal; receive a third signal from the NAND memory cell via the second interconnect terminal, the third signal indicating that the NAND memory cell is ready to receive data associated with the write operation; and provide the data associated with the write operation to the NAND memory cell via the second interconnect terminal and the third interconnect terminal.

[0068] In Example 14, the subject matter of any one of Examples 8-13 further includes: a clock generation circuit coupled to a fourth interconnect terminal among the plurality of interconnect terminals, the clock generation circuit being used to generate a timing signal to be provided to the memory device via the fourth interconnect terminal among the plurality of interconnect terminals.

[0069] Example 15 is a method comprising: receiving a first signal from a memory device via a first interconnect terminal among a plurality of interconnect terminals indicating that the memory device includes a NAND memory cell; determining, by a processing device, whether a second signal has been received from the memory device via a second interconnect terminal among the plurality of interconnect terminals, the second signal indicating that the NAND memory cell is initialized; and in response to determining that the second signal indicating that the NAND memory cell is initialized has been received from the memory device, performing an operation associated with the NAND memory cell via a second interconnect terminal and a third interconnect terminal among the plurality of interconnect terminals.

[0070] In Example 16, the subject matter of Example 15, wherein performing an operation associated with the NAND memory cell includes: sending an instruction corresponding to a read operation to the NAND memory cell via the second interconnect terminal and the third interconnect terminal; receiving a third signal from the NAND memory cell via the second interconnect terminal, the third signal indicating that the NAND memory cell is ready to provide data associated with the read operation; and, receiving data associated with the read operation from the NAND memory cell via the second interconnect terminal and the third interconnect terminal.

[0071] In Example 17, the subject matter of any of Examples 15-16, wherein performing an operation associated with the NAND memory cell includes: sending an instruction corresponding to a write operation to the NAND memory cell via the second interconnect terminal and the third interconnect terminal; receiving a third signal from the NAND memory cell via the second interconnect terminal, the third signal indicating that the NAND memory cell is ready to receive data associated with the write operation; and, providing the data associated with the write operation to the NAND memory cell via the second interconnect terminal and the third interconnect terminal.

[0072] In Example 18, the subject matter of any of Examples 15-17 further includes receiving a third signal from the memory device via the second interconnect terminal, the third signal indicating that an operation associated with the NAND memory cell has been performed.

[0073] In Example 19, the subject matter of any of Examples 15-18 further includes receiving a third signal from the memory device via a second interconnect terminal of the plurality of interconnect terminals indicating that the NAND memory cell is not initialized.

[0074] In Example 20, the subject matter of any of Examples 15-19, wherein the plurality of interconnect terminals is less than 7 interconnect terminals.

[0075] Example 21 is an apparatus comprising means for performing the method as described in any one of Examples 15-20.

[0076] Example 22 is at least one machine-readable medium comprising a plurality of instructions, wherein the plurality of instructions are executed to implement a method or implement an apparatus as described in any one of Examples 15-20.

[0077] Example 23 is an apparatus comprising a unit for implementing the method as described in any of Examples 15-20.

[0078] Example 24 is an apparatus comprising a processor configured to perform the method as described in any of Examples 15-20.

[0079] Various embodiments may have different combinations of the above structural features. For example, all optional features of the above computing system may also be implemented with respect to the method or process described herein, and the details in the examples may be used anywhere in one or more embodiments.

[0080] While the present disclosure has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of the present disclosure.

[0081] In the description herein, many specific details are set forth, such as examples of specific types of processors and system configurations, specific hardware structures, specific architectural and microarchitectural details, specific register configurations, specific instruction types, specific system components, specific measurements / heights, specific processor pipeline stages and operations, etc., in order to provide a thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that these specific details need not be employed to implement the present disclosure. In other instances, well-known components or methods, such as specific and alternative processor architectures, specific logic circuits / code for the described algorithms, specific firmware code, specific interconnect operations, specific logic configurations, specific manufacturing techniques and materials, specific compiler implementations, specific expressions of algorithms in code, specific power-off and gating techniques / logic, and other specific operational details of computer systems are not described in detail in order to avoid unnecessarily obscuring the present disclosure.

[0082] Embodiments may be described with reference to timestamp verification of components in solid-state memory devices in a particular integrated circuit, such as in a computing platform or microprocessor. Embodiments may also be applicable to other types of integrated circuits and programmable logic devices. For example, the disclosed embodiments are not limited to desktop computer systems or portable computers, such as Ultrabooks TM Computers, and can also be used in other devices such as handheld devices, tablets, other thin notebooks, system-on-chip (SoC) devices, and embedded applications. Some examples of handheld devices include cellular phones, Internet protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications typically include microcontrollers, digital signal processors (DSPs), system-on-chips, network computers (NetPCs), set-top boxes, network hubs, wide area network (WAN) switches, or any other system that can perform the functions and operations described below. It is described that the system can be any type of computer or embedded system. The disclosed embodiments can be particularly useful for low-end devices such as wearable devices (e.g., watches), electronic implants, sensory and control infrastructure equipment, controllers, supervisory control and data acquisition (SCADA) systems, etc. In addition, the apparatus, methods, and systems described herein are not limited to physical computing devices, but can also involve software optimization for energy conservation and efficiency. As will become apparent in the following description, the embodiments of the methods, apparatuses, and systems described herein (whether with reference to hardware, firmware, software, or a combination thereof) are critical to the future of "green technology" balanced with performance considerations.

[0083] Although the embodiments of this document are described with reference to a processor, other embodiments are also applicable to other types of integrated circuits and logic devices. Similar techniques and teachings of the embodiments of the present disclosure can be applied to other types of circuits or semiconductor devices that can benefit from higher pipeline throughput and improved performance. The teachings of the embodiments of the present disclosure are applicable to any processor or machine that performs data manipulation. However, the present disclosure is not limited to processors or machines that perform 512-bit, 256-bit, 128-bit, 64-bit, 32-bit or 16-bit data operations, and can be applied to any processor and machine that performs manipulation or management of data therein. In addition, the description here provides examples, and the accompanying drawings show various examples for illustrative purposes. However, these examples should not be interpreted as limiting meanings, because they are only intended to provide examples of embodiments of the present disclosure, rather than providing an exhaustive list of all possible implementations of embodiments of the present disclosure.

[0084] Although the following examples describe instruction processing and distribution in the context of execution units and logic circuits, other embodiments of the present disclosure may be implemented by data or instructions stored on a machine-readable tangible medium, wherein the data or instructions, when executed by a machine, cause the machine to perform functions consistent with at least one embodiment of the present disclosure. In one embodiment, the functions associated with the embodiments of the present disclosure are embodied in machine executable instructions. The instructions can be used to cause a general or special processor programmed with instructions to perform the steps of the present disclosure. The embodiments of the present disclosure may be provided as a computer program product or software, which may include a machine or computer-readable medium having instructions stored thereon, which instructions may be used to program a computer (or other electronic device) to perform one or more operations according to the embodiments of the present disclosure. Alternatively, the operations of the embodiments of the present disclosure may be performed by specific hardware components containing fixed-function logic for performing operations, or by any combination of programmed computer components and fixed-function hardware components.

[0085] Instructions for programming logic to perform embodiments of the present disclosure may be stored in a memory in the system, such as a DRAM, cache, flash memory, or other storage device. In addition, instructions may be distributed via a network or by other computer-readable media. Therefore, a machine-readable medium may include any mechanism for storing or transmitting information in a machine (e.g., computer) readable form, but is not limited to, a floppy disk, an optical disk, a compressed disk, a read-only memory (CD-ROM), a magneto-optical disk, a read-only memory (ROM), a random access memory (RAM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic card or an optical card, a flash memory, or a tangible machine-readable storage device for transmitting information via an electrical, optical, acoustic, or other form of propagation signal (e.g., a carrier wave, an infrared signal, a digital signal, etc.) via the Internet. Therefore, a computer-readable medium includes any type of tangible machine-readable medium suitable for storing or transmitting electronic instructions or information in a machine (e.g., computer) readable form.

[0086] The design may go through various stages from creation to simulation to manufacturing. The data representing the design may represent the design in a variety of ways. First, as useful in simulation, a hardware description language or another functional description language may be used to represent the hardware. In addition, a circuit-level model with logic and / or transistor gates may be generated at certain stages of the design process. In addition, most designs reach a data level representing the physical placement of various devices in the hardware model at some stage. In the case of using traditional semiconductor manufacturing technology, the data representing the hardware model may be data specifying the presence or absence of various features on different mask layers of a mask used to manufacture an integrated circuit. In any representation of the design, the data may be stored in any form of machine-readable medium. A memory or a magnetic or optical storage device such as a disk may be a machine-readable medium for storing information transmitted via light waves or electric waves modulated or otherwise generated to transmit such information. When an electric carrier wave indicating or carrying a code or design is transmitted, a new copy is made to the extent that the electric signal is copied, buffered, or retransmitted. Therefore, a communication provider or a network provider may store at least temporarily an article of information encoded into a carrier wave embodying the technology of an embodiment of the present disclosure on a tangible machine-readable medium.

[0087] As used herein, a module refers to any combination of hardware, software, and / or firmware. As an example, a module includes hardware, such as a microcontroller, associated with a non-transitory medium storing a code suitable for execution by the microcontroller. Therefore, in one embodiment, a reference to a module refers to hardware that is particularly configured to identify and / or execute a code to be maintained on a non-transitory medium. In addition, in another embodiment, the use of a module refers to a non-transitory medium comprising a code that is particularly suitable for execution by a microcontroller to implement a predetermined operation. And, as can be inferred, in yet another embodiment, the term module (in this example) may refer to a combination of a microcontroller and a non-transitory medium. Typically, the boundaries of modules illustrated as separate typically vary and may overlap. For example, a first module and a second module may share hardware, software, firmware, or a combination thereof, while possibly retaining some independent hardware, software, or firmware. In one embodiment, the use of the term logic includes hardware, such as transistors, registers, or other hardware, such as programmable logic devices.

[0088] In one embodiment, the use of the phrase "configured to" refers to a device, hardware, logic or element that is arranged, put together, manufactured, provided for sale, imported and / or designed to perform a specified or determined task. In this example, a device or element thereof that is not operating is still 'configured to' perform a specified task if it is designed, coupled and / or interconnected to perform the specified task. Purely as an illustrative example, a logic gate can provide 0 or 1 during operation. But a logic gate that is 'configured to' provide an enable signal to a clock does not include every possible logic gate that can provide 1 or 0. Instead, the logic gate is a logic gate that is coupled in a certain way that a 1 or 0 output is used to enable the clock during operation. Note again that the use of the term 'configured to' does not require operation, but focuses on the potential state of the device, hardware and / or element, where in the potential state, the device, hardware and / or element is designed to perform a specific task when the device, hardware and / or element is operating.

[0089] Furthermore, in one embodiment, the use of the phrases "for", "can / capable of", and / or "operable for" refers to a certain device, logic, hardware, and / or element designed in such a manner to enable the use of the device, logic, hardware, and / or element in a specified manner. As mentioned above, in one embodiment, the use of for, capable of, or operable for refers to a potential state of a device, logic, hardware, and / or element, wherein the device, logic, hardware, and / or element is not operating, but is designed to enable the use of the device in a specified manner.

[0090] As used herein, a value includes any known representation of a number, state, logic state, or binary logic state. Typically, the use of logic levels, logic levels, logic values, or logical values ​​is also referred to as 1 and 0, which simply represent binary logic states. For example, 1 represents a high logic level, and 0 represents a low logic level. In one embodiment, a storage unit such as a transistor or a flash memory cell can hold a single logic value or multiple logic values. However, other representations of values ​​in computer systems have been used. For example, the decimal tens can also be represented as the binary value 1010 and the hexadecimal letter A. Therefore, a value includes any information representation that can be stored in a computer system.

[0091] In addition, a state may be represented by a value or a portion of a value. As an example, a first value such as a logical 1 may represent a default or initial state, while a second value such as a logical 0 may represent a non-default value. Additionally, in one embodiment, the terms reset and set refer to a default value or state and an updated value or state, respectively. For example, a default value may include a high logic value, i.e., reset, while an updated value may include a low logic value, i.e., set. Note that any combination of values ​​may be used to represent any number of states.

[0092] Embodiments of the methods, hardware, software, firmware, or code described above may be implemented via instructions or code stored on a machine-accessible, machine-readable, computer-accessible, or computer-readable medium that is executable by a processing element. Non-transitory machine-accessible / readable media include any mechanism that provides (i.e., stores and / or transmits) information in a form that can be read by a machine, such as a computer or electronic system. For example, non-transitory machine-accessible media include random access memory (RAM), such as static RAM (SRAM) or dynamic RAM (DRAM); ROM; magnetic or optical storage media; flash memory devices; electrical storage devices; optical storage devices; acoustic storage devices; other forms of storage devices for storing information received from a temporary (propagating) signal (e.g., a carrier wave, an infrared signal, a digital signal); etc., which are distinguished from the non-transitory medium from which information can be received.

[0093] Instructions for programming logic to perform embodiments of the present disclosure may be stored in a memory in the system, such as a DRAM, cache, flash memory, or other storage device. In addition, instructions may be distributed via a network or by other computer-readable media. Therefore, a machine-readable medium may include any mechanism for storing or sending information in a machine (e.g., computer) readable form, but is not limited to a floppy disk, an optical disk, a compressed disk, a read-only memory (CD-ROM) and a magneto-optical disk, a read-only memory (ROM), a random access memory (RAM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic card or an optical card, a flash memory, or a tangible machine-readable storage device used in transmitting information via an electrical, optical, acoustic, or other form of propagation signal (e.g., a carrier wave, an infrared signal, a digital signal, etc.) through the Internet. Therefore, a computer-readable medium includes any type of tangible machine-readable medium suitable for storing or sending electronic instructions or information in a machine (e.g., computer) readable form.

[0094] References throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present disclosure. Thus, the phrases "in one embodiment" or "in an embodiment" appearing in various places throughout this specification do not necessarily all refer to the same embodiment. Furthermore, particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0095] In the foregoing description, reference has been made to specific exemplary embodiments for detailed description. However, it will be apparent that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present disclosure as set forth in the appended claims. The description and drawings are therefore to be considered in an illustrative rather than a restrictive sense. Furthermore, the foregoing use of embodiments and other exemplary language does not necessarily refer to the same embodiment or the same example, but may refer to different and unique embodiments as well as possibly the same embodiment.

[0096] Some parts of the detailed description are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the art of data processing to most effectively convey the essence of their work to other persons skilled in the art. An algorithm is here and generally considered to be a self-consistent sequence of operations that leads to a desired result. An operation is an operation that requires physical manipulation of physical quantities. Typically, although not necessarily, these quantities take the form of electrical or magnetic signals that can be stored, transmitted, combined, compared, and otherwise manipulated. Sometimes, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc. The blocks described here can be hardware, software, firmware, or a combination thereof.

[0097] It should be remembered, however, that all of these and similar terms are associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless clearly indicated from the above discussion, it should be appreciated that throughout the specification, discussions utilizing terms such as "store," "receive," "determine," "output," "convert," etc. refer to the actions and processes of a computing system or similar electronic computing device that manipulates and transforms data represented as physical (e.g., electronic) quantities within the computing system's registers and memories into other data similarly represented as physical quantities within the computing system's memories or registers or other such information storage, transmission, or display devices.

[0098] The words "example" or "exemplary" are used herein to mean used as an example, instance or illustration. Any aspect or design described herein as "example" or "exemplary" is not necessarily to be interpreted as being more preferred or advantageous than other aspects or designs. On the contrary, the use of the words "example" or "exemplary" is intended to present concepts in a specific way. As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless otherwise specified or clear from the context, "X includes A or B" is intended to mean any natural inclusive arrangement. That is, if X includes A; X includes B; or X includes A and B, then "X includes A or B" is satisfied in any of the foregoing cases. In addition, unless otherwise specified or clearly pointed to the singular form from the context, the words "one" and "an" used in this application and the appended claims are generally understood to mean "one or more". In addition, unless so described, the use of the terms "embodiment" or "one embodiment" or "implementation" or "one implementation" throughout this article is not intended to represent the same embodiment or implementation. Furthermore, the terms “first,” “second,” “third,” “fourth,” etc. used herein are meant as labels for distinguishing different elements, and do not necessarily have ordinal meanings according to their numerical labels.

Claims

1. A processing device comprising: A hardware logic circuit, which is used to implement a hardware state machine; as well as A plurality of interconnect terminals coupled to the hardware logic circuit, the hardware logic circuit being configured to: receiving, via a serial communication interface, a first signal from a memory device at a first interconnect terminal of the plurality of interconnect terminals indicating that the memory device is a NAND-type memory device; determining whether a second signal has been received from the memory device at a second interconnect terminal of the plurality of interconnect terminals, the second signal indicating that the NAND-type memory device is initialized; as well as In response to determining that the second signal indicating that the NAND-type memory device is initialized has been received from the memory device, an operation associated with the NAND-type memory device is performed at the second and third interconnection terminals among the plurality of interconnection terminals.

2. The processing device according to claim 1, further comprising: A clock generation circuit is coupled to a fourth interconnect terminal of the plurality of interconnect terminals, the clock generation circuit being used to generate a timing signal to be provided to the memory device at the fourth interconnect terminal of the plurality of interconnect terminals.

3. The processing device according to claim 1, wherein: The operation is a read operation, wherein the hardware logic circuit for the read operation is used to: sending a first read control signal to the NAND type memory device at the second interconnect terminal and the third interconnect terminal; receiving a second read control signal from the NAND-type memory device at the second interconnect terminal, the second read control signal indicating that the NAND-type memory device is ready to provide data associated with the read operation; and The data associated with the read operation is received from the NAND type memory device at the second interconnect terminal and the third interconnect terminal.

4. The processing device according to claim 1, wherein: The operation is a write operation, wherein the hardware logic circuit for the write operation is used to: sending a first write control signal to the NAND type memory device at the second interconnect terminal and the third interconnect terminal; receiving a second write control signal from the NAND-type memory device at the second interconnect terminal, the second write control signal indicating that the NAND-type memory device is ready to receive data associated with the write operation; and The data associated with the write operation is provided to the NAND type memory device at the second interconnect terminal and the third interconnect terminal.

5. The processing device of claim 1, further comprising: a sample and hold circuit for measuring a value associated with a signal received at the plurality of interconnected terminals, holding the value associated with the signal and generating an output corresponding to the value; as well as A data buffer is operably coupled to the sample and hold circuit, the data buffer being configured to store the output corresponding to the value.

6. The processing device according to claim 1, wherein: The hardware logic circuit is also used for: A third signal indicating that the NAND-type memory device is not initialized is received from the memory device at the second interconnection terminal among the plurality of interconnection terminals.

7. The processing device according to claim 1, wherein: The plurality of interconnect terminals is less than seven interconnect terminals.

8. A system comprising: a processing device comprising a plurality of interconnected terminals; as well as A memory device comprising a NAND-type memory device operably coupled to the processing device at the plurality of interconnection terminals via a serial communication interface, wherein the NAND-type memory device is used to send signals to the processing device via the plurality of interconnection terminals, the processing device being used to: receiving a first signal at a first interconnect terminal among the plurality of interconnect terminals; determining, based on the first signal, that the memory device comprises the NAND-type memory device; receiving a second signal at a second interconnect terminal among the plurality of interconnect terminals; determining that the NAND-type memory device is initialized based on the second signal; and An operation associated with the NAND type memory device is performed at the second interconnection terminal and the third interconnection terminal among the plurality of interconnection terminals.

9. The system of claim 8, wherein: The second interconnection terminal among the plurality of interconnection terminals includes a dual-purpose input-output terminal.

10. The system of claim 8, wherein: The third interconnect terminal of the plurality of interconnect terminals comprises an input-output terminal for providing or receiving a signal from the memory device.

11. The system of claim 8, further comprising: A hardware state machine is provided for monitoring signals sent from the memory device at the plurality of interconnect terminals.

12. The system of claim 8, wherein: The operation is a read operation, wherein the processing device is configured to: sending a first read control signal to the NAND type memory device at the second interconnect terminal and the third interconnect terminal; receiving a second read control signal from the NAND-type memory device at the second interconnect terminal, the second read control signal indicating that the NAND-type memory device is ready to provide data associated with the read operation; and The data associated with the read operation is received from the NAND type memory device at the second interconnect terminal and the third interconnect terminal.

13. The system of claim 8, wherein: The operation is a write operation, wherein the processing device is configured to: sending a first write control signal to the NAND type memory device at the second interconnect terminal and the third interconnect terminal; receiving a second write control signal from the NAND-type memory device at the second interconnect terminal, the second write control signal indicating that the NAND-type memory device is ready to receive data associated with the write operation; and The data associated with the write operation is provided to the NAND type memory device at the second interconnect terminal and the third interconnect terminal.

14. The system of claim 8, further comprising: A clock generation circuit is coupled to a fourth interconnect terminal of the plurality of interconnect terminals, the clock generation circuit being used to generate a timing signal to be provided to the memory device at the fourth interconnect terminal of the plurality of interconnect terminals.

15. A method comprising: receiving, via a serial communication interface, a first signal from a memory device at a first interconnect terminal of a plurality of interconnect terminals indicating that the memory device comprises a NAND-type memory device; determining, by a processing device, whether a second signal has been received from the memory device at a second interconnect terminal of the plurality of interconnect terminals, the second signal indicating that the NAND-type memory device is initialized; as well as In response to determining that the second signal indicating that the NAND-type memory device is initialized has been received from the memory device, an operation associated with the NAND-type memory device is performed at the second and third interconnection terminals among the plurality of interconnection terminals.

16. The method of claim 15, wherein: The operation is a read operation, comprising: sending a first read control signal to the NAND type memory device at the second interconnect terminal and the third interconnect terminal; receiving a second read control signal from the NAND-type memory device at the second interconnect terminal, the second read control signal indicating that the NAND-type memory device is ready to provide data associated with the read operation; and The data associated with the read operation is received from the NAND type memory device at the second interconnect terminal and the third interconnect terminal.

17. The method of claim 15, wherein: The operation is a write operation, comprising: sending a first write control signal to the NAND type memory device at the second interconnect terminal and the third interconnect terminal; receiving a second write control signal from the NAND-type memory device at the second interconnect terminal, the second write control signal indicating that the NAND-type memory device is ready to receive data associated with the write operation; and The data associated with the write operation is provided to the NAND type memory device at the second interconnect terminal and the third interconnect terminal.

18. The method of claim 15, further comprising: A third signal is received from the memory device at the second interconnect terminal indicating that an operation associated with the NAND-type memory device has been performed.

19. The method of claim 15, further comprising: A third signal indicating that the NAND-type memory device is not initialized is received from the memory device at the second interconnection terminal among the plurality of interconnection terminals.

20. The method of claim 15, wherein: The plurality of interconnect terminals is less than seven interconnect terminals.

21. An apparatus comprising means for performing the method according to any one of claims 15 to 20.

22. An apparatus comprising: A processor, wherein the processor is configured to execute the method according to any one of claims 15 to 20.

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