Apparatus and method for handling fractional reciprocal operations

Abstract

Apparatuses and methods for processing reciprocal of fraction operations are provided. An apparatus and method for performing a reciprocal. For example, one embodiment of a processor includes a decoder to decode a reciprocal instruction to generate a decoded reciprocal instruction, a source register to store at least one packed input data element, a destination register to store a result data element, and a reciprocal execution circuit to execute the decoded reciprocal instruction, the reciprocal execution circuit to use a first portion of the packed input data element as an index to a data structure containing a plurality of sets of coefficients to identify a first set of coefficients from the plurality of sets of coefficients, the reciprocal execution circuit to generate a reciprocal of the packed input data element using a combination of the coefficients and a second portion of the packed input data element.

Description

Background Technology Technical Field

[0002] The embodiments of the present invention generally relate to the field of computer processors. More specifically, the embodiments relate to apparatus and methods for processing operations involving reciprocals of fractions and square roots.

[0003] Related technical descriptions

[0004] The instruction set, or instruction set architecture (ISA), is the programming-related part of a computer architecture, including primitive data types, instructions, register architecture, addressing modes, memory architecture, interrupt and exception handling, and external input and output (I / O). It should be noted that the term "instruction" in this article generally refers to macro-instructions—that is, instructions provided to the processor for execution—rather than micro-instructions or micro-operations—that is, the result of the processor's decoder decoding macro-instructions. Micro-instructions or micro-operations can be configured to instruct execution units on the processor to perform operations to implement the logic associated with macro-instructions.

[0005] An instruction set assembly (ISA) differs from a microarchitecture, which is a collection of processor design techniques used to implement an instruction set. Processors with different microarchitectures can share a common instruction set. For example, Pentium 4 processor, Core TM (Core TM The processors, and several processors from Advanced Micro Devices, Inc. in Sunnyvale, California, implement nearly identical versions of the x86 instruction set (with some extensions added with newer versions), but with different internal designs. For example, the same register architecture of the ISA can be implemented differently in different microarchitectures using known techniques, including dedicated physical registers, one or more dynamically allocated physical registers using register renaming mechanisms (e.g., using register alias tables (RATs), reorder buffers (ROBs), and retired register files). Unless otherwise specified, the phrases “register architecture,” “register file,” and “register” are used herein to refer to the register architecture, register file, and register as visible to the software / programmer and to how registers are specified in instructions. Where distinction is required, the adjectives “logical,” “architectural,” or “software visible” will be used to indicate registers / register files within a register architecture, while different adjectives will be used to specify registers (e.g., physical registers, reorder buffers, retired registers, register pools) within a given microarchitecture.

[0006] Multiplication-accumulation is a common digital signal processing operation that calculates the product of two numbers and adds that product to an accumulated value. Existing Single Instruction Multiple Data (SIMD) microarchitectures implement multiplication-accumulation by executing a sequence of instructions. For example, multiplication instructions followed by a 4-way addition, and then accumulation using the destination four-word data, can be used to perform multiplication-accumulation to produce two 64-bit saturated results. Attached Figure Description

[0007] A better understanding of the present invention can be obtained from the following detailed embodiments, in conjunction with the accompanying drawings, wherein:

[0008] Figure 1A and Figure 1B This is a block diagram illustrating a general vector-friendly instruction format and its instruction template according to an embodiment of the present invention;

[0009] Figures 2A-2C This is a block diagram illustrating an exemplary VEX instruction format according to an embodiment of the present invention;

[0010] Figure 3 This is a block diagram of a register architecture according to an embodiment of the present invention; and

[0011] Figure 4A The diagram illustrates both an exemplary ordered fetch, decode, and de-fetch pipeline and an exemplary out-of-order release / execution pipeline for register renaming, according to an embodiment of the present invention.

[0012] Figure 4B This is a block diagram illustrating an exemplary embodiment of an ordered fetch, decode, and retire core to be included in a processor, and an exemplary out-of-order release / execution architecture core for register renaming, according to an embodiment of the present invention;

[0013] Figure 5A It is a block diagram of a single processor core and its connection to the interconnect network on the die;

[0014] Figure 5B The figure illustrates an embodiment of the present invention. Figure 5A An expanded diagram of the processor core;

[0015] Figure 6 This is a block diagram of a single-core processor and a multi-core processor having an integrated memory controller and a graphics device according to embodiments of the present invention;

[0016] Figure 7 The figure shows a block diagram of a system according to an embodiment of the present invention;

[0017] Figure 8 The figure shows a block diagram of a second system according to an embodiment of the present invention;

[0018] Figure 9 The figure illustrates a block diagram of a third system according to an embodiment of the present invention;

[0019] Figure 10 The figure illustrates a block diagram of a system-on-a-chip (SoC) according to an embodiment of the present invention;

[0020] Figure 11 The figure illustrates a block diagram illustrating the conversion of binary instructions in a source instruction set into binary instructions in a target instruction set using a software instruction converter, according to an embodiment of the present invention.

[0021] Figure 12 The figure illustrates a processor architecture on which embodiments of the present invention can be implemented;

[0022] Figure 13 The figure illustrates multiple compressed data elements containing real and complex values ​​according to one embodiment;

[0023] Figure 14 The diagram illustrates an embodiment of an architecture on which instructions for reciprocal fractions and reciprocal square roots can be implemented;

[0024] Figure 15 The illustration shows an example of an embodiment for processing fraction reciprocal instructions;

[0025] Figure 16 The figure illustrates a method for processing the reciprocal of a fraction according to an embodiment of the present invention;

[0026] Figure 17 The illustration shows an example of an embodiment for processing fraction reciprocal instructions; and

[0027] Figure 18 The illustration shows a method for processing fraction reciprocals according to an embodiment of the present invention. Detailed Implementation

[0028] In the following description, numerous specific details are set forth for purposes of explanation in order to provide a thorough understanding of the embodiments of the invention described below. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form to avoid obscuring the fundamental principles of embodiments of the invention.

[0029] Exemplary processor architecture, instruction format, and data types

[0030] An instruction set includes one or more instruction formats. A given instruction format defines various fields (number of bits, bit positions) to specify the operation to be performed (opcode) and the operand(s) to which the operation will be performed, etc. Some instruction formats are further decomposed by defining instruction templates (or subformats). For example, an instruction template for a given instruction format can be defined as a different subset of the fields of that instruction format (the included fields are generally in the same order, but at least some fields have different bit positions because fewer fields are included), and / or defined as a given field that is interpreted in a different way. Thus, each instruction of the ISA is expressed using a given instruction format (and, if defined, according to a given instruction template in the instruction template of that instruction format) and includes fields for specifying the operation and operands. For example, the exemplary ADD (addition) instruction has a specific opcode and instruction format, which includes an opcode field for specifying the opcode and an operand field for selecting operands (source 1 / destination and source 2); and the appearance of the ADD instruction in the instruction stream will cause specific content in the operand field to select a specific operand.

[0031] Examples of the instructions described herein can be embodied in different formats. Furthermore, exemplary systems, architectures, and pipelines are detailed below. Examples of the instructions can be executed on such systems, architectures, and pipelines, but are not limited to those detailed herein.

[0032] General Vector-Friendly Instruction Format

[0033] A vector-friendly instruction format is an instruction format suitable for vector instructions (e.g., the existence of specific fields dedicated to vector operations). Although an embodiment in which both vector and scalar operations are supported via a vector-friendly instruction format has been described, alternative embodiments use only vector operations via the vector-friendly instruction format.

[0034] Figures 1A-1B This is a block diagram illustrating a general vector-friendly instruction format and its instruction template according to an embodiment of the present invention. Figure 1A This is a block diagram illustrating a general vector-friendly instruction format and its Class A instruction template according to an embodiment of the present invention; and Figure 1B This is a block diagram illustrating a general vector-friendly instruction format and its Class B instruction template according to an embodiment of the present invention. Specifically, Class A and Class B instruction templates are defined for the general vector-friendly instruction format 100, both of which include instruction templates for no memory access 105 and instruction templates for memory access 120. In the context of the vector-friendly instruction format, the term "general" means an instruction format that is not bound to any particular instruction set.

[0035] Although embodiments of the invention described herein support the following in the case of vector-friendly instruction formats: 64-byte vector operand length (or size) with a 32-bit (4-byte) or 64-bit (8-byte) data element width (or size) (and thus, the 64-byte vector consists of 16 double-word-sized elements, or alternatively, 8 quad-word-sized elements); 64-byte vector operand length (or size) with a 16-bit (2-byte) or 8-bit (1-byte) data element width (or size); 32-byte vector operand length (or size) with a 32-bit (4-byte) or 64-bit (8-byte) data element width (or size); Byte), 64-bit (8-byte), 16-bit (2-byte), or 8-bit (1-byte) data element widths (or sizes); and 16-byte vector operand lengths (or sizes) with 32-bit (4-byte), 64-bit (8-byte), 16-bit (2-byte), or 8-bit (1-byte) data element widths (or sizes); however, alternative embodiments may support larger, smaller, and / or different vector operand sizes (e.g., 256-byte vector operands) with larger, smaller, or different data element widths (e.g., 128-bit (16-byte) data element widths).

[0036] Figure 1A The Class A instruction templates include: 1) within the instruction template for no memory access 105, an instruction template showing a full rounding control operation 110 without memory access and an instruction template showing a data transformation operation 115 without memory access; and 2) within the instruction template for memory access 120, an instruction template showing the timeliness of memory access 125 and the timelessness of memory access 130. Figure 1B The B-type instruction templates include: 1) within the instruction template for no memory access 105, an instruction template showing a partial rounding control type operation 112 for write mask control without memory access and an instruction template showing a vsize type operation 117 for write mask control without memory access; and 2) within the instruction template for memory access 120, an instruction template showing write mask control 127 for memory access.

[0037] The general vector-friendly instruction format 100 includes the following as listed in Figures 1A-1B The fields in the order shown in the diagram are as follows.

[0038] Format field 140 – A specific value (instruction format identifier value) in this field uniquely identifies the vector-friendly instruction format, and thus indicates that the instruction appears in the instruction stream in the vector-friendly instruction format. Therefore, this field is not required for instruction sets that only have a general vector-friendly instruction format, and in this sense, it is optional.

[0039] Basic Operation Field 142 – Its content distinguishes different basic operations.

[0040] Register index field 144—its contents, either directly or generated from addresses, specify the location of the source or destination operand in a register or in memory. These fields include a sufficient number of bits to select N registers from a PxQ (e.g., 32x512, 16x128, 32x1024, 64x1024) register file. Although in one embodiment N can be up to three source registers and one destination register, alternative embodiments may support more or fewer source and destination registers (e.g., up to two sources, where one of these sources also serves as the destination; up to three sources, where one of these sources also serves as the destination; up to two sources and one destination).

[0041] The modifier field 146 distinguishes between instructions in the generic vector instruction format that specify memory access and those that do not; that is, it differentiates between instruction templates with no memory access 105 and instruction templates with memory access 120. Memory access operations read and / or write to the memory hierarchy (in some cases, using values ​​in registers to specify source and destination addresses), while non-memory access operations do not (e.g., the source and / or destination are registers). Although in one embodiment, this field also selects between three different ways to perform memory address calculations, alternative embodiments may support more, fewer, or different ways to perform memory address calculations.

[0042] The extended operation field 150 distinguishes which of the various operations to be performed in addition to the basic operation. This field is context-dependent. In one embodiment of the invention, this field is divided into a class field 168, an α field 152, and a β field 154. The extended operation field 150 allows multiple sets of common operations to be performed in a single instruction, rather than two, three, or four instructions.

[0043] Ratio field 160 — its contents allow for use in memory address generation (e.g., for using...)

[0044] (2 比例 The content of the index field is scaled proportionally by the address generated by the index + base address.

[0045] Displacement field 162A – its contents are used as part of memory address generation (e.g., for use with (2 比例 Address generation (index + base address + offset).

[0046] The displacement factor field 162B (note that the offset field 162A directly indicates the use of one or the other on the offset factor field 162B) – its contents are used as part of the address generation; it specifies the displacement factor that will scale the size (N) of the memory access – where N is the number of bytes in the memory access (e.g., for use with (2 比例 *Address generation (index + base address + scaled displacement). Redundant low-order bits are ignored, and therefore the contents of the displacement factor field are multiplied by the total memory operand size (N) to generate the final displacement that will be used in calculating the effective address. The value of N is determined by the processor hardware at runtime based on the full opcode field 174 (described later herein) and the data manipulation field 154C. Displacement field 162A and displacement factor field 162B are not used in the instruction template for no memory access 105 and / or different embodiments may implement only one of them or neither of them; in this sense, displacement field 162A and displacement factor field 162B are optional.

[0047] The data element width field 164—its content distinguishes which of the multiple data element widths will be used (in some embodiments for all instructions; in other embodiments for only some instructions). This field is unnecessary if only one data element width is supported and / or if one aspect of the opcode is used to support the data element width; in this sense, the field is optional.

[0048] The write mask field 170—its contents control, element-by-element position, whether the position of data elements in the destination vector operand reflects the results of the base and augmentation operations. Type A instruction templates support merge-write masking, while Type B instruction templates support both merge-write masking and zero-write masking. When merging, the vector mask allows protecting any set of elements in the destination from updates during the execution of any operation (specified by the base and augmentation operations); in another embodiment, it preserves the old value of each element in the destination where the corresponding mask bit has a 0. Conversely, when zeroing, the vector mask allows zeroing any set of elements in the destination during the execution of any operation (specified by the base and augmentation operations); in one embodiment, the elements in the destination are set to 0 when the corresponding mask bit has a 0 value. A subset of this functionality is the ability to control the vector length of the operation being performed (i.e., the span from the first to the last element being modified), however, the modified elements do not necessarily have to be consecutive. Thus, the write mask field 170 allows for some vector operations, including load, store, arithmetic, logical, etc. Although an embodiment of the invention has been described in which the content of the write mask field 170 selects one of a plurality of write mask registers containing the write mask to be used (and thus the content of the write mask field 170 indirectly identifies the mask to be performed), alternative embodiments may alternatively or additionally allow the content of the mask write field 170 to directly specify the mask to be performed.

[0049] Immediate number field 172 – its contents allow for the specification of immediate numbers. This field is optional in implementations of generic vector-friendly formats that do not support immediate numbers and in instructions that do not use immediate numbers.

[0050] Class field 168 – its content distinguishes instructions from different classes. (See reference) Figures 1A-1B The content of this field allows selection between Class A and Class B instructions. Figures 1A-1B In this context, rounded rectangles are used to indicate that a specific value exists in a field (e.g., in...). Figures 1A-1B The two fields are used for class field 168 (Class A 168A and Class B 168B, respectively).

[0051] Type A Instruction Template

[0052] In the case of the instruction template for Class A non-memory access 105, the α field 152 is interpreted as the RS field 152A, whose content distinguishes which of the different extended operation types to be performed (e.g., the instruction templates for rounding operation 110 and data transformation operation 115 without memory access specify rounding 152A.1 and data transformation 152A.2, respectively). The β field 154 distinguishes which of the specified types of operations to be performed. In the instruction template for non-memory access 105, the scaling field 160, the displacement field 162A, and the displacement-scale field 162B are absent.

[0053] Instruction template without memory access – fully round-control operation

[0054] In the instruction template of a fully round-controlled operation 110 without memory access, the β field 154 is interpreted as a rounding control field 154A that provides static rounding for its(plural) contents. Although the rounding control field 154A in the described embodiment of the invention includes a suppress all floating-point exception (SAE) field 156 and a rounding operation control field 158, alternative embodiments may support both concepts, which may be encoded as the same field, or only one or the other of these concepts / fields may be present (e.g., only the rounding operation control field 158 may be present).

[0055] SAE field 156 – Its content distinguishes whether exception event reporting is disabled; when the content of SAE field 156 indicates that suppression is enabled, the given instruction does not report any kind of floating-point exception flags and does not invoke any floating-point exception handlers.

[0056] The rounding operation control field 158 distinguishes which of a set of rounding operations to perform (e.g., round up, round down, round to zero, and round to nearest). Thus, the rounding operation control field 158 allows the rounding mode to be changed instruction-by-instruction. In one embodiment of the invention, where the processor includes a control register for specifying the rounding mode, the content of the rounding operation control field 150 overrides that register value.

[0057] Instruction template without memory access – data transformation operations

[0058] In the instruction template of the data transformation operation 115 without memory access, the β field 154 is interpreted as the data transformation field 154B, the contents of which distinguish which of the multiple data transformations to be performed (e.g., no data transformation, mixing, broadcasting).

[0059] In the case of instruction template 120 for Class A memory access, field 152 is interpreted as eviction hint field 152B, the content of which distinguishes which eviction hint to use (in... Figure 1A In the instruction template for memory access timing 125 and memory access non-timing 130, timing 152B.1 and non-timing 152B.2 are specified respectively, while the β field 154 is interpreted as a data manipulation field 154C, the contents of which distinguish which of the multiple data manipulation operations (also called primitives) to be performed (e.g., no manipulation, broadcast, source upcast, and destination downcast). The instruction template for memory access 120 includes a scaling field 160 and optionally includes a displacement field 162A or a displacement scaling field 162B.

[0060] Vector memory instructions use translation support to perform vector loads from and vector stores to memory. Like regular vector instructions, vector memory instructions transfer data to / from memory in an element-by-element manner, where the actual elements transferred are specified by the contents of a vector mask selected as the write mask.

[0061] Instruction templates for memory access – time-sensitive

[0062] Time-sensitive data is data that can be reused quickly enough to benefit from cache operations. However, this is a hint, and different processors can implement it in different ways, including ignoring the hint entirely.

[0063] Instruction templates for memory access – non-time-sensitive

[0064] Non-time-sensitive data is data that is unlikely to be reused quickly enough to benefit from cache operations in the L1 cache and should be given eviction priority. However, this is a hint, and different processors can implement it in different ways, including ignoring the hint entirely.

[0065] Type B Instruction Template

[0066] In the case of the B-type instruction template, the α field 152 is interpreted as the write mask control (Z) field 152C, the content of which distinguishes whether the write mask controlled by the write mask field 170 should be merged or zeroed.

[0067] In the case of instruction template B-type non-memory access 105, a portion of β field 154 is interpreted as RL field 157A, the content of which distinguishes which of the different extended operation types to be performed (for example, the instruction template for instruction template of write mask control type operation 112 for non-memory access and instruction template for write mask control type operation 117 for non-memory access specify rounding 157A.1 and vector length (VSIZE) 157A.2, respectively), while the remainder of β field 154 distinguishes which of the specified types of operations to be performed. In instruction template of non-memory access 105, the scaling field 160, the displacement field 162A, and the displacement scaling field 162B are absent.

[0068] In the instruction template of the write mask control section round control operation 110 without memory access, the remainder of the β field 154 is interpreted as the round operation field 159A, and exception event reporting is disabled (the given instruction does not report any kind of floating-point exception flag and does not invoke any floating-point exception handler).

[0069] Rounding operation control field 159A—like rounding operation control field 158—distinguishes which of a set of rounding operations to perform (e.g., round up, round down, round to zero, and round to nearest). Thus, rounding operation control field 159A allows the rounding mode to be changed instruction-by-instruction. In one embodiment of the invention, where the processor includes a control register for specifying the rounding mode, the content of rounding operation control field 150 overrides that register value.

[0070] In the instruction template of write mask control VSIZE type operation 117 without memory access, the remainder of β field 154 is interpreted as vector length field 159B, the contents of which distinguish which of the multiple data vector lengths to be executed (e.g., 128 bytes, 256 bytes, or 512 bytes).

[0071] In the case of the instruction template for Class B memory access 120, a portion of the β field 154 is interpreted as a broadcast field 157B, the content of which distinguishes whether a broadcast data manipulation operation is to be performed, while the remainder of the β field 154 is interpreted as a vector length field 159B. The instruction template for memory access 120 includes a scaling field 160 and optionally includes a displacement field 162A or a displacement-scaling field 162B.

[0072] For the general vector-friendly instruction format 100, the complete opcode field 174 is shown to include a format field 140, a basic operation field 142, and a data element width field 164. Although one embodiment is shown in which the complete opcode field 174 includes all of these fields, in embodiments that do not support all of these fields, the complete opcode field 174 includes fewer than all of them. The complete opcode field 174 provides the operation code (opcode).

[0073] The expanded operation field 150, data element width field 164, and write mask field 170 allow these features to be specified on an instruction-by-instruction basis in a generic vector-friendly instruction format.

[0074] Combining the write mask field and the data element width field creates various types of instructions, as these instructions allow the mask to be applied based on different data element widths.

[0075] The various instruction templates appearing within classes A and B are advantageous in different situations. In some embodiments of the invention, different processors or different cores within a processor may support only class A, only class B, or both. For example, a high-performance general-purpose out-of-order core designed for general-purpose computing may support only class B, a core designed primarily for graphics and / or scientific (throughput) computing may support only class A, and a core designed for both general-purpose computing and graphics and / or scientific (throughput) computing may support both class A and class B (of course, cores with some mixture of templates and instructions from both classes, but not all templates and instructions from both classes, are within the scope of the invention). Similarly, a single processor may include multiple cores, all of which support the same class, or different cores that support different classes. For example, in a processor with separate graphics cores and general-purpose cores, one graphics core designed primarily for graphics and / or scientific computing may support only class A, while one or more general-purpose cores may be high-performance general-purpose cores with out-of-order execution and register renaming designed for general-purpose computing and supporting only class B. Another processor, which does not have a separate graphics core, may include one or more general-purpose ordered or out-of-order cores that support both Class A and Class B. Of course, in different embodiments of the invention, features from one class may also be implemented in other classes. This will enable programs written in high-level languages ​​to become (e.g., just-in-time compiled or statically compiled) various different executable forms, including: 1) forms having only instructions from the class(s) supported by the target processor(s) for execution; or 2) forms having alternative routines and control flow code that uses different combinations of instructions from all classes, the control flow code selecting these routines to execute based on instructions supported by the processor currently executing the code.

[0076] VEX command format

[0077] VEX encoding allows instructions to have more than two operands and allows SIMD vector registers to be longer than 28 bits. The use of the VEX prefix provides three-operand (or more) syntax. For example, the previous two-operand instructions performed operations such as A = A + B, which overwrite the source operand. The use of the VEX prefix allows operands to perform non-destructive operations such as A = B + C.

[0078] Figure 2A The diagram illustrates an exemplary AVX instruction format, including the VEX prefix 202, the actual opcode field 230, the Mod R / M byte 240, the SIB byte 250, the offset field 262, and the IMM8 272. Figure 2B The diagram shows the source Figure 2A Which fields constitute the complete opcode field 274 and the basic operation field 241? Figure 2C The diagram shows the source Figure 2A Which fields constitute register index field 244?

[0079] The VEX prefix (bytes 0-2) 202 is encoded in three-byte form. The first byte is the format field 290 (VEX byte 0, bits [7:0]), which contains the explicit C4 byte value (a unique value used to distinguish the C4 instruction format). The second and third bytes (VEX bytes 1-2) include several bit fields that provide special capabilities. Specifically, the REX field 205 (VEX byte 1, bits [7-5]) consists of the VEX.R bit field (VEX byte 1, bits [7]-R), the VEX.X bit field (VEX byte 1, bits [6]-X), and the VEX.B bit field (VEX byte 1, bits [5]-B). The other fields of these instructions encode the lower three bits (rrr, xxx, and bbb) of the register index as known in the art, so that Rrrr, Xxxx, and Bbbb can be formed by adding VEX.R, VEX.X, and VEX.B. The opcode mapping field 215 (VEX byte 1, bits [4:0] – mmmmmm) contains the content used to encode the implicit preamble opcode byte. The W field 264 (VEX byte 2, bits [7] – W) is represented by the notation VEX.W and provides different functions depending on the instruction. The function of VEX.vvvv 220 (VEX byte 2, bits [6:3] – vvvv) can be as follows: 1) VEX.vvvv encodes the first source register operand specified in reverse (two's complement) form and is valid for instructions with two or more source operands; 2) VEX.vvvv encodes the destination register operand specified in two's complement form for some vector shift; or 3) VEX.vvvv does not encode any operand, this field is reserved and should contain 1111b. If the VEX.L 268 size field (VEX byte 2, bits [2]-L) = 0, it indicates a 28-bit vector; if VEX.L = 1, it indicates a 256-bit vector. The prefix encoding field 225 (VEX byte 2, bits [1:0]-pp) provides additional bits for the basic operation field 241.

[0080] The actual opcode field 230 (byte 3) is also known as the opcode byte. Part of the opcode is specified in this field.

[0081] The MOD R / M field 240 (byte 4) includes the MOD field 242 (bits [7-6]), the Reg field 244 (bits [5-3]), and the R / M field 246 (bits [2-0]). The Reg field 244 may encode the destination register operand or the source register operand (rrr of Rrrr); or it may be treated as an opcode extension and not used to encode any instruction operand. The R / M field 246 may encode the instruction operand that references a memory address; or it may encode the destination register operand or the source register operand.

[0082] The scale, index, base address (SIB) field 250 (byte 5) contains SS252 (bits [7-6]), which is used for memory address generation. The contents of SIB.xxx 254 (bits [5-3]) and SIB.bbb 256 (bits [2-0]) have been previously mentioned for register indices Xxxx and Bbbb.

[0083] The displacement field 262 and the immediate numeric field (IMM8) 272 contain data.

[0084] Exemplary Register Architecture

[0085] Figure 3 This is a block diagram of a register architecture 300 according to an embodiment of the present invention. In the illustrated embodiment, there are 32 512-bit wide vector registers 310; these registers are referenced as zmm0 to zmm31. The lower-order 256 bits of the lower 6 zmm registers are overlaid on registers ymm0-15. The lower-order 128 bits of the lower 6 zmm registers (the lower-order 128 bits of the ymm registers) are overlaid on registers xmm0-15.

[0086] General Purpose Register 325 — In the illustrated embodiment, there are sixteen 64-bit general purpose registers that are used in conjunction with existing x86 addressing modes for addressing memory operands. These registers are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.

[0087] A scalar floating-point stack register file (x87 stack) 345 is overlaid with an MMX compact integer flat register file 350. In the illustrated embodiment, the x87 stack is an octal stack used to perform scalar floating-point operations on 32 / 64 / 80-bit floating-point data using x87 instruction set extensions; while the MMX registers are used to perform operations on 64-bit compact integer data and to store operands for some operations performed between the MMX and XMM registers.

[0088] Alternative embodiments of the invention may use wider or narrower registers. Furthermore, alternative embodiments of the invention may use more, fewer, or different register files and registers.

[0089] Exemplary core architectures, processors, and computer architectures

[0090] Processor cores can be implemented in different ways, for different purposes, and in different processors. For example, implementations of such cores may include: 1) general-purpose ordered cores intended for general-purpose computing; 2) high-performance general-purpose out-of-order cores intended for general-purpose computing; and 3) dedicated cores intended primarily for graphics and / or scientific (throughput) computing. Implementations of different processors may include: 1) CPUs, which include one or more general-purpose ordered cores and / or one or more general-purpose out-of-order cores intended for general-purpose computing; and 2) coprocessors, which include one or more dedicated cores intended primarily for graphics and / or scientific (throughput) computing. These different processors result in different computer system architectures, which may include: 1) coprocessors on a separate chip from the CPU; 2) coprocessors in the same package as the CPU but on a separate die; 3) coprocessors on the same die as the CPU (in this case, such coprocessors are sometimes referred to as dedicated logic or dedicated cores, such as integrated graphics and / or scientific (throughput) logic); and 4) systems-on-a-chip that can include the described CPU (sometimes referred to as application cores or application processors), the coprocessors described above, and additional functionality on the same die. Exemplary core architectures are then described, followed by exemplary processors and computer architectures. Circuits (units) including example cores, processors, etc., are described in detail herein.

[0091] Exemplary core architecture

[0092] Figure 4A This is a block diagram illustrating an exemplary ordered pipeline and an exemplary out-of-order release / execution pipeline for register renaming according to various embodiments of the present invention. Figure 4B This is a block diagram illustrating exemplary embodiments of ordered architecture cores to be included in a processor according to various embodiments of the present invention, and exemplary out-of-order release / execution architecture cores with register renaming. Figures 4A-4B The solid-line boxes in the diagram illustrate ordered pipelines and ordered cores, while the optional additions to the dashed boxes illustrate register renaming, out-of-order release / execution pipelines, and cores. Since the ordered aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described.

[0093] exist Figure 4AIn the processor pipeline 400, there are fetch stage 402, length decoding stage 404, decoding stage 406, allocation stage 408, renaming stage 410, scheduling (also known as dispatch or issue) stage 412, register read / memory read stage 414, execution stage 416, write-back / memory write stage 418, exception handling stage 422 and commit stage 424.

[0094] Figure 4B A processor core 490 is shown, which includes a front-end unit 430 coupled to an execution engine unit 450, and both the front-end unit 430 and the execution engine unit 450 are coupled to a memory unit 470. Core 490 can be a Reduced Instruction Set Computing (RISC) core, a Complex Instruction Set Computing (CISC) core, a Very Long Instruction Word (VLIW) core, or a hybrid or alternative core type. Alternatively, core 490 can be a dedicated core, such as, for example, a network or communication core, a compression engine, a coprocessor core, a general-purpose computing graphics processing unit (GPGPU) core, a graphics core, etc.

[0095] Front-end unit 430 includes branch prediction unit 432 coupled to instruction cache unit 434 coupled to instruction translation lookup buffer (TLB) 436 coupled to instruction fetch unit 438 coupled to decoding unit 440. Decoding unit 440 (or decoder) decodes instructions and generates one or more micro-operations, microcode entry points, microinstructions, other instructions, or other control signals as output, which are decoded from, or otherwise reflect, the original instructions or derived from them. Decoding unit 440 can be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLAs), microcode read-only memory (ROM), etc. In one embodiment, core 490 includes microcode ROM or other media (e.g., in decoding unit 440 or otherwise within front-end unit 430) storing microcode for certain macro instructions. The decoding unit 440 is coupled to the rename / allocator unit 452 in the execution engine unit 450.

[0096] Execution engine unit 450 includes a rename / allocator unit 452 coupled to a retirement unit 454 and a set 456 of one or more scheduler units. The scheduler units 456 represent any number of different schedulers, including reservation stations, central instruction windows, etc. The scheduler units 456 are coupled to physical register file units 458. Each physical register file unit in the physical register file units 458 represents one or more physical register files, where different physical register files store one or more different data types, such as scalar integers, scalar floating-point numbers, compressed integers, compressed floating-point numbers, vector integers, vector floating-point numbers, status (e.g., an instruction pointer as the address of the next instruction to be executed), etc. In one embodiment, the physical register file units 458 include vector register units and scalar register units. These register units may provide architectural vector registers, vector mask registers, and general-purpose registers. Multiple physical register file units 458 are overlapped by retirement units 454 to illustrate various ways in which register renaming and out-of-order execution can be implemented (e.g., using multiple reorder buffers and multiple retirement register files; using multiple future files, multiple history buffers, and multiple retirement register files; using register mappings and register pools, etc.). Retirement units 454 and multiple physical register file units 458 are coupled to multiple execution clusters 460. Multiple execution clusters 460 include a set 462 of one or more execution units and a set 464 of one or more memory access units. Execution units 462 can perform various operations (e.g., shift, addition, subtraction, multiplication) and can perform operations on various data types (e.g., scalar floating-point, compressed integer, compressed floating-point, vector integer, vector floating-point). While some embodiments may include multiple execution units dedicated to a particular function or set of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. The scheduler unit 456, physical register file unit 458, and execution cluster 460 are shown as possibly multiple, because some embodiments create separate pipelines for certain types of data / operations (e.g., scalar integer pipelines, scalar floating-point / compact integer / compact floating-point / vector integer / vector floating-point pipelines, and / or memory access pipelines each having their own scheduler unit, physical register file unit, and / or execution cluster—and in the case of separate memory access pipelines, some embodiments are implemented where only the execution cluster of that pipeline has multiple memory access units 464). It should also be understood that, in the case of using separate pipelines, one or more of these pipelines may be out-of-order deployment / execution, and the remaining pipelines may be ordered.

[0097] A set of memory access units 464 is coupled to a memory unit 470, which includes a data TLB unit 472, which is coupled to a data cache unit 474, which is coupled to a Level 2 (L2) cache unit 476. In one exemplary embodiment, the memory access unit 464 may include a load unit, a memory address unit, and a memory data unit, each of which is coupled to the data TLB unit 472 in the memory unit 470. An instruction cache unit 434 is also coupled to the Level 2 (L2) cache unit 476 in the memory unit 470. The L2 cache unit 476 is coupled to one or more other levels of cache and ultimately to main memory.

[0098] As an example, the exemplary register renaming out-of-order release / execution core architecture can implement pipeline 400 as follows: 1) Instruction fetch 438 executes fetch stage 402 and length decoding stage 404; 2) Decoding unit 440 executes decoding stage 406; 3) Rename / allocator unit 452 executes allocation stage 408 and rename stage 410; 4) (multiple) scheduler units 456 execute scheduling stage 412; 5) (multiple) physical register file units 458 and memory units 470 execute register read / memory read stage 414; execution cluster 460 executes execution stage 416; 6) memory unit 470 and (multiple) physical register file units 458 execute write-back / memory write stage 418; 7) each unit may involve exception handling stage 422; and 8) retirement unit 454 and (multiple) physical register file units 458 execute commit stage 424.

[0099] Core 490 may support one or more instruction sets (e.g., the x86 instruction set (with some extensions added with newer versions); the MIPS instruction set of MIPS Technologies, Inc., Sunnyvale, California; the ARM instruction set of ARM Holdings, Inc., Sunnyvale, California (with optional additional extensions such as NEON)), including the instructions described herein. In one embodiment, Core 490 includes logic for supporting compressed data instruction set extensions (e.g., AVX1, AVX2), thereby allowing the use of compressed data to perform operations used by many multimedia applications.

[0100] It should be understood that a core can support multithreading (execution of two or more parallel operations or a set of threads), and this multithreading can be accomplished in various ways, including time-division multithreading, simultaneous multithreading (where a single physical core provides a logical core for each thread in the simultaneous multithreading of the physical core), or combinations thereof (e.g., time-division fetching and decoding, and subsequent operations such as...). Simultaneous multithreading in hyper-threading technology.

[0101] Although register renaming is described in the context of out-of-order execution, it should be understood that register renaming can also be used in ordered architectures. While the illustrated processor embodiment also includes separate instruction and data cache units 434 / 474 and a shared L2 cache unit 476, alternative embodiments may have a single internal cache for both instructions and data, such as, for example, a Level 1 (L1) internal cache or multiple levels of internal caches. In some embodiments, the system may include a combination of internal caches and external caches located outside the core and / or processor. Alternatively, all caches may be located outside the core and / or processor.

[0102] Specific exemplary ordered core architecture

[0103] Figures 5A-5B The diagram illustrates a more specific exemplary ordered core architecture, where the core is one of several logic blocks within a chip (including other cores of the same and / or different types). Depending on the application, the logic block communicates with some fixed functional logic, memory I / O interfaces, and other necessary I / O logic via a high-bandwidth interconnect network (e.g., a ring network).

[0104] Figure 5A This is a block diagram of a single processor core according to an embodiment of the invention, its connection to an on-die interconnect network 502, and a local subset 504 of its second-level (L2) cache. In one embodiment, the instruction decoder 500 supports the x86 instruction set with a compact data instruction set extension. The L1 cache 506 allows low-latency access to cache memory into the scalar and vector units. Although in one embodiment (for simplicity), the scalar unit 508 and the vector unit 510 use separate sets of registers (scalar register 512 and vector register 514, respectively), and data transferred between these registers is written to memory and subsequently read back from the first-level (L1) cache 506, alternative embodiments of the invention may use different methods (e.g., using a single set of registers or including a communication path that allows data to be transferred between these two register sets without being written and read back).

[0105] The local subset 504 of the L2 cache is part of the global L2 cache, which is divided into multiple separate local subsets, one for each processor core. Each processor core has a direct access path to its own local subset 504 of the L2 cache. Data read by a processor core is stored in its L2 cache subset 504 and can be accessed quickly in parallel with other processor cores accessing their own local L2 cache subsets. Data written by a processor core is stored in its own L2 cache subset 504 and is dumped from other subsets if necessary. The ring network ensures the consistency of shared data. The ring network is bidirectional to allow agents such as processor cores, L2 caches, and other logic blocks to communicate with each other within the chip. In some embodiments, each ring data path is 1024 bits wide in each direction.

[0106] Figure 5B This is an embodiment of the present invention. Figure 5A An expanded diagram of a portion of the processor core. Figure 5B This includes the L1 data cache 506A portion of L1 cache 504, and further details regarding vector unit 510 and vector register 514. Specifically, vector unit 510 is a 16-wide vector processing unit (VPU) (see 16-wide ALU 528) that executes one or more of integer, single-precision floating-point, and double-precision floating-point instructions. This VPU supports mixing of register inputs via mixing unit 520, numerical conversion via value conversion units 522A-B, and copying of memory inputs via copy unit 524.

[0107] Processor with integrated memory controller and graphics device

[0108] Figure 6 This is a block diagram of a processor 600 according to an embodiment of the present invention, which may have more than one core, may have an integrated memory controller, and may have an integrated graphics device. Figure 6 The solid-line box illustration shows a processor 600 having a single core 602A, a system agent 610, and a set 616 of one or more bus controller units, while the optional additional illustration with dashed boxes shows an alternative processor 600 having multiple cores 602A-N, a set 614 of one or more integrated memory controller units from the system agent units 610, and dedicated logic 608.

[0109] Therefore, different implementations of processor 600 may include: 1) a CPU, wherein dedicated logic 608 is integrated graphics and / or scientific (throughput) logic (which may include one or more cores), and cores 602A-N are one or more general-purpose cores (e.g., general-purpose ordered cores, general-purpose out-of-order cores, or a combination of both); 2) a coprocessor, wherein cores 602A-N are a large number of dedicated cores designed primarily for graphics and / or scientific (throughput); and 3) a coprocessor, wherein cores 602A-N are a large number of general-purpose ordered cores. Thus, processor 600 may be a general-purpose processor, coprocessor, or dedicated processor, such as, for example, a network or communication processor, a compression engine, a graphics processor, a GPGPU (General-Purpose Graphics Processing Unit), a high-throughput integrated many-core (MIC) coprocessor (including 30 or more cores), an embedded processor, etc. The processor may be implemented on one or more chips. Processor 600 may be part of one or more substrates, and / or may be implemented on one or more substrates using any of a variety of process technologies (e.g., BiCMOS, CMOS, or NMOS).

[0110] The memory hierarchy includes one or more cache levels within cores 604A-N, a set 606 of one or more shared cache units, and external memory (not shown) coupled to a set 614 of integrated memory controller units. The set 606 of shared cache units may include one or more intermediate-level caches, such as Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache, Last Level Cache (LLC), and / or combinations thereof. While in one embodiment, ring-based interconnect units 612 interconnect integrated graphics logic 608, the set 606 of shared cache units, and system proxy units 610 / (multiple) of integrated memory controller units 614, alternative embodiments may use any number of known techniques to interconnect such units. In one embodiment, consistency is maintained between one or more cache units 606 and cores 602A-N.

[0111] In some embodiments, one or more cores 602A-N can be multithreaded. System agent 610 includes those components that coordinate and operate core 602A-N. System agent unit 610 may include, for example, a power control unit (PCU) and a display unit. The PCU may be, or may include, the logic and components required to regulate the power state of core 602A-N and integrated graphics logic 608. The display unit is used to drive one or more externally connected displays.

[0112] The 602A-N cores can be homogeneous or heterogeneous in terms of their instruction set architecture; that is, two or more cores in the 602A-N cores may be able to execute the same instruction set, while other cores may be able to execute only a subset of that instruction set or a different instruction set.

[0113] Exemplary computer architecture

[0114] Figures 7-10 This is a block diagram of an exemplary computer architecture. Other system designs and configurations known in the art for laptops, desktops, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, cellular phones, portable media players, handheld devices, and various other electronic devices are also suitable. Generally, a wide variety of systems or electronic devices capable of incorporating processors and / or other execution logic as disclosed herein are generally suitable.

[0115] Now for reference Figure 7 The diagram illustrates a system 700 according to an embodiment of the present invention. System 700 may include one or more processors 710, 715 coupled to a controller hub 720. In one embodiment, the controller hub 720 includes a graphics memory controller hub (GMCH) 790 and an input / output hub (IOH) 750 (which may be on separate chips); the GMCH 790 includes memory and a graphics controller, to which a memory 740 and a coprocessor 745 are coupled; the IOH 750 couples an input / output (I / O) device 760 to the GMCH 790. Alternatively, one or both of the memory and the graphics controller may be integrated within a processor (as described herein), with the memory 740 and the coprocessor 745 directly coupled to the processor 710, and the controller hub 720 and the IOH 750 residing on a single chip.

[0116] The optionality of the additional processor 715 is in Figure 7 The numbers are indicated by dashed lines. Each processor 710, 715 may include one or more of the processing cores described herein, and may be a version of processor 600.

[0117] The memory 740 may be, for example, dynamic random access memory (DRAM), phase-change memory (PCM), or a combination of both. In at least one embodiment, the controller hub 720 communicates with the processors(s)(s) 710, 715 via a multi-branch bus such as a front-side bus (FSB), a point-to-point interface, or a similar connection 795.

[0118] In one embodiment, the coprocessor 745 is a dedicated processor, such as, for example, a high-throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, and so on. In one embodiment, the controller hub 720 may include an integrated graphics accelerator.

[0119] There can be various differences between physical resources 710 and 715 in terms of a range of quality metrics, including architecture, microarchitecture, thermal and power consumption characteristics.

[0120] In one embodiment, processor 710 executes instructions that control general-type data processing operations. Embedded within these instructions may be coprocessor instructions. Processor 710 recognizes these coprocessor instructions as having a type that should be executed by an attached coprocessor 745. Therefore, processor 710 issues these coprocessor instructions (or control signals representing coprocessor instructions) to coprocessor 745 on a coprocessor bus or other interconnect. Coprocessors 745(a) receive and execute the received coprocessor instructions.

[0121] See now Figure 8 The diagram shown is a block diagram of a first, more specific, exemplary system 800 according to an embodiment of the present invention. Figure 8 As shown, the multiprocessor system 800 is a point-to-point interconnect system and includes a first processor 870 and a second processor 880 coupled via a point-to-point interconnect 850. Each of processors 870 and 880 may be a version of processor 600. In one embodiment of the invention, processors 870 and 880 are processors 710 and 715, respectively, and coprocessor 838 is coprocessor 745. In another embodiment, processors 870 and 880 are processor 710 and coprocessor 745, respectively.

[0122] Processors 870 and 880 are shown as including integrated memory controller (IMC) units 872 and 882, respectively. Processor 870 also includes point-to-point (PP) interfaces 876 and 878 as part of its bus controller unit; similarly, the second processor 880 includes PP interfaces 886 and 888. Processors 870 and 880 can exchange information via a PP interface 850 using point-to-point (PP) interface circuits 878 and 888. Figure 8 As shown, IMC 872 and 882 couple the processor to the corresponding memory, namely memory 832 and memory 834, which may be portions of the main memory locally attached to the corresponding processor.

[0123] Processors 870 and 880 can each exchange information with chipset 890 via their respective PP interfaces 852 and 854 using point-to-point interface circuits 876, 894, 886, and 898. Chipset 890 can optionally exchange information with coprocessor 838 via high-performance interface 892. In one embodiment, coprocessor 838 is a dedicated processor, such as, for example, a high-throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, etc.

[0124] A shared cache (not shown) may be included in either processor or external to both processors but connected to them via a PP interconnect, such that if the processors are in a low-power mode, the local cache information of either or both processors may be stored in the shared cache.

[0125] Chipset 890 can be coupled to first bus 816 via interface 896. In one embodiment, first bus 816 may be a peripheral component interconnect (PCI) bus or a bus such as PCI fast bus or another I / O interconnect bus, but the scope of the invention is not limited thereto.

[0126] like Figure 8 As shown, various I / O devices 814 may be coupled to a first bus 816 together with a bus bridge 818, which couples the first bus 816 to a second bus 820. In one embodiment, one or more additional processors 815, such as a coprocessor, a high-throughput MIC processor, a GPGPU, an accelerator (such as, for example, a graphics accelerator or digital signal processing (DSP) unit), a field-programmable gate array, or any other processor, are coupled to the first bus 816. In one embodiment, the second bus 820 may be a low pin count (LPC) bus. In one embodiment, various devices may be coupled to the second bus 820, including, for example, a keyboard and / or mouse 822, a communication device 827, and a storage unit 828, such as a disk drive that may include instruction / code and data 830, or other mass storage devices. Additionally, audio I / O 824 may be coupled to the second bus 820. Note that other architectures are possible. For example, instead of… Figure 8 The point-to-point architecture allows the system to implement multi-branch buses or other similar architectures.

[0127] Now for reference Figure 9 The diagram shown is a block diagram of a second, more specific, exemplary system 900 according to an embodiment of the present invention. Figure 8 and 9 Similar elements in the figure use similar reference numerals, and from Figure 9 The middle part is omitted Figure 8certain aspects to avoid confusion Figure 9 Other aspects.

[0128] Figure 9 The illustrated processors 870 and 880 may include integrated memory and I / O control logic (“CL”) 971 and 982, respectively. Therefore, CL 972 and 982 include an integrated memory controller unit and I / O control logic. Figure 9 The diagram shows that not only are the memories 832 and 834 coupled to CLs 972 and 982, but the I / O device 914 is also coupled to the control logic 972 and 982. The conventional I / O device 915 is coupled to the chipset 890.

[0129] Now for reference Figure 10 The diagram shown is a block diagram of a SoC 1000 according to an embodiment of the present invention. Figure 6 Similar elements in the figure use similar reference numerals. Additionally, dashed boxes are optional features on more advanced SoCs. Figure 10 In this configuration, multiple interconnect units 1002 are coupled to: an application processor 1010, which includes a set of one or more cores 602A-N, cache units 604A-N, and multiple shared cache units 606; a system proxy unit 610; multiple bus controller units 616; multiple integrated memory controller units 614; a set of one or more coprocessors 1020, which may include integrated graphics logic, an image processor, an audio processor, and a video processor; a static random access memory (SRAM) unit 1030; a direct memory access (DMA) unit 1032; and a display unit 1040 for coupling to one or more external displays. In one embodiment, the multiple coprocessors 1020 include dedicated processors, such as, for example, network or communication processors, compression engines, GPGPUs, high-throughput MIC processors, or embedded processors, etc.

[0130] The various embodiments of the mechanisms disclosed herein can be implemented in hardware, software, firmware, or a combination of such implementations. Embodiments of the invention can be implemented as computer programs or program code executable on a programmable system including at least one processor, a storage system (including volatile and non-volatile memories and / or storage elements), at least one input device, and at least one output device.

[0131] Program code (such as, Figure 8The code 830 shown in the diagram is applied to input instructions to perform the functions described herein and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, the processing system includes any system having a processor, such as, for example, a digital signal processor (DSP), a microcontroller, an application-specific integrated circuit (ASIC), or a microprocessor.

[0132] The program code can be implemented using a high-level procedural or object-oriented programming language to communicate with the processing system. Assembly or machine language can also be used if needed. In fact, the mechanisms described herein are not limited to any particular programming language. In any case, the language can be a compiled or interpreted language.

[0133] One or more aspects of at least one embodiment can be implemented by representational instructions stored on a machine-readable medium, which represent various logics in a processor, and which, when read by a machine, cause the machine to manufacture logic for performing the techniques described herein. Such representations, referred to as “IP cores,” can be stored on tangible machine-readable media and can be supplied to various customers or production facilities for loading into manufacturing machines that actually manufacture the logic or processor.

[0134] Such machine-readable storage media can include, but are not limited to, non-transitory, tangible arrangements of articles made or formed by a machine or device, including storage media such as hard disks; any other type of disk, including floppy disks, optical disks, compact disc read-only memory (CD-ROM), rewritable compact discs (CD-RW), and magneto-optical disks; semiconductor devices such as read-only memory (ROM), random access memory (RAM) such as dynamic random access memory (DRAM) and static random access memory (SRAM), erasable programmable read-only memory (EPROM), flash memory, electrically erasable programmable read-only memory (EEPROM); phase-change memory (PCM); magnetic cards or optical cards; or any other type of medium suitable for storing electronic instructions.

[0135] Therefore, embodiments of the invention also include a non-transitory tangible machine-readable medium containing instructions or design data, such as a hardware description language (HDL), that defines the architectures, circuits, devices, processors, and / or system features described herein. These embodiments are also referred to as program products.

[0136] Simulation (including binary transformation, code transformation, etc.)

[0137] In some cases, instruction translators can be used to translate instructions from a source instruction set to a target instruction set. For example, an instruction translator can transform instructions (e.g., using static binary transformation, including dynamically compiled binary transformation), modify, emulate, or otherwise convert them into one or more other instructions to be processed by the kernel. Instruction translators can be implemented in software, hardware, firmware, or a combination thereof. Instruction translators can be on the processor, off the processor, or partially on and partially off the processor.

[0138] Figure 11 This is a block diagram illustrating the use of a software instruction converter to convert binary instructions in a source instruction set into binary instructions in a target instruction set, according to an embodiment of the present invention. In the illustrated embodiment, the instruction converter is a software instruction converter; however, alternatively, the instruction converter can be implemented using software, firmware, hardware, or various combinations thereof. Figure 11 A program of the form of a high-level language 1102 can be compiled using a first compiler 1104 to generate first binary code (e.g., x86) 1106 that can be natively executed by a processor 1116 having at least one first instruction set core. In some embodiments, a processor 1116 having at least one first instruction set core represents any processor that performs substantially the same function as an Intel processor having at least one x86 instruction set core by compatibly executing or otherwise performing: 1) an essential portion of the instruction set of an Intel x86 instruction set core, or 2) a version of object code for an application or other software aimed at running on an Intel processor having at least one x86 instruction set core to achieve substantially the same results as an Intel processor having at least one x86 instruction set core. The first compiler 1104 represents a compiler operable to generate binary code 1106 (e.g., object code) in the first instruction set, which can be executed on the processor 1116 having at least one first instruction set core, with or without additional linking processing. Similarly, Figure 11A program of the form of a high-level language 1102 can be compiled using an alternative instruction set compiler 1108 to generate alternative instruction set binary code 1110 that can be natively executed by a processor 1114 that does not have at least one first instruction set core (e.g., a processor with a core that executes the MIPS instruction set of MIPS Technologies, Inc., Sunnyvale, California, and / or the ARM instruction set of ARM Holdings, Inc., Sunnyvale, California). An instruction converter 1112 is used to translate the first binary code 1106 into code that can be natively executed by the processor 1114 that does not have a first instruction set core. This translated code is unlikely to be identical to the alternative instruction set binary code 1110 because an instruction converter capable of doing so would be difficult to manufacture; however, the translated code will perform general operations and consists of instructions from the alternative instruction set. Therefore, the instruction converter 1112 represents, through emulation, simulation, or any other process, software, firmware, hardware, or a combination thereof that allows a processor or other electronic device without a first instruction set processor or core to execute the first binary code 1106.

[0139] Exemplary digital signal processing architecture

[0140] One embodiment of the invention includes circuitry and / or logic for processing digital signal processing (DSP) instructions. Specifically, one embodiment includes a multiplication-accumulation (MAC) architecture with eight 16×16-bit multipliers and two 64-bit accumulators. The instruction set architecture (ISA) described below can handle various multiplication and MAC operations on 128-bit compressed (8-bit, 16-bit, or 32-bit data elements) integer, fixed-point, and complex data types. Additionally, some instructions have direct support for highly efficient Fast Fourier Transform (FFT) and Finite Impulse Response (FIR) filtering, as well as post-processing of accumulated data through shift, rounding, and saturation operations.

[0141] One embodiment of the new DSP instructions uses opcode encoding based on the VEX.128 prefix, and several instructions in the SSE / SSE2 / AVX instructions for post-processing of data disposal are used in conjunction with the DSP ISA. VEX-encoded 128-bit DSP instructions with memory operands can have relaxed memory alignment requirements.

[0142] In one embodiment, the instructions also support various integer and fixed-point data types, including:

[0143] 1) It has more than 16 bits of Q31 data type for signals that require analog-to-digital conversion (ADC) and digital-to-analog conversion (DAC);

[0144] 2) The Q15 data type commonly used in DSP algorithms;

[0145] 3) 16-bit complex number data type; and

[0146] 4) 32-bit complex number data type.

[0147] The instruction set architecture described in this paper is designed for a wide range of standard DSPs (e.g., FFT, filtering, pattern matching, correlation, multinomial estimation, etc.) and statistical operations (e.g., mean, moving average, variance, etc.).

[0148] Target applications of embodiments of the present invention include sensors, audio, classification tasks for computer vision, and speech recognition. The DSP ISA described herein includes a broad range of instructions applicable to deep neural networks (DNNs), automatic speech recognition (ASR), sensor fusion using Kalman filtering, and other major DSP applications. Given a weight sequence {w1, w2, ... w... k} and the input sequence {x1,x2,x3,…x} n Many image processing and machine learning tasks require computation of y i =w1x i +w2x i+1 +…+w k x i+k-1 The defined result sequence {y1,y2,y3,…y n+1-k}

[0149] Figure 12 The illustration shows an exemplary processor 1255 on which embodiments of the present invention can be implemented, the exemplary processor 1255 including multiple cores 0-N for executing multiple instruction threads simultaneously. The illustrated embodiment includes DSP instruction decoding circuitry / logic 1231 within a decoder 1230 and DSP instruction execution circuitry / logic 1241 within an execution unit 1240. These pipeline components can perform the operations described herein in response to the decoding and execution of DSP instructions. Although in Figure 12 Details of only a single core (core 0) are shown, but it will be understood that each of the other cores of the processor 1255 may include similar components.

[0150] Before describing the specific details of embodiments of the invention, a description of the components of an exemplary processor 1255 is provided directly below. Multiple cores 0-N may each include a memory management unit 1290 for performing memory operations (e.g., load / store operations), a set of general-purpose registers (GPRs) 1205, a set of vector registers 1206, and a set of mask registers 1207. In one embodiment, multiple vector data elements are compressed into each vector register 1206, each vector register 1206 may have a 512-bit width for storing two 256-bit values, four 128-bit values, eight 64-bit values, sixteen 32-bit values, etc. However, the basic principles of the invention are not limited to any particular size / type of vector data. In one embodiment, mask register 1207 includes eight 64-bit operand mask registers (e.g., implemented as mask registers k0-k7 as described herein) for performing bitmasking operations on the values ​​stored in vector registers 1206. However, the basic principles of the invention are not limited to any particular mask register size / type.

[0151] Each core 0-N may include a dedicated Level 1 (L1) cache 1212 and a Level 2 (L2) cache 1211 for caching instructions and data according to a specified cache management policy. The L1 cache 1212 includes a separate instruction cache 1220 for storing instructions and a separate data cache 1221 for storing data. Instructions and data stored in each processor cache are managed at the granularity of cache lines, which may be of fixed size (e.g., 64 bytes, 128 bytes, or 512 bytes in length). Each core in this exemplary embodiment has an instruction fetch unit 1210 for fetching instructions from main memory 1200 and / or a shared Level 3 (L3) cache 1216. The instruction fetch unit 1210 includes various known components, including: a next instruction pointer 1203 for storing the address of the next instruction to be fetched from memory 1200 (or one of the caches); a translation lookup buffer (ITLB) 1204 for storing a mapping of recently used virtual to physical instruction addresses to improve address translation speed; a branch prediction unit 1202 for speculatively predicting instruction branch addresses; and a branch target buffer (BTB) 1201 for storing branch addresses and target addresses.

[0152] As mentioned, the decoding unit 1230 includes DSP instruction decoding circuitry / logic 1231 for decoding the DSP instructions described herein into micro-operations or "uops" and DSP instruction execution circuitry / logic 1241 for executing the DSP instructions. The write-back / retreat unit 1250 retres the executed instructions and writes back the results.

[0153] An embodiment of the first instruction is represented as VPRCPUFW xmm1,xmm2 / m128, where xmm2 / m128 is the source register or memory location storing the input word value whose reciprocal will be calculated, and xmm1 is the destination register for storing the reciprocal result. The second instruction, represented as VPRCPUFD xmm1,xmm2 / m128, takes the reciprocal of the double-word value stored in xmm2 / m128 and stores the reciprocal in xmm1.

[0154] Figure 13 The illustration shows exemplary data elements and bit distributions for exemplary source and / or destination registers (SRCx / DESTx). As illustrated, data elements can be compressed into source and / or destination registers in words (16 bits), double words (32 bits), and / or quad words (64 bits). In some embodiments that handle complex numbers, the real and imaginary parts may be stored in adjacent data element locations. For example, the real part may be stored as data element A, and the corresponding imaginary part may be stored as data element B. However, in some embodiments described herein, including reciprocal instructions and square root reciprocal instructions, the compressed data elements do not represent complex numbers. Instead, in these embodiments, the compressed data elements are real words and double words.

[0155] Figure 14 The diagram illustrates an exemplary architecture for executing various DSP instructions, including at least some of the operations required for fractional reciprocal and square root reciprocal instructions. The general operation of this architecture will be described first, followed by a specific implementation of the reciprocal instruction. When a DSP instruction is executed, one or more compacted word, double-word, or quad-word values ​​are stored in registers SRC 1401 and / or SRC 1402. A set of multipliers 1405 multiplies the selected compacted data element in SRC 1401 with the selected compacted data element in SRC 1402. Different data element sizes and different combinations of compacted data elements can be selected for the multiplication based on the specific DSP instruction being executed. Adder networks 1410-1411 can then add / subtract the products obtained from multiplications in different combinations, according to the instructions.

[0156] Depending on the instructions, accumulators 1420-1421 can combine the results generated by the selected multipliers 1405 and / or adder networks 1410-1411 with the accumulated results in the SRC / DEST register 1460. Saturation units 1440-1441 generate saturated data elements from the accumulated results (again, depending on the instructions), and output multiplexer 1450 forwards the final result to the SRC / DEST register 1460.

[0157] Depending on the instructions, various other operations can be performed, such as shifting, fetching, loading, storing, permuting, zero-extending, sign-extending, and rounding, to name just a few. Furthermore, the product generated by multiplier 1405 and the result generated by adder networks 1410-1411 can be stored in temporary registers or memory locations not shown. Some of these temporary storage locations are referred to below as ftmp[n], where n is an integer identifying the particular temporary storage location.

[0158] In one embodiment, the following functions, which operate on unsigned words and double words, are used in a fixed-point DSP algorithm:

[0159] y = 1 / x (reciprocal of a fraction); and

[0160] y = 1 / sqrt(x) (reciprocal of the square root).

[0161] The following section first describes an example of the fraction reciprocal instruction in Part A. Then, in Part B, an example of the square root reciprocal instruction is described.

[0162] A. Examples for performing fractional reciprocal operations on compressed data elements

[0163] One embodiment of the invention includes a first instruction for determining the reciprocal of an unsigned word and a second instruction for determining the reciprocal of an unsigned double word. Within the source and destination registers described herein, word values ​​can be stored as compacted 16-bit data elements, and double-word values ​​can be stored as compacted 32-bit data elements.

[0164] Given an input value x, one embodiment of the present invention calculates y = 1 / x. A first instruction (e.g., VPRCPUFD) can be executed for a double-word value of x, and a second instruction (e.g., VPRCPUFW) can be executed for a word value of x. The double-word implementation will be described first, followed by the word implementation.

[0165] 1. Exemplary double-word reciprocal operation

[0166] In one embodiment, the input x is a double word with an unsigned Q0.32 format. Q specifies the fixed-point number format, which specifies the number of fractional digits and the potential number of integer digits. For example, a Q1.14 number has 1 integer digit and 14 fractional digits. In the current application, the Q0.32 number format for x has 32 fractional digits and is therefore scaled by 2. 32 In one embodiment, the range of x is set between 0.5 and 1 (i.e., [0.5, 1]) or [0x80000000, 0xFFFFFFFF]). Furthermore, in one embodiment, the resulting y is an unsigned Q1.31 number and is therefore scaled by 2. 31In one embodiment, the permissible range of y is between 1 and 2 (i.e., [1,2] or [0x80000000,0xFFFFFFFF]). In one implementation, the maximum absolute error of the reciprocal operation is 1.09 ulp, and the reciprocal is estimated to be almost 16 bits using a 3rd-order polynomial.

[0167] Figure 15 The diagram illustrates an exemplary execution circuit 1240 for executing the fraction reciprocal instruction y = 1 / x, according to the above specifications. Figure 15 The execution circuitry may include components from... Figure 14 The components of the DSP architecture can be used and / or different execution circuits can be employed. In one embodiment, the input value X comprises a double-word value (32 bits), where bits b30 and b29 are used to index the coefficient table shown. Each row in the coefficient table includes a different set of coefficients c3. n c2 n c1 n and c0 n The set of values ​​for b30 and b29 is selected. In one embodiment, a substitution instruction such as VPERMILPS is executed to read coefficients from rows of a coefficient table identified by the values ​​of b30 and b29. For example, based on a specified control value, the VPERMILPS instruction can retrieve different coefficients from different register or memory locations.

[0168] In one embodiment, multiplier 1405 then reads a coefficient from one of source registers 1401-1402 (via input multiplexer 1403) and as... Figure 15 The indicated multiplication is of the compressed values. For example, in the implementation shown, c32 is multiplied by R. 3 Multiply c22 by R 2 And multiply c12 by R. The adder network 1410-1411 then multiplies the resulting products c12*R and c22*R. 2 c32*R 3 Adding c02 to generate the result: c02 + c12*R + c22*R 2 +c32*R 3 .

[0169] In one embodiment, the Newton-Rapson logic / circuit 1510 applies the Newton-Rapson approximation technique to approximately double the accuracy of the result. This can be achieved by calculating the relative error for the initial approximation and then applying a refinement step to the approximation. However, the basic principle of the invention does not require the Newton-Rapson technique. In one embodiment, for out-of-range inputs (e.g., x < 0.5), the output is 0xFFFFFFFF.

[0170] In one embodiment, the word reciprocal operation is implemented in a similar manner, but using word values ​​instead of double word values. The overall computation is also y = 1 / x, where the input x is in unsigned Q0.16 format and is therefore scaled by 2. 16 The range of x is in [0.5, 1] ​​or [0x8000, 0xFFFF], and the result y uses the unsigned Q1.15 format and is therefore scaled by 2. 15 The range of y is [1,2] or [0x8000,0xFFFF].

[0171] In the word implementation, the coefficient table is an 8-entry table, and the three leading bits of the input (i.e., bits 14, 13, and 12 in one embodiment) are used as table indexes to retrieve coefficient c3 from the 8-entry table. n c2 n c1 n and c0 n (where n is in the range [0,7]). The remaining input bits [11:0] of the fraction R are used as the polynomial c3*R. 3 +c2*R 2 The polynomial is defined as x + c1*R + c0. The result of evaluating this polynomial is the output of the instruction (for inputs within the range). For inputs outside the range (e.g., x < 0.5), the output is 0xFFFF.

[0172] Similar to the double-word reciprocal instruction described above, multiplier 1405 multiplies the input value (R) by a coefficient, and adder networks 1410-1411 add / subtract the results (as shown in the code example below). In the case of a double-word instruction, Newton-Raphson logic / circuit 1510 can apply Newton-Raphson estimation techniques to the result to approximately double the accuracy. In one embodiment, this is achieved by calculating a relative error for the initial approximation and then applying a refinement step to the approximation. However, the basic principle of the present invention does not require Newton-Raphson techniques.

[0173] exist Figure 16 The diagram illustrates a method according to an embodiment of the present invention. This method can be implemented within the context of the processor and system architecture described above, but is not limited to any particular system architecture.

[0174] At 1601, the countdown instruction is retrieved, which has fields for the opcode, the compressed data source operand, and the compressed data destination operand. At 1602, the countdown instruction is decoded to generate a decoded countdown instruction (e.g., decoded into multiple micro-operations that perform the various operations described herein).

[0175] At 1603, the coefficient value required to perform the countdown operation is retrieved (e.g., from cache / memory) and stored in a temporary register or other storage location. Additionally, input data is retrieved and stored in a source register (e.g., SRC 1401). As mentioned, double-word countdown instructions use double-word values ​​to determine the countdown, while word countdown instructions use word values. Therefore, the input data can be stored in the first source register as either a compressed double-word (32-bit) or a compressed word (16-bit) value, depending on the implementation. As mentioned, in one embodiment, the source register is a 128-bit compressed data register. The operations of the countdown instructions are scheduled. For example, the micro-operations that decode the instructions into can be queued for execution on multiple different functional units of the execution circuitry.

[0176] At 1604, the first decoded instruction is executed by using a first portion of the input data as an index value to identify the coefficients to be used from the coefficient table. In one embodiment, the coefficient table is distributed across multiple temporary storage locations. In an alternative embodiment, it may be stored in... Figure 14 In one of the source registers shown. Regardless of where it is stored, a substitution instruction is executed to perform a lookup operation by using the first portion of the input data as an index value (described in detail below). In one embodiment, the first portion of the input data includes bits 29 and 30 for a double-word value, and bits 12, 13, and 14 for a word value. Thus, in a double-word implementation, bits 29-30 are used for one of four entries in the index coefficient table, and in a word implementation, bits 12-14 are used for one of eight entries in the index coefficient table.

[0177] Once the coefficients are identified, multiplication is performed on the second part (R) of the input data and / or the coefficients to determine a temporary value c3*R. 3 c2*R 2 And c1*R. Then according to the polynomial c3*R 3 +c2*R 2 The addition of `+c1*R+c0` to the temporary value and coefficients generates the first result. If the Newton-Raphson technique is used, these are applied to the first result to generate the final result. At 1605, the final result is stored in the compacted destination register.

[0178] 2. Example code sequence for double-word reciprocal operations

[0179] a. Countdown code sequence

[0180] In one embodiment, when a fraction reciprocal instruction is executed on a two-word input, the architecture performs the following sequence of operations:

[0181]

[0182]

[0183]

[0184]

[0185]

[0186]

[0187] b. Analysis of the reciprocal code sequence

[0188] In the code above, each of the four possible values ​​for the four coefficients c0, c1, c2, and c3 is specified. For example, the four possible values ​​for c3 are 0xA2D2ED1E, 0x488414BD, 0x250AB12B, and 0x14D9F815. Additionally, the variables RMASK and NEG_MASK are set (i.e., initialized to 0xffffffff), and the variable 1 is also set (initialized to 0x80000000f0000000).

[0189] The "fmtpn" variable in the code identifies different temporary storage locations. For example, the initial instruction vmovdqa ftmp0,xmm2 / m128 moves the input value X from the xmm2 register (or 128-bit memory location) to the temporary storage location ftmp0.

[0190] The instruction vector AND instruction vandps then performs a bitwise AND operation between the source value X stored in fmtp0 and the RMASK value, based on the requirements of the reciprocal calculation, to reduce the source value to R. The resulting value is stored in ftmp6. Then, with both the source and destination set to ftmp6, the vector AND instruction vpanddd is executed to adjust the scaling factor used for the reciprocal.

[0191] Then, the right-shift compact data instruction vpsrld is executed to isolate the two leading bits of the fraction value from ftmp0. Specifically, the value is shifted right by 29, thereby separating the two index bits (e.g., ...) Figure 15 The bits shown (b29 and b30) are placed in the least significant bit position of the temporary storage ftmp1.

[0192] The following instruction sequence will move the coefficient data of c3 and c1 to ftmp5 and ftmp3 respectively:

[0193] vmovdqa ftmp5,XMMWORD PTR[__c3]

[0194] vmovdqa ftmp3,XMMWORD PTR[__c1]

[0195] The vpermilps substitution instruction then uses the index values ​​in ftmp1 (including b29 and b30 or the input values) to select specific c3 and c1 compressed data values ​​from ftmp5 and ftmp3 respectively (which is equivalent to a table lookup using these index values):

[0196] vpermilps ftmp5,ftmp5,ftmp1 / / c3

[0197] vpermilps ftmp3,ftmp3,ftmp1 / / c1

[0198] Multiplication operation (c3*2) 31 )*(R*2 32 This can be achieved through the following set of instructions:

[0199] vpmuludq ftmp4,ftmp5,ftmp6

[0200] vmovdqa XMMWORD PTR[temp1],ftmp6

[0201] vpmuludhhq ftmp5,ftmp5,ftmp6

[0202] In one embodiment, the mixing instruction can then be used to combine the results from the two multiplications into a single SIMD register (two 32x32->64-bit MUL instructions are used for each 4-way SIMD multiplication step). Specifically, the operation c3*R*2 31 This is achieved by the right shift instruction `vpsrlq`, which shifts the 64-bit product in `ftmp4` by 32 bits (aligning the relevant 32 bits), followed by the blending instruction `vpblendw`, which combines the relevant word data elements from `ftmp4` and `ftmp5` into `ftmp5`.

[0203] vpsrlq ftmp4,ftmp4,32

[0204] vpblendw ftmp5,ftmp5,ftmp4,0x33

[0205] Use the double multiplication instruction to determine the value c1*R*2 (32+31) The double multiplication instruction multiplies the different components of c1 stored in ftmp3 by the components of the source value stored in ftmp6:

[0206] vpmuludq ftmp2,ftmp3,ftmp6

[0207] vpmuludhhq ftmp3,ftmp3,ftmp6

[0208] Then, the value c1*R*2 is determined by right shifting followed by mixing. 31 As discussed above regarding c3:

[0209] vpsrlq ftmp2,ftmp2,32

[0210] vpblendw ftmp3,ftmp3,ftmp2,0x33

[0211] The value R2*2 is determined by using the double multiplication instruction discussed above and different components of the source data in ftmp6. 64 :

[0212] vpmuludq ftmp7,ftmp6,ftmp6

[0213] VPMULUDHHQ ftmp6,ftmp6,ftmp6

[0214] Then, the value R is determined using the right shift and blend instructions discussed above. 2 *2 32 :

[0215] vpsrlq ftmp7,ftmp7,32

[0216] vpblendw ftmp6,ftmp6,ftmp7,0x33

[0217] In one embodiment, the following sequence of instructions moves coefficient data from c2 and c0 to ftmp4 and ftmp2 respectively, and then uses the substitution instruction vpermilps to perform table lookups on c2 and c0 respectively (as discussed above for c3 and c1):

[0218] vmovdqa ftmp4,XMMWORD PTR[__c2]

[0219] vmovdqa ftmp2,XMMWORD PTR[__c0]

[0220] vpermilps ftmp4,ftmp4,ftmp1 / / c2

[0221] vpermilps ftmp2,ftmp2,ftmp1 / / c0

[0222] Use the subtraction command `vpsubd ftmp4,ftmp4,ftmp5` to determine the value (c2-c3*R)*2. 31 And the value (c0-c1*R)*2 is determined using the subtraction command vpsubd ftmp2,ftmp2,ftmp3. 31 .

[0223] In one embodiment, the value (c2-c3*R)*R is then determined via double multiplication operations vpmuludq ftmp7,ftmp6,ftmp4 and vpmuludhhq ftmp6,ftmp6,ftmp4. 2 *2 63 The value (c2-c3*R)*R is determined by the right shift and blend operations vpsrlq ftmp7,ftmp7,32 and vpblendw ftmp6,ftmp6,ftmp7,0x33. 2 *2 31 The value (c0-c1*R)*2 is determined using the addition instruction vpaddd ftmp6,ftmp6,ftmp2. 31 +(c2-c3*R)*R 2 *2 31 .

[0224] At this stage, the initial approximation is stored in ftmp6:

[0225] vmovdqa ftmp4,XMMWORD PTR[ONE]

[0226] vmovdqa ftmp2,XMMWORD PTR[ONE]

[0227] The value x*rcp*2 is determined using the double multiplication instructions vpmuludq ftmp1,ftmp0,ftmp6 and vpmuludhhq ftmp5,ftmp0,ftmp6. 63 The value eps*2 is determined via the subtraction instructions vpsubq ftmp4,ftmp4,ftmp1 and vpsubq ftmp2,ftmp2,ftmp5. 63 = (1-x*rcp)*2 63 .

[0228] In this example, the 64-bit relative error term is in (ftmp4, ftmp2). In one embodiment, the correction mask is prepared as follows:

[0229] vpsrad ftmp0,ftmp0,32

[0230] vpxor ftmp0,ftmp0,XMMWORD PTR[NEG_MASK]

[0231] / / For inputs within the range, ftmp0 = 0; otherwise, 0xFFFFFFFF

[0232] The following commands are used to increase eps*2 32 The accuracy (for example, as part of the Newton-Rapson technique mentioned above). The following two shift instructions shift the values ​​in ftmp4 and ftmp2 to the right and left by a specified amount (31 and 1, respectively):

[0233] vpsrlq ftmp4,ftmp4,31

[0234] vpsllq ftmp2,ftmp2,1

[0235] The blending instruction `vpblendw` then blends the selected data elements from `ftmp4` and `ftmp2` and stores them in `ftmp4`:

[0236] vpblendw ftmp4,ftmp2,ftmp4,0x33

[0237] The vpsrad command then uses vpsrad ftmp3,ftmp4,31 to determine the sign of the value (eps) in ftmp4.

[0238] Because eps is signed, the following correction term is then used, but the unsigned MUL operation is used:

[0239] vpandn ftmp3,ftmp3,ftmp6

[0240] Specifically, the AND NOT instruction is used by using values ​​from ftmp6 and ftmp3 and the result is stored in ftmp3.

[0241] The following two multiplication instructions are used to determine the value rcp*eps*2 63 Multiply the selected elements from ftmp4 and ftmp6:

[0242] vpmuludq ftmp2,ftmp6,ftmp4

[0243] vpmuludhhq ftmp6,ftmp6,ftmp4

[0244] Then, the value rcp*eps*2 is determined by executing right shift and blend instructions. 31 :

[0245] vpsrlq ftmp2,ftmp2,32

[0246] vpblendw ftmp6,ftmp6,ftmp2,0x33

[0247] The final result is then determined by adding the element from ftmp3 to ftmp6 and storing the result in ftmp6.

[0248] vpaddd ftmp6,ftmp6,ftmp3

[0249] The result of ftmp6 can be ORed with ftmp to correct out-of-range input (i.e., if out of range, ftmp0 = 0xFFFFFFFFF):

[0250] vpor xmm1,ftmp0,ftmp6

[0251] 3. Example code sequence for word reversal operation

[0252] a. Countdown code sequence

[0253] As mentioned, the overall calculation is y = 1 / x, where the input x is in unsigned Q0.16 format and is therefore scaled by 2. 16 The range of x is in [0.5, 1] ​​or [0x8000, 0xFFFF], and the result y uses the unsigned Q1.15 format and is therefore scaled by 2. 15 The range of y is [1,2] or [0x8000,0xFFFF].

[0254] Coefficient table 1505 is an 8-entry table, and the three leading bits of the input (i.e., bits 14, 13, and 12 in one embodiment) are used as a table index to retrieve coefficient c3 from the 8-entry table. n c2 n c1 n and c0 n (where n is in the range [0,7]). The remaining input bits [11:0] of the fraction R are used as the polynomial c3*R. 3 +c2*R 2 The polynomial is defined as x + c1*R + c0. The result of evaluating this polynomial is the output of the instruction (for inputs within the range). For inputs outside the range (e.g., x < 0.5), the output is 0xFFFF.

[0255]

[0256]

[0257]

[0258]

[0259] b. Analysis of code sequences

[0260] As can be seen from the code above, many of the same techniques used for double-word instructions are applied to the reciprocal instruction. The overall calculation is y = 1 / x, where the input x is in unsigned Q0.16 format and is therefore scaled by 2. 16 The range of x is in [0.5, 1] ​​or [0x8000, 0xFFFF], and the result y uses the unsigned Q1.15 format and is therefore scaled by 2. 15 The range of y is [1,2] or [0x8000,0xFFFF].

[0261] In the word implementation, the coefficient table is an 8-entry table, and the three leading bits of the input (i.e., bits 14, 13, and 12 in one embodiment) are used as table indexes to retrieve coefficient c3 from the 8-entry table. n c2 n c1 n and c0 n (where n is in the range [0,7]). Therefore, the code is c3. n c2 n c1 n and c0 n Specify eight distinct values. For example, specify the values ​​0xC9EC, 0x8146, 0x5690, 0x3C20, 0x2B0E, 0x1FA2, 0x17C3, and 0x1232 for c3. The remaining input bits [11:0] of the fraction R are used as the polynomial c3*R. 3 +c2*R 2 The polynomial is defined as x + c1*R + c0. The result of evaluating this polynomial is the output of the instruction for inputs within the range. For inputs outside the range (e.g., x < 0.5), the output is 0xFFFF.

[0262] B. Implementation example for performing the square root reciprocal operation on compressed data elements

[0263] One embodiment of the invention includes a first instruction for performing a square root reciprocal on an unsigned double word and a second instruction for performing a square root reciprocal on an unsigned double word. Within the source and destination registers described herein, the double word value can be stored as a compressed 32-bit data element, and the double word value can be stored as a compressed 16-bit data element.

[0264] An embodiment of the first instruction is represented as VPRSQRTUFD xmm1,xmm2 / m128, which takes the reciprocal of the square root of the double-word value stored in xmm2 / m128 and stores the reciprocal in xmm1. An embodiment of the second instruction is represented as VPRSQRTUFW xmm1,xmm2 / m128, where xmm2 / m128 is a source register or memory location storing the input word value for which the reciprocal of the square root will be calculated, and xmm1 is a destination register for storing the reciprocal result.

[0265] As described above and Figure 14 These instructions are executed on the illustrated architecture. As previously described, when a DSP instruction is executed, one or more compact word, double word, or quad word values ​​are stored in registers SRC 1401 and / or SRC 1402. The set of multipliers 1405 multiplies the selected compact data element in SRC 1401 with the selected compact data element in SRC 1402. Different data element sizes and different combinations of compact data elements can be selected for the multiplication based on the specific DSP instruction being executed. The adder network 1410-1411 can then add / subtract the products obtained from the multiplications in different combinations, according to the instructions.

[0266] Depending on the instructions, accumulators 1420-1421 can combine the results generated by the selected multipliers 1405 and / or adder networks 1410-1411 with the accumulated results in the SRC / DEST register 1460. Saturation units 1440-1441 generate saturated data elements from the accumulated results (again, depending on the instructions), and output multiplexer 1450 forwards the final result to the SRC / DEST register 1460.

[0267] Various other operations can be performed based on the executed instructions, such as left / right shifting, fetching, loading, storing, permuting, zero-extending, sign-extending, rounding, and performing bitwise operations (e.g., AND, OR, NAND, etc.), to name just a few. Furthermore, the product generated by multiplier 1405 and the result generated by adder networks 1410-1411 can be stored in temporary registers or memory locations not shown. Some of these temporary storage locations are referred to below as FTMPx (where x is an integer identifying a particular temporary storage region).

[0268] 1. Exemplary double-word square root reciprocal operation

[0269] In one embodiment, the value y = 1 / sqrt(x) is determined, where the input x is an unsigned Q0.32 value scaled by 2. 32The range of x is in [0.25, 1] ​​or [0x40000000, 0xFFFFFFFF], and the result y is in unsigned Q1.31 format, scaled by 2. 31 The range of y is [1,2] or [0x80000000,0xFFFFFFFF]. In one embodiment, the maximum absolute error is 1.26 ulp and can be further improved with a loss of approximately 2 cycles as described herein. The reciprocal of the square root can be approximated to almost 7.65 bits (linear interpolation). In the case of the reciprocal instruction described above, the permutation instruction can be used to retrieve 16-bit coefficients from the table (e.g., VPERMW). The relative error is calculated, and then a cubic polynomial is applied.

[0270] In one embodiment, if the initial input is x < 0.5, the input x is "normalized" to [0.5, 1] ​​and bit 31 is set to 0. The leading bits of the "normalized input" (bits 31, 30, 29) are then used as table indexes to retrieve coefficients c0, c1 from an 8-entry table. The remaining input bits (R = bits 28, 27, ..., 0) are used as the argument for c0 + c1 * R, which is the initial approximation of the square root reciprocal (RS) and is good to approximately 7.65 bits. After calculating the relative error eps, the final output is evaluated to be RS + RS * eps * (pc1 + pc2 * eps + pc3 * eps). 2 ), where pc1, pc2 and pc3 are constant coefficients.

[0271] Figure 17 The diagram illustrates an exemplary execution circuit 1240 for executing the square root reciprocal instruction y = 1 / sqrt(x) according to the above specifications. Specifically, the input value X includes the "normalized" input described above, which is a double-word (32-bit) value, where bits b31, b30, and b29 are used to index the coefficient table 1705 shown. Each row in the coefficient table 1705 includes a distinct pair of coefficients c1 n and c0 n The values ​​of b31, b30, and b29 are used to select one pair from the rows. In one embodiment, a substitution instruction is executed to read coefficients from the rows of the coefficient table identified by the values ​​of b31, b30, and b29. The remaining input bits (R = bits 28, 27, ..., 0) are used as arguments to c0 + c1 * R. Specifically, multiplier 1405 performs the multiplication of c1 * R, and adder networks 1410-1411 determine c0 + c1 * R.

[0272] The error evaluation circuit / logic 1710 determines the relative error value eps. After calculating the relative error, the final output value is RS + RS * eps * (pc1 + pc2 * eps + pc3 * eps). 2), where pc1, pc2, and pc3 are constant coefficients and RS = c0 + c1 * R. Therefore, multiplier 1405 performs the operations pc2 * eps and pc3 * eps. 2 And adder network 1410-1411 performs the operation pc1+pc2*eps+pc3*eps 2 Multiplier 1405 uses this value to perform the operation RS*eps*(pc1+pc2*eps+pc3*eps). 2 The adder network generates the final result: RS + RS*eps*(pc1 + pc2*eps + pc3*eps) 2 ).

[0273] In one embodiment, the word implementation of the square root reciprocal instruction operates in a manner similar to that described above. In this embodiment, the input x is in unsigned Q0.16 format, scaled by 2. 16 The word value. The value x is in the range [0.25, 1] ​​or [0x4000, 0xFFFF], and the result y is an unsigned Q1.15 value, scaled by 2. 15 The y-value is in the range [1,2] or [0x8000,0xFFFF]. In one embodiment, the maximum absolute error is 1.23 ulp (which can be further improved with a loss of approximately 2 cycles). The reciprocal of the square root is approximated as a cubic polynomial, where the coefficients are extracted from a lookup table as in the previous embodiment.

[0274] In one embodiment, if the initial input is x < 0.5, the input x is "normalized" to [0.5, 1] ​​and bit 15 is set to 0. The leading bits (bits 15, 14, 13) of the "normalized input" are then used as table indexes to retrieve coefficients c3, c2, c1, c0 from an 8-entry table. The remaining input bits (fraction R = bits 11, 10, ..., 0) are used for the following polynomial c3*R. 3 +c2*R 2 The polynomial is defined as x + c1*R + c0. The result of evaluating this polynomial is the output instruction (for inputs within the range). For inputs outside the range (x < 0.5), the output is 0xFFFF.

[0275] exist Figure 18 The diagram illustrates a method according to an embodiment of the present invention. This method can be implemented within the context of the processor and system architecture described above, but is not limited to any particular system architecture.

[0276] At 1801, the square root reciprocal (SR) instruction is retrieved, which has fields for the opcode, the compressed data source operand, and the compressed data destination operand. At 1802, the square root reciprocal instruction is decoded to generate a decoded square root reciprocal instruction (e.g., decoded into multiple micro-operations, the remainder of the execution method).

[0277] At 1803, the coefficient values ​​required for executing the square root reciprocal and the input data for the square root reciprocal instruction are retrieved and stored in a compressed data source register or temporary storage location. The operation of the reciprocal instruction is scheduled. For example, micro-operations generated during the decoding stage can be queued and scheduled for execution on multiple functional units of the execution circuitry.

[0278] At 1804, the decoded reciprocal instruction is executed by using the first part of the input data as an index to identify the coefficients. For the double-word implementation, the indices include c0 and c1, and for the word implementation, the indices include c0, c1, c2, and c3. Furthermore, for the double-word implementation, constant values ​​pc1, pc2, and pc3 are read from storage. Then, multiplication and addition are performed using the coefficients, constants (for double-word), and the second part (R) of the input data to determine RS*eps*(pc1+pc2*eps+pc3*eps) for the double-word. 2 Or determine c3*R for the character. 3 +c2*R 2 +c1*R+c0.

[0279] At 1805, the result is stored in the compacted destination register.

[0280] 2. Example code sequence for reciprocal of double-word square roots

[0281] a. Square root reciprocal code sequence

[0282] When executing the double-word square root reciprocal instruction, one embodiment performs the following sequence of operations:

[0283]

[0284]

[0285]

[0286]

[0287]

[0288]

[0289]

[0290] b. Analysis of code sequences

[0291] Therefore, first specify eight potential values ​​for the coefficients c0 and c1. For example, depending on the index value used for the index lookup table, c1 can be set to 0x6bdb, 0x4fad, 0x3df4, 0x31f4, 0x4c44, 0x3857, 0x2bcf, or 0x235. Specify the polynomial coefficients pc1, pc2, and pc3, and specify another constant (CRANGE) for the correction operation.

[0292] A sequence of multiplication, mixing, and shift operations is performed using coefficients and a mask value (ABSMASK) to generate an initial approximation, which is stored in ftmp6 (identified as R in subsequent code). A relative error term (e.g., eps) is determined and stored in fmtp4. Then, the operation on pc1*eps + pc2*eps is initiated. 2 +pc3*eps 3 The evaluation uses 64 bits to perform calculations (e.g., PADDQ) for sufficient accuracy. Various shift operations are performed to adjust the scaling factor, and combinations are used to compress 32-bit data elements into a single SIMD register. The result is determined by (pc1 + pc2 * eps + pc3 * eps). 2 The value of ) is given by the temporary variable P, which represents eps*(pc1+pc2*eps+pc3*eps). 2 Initially, the final result is RS + RS * eps * (pc1 + pc2 * eps + pc3 * eps). 2 The result is stored in ftmp6 and then ORed with the calculated correction value stored in ftmp0. The final result is stored in the xmm1 register. Note that in the code sequence shown, R = RS.

[0293] 3. Example code sequence for reciprocal of the square root of a word

[0294] a. Square root reciprocal code sequence

[0295] When executing the double-word square root reciprocal instruction, one embodiment performs the following sequence of operations:

[0296]

[0297]

[0298]

[0299]

[0300]

[0301] b. Analysis of code sequences

[0302] Therefore, the mask values ​​ABSMASK and CMASK, as well as the variables MONE and ZERO, are initialized, and eight potential values ​​for the coefficients c0, c1, c2, and c3 are specified first. For example, depending on the index value used for the index lookup table, c1 can be set to 0xffa8, 0xb70a, 0x8b49, 0x6e8c, 0xb4c6, 0x816e, 0x627d, or 0x4e2b. The polynomial coefficients pc1, pc2, and pc3 used for the double-word reciprocal are not used.

[0303] A sequence of multiplication, mixing, and shift operations is performed, starting with a shift operation to transfer the input value from xmm2 to ftmp0, using coefficients and mask values. After transferring the coefficients to a temporary storage location (ftmpn), a permutation operation sequence (vpermw) is performed to perform a table lookup to determine the correct set of coefficients to use. As mentioned, bits 15, 14, and 13 are used to perform the table lookup. The remaining input bits (fraction R = bits 11, 10, ..., 0) are used for the polynomial c3*R. 3 +c2*R 2 The independent variable is +c1*R+c0.

[0304] In one implementation, two leading bits of c0 are shifted out to improve accuracy. These bits are not accommodated in c0*2 stored in the table. 18 The lower 16 bits are used. These leading bits are 11 when x is in [0.25, 0.5], and 10 for x in [0.5, 1]. In the example code, they are stored in ftmp1 and subsequently added to the result stored in ftmp0. The result in ftmp0 is then ORed with the correction mask value from ftmp4 (which is set to 0xFFFF for out-of-range input), and the final result is c3*R. 3 +c2*R 2 +c1*R+c0 (for inputs within the range) or 0xFFFF (for inputs outside the range) is stored in xmm1. In the foregoing specification, embodiments of the invention have been described with reference to specific exemplary embodiments thereof. However, it will be apparent that various modifications and changes may be made to these embodiments without departing from the broader spirit and scope of the invention as set forth in the appended claims. Therefore, the specification and drawings should be considered illustrative rather than restrictive.

[0305] Embodiments of the present invention may include the steps described above. These steps may be embodied in machine-executable instructions that can be used to cause a general-purpose or special-purpose processor to perform these steps. Alternatively, these steps may be performed by a special-purpose hardware component containing hard-wired logic for performing these steps, or by any combination of a programmed computer component and a custom hardware component.

[0306] As described herein, instructions can refer to a specific configuration of hardware, such as an application-specific integrated circuit (ASIC) configured to perform certain operations or have a predetermined function, or software instructions stored in memory embodied in a non-transitory computer-readable medium. Therefore, the techniques illustrated in the figures can be implemented using code and data stored on and executed on one or more electronic devices (e.g., terminal stations, network elements, etc.). Such electronic devices use computer-readable media such as non-transitory computer-readable storage media (e.g., disks; optical disks; random access memory; read-only memory; flash memory devices; phase-change memory) and transient computer-readable communication media (e.g., electrical, optical, acoustic, or other forms of propagated signals—such as carrier waves, infrared signals, digital signals, etc.) to store and transmit code and data (internally and / or via a network with other electronic devices). Additionally, such electronic devices typically include a collection of one or more processors coupled to one or more other components, such as one or more storage devices (non-transitory machine-readable storage media), user input / output devices (e.g., keyboards, touchscreens, and / or displays), and network connectivity. The coupling of this processor set with other components is typically via one or more buses and bridges (also referred to as bus controllers). Storage devices and signals carrying network traffic represent one or more machine-readable storage media and machine-readable communication media, respectively. Therefore, the storage devices of a given electronic device typically store code and / or data for execution on one or more processor sets of that electronic device. Of course, one or more portions of embodiments of the invention may be implemented using different combinations of software, firmware, and / or hardware. Throughout this detailed description, numerous specific details have been set forth for purposes of explanation in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without some of these specific details. In some instances, well-known structures and functions have not been described exhaustively so as not to obscure the subject matter of the invention. Therefore, the scope and spirit of the invention should be determined based on the appended claims.

Claims

1. A processor comprising: a decoder to decode an instruction; a source register to store at least one packed input data element; a destination register to store a result data element; and an execution circuit to execute the decoded instruction, the execution circuit to use a first portion of the packed input data element as an index into a data structure containing a plurality of sets of coefficients to identify a first set of coefficients from the plurality of sets of coefficients, wherein the packed input data element comprises a doubleword, and wherein the first portion of the packed input data element comprises two bits to index a coefficient table containing four entries, the execution circuit to generate an inverse of the packed input data element by using a combination of a coefficient and a second portion of the packed input data element, and to store the inverse as the result data element in the destination register, wherein the combination of the coefficient and the second portion of the packed input data element comprises a multiplication of the coefficient and the second portion of the packed input data element. the packed input data element comprises a word, and wherein the first portion of the packed input data element comprises three bits to index a coefficient table containing eight entries.

2. The processor of claim 1, wherein, combining the coefficient with the second portion of the packed input data element comprises evaluating a polynomial function with the coefficient as a polynomial coefficient and the second portion of the packed input data element as an input to the polynomial function.

3. The processor of claim 1, wherein, the inverse execution circuit comprises a plurality of multipliers to multiply one or more coefficients of the first set of coefficients with the second portion of the packed input data or a data value derived from the second portion of the packed input data, the multiplying generating a plurality of temporary products.

4. The processor of claim 3, wherein, The polynomial function includes c3*R 3 + c2*R 2 + c1*R + c0, where c0, c1, c2, and c3 are coefficients and R is a second portion of the packed input data element.

5. The processor of claim 1 or 4, wherein, the execution circuit further comprises a network of adders to add the temporary products to generate the result.

6. The processor of claim 5, wherein, 7. The processor of claim 6, further comprising: a Newton-Raphson circuit to implement an approximation technique to improve accuracy of the result to generate a final result. the final result to be stored in the destination register as a result packed data element.

8. The processor of claim 7, wherein, 9. A method comprising: decoding an instruction; executing the decoded instruction to use a first portion of a packed input data element of a source register as an index into a data structure containing a plurality of sets of coefficients to identify a first set of coefficients from the plurality of sets of coefficients, wherein the packed input data element comprises a doubleword, and wherein the first portion of the packed input data element comprises two bits to index a coefficient table containing four entries; generating an inverse of the packed input data element using a combination of a coefficient and a second portion of the packed input data element, and storing the inverse in a destination register, wherein the combination of the coefficient and the second portion of the packed input data element comprises a multiplication of the coefficient and the second portion of the packed input data element. the packed input data element comprises a word, and wherein the first portion of the packed input data element comprises three bits to index a coefficient table containing eight entries.

10. The method of claim 9, wherein, ​ 11. The method of claim 9 or 10, wherein, Combining the coefficient with the second portion of the packed input data element includes evaluating a polynomial function with the coefficient as a polynomial coefficient and the second portion of the packed input data element as an input to the polynomial function.

12. The method of claim 11, wherein, The polynomial function includes c3*R 3 + c2*R 2 + c1*R + c0, where c0, c1, c2, and c3 are coefficients and R is a second portion of the packed input data element.

13. The method of claim 9 or 12, further comprising: Multiplying one or more of the coefficients in the first set of coefficients with the second portion of the packed input data or a data value derived from the second portion of the packed input data, the multiplying generating a plurality of temporary products.

14. The method of claim 13, further comprising: Adding the temporary products to generate a result.

15. The method of claim 14, further comprising: implementing an approximation technique to improve accuracy of the result, thereby generating a final result.

16. The method of claim 15, wherein, the final result is used as a packed data element stored in the destination register.

17. A machine-readable medium having stored thereon program code which, when executed by a machine, causes the machine to: decode an instruction; executing the decoded instruction to use a first portion of the packed input data elements of the source register as an index to a data structure containing a plurality of sets of coefficients to identify a first set of coefficients from the plurality of sets of coefficients, wherein, the packed input data element includes a doubleword, and wherein the first portion of the packed input data element includes two bits used to index a table of coefficients containing four entries; and generating an inverse of the packed input data element using a combination of a coefficient and a second portion of the packed input data element, and storing the inverse in a destination register, wherein the combination of the coefficient and the second portion of the packed input data element includes a multiplication of the coefficient and the second portion of the packed input data element.

18. The machine readable medium of claim 17, wherein, the packed input data element includes a doubleword, and wherein the first portion of the packed input data element includes two bits used to index a table of coefficients containing four entries; and 19. The machine readable medium of claim 17 or 18, wherein, Combining the coefficient with the second portion of the packed input data element includes evaluating a polynomial function with the coefficient as a polynomial coefficient and the second portion of the packed input data element as an input to the polynomial function.

20. The machine readable medium of claim 19, wherein, The polynomial function includes c3*R 3 + c2*R 2 + c1*R + c0, where c0, c1, c2, and c3 are coefficients and R is a second portion of the packed input data element.

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