Embedded multi-die interconnect bridge package with lithographically formed bump pitch and method of assembly thereof

Abstract

An embedded multi-die interconnect bridge device and method is disclosed that includes lithographically formed interconnects coupled to laser-drilled interconnects. Several structures in the embedded multi-die interconnect bridge device exhibit feature planarization during fabrication and assembly.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to embedded multi-die interconnect bridge packages including photo-lithographically formed bumps. BACKGROUND

[0002] Semiconductor device miniaturization during packaging presents challenges for bump pitch scaling that allows for close pitch electrical bumps on the semiconductor device package surface. BRIEF DESCRIPTION OF DRAWINGS

[0003] The disclosed embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals can refer to similar elements, in which:

[0004] Figure 1A is a cross-sectional elevation view of a semiconductor package substrate during fabrication according to an embodiment;

[0005] Figure 1B is a cross-sectional elevation view of a precursor package substrate after further processing according to an embodiment; Figure 1A shown in FIG. 1 1 1 1 ;

[0006] Figure 1C is a cross-sectional elevation view of a precursor package substrate after further processing according to an embodiment; Figure 1B shown in FIG. 1 1 1 1 ;

[0007] Figure 1D is a cross-sectional elevation view of a precursor package substrate after further processing according to an embodiment; Figure 1C shown in FIG. 1 1 1 1 ;

[0008] Figure 1E is a cross-sectional elevation view of a precursor package substrate and bridge die after further processing according to an embodiment;

[0009] Figure 1F is a cross-sectional elevation view of an embedded multi-die interconnect bridge device after further processing Figure 1E shown in FIG. 1 1 1 1 ;

[0010] Figure 2 is a detail cross-section taken from Figure 1F shown in FIG. 1 1 1 1 ;

[0011] Figure 3 is a cross-sectional elevation view of a semiconductor device including an embedded multi-die interconnect bridge according to an embodiment;

[0012] Figure 3A is a top view of a portion of a semiconductor device including an EMIB according to an embodiment; Figure 3 shown in FIG. 1 1 1 1 ;

[0013] Figure 4is a process flow diagram according to embodiments;

[0014] Figure 5 are included to illustrate examples of higher level device applications for the disclosed embodiments; and

[0015] Figure 6 is a cross-sectional elevation view of a semiconductor device including EMIB with through silicon via access in a bridge die according to embodiments. DETAILED DESCRIPTION

[0016] Multi-die semiconductor device packages are assembled and tested with a good substrate (KGS), and a known good silicon bridge (KGB) to achieve high yield embedded multi-die interconnect bridge (EMIB) semiconductor package devices.

[0017] Embodiments achieve bump pitch scaling below 40 microns (pm). Thus, embedded multi-die interconnect embodiments can be used for several applications, such as for modular die fabric interconnect (MDFI).

[0018] Bump thickness variation is controlled by planarizing both the package substrate and the silicon bridge bumps after the bridge die is embedded in the cavity. Similarly, package substrate thickness and shrinkage variation is controlled by assembly onto a rigid and substantially flat carrier.

[0019] Figure 1A is a cross-sectional elevation view of a semiconductor package substrate 101 during fabrication according to embodiments. The precursor package substrate 110 includes several layers. The precursor package substrate 110 includes a back surface 109 and a precursor top surface 111. Each layer in the precursor package substrate 110 contains metallization with interconnects or traces, or contains dielectric build-up layers for insulation and structural integrity. The metallization layers include interconnect layers 112, 116, and 124 and trace layers 114, 118, 122, and 126.

[0020] In embodiments, the precursor package substrate 110 can be referred to as a low layer count package substrate 110 with four trace layers and four interconnect layers. Several build-up layers within the precursor package substrate 110 are not specifically identified as they can be formed in conjunction with several interconnect and trace layers.

[0021] In embodiments, the precursor package substrate 110 is assembled on a rigid carrier 128, such as polished glass or polished stainless steel. The rigid carrier 128 is both rigid and flat, which is useful to constrain film thickness variation and material shrinkage variation, which is low for design rule geometries including bump pitches of about 30 pm or lower.

[0022] In an embodiment, the interconnects 112 are placed on the rigid carrier 128 through a first build-up layer 113, which can first be laser drilled to form a conical or frustoconical recess, where the interconnects 112 are filled. In an embodiment, a low-loss (low electrical loss) material is used for the ILD, such as a material with glass fiber reinforcement, to impart a useful stiffness to the silicon bridge package substrate.

[0023] Formation of the interconnects is performed by a plating process such as semi-additive plating (SAP) of electronic grade copper (Cu) to form, for example, the conical interconnects 112. In an embodiment, the interconnects 112, 116, 120, and 124 are also referred to as conical vias.

[0024] Figure 1B is a cross-sectional elevation view 102 of the precursor package substrate 110 after further processing according to an embodiment. Figure 1A The multiple posts 130 (four posts are shown) are formed onto the bond pads 132 disposed on the precursor package top surface 111. The posts 130 can also be referred to as package posts 130. Although the multiple interconnects 112, 116, 120, and 124 (enumerated in Figure 1A have a generally frustoconical (conical in cross-section) shape due to laser drilling of the contact vias in which they are formed, the multiple posts 130 have a generally right solid cylindrical shape due to formation of the multiple posts 130 using photolithography.

[0025] In an embodiment, the multiple interconnects 112, 116, 120, and 124 are formed by laser drilling into the ILD separating the interconnects and traces in the precursor package substrate 110. The shape and quality of the interconnect recesses in which the multiple interconnects 112, 116, 120, and 124 are formed can be described as a characteristic of the laser drilling. One characteristic of the laser drilling is a conical shape. One characteristic of the laser drilling is the ablation chemistry quality of the conical wall of build-up material compared to anywhere else in the bulk of the build-up layer where no ablation occurs.

[0026] The formation of the plurality of pillars 130 is accomplished by patterning a photolithographic mask (not shown) and depositing the pillars 130, such as by electroplating, followed by removal of the mask. The plurality of pillars are plated using a process such as semi-additive plating (SAP) in an embodiment. The shape and quality of the plurality of pillars 130 can be described as features formed by the photolithography. One feature formed by the photolithography includes the substantially right angles of the solid cylindrical pillars 130. One feature formed by the photolithography includes microscopically inspecting the vertical aspects of the pillars 130 and observing the negative image profile imprinted on the pillar walls by the patterned mask. In any case, within a given known good substrate including a recess for accommodating a known good bridge die, the positive solid cylindrical shape of the pillars 130 can be distinguished from the solid truncated cone shape of the plurality of interconnects 112, 116, 120, and 124 formed by laser drilling into the ILD.

[0027] Figure 1C According to the embodiment after further processing Figure 1B 103 of a cross-sectional elevation of a precursor package substrate 110 is shown in FIG. A lamination layer 134 has been formed over a plurality of pillars 130 and on precursor top surface 111, and a bridge recess 136 has been drilled into lamination layer 134 and through precursor top surface 111 until traces 122 are uncovered. Adhesive 138 is deposited in bridge recess 136, and a silicon bridge 140 (also referred to as bridge die 140) is positioned within bridge recess 136 on adhesive 138. Although traces 122 at this level of precursor package substrate 110 are depicted as a base for silicon bridge 140, in accordance with an embodiment, the lowest point of bridge recess 136 is above this level (positive Z direction).

[0028] Before assembling the bridge die 140 into the bridge recess 136, the bridge die 140 and the precursor package substrate 110 are tested so that a known good bridge (KGB) 140 is assembled to a known good substrate (KGS) 110. Thus, yield of embedded bridges is achieved to a useful level.

[0029] Figure 1D According to the embodiment after further processing Figure 1C 104. Encapsulation material 142 has been filled into bridge recess 136, and both laminate layer 134 and encapsulation material 142 have been planarized to form respective planarized laminates 135 and 142. By achieving planarized laminate layer 135 and encapsulation material 142, useful package flatness is achieved for further processing.

[0030] In embodiments, the package bond pads 144, bridge die bond pads 146, and package-to-bridge traces 148 (only one shown) are plated onto the planarized laminates 135 and 142. In embodiments, a process such as semi-additive plating (SAP) is used to plate the package bond pads 144, bridge die bond pads 146, and package-to-bridge die traces 148.

[0031] Figure 1E is a cross-sectional elevation view 105 of the precursor package substrate 110 and bridge die 140 after further processing according to embodiments. A patterned photoresist layer 150 has been formed over the package bond pads 144, bridge die bond pads 146, and package-to-bridge traces 148. In embodiments, the photoresist layer 150 has been patterned to partially re-expose the package bond pads 144, bridge die bond pads 146, and package-to-bridge traces 148. In embodiments, a protective contact film 152 such as a nickel-palladium-gold (NiPdAu) alloy 152 is plated onto the exposed portions of the package bond pads 144, bridge die bond pads 146, and package-to-bridge traces 148. In embodiments, the protective contact film 152 provides useful adhesion, low resistivity, and protection against a later-to-be-plated tin or nickel-tin (Sn or NiSn) bond layer.

[0032] Figure 1F is a cross-sectional elevation view 106 of an embedded multi-die interconnect bridge (EMIB) package 106 after further processing of the precursor package substrate 110 and bridge die 140 shown in Figure 1E . Plating onto the protective contact film 152 has been completed to include a copper flash layer 154 and a Sn or NiSn bond layer 156 described herein on the copper flash layer 154.

[0033] After the lithography formation of the structure over the top surface 111 of the precursor package substrate 110, a protective carrier (not shown) is disposed over the exposed structure over the top surface 111. The rigid carrier 128 (see, e.g., Figure 1E ) is removed and a middle level interconnect (MLI) 158 and 160 is plated onto the interconnects 112 exposed through the back surface 109 of the first ILD layer 113.

[0034] Figure 2 is a detail cross-section 200 taken from the cross-sectional circle 2 in Figure 1F . The bridge die 140 includes a bridge die pillar 162 formed by lithography prior to the bridge die 140 being disposed into the bridge recess 136. In embodiments, the bridge die pillar 162 has a diameter 163 (X-direction) of approximately 10 pm. In embodiments, the formation of the photoresist layer 150 allows the bridge die bond layer 156 to have a diameter 155 of approximately 20 pm.

[0035] In embodiments, the protective contact film 152, coupled between the bridge die pillar 158 and the bond layer 156, is also patterned and formed to have a diameter of about 10 pm. In embodiments, the bridge die bond pad 146 has a diameter of about 25 pm.

[0036] In embodiments, the bond layer 156, plated over the pillar 130, has a diameter of about 40 pm.

[0037] Reference is made to Figure 1F The via structures formed below (negative Z direction) the levels of the plurality of pillars 130 have the shape of laser drilling and SAP formed features, while the pillars 130 are formed by photolithography process. The micro-vias 120, 124 are formed by laser drilling, as shown by the conical shape. The via structures above the levels of the upper surface 111, including the plurality of pillars 130 and structures above (positive Z direction) the pillars, have the shape of photolithographically patterned vias.

[0038] Figure 3 is a cross-sectional elevation view of a semiconductor device 300 including an EMIB, in accordance with embodiments. The selected reference numerals are from Figures 1A to 1F .

[0039] In embodiments, the embedded multi-die interconnect bridge package (EMIB) device 106 from Figure 1F includes a known good substrate 110 (see Figure 1F ) and a known good bridge 140. The EMIB device 106 is disposed on an interposer 374. The interposer 374 can include a routing layer and a second level interconnect (SLI) 392, build-up layers 378 and 380, a core 382, and a middle level interconnect (MLI) layer 384.

[0040] In embodiments, a first die 370 and a subsequent die 372 are disposed on the EMIB device 106, such that the bridge die 140 provides a communication bridge between these respective dies 370 and 372, and communication between either of the dies 370 and 372 can be directed through the interposer 374.

[0041] In embodiments, a larger pitch series of electrical bumps (one example is denoted 386) contact the EMIB device 106 in a configuration that allows such contact to fan out on the EMIB device 106.

[0042] In embodiments, a smaller pitch series of electrical bumps (one example is denoted 388) contact the known good bridge die 140 and the respective first die 370 and subsequent die 372. In embodiments, the pitch of the smaller pitch series of electrical bumps is about 30 pm, center to center between adjacent electrical bumps 388.

[0043] In an embodiment, planarization is performed on the electrical bumps 386 and 388 prior to disposing the first die 370 and the subsequent die 372. In an embodiment, the electrical bumps 386 and 388 are retained in a patterned mask (not shown) and the planarization is performed to the re-planarization level 390. Thus, the electrical bumps 386 and 388 have already been planarized at the level of the upper surface 111, as well as at the level of the support package bond pads 144, the bridge die bond pads 146, and the package-to-bridge die traces 148. Figure 1F The known good die EMIB device 106 shown in FIG. 1 is planarized to include a known good substrate. Similarly and thus, the re-planarization of the semiconductor device 300 including the EMIB includes planarizing the electrical bumps 386 and 388 at the re-planarization level 390.

[0044] In an embodiment, the electrical bumps 386 and 388 are reflowed from solder paste, planarized to the re-planarization level 390, and then the dies 370 and 372 are bonded to the electrical bumps 386 and 388 by thermocompression bonding (TCB). The TCB is performed by adding a net heat flow to the planarized electrical bumps 386 and 388, while also adding a net increased pressure on the bumps.

[0045] In an embodiment, the alignment within the semiconductor device 300 including the EMIB includes a smaller bump pitch for the electrical bumps 386 plus or minus 5 pm, and a Z-direction die bond variation amplitude between the bridge die 140 and any of the respective dies 370 and 372 plus or minus 4.5 pm.

[0046] In an embodiment, the first die 370 is a processor die, such as a processor die manufactured by Intel Corporation of Santa Clara, California. In an embodiment, the first die 370 is doubled (the doubled die (see FIG. 1C) is disposed in the same X-Z space as the first die, but in a different Y direction out of the plane of the figure). With the doubled die or fourth die 370', the subsequent die 372 is a graphics processor, and the first die 370 and the fourth die 370' are logic processors, and the graphics processor 372 is all coupled to the bridge die 140. Figure 3A

[0047] ​As shown, each of the tapered vias 112, 116, 120, and 132 contacts a respective trace 114, 118, 122, and 132 in order. In other words, the first tapered via 112 contacts the first trace 114, the second tapered via 116 contacts the second trace 118, the third tapered via 120 contacts the third trace 122, and the fourth tapered via 124 contacts the fourth trace 132. The fourth trace 132 is disposed at the planarization layer stack, and the fourth trace 132 contacts the encapsulation post 130 and the fourth tapered via 124. In other words, the sequentially ordered tapered vias 112, 116, 120, and 132 contact the respective sequentially ordered traces 114, 118, 122, and 132.

[0048] In embodiments, after the electrical bumps 392 are formed on the interposer 374, the interposer 374 is disposed on a board 394, such as a motherboard 384. In embodiments, the board 394 includes a housing 396 that provides physical and electrical isolation for devices within the housing 396.

[0049] Figure 3A is a top plan view of a portion of a semiconductor device 300 including EMIB, in accordance with embodiments Figure 3 is a top plan view of a portion of a semiconductor device 300 including EMIB, in accordance with embodiments Figure 3 selected reference numerals from

[0050] In embodiments, the first die 370 and the fourth die 370' are processor dies, such as processor dies manufactured by Intel Corporation of Santa Clara, California. In embodiments, the second die is a graphics processor, and the dies 370, 370', and 372 are coupled to a bridge die 140. Thus, the first die 370, the subsequent die 372, and the bridge die 140 are supplemented by the die 370' as the fourth die 370'. In embodiments, the first die 370 and the fourth die 370' are logic processors, and the subsequent die 372 is a graphics processor.

[0051] Figure 4 is a process flow diagram 400, in accordance with embodiments.

[0052] At 410, the process includes photo-etching a post on a precursor package substrate including a laser-drilled via.

[0053] At 420, the process includes opening a recess in the precursor package substrate.

[0054] At 430, the process includes disposing a bridge die in the recess.

[0055] At 440, the process includes planarizing the precursor package substrate and a layer stack above the bridge die.

[0056] At 450, the process includes forming package bond pads on the column, forming bridge bond pads on the bridge die, and forming package-to-bridge traces between the package and bridge die bond pads to form a semiconductor package including an EMIB.

[0057] At 460, the process includes planarizing electrical bumps contacting the semiconductor package including an EMIB at bond pads coupled to the package substrate and coupled to the bridge die.

[0058] At 470, the process includes disposing first and subsequent dies on the planarized electrical bumps to couple each die to the bridge die and the package substrate to form an EMIB device.

[0059] At 480, the process includes assembling the EMIB device to a computing system.

[0060] Figure 5 Examples are included to illustrate more advanced device applications for the disclosed embodiments. The EMIB device embodiments can be found in several parts of a computing system. In embodiments, the EMIB device is part of a communication device, such as part of a communication device fixed to a cellular communication tower. In embodiments, the computing system 500 includes, but is not limited to, a desktop computer. In embodiments, the system 500 includes, but is not limited to, a laptop computer. In embodiments, the system 500 includes, but is not limited to, a netbook. In embodiments, the system 500 includes, but is not limited to, a tablet. In embodiments, the system 500 includes, but is not limited to, a notebook computer. In embodiments, the system 500 includes, but is not limited to, a personal digital assistant (PDA). In embodiments, the system 500 includes, but is not limited to, a server. In embodiments, the system 500 includes, but is not limited to, a workstation. In embodiments, the system 500 includes, but is not limited to, a cellular telephone. In embodiments, the system 500 includes, but is not limited to, a mobile computing device. In embodiments, the system 500 includes, but is not limited to, a smart phone. In embodiments, the system 500 includes, but is not limited to, an internet appliance device. Other types of computing devices can be configured with microelectronic devices including multilayer solder resist on semiconductor device package substrate embodiments.

[0061] In embodiments, the processor 510 has one or more processing cores 512 and 512N, where 512N represents the Nth processing core within the processor 510, where N is a positive integer. In embodiments, the electronic device system 500 is implemented using an EMIB device embodiment that includes multiple processors, including 510 and 505, where the processor 505 has logic similar or equivalent to the logic of the processor 510. In embodiments, the processing core 512 includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions, etc. In embodiments, the processor 510 has a cache memory 516 to cache at least one of instructions and data for the EMIB device in the system 500. The cache memory 516 can be organized into a hierarchy that includes one or more levels of cache memory.

[0062] In embodiments, the processor 510 includes a memory controller 514 operable to perform functions that enable the processor 510 to access and communicate with a memory 530 that includes at least one of a volatile memory 532 and a non-volatile memory 534. In embodiments, the processor 510 is coupled with the memory 530 and a chipset 520. In embodiments, the chipset 520 is part of a system-on-a-chip (SoC) that includes the EMIB device shown in FIG. 5. The processor 510 can also be coupled to a wireless antenna 578 to communicate with any device configured to at least one of transmit and receive wireless signals. In embodiments, the wireless antenna interface 578 operates according to, but is not limited to, IEEE 802.11 standards and their related series, HomePlug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol. Figure 1F

[0063] In embodiments, the volatile memory 532 includes, but is not limited to, a synchronous dynamic random access memory (SDRAM), a dynamic random access memory (DRAM), a RAMBUS dynamic random access memory (RDRAM), and / or any other type of random access memory device. The non-volatile memory 534 includes, but is not limited to, a flash memory, a phase change memory (PCM), a read only memory (ROM), an electrically erasable programmable read only memory (EEPROM), or any other type of non-volatile memory device.

[0064] ​Memory 530 stores information and instructions to be executed by processor 510. In an embodiment, memory 530 can also store temporary variables or other intermediate information during execution of instructions by processor 510. In the illustrated embodiment, chipset 520 is connected with processor 510 via point-to-point (PtP or P-P) interfaces 517 and 522. Any of the PtP embodiments set forth in the present disclosure can be implemented using EMIB device embodiments. Chipset 520 enables processor 510 to connect to the other elements in system 500, in EMIB device embodiments. In an embodiment, interfaces 517 and 522 operate in accordance with a PtP communication protocol such as QuickPath Interconnect (QPI). In other embodiments, different interconnects can be used.

[0065] In an embodiment, chipset 520 is operable to communicate with processor 510, 505N, display 540, and other devices 572, 576, 574, 560, 562, 564, 566, 577, etc. Chipset 520 can also be coupled to wireless antenna 578 to communicate with any device configured to at least one of transmit and receive wireless signals.

[0066] Chipset 520 is connected with display 540 via interface 526. For instance, display 540 can be a liquid crystal display (LCD), a plasma display, a cathode ray tube (CRT) display, or any other form of visual display device. In an embodiment, processor 510 and chipset 520 are fused into an EMIB device in the system. Further, chipset 520 is connected to one or more buses 550 and 555 that interconnect various elements 574, 560, 562, 564, and 566. Buses 550 and 555 can be interconnected together via a bus bridge 572, which is, for example, at least one EMIB device on a semiconductor device package substrate embodiment. In an embodiment, chipset 520 is coupled with nonvolatile memory 560, mass storage device 562, keyboard / mouse 564, network interface 566, smart television 576, and consumer electronic device 577, etc. via interface 524.

[0067] ​In embodiments, mass storage devices 562 include, but are not limited to, solid state drives, hard disk drives, universal serial bus flash memory drives, or any other form of computer data storage media. In one embodiment, network interface 566 is implemented via any type of well-known network interface standards, including, but not limited to, an Ethernet interface, a universal serial bus (USB) interface, a peripheral component interconnect (PCI) express interface, a wireless interface, and / or any other appropriate type of interface. In one embodiment, the wireless interface operates in accordance with, but is not limited to, IEEE 802.11 standards and their associated series, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

[0068] Although Figure 5 The modules shown in FIG. 6 are depicted as separate blocks within the EMIB device embodiment in computing system 500, the functionality performed by some of these blocks can be integrated within a single semiconductor circuit or can be implemented using two or more separate integrated circuits. For example, although cache memory 516 is depicted as a separate block within processor 510, cache memory 516 (or selected aspects of 516) can be incorporated into processor core 512.

[0069] In useful cases, computing system 500 can have a broadcast structure interface, e.g., for securing a device to a cell tower.

[0070] Figure 6 is a cross-sectional elevation view of a semiconductor device 600 including EMIB with through-silicon via (TSV) access in a bridge die 640 according to embodiments. The semiconductor device 600 includes selected reference numerals from Figures 1A to 1F and Figure 3 EMIB package 606 is prepared according to several processing embodiments.

[0071] In embodiments, bridge die 640 includes at least one TSV 639, and adhesive 638 is patterned to allow at least one backside bump 641 to contact trace 622. In embodiments, at least one TSV 639' contacts at least one backside bump 641' through adhesive 638 to contact bond pad 623 within EMIB package 606.

[0072] In cases where direct contact from bridge die 640 into EMIB package 606 includes package-to-bridge trace 148, disclosed TSV embodiments 639 and 639' allow direct contact through the backside of bridge die 640 into EMIB package 606.

[0073] Referring to Figure 3A In embodiments, at least one TSV (as Figure 6at least one TSV (as shown in FIG. 3) is positioned directly below the first die 370. In embodiments, the at least one TSV (as shown in FIG. 3) is positioned directly below the subsequent die 372. In embodiments, the at least one TSV (as shown in FIG. 3) is positioned directly below the fourth die 370'. Figure 6 at least one TSV (as shown in FIG. 3) is positioned directly below the first die 370. In embodiments, the at least one TSV (as shown in FIG. 3) is positioned directly below the subsequent die 372. In embodiments, the at least one TSV (as shown in FIG. 3) is positioned directly below the fourth die 370'. Figure 6 at least one TSV (as shown in FIG. 3) is positioned directly below the first die 370. In embodiments, the at least one TSV (as shown in FIG. 3) is positioned directly below the subsequent die 372. In embodiments, the at least one TSV (as shown in FIG. 3) is positioned directly below the fourth die 370'.

[0074] To illustrate the EMIB device embodiments and methods disclosed herein, a non-limiting list of examples is provided herein:

[0075] Example 1 is a semiconductor package device, comprising: a bridge die disposed in a recess of a semiconductor package substrate, wherein the semiconductor package substrate comprises a fill via coupled to a package post; a laminate over the package post and the bridge die, wherein the bridge die comprises a bridge die bond pad; electrical bumps coupled to the package post and electrical bumps coupled to the bridge die bond pad; a first semiconductor device coupled to the electrical bumps coupled to the package post; and a subsequent semiconductor device coupled to the electrical bumps coupled to the bridge die bond pad.

[0076] In Example 2, the subject matter of Example 1 optionally includes a package bond pad patterned on the laminate and contacting the package post; a bridge die bond pad patterned on the laminate and contacting the bridge die post; and a package to bridge trace patterned on the laminate and contacting the bridge die post and the package post.

[0077] In Example 3, the subject matter of any one or more of Examples 1-2 optionally includes a package bond pad patterned on the laminate and contacting the package post; a bridge die bond pad patterned on the laminate and contacting the bridge die post; a package to bridge trace patterned on the laminate and contacting the bridge die post and the package post; and a protective contact film disposed on each of the package bond pad and the bridge to die bond pad and patterned through the patterned photoresist layer.

[0078] In Example 4, the subject matter of any one or more of Examples 1-3 optionally includes a package bond pad patterned on the laminate and contacting the package post; a bridge die bond pad patterned on the laminate and contacting the bridge die post; and a package to bridge trace patterned on the laminate and contacting the bridge die post and the package post, wherein the bridge die is disposed on an adhesive, and wherein the package bond pad and the bridge die bond pad exhibit planarization over the patterned photoresist.

[0079] In Example 5, the subject matter of any one or more of Examples 1-4 optionally includes, wherein the bridge die is disposed on an adhesive, and wherein the package bond pad and the bridge die bond pad exhibit planarization over the patterned photoresist.

[0080] In Example 6, the subject matter of any one or more of Examples 1-5 optionally include, wherein the bridge die is disposed on an adhesive, and wherein the package bond pads and the bridge die bond pads present a planarization over the patterned photoresist, further comprising a mid-level interconnect on the back surface, wherein the mid-level interconnect contacts a tapered via within the semiconductor package substrate.

[0081] In Example 7, the subject matter of any one or more of Examples 1-6 optionally include, wherein the semiconductor package substrate comprises a back surface, further comprising: a mid-level interconnect on the back surface, wherein the mid-level interconnect contacts a tapered via within the semiconductor package substrate.

[0082] In Example 8, the subject matter of any one or more of Examples 1-7 optionally include, wherein the semiconductor package substrate comprises a back surface, further comprising: a mid-level interconnect on the back surface, wherein the mid-level interconnect contacts a tapered via; and an interposer coupled to the mid-level interconnect.

[0083] In Example 9, the subject matter of any one or more of Examples 1-8 optionally include, wherein the semiconductor package substrate comprises a back surface, further comprising: a mid-level interconnect on the back surface, wherein the mid-level interconnect contacts a tapered via; an interposer coupled to the mid-level interconnect; a ball grid array on the interposer; and a board coupled to the ball grid array.

[0084] In Example 10, the subject matter of any one or more of Examples 1-9 optionally include, wherein the semiconductor package substrate comprises a back surface, further comprising: a mid-level interconnect on the back surface, wherein the mid-level interconnect contacts a tapered via, and wherein the semiconductor package substrate comprises a first tapered via, a second tapered via, a third tapered via, and a fourth tapered via, and a first trace, a second trace, a third trace, and a fourth trace, wherein each tapered via contacts a trace in order, and wherein the fourth trace is disposed at a laminate, and wherein the fourth trace contacts a package post of one of the fourth tapered vias.

[0085] In Example 11, the subject matter of any one or more of Examples 1-10 optionally include a fourth die, wherein the first die, the subsequent die, and the fourth die are each coupled to the bridge die.

[0086] In Example 12, the subject matter of any one or more of Examples 1-11 optionally include, wherein the semiconductor package substrate comprises four tapered vias that contact four respective sequentially ordered traces in order, and wherein the fourth trace further contacts a package post.

[0087] Example 13 is a process of forming a semiconductor package apparatus, comprising: lithographically forming package posts on a precursor package substrate to couple the package posts to laser-drilled vias; disposing a bridge die in a recess in the precursor package substrate; forming a planarization laminate over the precursor package substrate and the bridge die; forming planarized electrical bumps coupled to the precursor package substrate and the bridge die; and disposing first semiconductor devices and subsequent semiconductor devices on the planarized electrical bumps under conditions that the bridge die provides a communication bridge between the first semiconductor devices and the subsequent semiconductor devices.

[0088] In Example 14, the subject matter of Example 13 optionally includes, wherein lithographically forming package posts on a precursor package substrate comprises forming package posts on traces that contact the package posts with laser-drilled vias.

[0089] In Example 15, the subject matter of any one or more of Examples 13-14 optionally includes, filling the recess with a laminate after disposing the bridge die, followed by forming the planarization laminate over the precursor package substrate and the bridge die.

[0090] In Example 16, the subject matter of any one or more of Examples 13-15 optionally includes, disposing the precursor package substrate on a carrier; forming package bond pads and bridge die bond pads on the planarization laminate; patterning a photoresist layer on the planarization laminate; patterning a bond layer through the photoresist to couple to the posts and the bridge die; and forming solder paste electrical bumps on the bond layer, followed by forming the planarized electrical bumps.

[0091] In Example 17, the subject matter of any one or more of Examples 13-16 optionally includes, bonding the first die and the subsequent die on the planarized electrical bumps by using increased heat and pressure.

[0092] Example 18 is a computing system, comprising: a bridge die disposed in a recess of a semiconductor package substrate, wherein the semiconductor package substrate comprises filled vias coupled to package posts; a laminate over the package posts and the bridge die, wherein the bridge die comprises bridge die bond pads; electrical bumps coupled to the package posts and electrical bumps coupled to the bridge die bond pads; first semiconductor devices coupled to the electrical bumps coupled to the package posts; and subsequent semiconductor devices coupled to the electrical bumps coupled to the bridge die bond pads; an intermediate interconnect on a surface of the semiconductor package substrate, wherein the intermediate interconnect contacts a tapered via; an interposer coupled to the intermediate interconnect; and a board coupled to the interposer, wherein the board is coupled to the interposer, wherein the board comprises a housing.

[0093] In Example 19, the subject matter of Example 18 optionally includes, wherein the bridge die is coupled to a chipset.

[0094] In Example 20, the subject matter of any one or more of Examples 18-19 optionally include, wherein the subsequent die is a graphics processor, further comprising a fourth die also coupled to the bridge die, wherein the first die and the fourth die are logic processors.

[0095] Example 21 is a semiconductor package apparatus comprising: a bridge die disposed in a recess of a semiconductor package substrate, wherein the semiconductor package substrate comprises laser-drilled fill via features coupled to lithographically patterned package post features; at least one through-silicon via (TSV) in communication through the bridge die to couple with at least one of a trace and a bond pad within the semiconductor package substrate; a laminate over the package posts and the bridge die, wherein the bridge die comprises a bridge die bond pad; electrical bumps coupled to the package posts and electrical bumps coupled to the bridge die bond pad; a first semiconductor device coupled to the electrical bumps coupled to the package posts; and a subsequent semiconductor device coupled to the electrical bumps coupled to the bridge die bond pad.

[0096] In Example 22, the subject matter of Example 21 optionally includes, wherein the at least one TSV is coupled to one selected from the group consisting of the trace and the bond pad within the semiconductor package substrate.

[0097] In Example 23, the subject matter of any one or more of Examples 21-22 optionally include a fourth die, wherein the first die, the subsequent die, and the fourth die are each coupled to the bridge die.

[0098] Example 24 is a semiconductor package apparatus comprising: a bridge die disposed in a recess of a semiconductor package substrate, wherein the semiconductor package substrate comprises laser-drilled fill via features coupled to lithographically patterned package post features; a planarized laminate over the package posts and the bridge die, wherein the bridge die comprises a bridge die bond pad; planarized electrical bumps coupled to the package posts and planarized electrical bumps coupled to the bridge die bond pad; a first semiconductor device coupled to the planarized electrical bumps coupled to the package posts; a subsequent semiconductor device coupled to the planarized electrical bumps coupled to the bridge die bond pad; a package bond pad patterned on the planarized laminate and contacting the package posts; a bridge die bond pad patterned on the planarized laminate and contacting the bridge die posts; and a package-to-bridge trace patterned on the planarized laminate and contacting the bridge die posts and the package posts.

[0099] In Example 25, the subject matter of Example 24 optionally includes, wherein the bridge die is disposed on an adhesive, further comprising: a through-silicon via (TSV) in communication through the bridge die; electrical bumps coupling the TSV to at least one of a trace and a bond pad within the semiconductor package substrate, and wherein the package bond pad and the bridge die bond pad exhibit planarization over patterned photoresist.

[0100] Example 26 is a semiconductor package apparatus comprising: a bridge die disposed in a recess of a semiconductor package substrate, wherein the semiconductor package substrate comprises laser-drilled fill via features coupled to lithographically patterned package post features; a planarization layer stack over the package posts and the bridge die, wherein the bridge die comprises a bridge die bond pad; planarized electrical bumps coupled to the planarization layer stack and coupled to the package posts and the bridge die bond pad; a first semiconductor device coupled to the planarized electrical bumps coupled to the package posts; and a subsequent semiconductor device coupled to the planarized electrical bumps coupled to the bridge die bond pad.

[0101] In Example 27, the subject matter of Example 26 optionally comprises package bond pads patterned on the planarization layer stack and contacting the package posts; bridge die bond pads patterned on the planarization layer stack and contacting the bridge die posts; and package-to-bridge traces patterned on the planarization layer stack and contacting the bridge die posts and the package posts.

[0102] In Example 28, the subject matter of any one or more of Examples 26-27 optionally comprises: package bond pads patterned on the planarization layer stack and contacting the package posts; bridge die bond pads patterned on the planarization layer stack and contacting the bridge die posts; package-to-bridge traces patterned on the planarization layer stack and contacting the bridge die posts and the package posts; and a protective contact film disposed on each of the package bond pads and the bridge-to-die bond pads and patterned through a patterned photoresist layer.

[0103] In Example 29, the subject matter of any one or more of Examples 26-28 optionally comprises: package bond pads patterned on the planarization layer stack and contacting the package posts; bridge die bond pads patterned on the planarization layer stack and contacting the bridge die posts; package-to-bridge traces patterned on the planarization layer stack and contacting the bridge die posts and the package posts, wherein the bridge die is disposed on an adhesive, and wherein the package bond pads and the bridge die bond pads exhibit planarization over the patterned photoresist.

[0104] In Example 30, the subject matter of any one or more of Examples 26-29 optionally comprises, wherein the bridge die is disposed on an adhesive, and wherein the package bond pads and the bridge die bond pads exhibit planarization over the patterned photoresist.

[0105] In Example 31, the subject matter of any one or more of Examples 26-30 optionally comprises, wherein the bridge die is disposed on an adhesive, and wherein the package bond pads and the bridge die bond pads exhibit planarization over the patterned photoresist, further comprising a mid-level interconnect on a back surface, wherein the mid-level interconnect contacts a tapered via within the semiconductor package substrate.

[0106] In Example 32, the subject matter of any one or more of Examples 26-31 optionally include, wherein the semiconductor package substrate includes a back surface, further comprising: a mid-level interconnect on the back surface, wherein the mid-level interconnect contacts the tapered via within the semiconductor package substrate.

[0107] In Example 33, the subject matter of any one or more of Examples 26-32 optionally include, wherein the semiconductor package substrate includes a back surface, further comprising: a mid-level interconnect on the back surface, wherein the mid-level interconnect contacts the tapered via; and an interposer coupled to the mid-level interconnect.

[0108] In Example 34, the subject matter of any one or more of Examples 26-33 optionally include, wherein the semiconductor package substrate includes a back surface, further comprising: a mid-level interconnect on the back surface, wherein the mid-level interconnect contacts the tapered via; an interposer coupled to the mid-level interconnect; a ball grid array on the interposer; and a board coupled to the ball grid array.

[0109] In Example 35, the subject matter of any one or more of Examples 26-34 optionally include, wherein the semiconductor package substrate includes a back surface, further comprising: a mid-level interconnect on the back surface, wherein the mid-level interconnect contacts the tapered via, and wherein the semiconductor package substrate includes a first tapered via, a second tapered via, a third tapered via, and a fourth tapered via, and a first trace, a second trace, a third trace, and a fourth trace, wherein each tapered via contacts a trace in order, and wherein the fourth trace is disposed at the planarization laminate, and wherein the fourth trace contacts a package post of one of the fourth tapered via.

[0110] In Example 36, the subject matter of any one or more of Examples 26-35 optionally include a fourth die, wherein the first die, the subsequent die, and the fourth die are each coupled to the bridge die.

[0111] In Example 37, the subject matter of any one or more of Examples 26-36 optionally include, wherein the semiconductor package substrate includes four tapered vias that contact four respective sequentially ordered traces in order, and wherein the fourth trace also contacts a package post.

[0112] Example 38 is a computing system comprising: a bridge die disposed in a recess of a semiconductor package substrate, wherein the semiconductor package substrate comprises laser-drilled fill via features coupled to lithographically patterned package post features; a planarization laminate over the package post and the bridge die, wherein the bridge die comprises a bridge die bond pad; planarization electrical bumps coupled to the package post and to the bridge die bond pad; a first semiconductor device coupled to the planarization electrical bumps coupled to the package post; a subsequent semiconductor device coupled to the planarization electrical bumps coupled to the bridge die bond pad; an intermediate interconnect on a surface of the semiconductor package substrate, wherein the intermediate interconnect contacts a cone-shaped via; an interposer coupled to the intermediate interconnect; and a board coupled to the interposer, wherein the board comprises a housing.

[0113] In Example 39, the subject matter of Example 38 optionally comprises, wherein the bridge die is coupled to a chipset.

[0114] In Example 40, the subject matter of any one or more of Examples 38-39 optionally comprise, wherein the subsequent die is a graphics processor, further comprising a fourth die also coupled to the bridge die, wherein the first die and the fourth die are logic processors.

[0115] Example 41 is a semiconductor package apparatus comprising: a bridge die disposed in a recess of a semiconductor package substrate, wherein the semiconductor package substrate comprises laser-drilled fill via features coupled to lithographically patterned package post features; at least one through-silicon via (TSV) in communication through the bridge die to at least one of a trace and a bond pad within the semiconductor package substrate.

[0116] In Example 42, the subject matter of Example 41 optionally comprises, wherein the at least one TSV is coupled to one selected from the group consisting of the trace and the bond pad in the semiconductor package substrate.

[0117] In Example 43, the subject matter of any one or more of Examples 41-42 optionally comprise a fourth die, wherein the first die, the subsequent die, and the fourth die are each coupled to the bridge die.

[0118] The DETAILED DESCRIPTION above includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the application can be practiced. These embodiments are also referred to as "examples." Such examples can include elements in addition to those shown or described. However, the present application also contemplates examples that are only partially illustrated or described. Moreover, the present application also contemplates examples using any combination or permutation of the illustrated, described or other elements.

[0119] In the event that there is a discrepancy between the usage in this document and that in any document incorporated by reference, the usage in this document controls.

[0120] In this document, the terms "a" and "an" are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of "at least one" or "one or more." In this document, the term "or" is used to mean, and is used interchangeably with, the term "and / or," unless otherwise indicated. In this document, the terms "including" and "comprising" are used as the plain-English equivalents of the respective terms "including," "comprising," and "wherein." In this document, the terms "coupled" and "connected," along with their derivatives, can be used to describe one or more structural

[0121] Method examples described herein can be at least partially processor- or computer- implemented. Some examples can include a computer- or machine- readable medium encoded with instructions that, when executed, perform a method described in the above examples. Implementations of such methods can include, for example, code (e.g., microcode, assembly language code, a higher-level language code, etc.) In addition, some examples can include a computer program product embodied on a computer- or machine-readable medium having stored thereon instructions that, when executed, can perform a method described in the above examples. Such a computer program product can be used, for example, to cause a computer or other processor-based device to perform a method described in the above examples. Such a computer program product can be used, for example, to cause a computer or other processor-based device to perform a method described in the above examples. Examples of computer- or machine-readable media include, but are not limited to, hard drives, removable magnetic disks, removable optical disks (e.g., compact disks and digital video disks), magnetic cassettes, memory cards or sticks, RAM, ROM, etc.

[0122] The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) can be used in combination with each other. Other embodiments can be used, such as by one of ordinary skill in the art reviewing the above description. The Abstract is provided to comply with 37 C.F.R. § 1.72(b) to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features can be grouped together to streamline the disclosure. This should not be interpreted as intending that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter can exist in less than all features of a particular disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, by way of examples, or embodiments, and each claim can stand on its own as a separate embodiment, and can be combined in various ways with one another. The scope of the embodiments should be determined with reference to the appended claims, along with the full range of equivalents to which such claims are entitled.

Claims

1. A semiconductor package apparatus comprising: a bridge die disposed in a recess of a semiconductor package substrate, wherein the semiconductor package substrate comprises a tapered shaped fill via having a laser drilled feature, the fill via coupled to a positive solid cylindrical shaped package post having a lithographically patterned feature; a planarization laminate over the package post and the bridge die; a package bond pad patterned on the planarization laminate and contacting the package post; a bridge die bond pad patterned on the planarization laminate and contacting a positive solid cylindrical shaped bridge die post having a lithographically patterned feature; a package to bridge trace patterned on the planarization laminate and contacting the bridge die post and the package post; a planarization electrical bump coupled to the package post and a planarization electrical bump coupled to the bridge die bond pad; a first die coupled to the planarization electrical bump coupled to the package post; and a subsequent die coupled to the planarization electrical bump coupled to the bridge die bond pad.

2. The semiconductor package apparatus of claim 1, further comprising: a protective contact film disposed on each of the package bond pad and the bridge die bond pad and patterned by a patterned photoresist layer.

3. The semiconductor package apparatus of claim 2, wherein, the bridge die is disposed on an adhesive, and wherein the package bond pad and the bridge die bond pad present a planarization over the patterned photoresist layer.

4. The semiconductor package apparatus of claim 2, wherein, the bridge die is disposed on an adhesive, and wherein the package bond pad and the bridge die bond pad present a planarization over the patterned photoresist layer, further comprising a mid-level interconnect on a back surface of the semiconductor package substrate, wherein the mid-level interconnect contacts a tapered via within the semiconductor package substrate.

5. The semiconductor package apparatus of claim 1, wherein, the semiconductor package substrate comprises a back surface, further comprising: a mid-level interconnect on the back surface, wherein the mid-level interconnect contacts a tapered via within the semiconductor package substrate.

6. The semiconductor package apparatus of claim 1, wherein, the semiconductor package substrate comprises a back surface, further comprising: a mid-level interconnect on the back surface, wherein the mid-level interconnect contacts a tapered via; and an interposer coupled to the mid-level interconnect.

7. The semiconductor package apparatus of claim 1, wherein, the semiconductor package substrate comprises a back surface, further comprising: a mid-level interconnect on the back surface, wherein the mid-level interconnect contacts a tapered via; an interposer coupled to the mid-level interconnect; a ball grid array on the interposer; and a board coupled to the ball grid array.

8. The semiconductor package apparatus of claim 1, wherein, the semiconductor package substrate comprises a back surface, further comprising: a mid-level interconnect on the back surface, wherein the mid-level interconnect contacts a tapered via, and wherein the semiconductor package substrate comprises a first tapered via, a second tapered via, a third tapered via, and a fourth tapered via, and a first trace, a second trace, a third trace, and a fourth trace, wherein each tapered via contacts a trace in order, and wherein the fourth trace is disposed at the planarization laminate, and wherein the fourth trace contacts the fourth tapered via and the package post. the semiconductor package substrate comprises a back surface, further comprising: a mid-level interconnect on the back surface, wherein the mid-level interconnect contacts a tapered via, and wherein the semiconductor package substrate comprises a first tapered via, a second tapered via, a third tapered via, and a fourth tapered via, and a first trace, a second trace, a third trace, and a fourth trace, wherein each tapered via contacts a trace in order, and wherein the fourth trace is disposed at the planarization laminate, and wherein the fourth trace contacts the fourth tapered via and the package post.

9. The semiconductor package device of claim 1, further comprising a fourth die, wherein, The first die, the subsequent die, and the fourth die are each coupled to the bridge die.

10. The semiconductor package apparatus of claim 8, wherein, The semiconductor package substrate includes four tapered vias that sequentially contact four respective sequentially ordered traces, and wherein the fourth trace also contacts a package post.

11. A process of forming a semiconductor package apparatus, comprising: lithographically forming a package post of positive solid cylindrical shape on a precursor package substrate to couple the package post with a laser-drilled tapered shape via; positioning a bridge die in a recess in the precursor package substrate; forming a planarization laminate over the precursor package substrate and the bridge die; patternizing a package bond pad on the planarization laminate, wherein the package bond pad contacts the package post; patternizing a bridge die bond pad on the planarization laminate, wherein the bridge die bond pad contacts a bridge die post of positive solid cylindrical shape with lithographically patternized features; patternizing a package-to-bridge trace on the planarization laminate, wherein the package-to-bridge trace contacts the bridge die post and the package post; forming planarization electrical bumps coupled to the precursor package substrate and the bridge die; and 12. The process of claim 11, wherein, positioning a first die and a subsequent die on the planarization electrical bumps under conditions in which the bridge die provides a communication bridge between the first die and the subsequent die. The lithographically forming the package post on the precursor package substrate includes forming the package post on a trace that contacts the package post with a laser-drilled via.

13. The process of claim 11, further comprising: after positioning the bridge die, filling the recess with a laminate, followed by forming the planarization laminate over the precursor package substrate and the bridge die.

14. The process of claim 11, further comprising: positioning the precursor package substrate on a carrier; forming a package bond pad and a bridge die bond pad on the planarization laminate; patterning a photoresist layer on the planarization laminate; patterning a bond layer through the photoresist layer to couple to the post and to the bridge die; and forming a solder paste electrical bump on the bond layer, followed by forming the planarization electrical bumps.

15. The process of claim 11, further comprising bonding the first die and the subsequent die on the planarization electrical bumps by using increased heat and pressure.

16. A computing system, comprising: a bridge die disposed in a recess of a semiconductor package substrate, wherein the semiconductor package substrate includes a tapered shape fill via with laser-drilled features coupled to a package post of positive solid cylindrical shape with lithographically patternized features; a planarization laminate over the package post and the bridge die; a package bond pad patternized on the planarization laminate and contacting the package post; a bridge die bond pad patternized on the planarization laminate and contacting a bridge die post of positive solid cylindrical shape with lithographically patternized features; package-to-bridge traces patterned on the planarization laminate and contacting the bridge die pillars and the package pillars; planarization electrical bumps coupled to the package pillars and planarization electrical bumps coupled to the bridge die bond pads; a first die coupled to the planarization electrical bumps coupled to the package pillars; a subsequent die coupled to the planarization electrical bumps coupled to the bridge die bond pads; a mid-level interconnect on a surface of the semiconductor package substrate, wherein the mid-level interconnect contacts a tapered via; an interposer coupled to the mid-level interconnect; and a board coupled to the interposer, wherein the board comprises a housing.

17. The computing system of claim 16, wherein, the bridge die is coupled to a chipset.

18. The computing system of claim 16, wherein, the subsequent die is a graphics processor, further comprising a fourth die also coupled to the bridge die, wherein the first die and the fourth die are logic processors.

19. A semiconductor package apparatus, comprising: a bridge die disposed in a recess of a semiconductor package substrate, wherein the semiconductor package substrate comprises a tapered shaped fill via having a laser drilled feature, the fill via coupled to a positive solid cylindrical shaped package pillar having a lithographically patterned feature; at least one through-silicon via (TSV) in communication through the bridge die to couple with at least one of a trace and a bond pad within the semiconductor package substrate; a planarization laminate over the package pillar and the bridge die; a package bond pad patterned on the planarization laminate and contacting the package pillar; a bridge die bond pad patterned on the planarization laminate and contacting a positive solid cylindrical shaped bridge die pillar having a lithographically patterned feature; package-to-bridge traces patterned on the planarization laminate and contacting the bridge die pillars and the package pillars; planarization electrical bumps coupled to the package pillars and planarization electrical bumps coupled to the bridge die bond pads; a first die coupled to the planarization electrical bumps coupled to the package pillars; and a subsequent die coupled to the planarization electrical bumps coupled to the bridge die bond pads.

20. The semiconductor package apparatus of claim 19, wherein, the at least one TSV is coupled to one selected from a trace and a bond pad in the semiconductor package substrate.

21. The semiconductor package apparatus of claim 19, further comprising a fourth die, wherein, the first die, the subsequent die, and the fourth die are each coupled to the bridge die. the at least one TSV is coupled to one selected from a trace and a bond pad in the semiconductor package substrate. the first die, the subsequent die, and the fourth die are each coupled to the bridge die.

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