Display Panel

Abstract

A display panel is provided. The display panel may include: an insulating substrate having a display area and a peripheral area adjacent to the display area; a plurality of insulating layers located on the insulating substrate; pixels located on the display area, the pixels including a thin film transistor and an organic light-emitting device connected to the thin film transistor; and a crack dam located on the peripheral area and spaced apart from the pixels. The crack dam may be arranged to be adjacent to one of the side surfaces of the insulating substrate extending in a first direction. The crack dam may include: a plurality of insulating patterns extending in a first direction and spaced apart from each other in a second direction intersecting the first direction; and a plurality of conductive patterns arranged to fill gap areas between the insulating patterns.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2018-0001884 filed on January 5, 2018, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a display panel and a method for manufacturing the display panel, and more particularly, to a high-reliability display panel and a method for manufacturing the high-reliability display panel. Background Art

[0003] The display panel includes a display area provided with pixels and used to display an image. If an electrical signal is applied to the pixel, the pixel emits light constituting the image in response to the applied electrical signal. During the process of manufacturing or using the display panel, the display panel is exposed to various external impacts. For example, an impact to be applied to the outside of the display panel is transmitted to the display area. As a result, some pixels in the display area may be damaged, resulting in a malfunction of the display panel. Summary of the invention

[0004] Aspects of embodiments according to the inventive concept relate to a display panel having improved use reliability and process reliability and a method of manufacturing the same. In addition, aspects of embodiments according to the inventive concept relate to a display panel having a reduced bezel area and a method of manufacturing the same.

[0005] According to an embodiment of the inventive concept, a display panel may include: an insulating substrate having a display area and a peripheral area adjacent to the display area; a plurality of insulating layers located on the insulating substrate; pixels located on the display area, the pixels including a thin film transistor and an organic light-emitting device connected to the thin film transistor; and a crack dam located on the peripheral area and spaced apart from the pixels, the crack dam being adjacent to one of the side surfaces of the insulating substrate extending in a first direction. The crack dam may include: a plurality of insulating patterns extending in a first direction and spaced apart from each other in a second direction intersecting the first direction; and a plurality of conductive patterns filling gap areas between the insulating patterns.

[0006] In an embodiment, the conductive patterns may extend in the first direction and may be spaced apart from each other in the second direction.

[0007] In an embodiment, each of the conductive patterns may be configured to connect adjacent insulating patterns to each other.

[0008] In an embodiment, the thin film transistor may include: a semiconductor pattern; a control electrode spaced apart from the semiconductor pattern when viewed in a plan view and overlapping the semiconductor pattern; an input electrode spaced apart from the control electrode and coupled to a portion of the semiconductor pattern; and an output electrode spaced apart from the control electrode and coupled to an opposite portion of the semiconductor pattern. The conductive pattern may include the same material as that of at least one of the control electrode, the input electrode, and the output electrode.

[0009] In an embodiment, the insulating layer may include: a first insulating layer located between the semiconductor pattern and the control electrode; and a second insulating layer located between the control electrode and the input electrode. The insulating pattern may be located on the same layer as at least one of the first insulating layer and the second insulating layer.

[0010] In an embodiment, each of the insulation patterns may have a double-layered structure.

[0011] In an embodiment, the display panel may further include a base layer between the thin film transistor and the insulating substrate. The base layer may include at least one of a barrier layer and a buffer layer, and the insulating pattern may be located on the same layer as the base layer.

[0012] In embodiments, the insulation pattern may be spaced apart from the base layer in the second direction.

[0013] In an embodiment, one of the conductive patterns may be configured to connect one of the insulating patterns to the base layer.

[0014] In embodiments, the insulating pattern may be connected to at least a portion of the base layer.

[0015] In an embodiment, the insulation pattern may include: a plurality of first insulation patterns spaced apart from each other in the second direction; and a plurality of second insulation patterns spaced apart from each other in the second direction and located on a different layer from the first insulation patterns.

[0016] In an embodiment, the display panel may further include an encapsulation layer located on the display area and configured to cover the pixel. The encapsulation layer may extend to cover the crack dam and contact the insulating pattern and the conductive pattern.

[0017] In an embodiment, each of the insulating pattern and the conductive pattern may include an inorganic material.

[0018] According to an embodiment of the inventive concept, a method for manufacturing a display panel may include: forming a pixel on a mother substrate, the mother substrate having a plurality of display areas and a peripheral area, the pixel being located on each of the display areas and including a thin film transistor and an organic light-emitting device connected to the thin film transistor, the thin film transistor including a semiconductor pattern, a control electrode, an input electrode, and an output electrode; correspondingly forming a plurality of crack dams on the peripheral area to be adjacent to the display area; and cutting the mother substrate along a cutting line defined between the display areas to form a plurality of display panels. The step of forming the crack dam may include: forming a plurality of insulating patterns arranged in a first direction; and filling a gap area between the insulating patterns with a conductive material to form a plurality of conductive patterns.

[0019] In an embodiment, the conductive pattern may be formed concurrently with the control electrode.

[0020] In an embodiment, the conductive pattern may be formed concurrently with the input electrode and the output electrode.

[0021] In an embodiment, the step of cutting the mother substrate may be performed using a laser beam.

[0022] According to an embodiment of the inventive concept, a display panel may include: an insulating substrate having a display area, a peripheral area adjacent to the display area, and a side surface extending in a first direction; a pixel located on the display area, the pixel including a thin film transistor and an organic light-emitting device connected to the thin film transistor; an encapsulation layer configured to cover the pixel and including an inorganic layer and an organic layer; and a crack dam located on the peripheral area, adjacent to the side surface, and extending in the first direction. The crack dam may include: a plurality of inorganic insulating patterns extending in the first direction and spaced apart from each other in a second direction intersecting the first direction; and a plurality of conductive patterns located between the inorganic insulating patterns, configured to connect adjacent inorganic insulating patterns among the inorganic insulating patterns to each other, and spaced apart from each other in the second direction.

[0023] In an embodiment, the inorganic layer of the encapsulation layer may be configured to cover the crack dam. When viewed in a plan view, the organic layer of the encapsulation layer may be spaced apart from the crack dam.

[0024] In embodiments, the inorganic insulating pattern may include a plurality of insulating patterns on different layers, and the inorganic layer of the encapsulation layer may have a step shape on the crack dam. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings.The accompanying drawings illustrate non-limiting example embodiments as described herein.

[0026] Figure 1 is a perspective view schematically illustrating a display panel according to an embodiment of the inventive concept.

[0027] Figure 2A It is shown Figure 1 An equivalent circuit diagram of a portion of a display panel is shown in FIG.

[0028] Figure 2B It is along Figure 1 A cross-sectional view taken along line II'.

[0029] Figure 2C It is shown Figure 2B An enlarged cross-sectional view of a portion of.

[0030] Figure 3A and Figure 3B is a cross-sectional view illustrating a portion of a display panel according to an embodiment of the inventive concept.

[0031] Figure 4A and Figure 4B is a cross-sectional view illustrating a region of a display panel according to an embodiment of the inventive concept.

[0032] FIG. 5A to FIG. 5C is a cross-sectional view illustrating a region of a display panel according to an embodiment of the inventive concept.

[0033] FIG. 6A to FIG. 6C is a schematic perspective view illustrating a method of manufacturing a display panel according to an embodiment of the inventive concept.

[0034] Fig. 7A is a cross-sectional view showing a region of a display panel according to a comparative example, and Figure 7B is a cross-sectional view illustrating a region of a display panel according to an embodiment of the inventive concept.

[0035] FIG. 8A to FIG. 8F is a cross-sectional view illustrating a method of manufacturing a display panel according to an embodiment of the inventive concept.

[0036] 9A to 9F is a cross-sectional view illustrating a method of manufacturing a display panel according to an embodiment of the inventive concept.

[0037] It should be noted that these drawings are intended to illustrate the general characteristics of the methods, structures and / or materials used in specific example embodiments and to supplement the written description provided below. However, these drawings may not be drawn to scale and may not accurately reflect the precise structure or performance characteristics of any given embodiment, and should not be interpreted as defining or limiting the range of values ​​or properties covered by the example embodiments. For example, the relative thickness and position of molecules, layers, regions and / or structural elements may be reduced or exaggerated for clarity. The use of similar or identical reference numerals in the various drawings is intended to indicate the presence of similar or identical elements or features. DETAILED DESCRIPTION

[0038] Example embodiments of the inventive concepts will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown. However, example embodiments of the inventive concepts may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those of ordinary skill in the art. In the accompanying drawings, the thickness of layers and regions is exaggerated for clarity. In the accompanying drawings, like reference numerals denote like elements, and therefore, their description will not be repeated.

[0039] It will be understood that when an element is referred to as being "connected to" or "coupled to" another element, the element may be directly connected to or directly coupled to the other element, or intervening elements may be present. Conversely, when an element is referred to as being "directly connected to" or "directly coupled to" another element, there are no intervening elements. Like reference numerals refer to like elements throughout.

[0040] For ease of description, spatially relative terms such as "below", "below", "below", "above", "above", etc. may be used here to describe the relationship between one element or feature and another (other) element or feature as shown in the drawings. It will be understood that in addition to the orientation depicted in the drawings, the spatially relative terms are also intended to include different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the elements described as "below" or "below" other elements or features will then be positioned as "above" the other elements or features. Therefore, the exemplary term "below" can include both above and below orientations. The device can be positioned otherwise (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptors used here can be interpreted accordingly.

[0041] The terms used herein are only for the purpose of describing specific embodiments and are not intended to be limitations of the exemplary embodiments. As used herein, unless the context clearly indicates otherwise, the singular forms of "a (kind / person)" and "the (the)" are also intended to include plural forms. It will also be understood that if the terms "comprise", "include" and variations thereof are used herein, the stated features, wholes, steps, operations, elements and / or components are indicated, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their groups are not excluded.

[0042] Figure 1 is a perspective view schematically illustrating a display panel according to an embodiment of the inventive concept. Figure 2A It is shown Figure 1 An equivalent circuit diagram of a portion of a display panel is shown in FIG. Figure 2B It is along Figure 1 A cross-sectional view taken along line II'. Figure 2C It is shown Figure 2B For ease of explanation, prepare Figure 2C The magnified shape of the region having the crack dam CRD is shown. Figures 1 to 2C Embodiments of the inventive concept are described.

[0043] The display panel 100 may include an insulating substrate BS, a base layer BL, a circuit layer DP-CL, a display device layer DP-OLED, an encapsulation layer TFE, and a crack dam CRD. The insulating substrate BS may be formed of an insulating material, or include an insulating material. The insulating substrate BS may be formed to have a flexible property. For example, the insulating substrate BS may include polyimide (PI). However, the inventive concept is not limited to this example, and in a specific embodiment, the insulating substrate BS may be formed of at least one of a glass material and a plastic material, or include at least one of a glass material and a plastic material.

[0044] The insulating substrate BS may include a display area DA and a peripheral area NDA. The display area DA may be a region of the display panel 100 for displaying an image. A plurality of pixels PX may be disposed on the display area DA.

[0045] The peripheral area NDA may be positioned adjacent to the display area DA. The peripheral area NDA is shown as having a frame shape surrounding the display area DA. However, the inventive concept is not limited to this example, and in a specific embodiment, the peripheral area NDA may be locally disposed at one of the edge areas of the display area DA. For ease of explanation, some elements constituting the display panel 100 (e.g., some pixels PX and the crack dam CRD) are exemplarily shown in FIG. Figure 1 middle.

[0046] The pixels PX may be arranged to be spaced apart from each other in the first direction DR1 and the second direction DR2. Figure 2A An equivalent circuit diagram of one pixel PX among the pixels PX is shown as an example. However, the inventive concept is not limited to this example, and in certain embodiments, the structure of the pixel PX may be variously changed.

[0047] like Figure 2AAs shown in , the pixel PX may include a first thin film transistor TR1, a capacitor CAP, a second thin film transistor TR2, and an organic light emitting device OLED. The first thin film transistor TR1 may be used as a switching device for controlling a switching (i.e., on / off) operation of the pixel PX. For example, the first thin film transistor TR1 may be used to transmit a data signal from the second signal line DL to the capacitor CAP or the second thin film transistor TR2 in response to a scan signal transmitted through the first signal line GL, or to prevent (e.g., cut off) such transmission of the data signal.

[0048] The capacitor CAP may be connected to the first thin film transistor TR1 and the first power line VDD. The capacitor CAP may be charged with an amount of charge corresponding to a voltage level difference between a data signal transmitted from the first thin film transistor TR1 and a first power voltage applied to the first power line VDD.

[0049] The second thin film transistor TR2 may be connected to the first thin film transistor TR1, the capacitor CAP, and the organic light emitting device OLED. The second thin film transistor TR2 may be used to control a driving current flowing through the organic light emitting device OLED according to the amount of charge stored in the capacitor CAP. The length of time of the on period of the second thin film transistor TR2 may depend on the amount of charge stored in the capacitor CAP. During the on period, the second thin film transistor TR2 may be used to supply a first power supply voltage transmitted through the first power line VDD to the organic light emitting device OLED.

[0050] The organic light emitting device OLED may be connected to the second thin film transistor TR2 and the power supply terminal VSS. The organic light emitting device OLED may be configured to emit light whose intensity is determined by a voltage level difference between a signal transmitted through the second thin film transistor TR2 and a second power supply voltage received through the power supply terminal VSS. A light emitting operation of the organic light emitting device OLED may be performed during a turn-on period of the second thin film transistor TR2.

[0051] The organic light emitting device OLED may be formed of a light emitting material or include a light emitting material. The organic light emitting device OLED may be configured to generate light, the color of which is determined by the light emitting material. The color of the light generated by the organic light emitting device OLED may be one of red, green, blue and white.

[0052] exist Figure 2B In FIG. 1 , some elements constituting the pixel PX (eg, a thin film transistor TR-P (hereinafter, referred to as a pixel transistor TR-P) and an organic light emitting device ED) are shown as examples. Figure 2B As shown in FIG. 1 , the pixel transistor TR-P may be disposed on an insulating substrate BS.

[0053] The pixel transistor TR-P may constitute the circuit layer DP-CL (e.g., may be a component of the circuit layer DP-CL). In the present embodiment, the display panel 100 may further include a base layer BL disposed between the circuit layer DP-CL and the insulating substrate BS. The base layer BL may include a single insulating layer or a plurality of insulating layers. For example, the base layer BL may include at least one of a buffer layer and a barrier layer. Therefore, the circuit layer DP-CL may be stably formed on the base layer BL, and oxygen or moisture that may enter through the insulating substrate BS may be prevented or substantially prevented from penetrating into the circuit layer DP-CL.

[0054] The pixel transistor TR-P may include a semiconductor pattern SP, a control electrode CE, an input electrode IE, and an output electrode OE. The control electrode CE of the pixel transistor TR-P may be spaced apart from the semiconductor pattern SP, and a first insulating layer 10 is interposed between the control electrode CE and the semiconductor pattern SP. The control electrode CE may be connected to Figure 2A The first thin film transistor TR1 is shown in FIG. 1 . The first insulating layer 10 may be used as a gate insulating layer.

[0055] The input electrode IE and the output electrode OE of the pixel transistor TR-P may be spaced apart from the control electrode CE of the pixel transistor TR-P, and the second insulating layer 20 is interposed between the input electrode IE and the output electrode OE and the control electrode CE. The input electrode IE and the output electrode OE of the pixel transistor TR-P may be disposed to penetrate the first insulating layer 10 and the second insulating layer 20, and may be respectively coupled to two separate regions of the semiconductor pattern SP. The input electrode IE of the pixel transistor TR-P may be connected to Figure 2A The capacitor CAP, the output electrode OE of the pixel transistor TR-P may be connected to the organic light emitting device ED.

[0056] Meanwhile, in the pixel transistor TR-P, the control electrode CE may be disposed above the semiconductor pattern SP, or the input electrode IE and the output electrode OE may be disposed above the semiconductor pattern SP. Alternatively, the input electrode IE and the output electrode OE may be disposed on the same layer as the semiconductor pattern SP and may be directly coupled to the semiconductor pattern SP. According to an embodiment of the inventive concept, the structure of the pixel transistor TR-P may be variously changed, and the inventive concept is not limited thereto.

[0057] The organic light emitting device ED may be disposed on the third insulating layer 30. The organic light emitting device ED and the fourth insulating layer 40 may constitute a display device layer DP-OLED. The organic light emitting device ED may include a first electrode E1, a light emitting layer EL, and a second electrode E2 sequentially stacked in the third direction DR3.

[0058] The first electrode E1 may be coupled to the pixel transistor TR-P through the third insulating layer 30. Although not shown, an additional connection electrode may be further disposed between the first electrode E1 and the pixel transistor TR-P, in which case the first electrode E1 may be electrically coupled to the pixel transistor TR-P through the connection electrode.

[0059] The fourth insulating layer 40 may be disposed on the third insulating layer 30. The fourth insulating layer 40 may be disposed to have an opening. The opening may be disposed to expose at least a portion of the first electrode E1. The fourth insulating layer 40 may serve as a pixel defining layer.

[0060] The light emitting layer EL may be disposed on the first electrode E1. The light emitting layer EL may be formed of a light emitting material, or include a light emitting material. For example, the light emitting layer EL may be formed of at least one of a fluorescent material and a phosphorescent material, or include at least one of a fluorescent material and a phosphorescent material. The light emitting layer EL may be configured to emit red light, green light, or blue light in response to a potential difference between the first electrode E1 and the second electrode E2.

[0061] The second electrode E2 may be disposed on the light emitting layer EL. The second electrode E2 may be disposed to face the first electrode E1. The second electrode E2 may be connected to the Figure 2A The organic light emitting device ED may receive a second power supply voltage through the second electrode E2.

[0062] The second electrode E2 may be formed of a transparent conductive material or a transflective conductive material, or include a transparent conductive material or a transflective conductive material. Therefore, the light generated by the light emitting layer EL may easily pass through the second electrode E2 and may travel in the third direction DR3. However, the inventive concept is not limited to this example, and in a specific embodiment, the organic light emitting device ED may be configured as a rear-side emission structure having a first electrode E1 including a transparent material or a transflective material, or as a double-side emission structure in which light is emitted through the top and bottom surfaces of the organic light emitting device ED.

[0063] Although not shown, the organic light emitting device ED may further include at least one organic layer disposed between the light emitting layer EL and the first electrode E1 or between the light emitting layer EL and the second electrode E2. The organic layer may be used to control the flow of charges supplied from the first electrode E1 and the second electrode E2 to the light emitting layer EL, which may improve the optical characteristics and lifespan of the organic light emitting device ED.

[0064] The encapsulation layer TFE may be disposed on the organic light emitting device ED to encapsulate the organic light emitting device ED. Although not shown, a capping layer covering the second electrode E2 may be further disposed between the second electrode E2 and the encapsulation layer TFE.

[0065] The encapsulation layer TFE may include a first inorganic layer IOL1, an organic layer OL, and a second inorganic layer IOL2 sequentially stacked in the third direction DR3. However, the inventive concept is not limited thereto, and in certain embodiments, the encapsulation layer TFE may also include a plurality of inorganic layers and a plurality of organic layers.

[0066] The first inorganic layer IOL1 may be disposed to cover the second electrode E2. The first inorganic layer IOL1 may prevent or substantially prevent external moisture or oxygen from penetrating into the organic light emitting device ED. For example, the first inorganic layer IOL1 may be formed of or include at least one of silicon nitride and silicon oxide. The first inorganic layer IOL1 may be formed by a deposition process.

[0067] The organic layer OL may be disposed on the first inorganic layer IOL1 to contact the first inorganic layer IOL1. The organic layer OL may be configured to improve the uneven surface profile caused by the first inorganic layer IOL1. For example, the organic layer OL may be configured to cover the first inorganic layer IOL1 having an uneven top surface or particles located on the first inorganic layer IOL1, which may be able to prevent or substantially prevent the uneven surface profile or particles of the first inorganic layer IOL1 from affecting the elements located on the organic layer OL. In addition, the organic layer OL may be configured to relieve stress between layers that are in contact with each other. The organic layer OL may be formed of an organic material, or include an organic material, and may be formed by a solution-based film forming process (e.g., a spin coating process, a slit coating process, or an inkjet process).

[0068] The second inorganic layer IOL2 may be disposed on the organic layer OL to cover the organic layer OL. Since the organic layer OL has a relatively flat top surface, the second inorganic layer IOL2 may be formed more stably than in the case where the second inorganic layer IOL2 is formed on the first inorganic layer IOL1. The second inorganic layer IOL2 may be configured to encapsulate the organic layer OL. The second inorganic layer IOL2 may be formed of or include at least one of silicon nitride and silicon oxide. The second inorganic layer IOL2 may be formed by a deposition process.

[0069] Although not shown, an input sensing unit including a plurality of sensor patterns may be further provided on the encapsulation layer TFE. The input sensing unit may be formed directly on the encapsulation layer TFE and may be used to sense external inputs such as touch events or pressure events. However, the inventive concept is not limited to this example, and in certain embodiments, the structure of the display panel 100 may be variously changed.

[0070] The display panel 100 may further include a thin film transistor TR-D (hereinafter, referred to as a driving transistor TR-D), conductive patterns E-VSS, E-CNT, VIN and CL, and dams DM1 and DM2 disposed on the peripheral area NDA.

[0071] The driving transistor TR-D may constitute the circuit layer DP-CL. In the present embodiment, the driving transistor TR-D may have a structure corresponding to the structure of the pixel transistor TR-P. For example, the driving transistor TR-D may include a semiconductor pattern SP disposed on the base layer BL, a control electrode CE disposed on the first insulating layer 10, and an input electrode IE and an output electrode OE disposed on the second insulating layer 20. Therefore, the pixel transistor TR-P and the driving transistor TR-D may be formed concurrently (e.g., simultaneously) by the same process, and therefore, the manufacturing process may be simplified and the process cost may be reduced. However, the inventive concept is not limited to this example, and in a specific embodiment, the driving transistor TR-D may have a structure different from that of the pixel transistor TR-P.

[0072] The conductive patterns E-VSS, E-CNT, VIN, and CL may include a power supply line E-VSS, a connection electrode E-CNT, an initialization voltage line VIN, and a signal line CL. The power supply line E-VSS may correspond to a power supply terminal VSS of the pixel PX. Therefore, the power supply line E-VSS may be used to supply a second power supply voltage to the organic light emitting device ED. In this embodiment, the second power supply voltage may be commonly supplied to a plurality of pixels PX.

[0073] The power supply line E-VSS as part of the circuit layer DP-CL may be disposed on the second insulating layer 20. The power supply line E-VSS and the input electrode IE or the output electrode OE of the driving transistor TR-D may be formed simultaneously or concurrently by the same process. However, the inventive concept is not limited to this example, and in a specific embodiment, the power supply line E-VSS may be formed by a process different from the process of forming the input electrode IE or the output electrode OE, and may be disposed on a layer different from the layer located below the input electrode IE or the output electrode OE.

[0074] The connection electrode E-CNT may be disposed on the third insulating layer 30 to constitute the display device layer DP-OLED. The connection electrode E-CNT may be electrically coupled to the power supply line E-VSS. The connection electrode E-CNT may extend from the top surface of the third insulating layer 30 to cover the top surface of the power supply line E-VSS exposed by the third insulating layer 30.

[0075] The second electrode E2 of the organic light emitting device ED may extend from the display area DA and may be coupled to the connection electrode E-CNT. The connection electrode E-CNT may receive a second power supply voltage from the power supply line E-VSS. Therefore, the second power supply voltage may be transmitted to the second electrode E2 through the connection electrode E-CNT and may be provided (e.g., transmitted) to each pixel PX.

[0076] The connection electrode E-CNT may be disposed on the same layer as the first electrode E1 of the organic light-emitting device ED and may be formed concurrently with the first electrode E1. However, the inventive concept is not limited to this example, and in certain embodiments, the connection electrode E-CNT may be disposed on a layer different from a layer below the first electrode E1.

[0077] In an embodiment, a plurality of signal lines CL may be disposed on the second insulating layer 20. The signal lines CL may be spaced apart from each other in the first direction DR1, and may be used to independently transmit electrical signals.

[0078] The initialization voltage line VIN can be used to provide an initialization voltage to the pixel PX. The initialization voltage line VIN can be coupled to a plurality of pixels PX correspondingly, and can be used to provide an initialization voltage to each pixel PX. In the present embodiment, the signal line CL and the initialization voltage line VIN can be formed on the same layer and formed concurrently (e.g., simultaneously) by the same process. However, the inventive concept is not limited to this example, and in a particular embodiment, the signal line CL and the initialization voltage line VIN can be independently formed by different processes.

[0079] When the organic layer OL of the encapsulation layer TFE is formed on the display area DA, the dams DM1 and DM2 may prevent or substantially prevent the organic layer OL from being formed outside the dams DM1 and DM2. The dams DM1 and DM2 may be disposed close to at least one of the edge regions of the display area DA. When viewed in a plan view, the dams DM1 and DM2 may be disposed to surround the display area DA. The dams DM1 and DM2 may include a plurality of dams (e.g., a first dam DM1 and a second dam DM2).

[0080] The first dam DM1 may be disposed closer to the display area DA than the second dam DM2. When viewed in a plan view, the first dam DM1 may overlap the power supply line E-VSS. In the present embodiment, when viewed in a cross-sectional view, the connection electrode E-CNT may include a portion disposed between the first dam DM1 and the power supply line E-VSS.

[0081] In the present embodiment, the first dam portion DM1 may be formed of or include the same material as that of the fourth insulating layer 40, and may be formed concurrently (e.g., simultaneously) using the same mask as that used for the fourth insulating layer 40. In this case, an additional process for forming the first dam portion DM1 may be omitted, and this may be able to simplify the manufacturing process and reduce the process cost.

[0082] The second dam portion DM2 may be disposed at a relatively outer region compared to the first dam portion DM1. The second dam portion DM2 may be disposed to cover a portion of the power supply line E-VSS. In an embodiment, the second dam portion DM2 may have a double-layer structure including a first layer DM2-L1 and a second layer DM2-L2. For example, the first layer DM2-L1 and the third insulating layer 30 may be formed simultaneously (e.g., concurrently), and the second layer DM2-L2 and the fourth insulating layer 40 may be formed simultaneously (e.g., concurrently). Therefore, the second dam portion DM2 may be easily formed without the need for an additional process.

[0083] In the present embodiment, the connection electrode E-CNT may be disposed on the first layer DM2-L1 of the second dam portion DM2 to overlap a portion of the first layer DM2-L1. For example, the connection electrode E-CNT may include an end portion disposed between the first layer DM2-L1 and the second layer DM2-L2. However, the inventive concept is not limited to this example, and in certain embodiments, the connection electrode E-CNT may not extend to the second dam portion DM2.

[0084] The first inorganic layer IOL1 and the second inorganic layer IOL2 may extend from the display area DA to the outer area of ​​the second dam DM2. Therefore, the first inorganic layer IOL1 and the second inorganic layer IOL2 may cover the first dam DM1 and the second dam DM2. The organic layer OL may be located in an inner area outside the second dam DM2 (e.g., an inner area away from the second dam DM2).

[0085] The crack dam CRD may be disposed on the peripheral area NDA. Figures 1 to 2C , the crack dam CRD may be disposed on the peripheral area NDA to be adjacent to the edge EG of the insulating substrate BS. Figure 2B and Figure 2C , one of the side surfaces of the insulating substrate BS is shown as an edge EG, and one crack dam CRD adjacent to the edge EG is shown. However, the inventive concept is not limited to this example, and in certain embodiments, a plurality of crack dams CRD may be provided adjacent to two or more of the side surfaces of the insulating substrate BS.

[0086] The crack dam CRD may extend in an extension direction of the edge EG adjacent thereto. In an embodiment, the extension direction of the edge EG may be parallel to the second direction DR2, and thus the crack dam CRD may extend in the second direction DR2. The crack dam CRD may include a plurality of inorganic insulation patterns ILP and a plurality of conductive patterns MTP.

[0087] The inorganic insulation patterns ILP may be arranged to be spaced apart from each other in the first direction DR1. In an embodiment, a gap region may be defined between the inorganic insulation patterns ILP. Each of the inorganic insulation patterns ILP may be a linear structure extending in the second direction DR2. The inorganic insulation patterns ILP may be arranged to be parallel to each other in the first direction DR1.

[0088] The inorganic insulating pattern ILP may prevent or substantially prevent an impact applied from the outside through the edge EG, or a crack therefrom from being transmitted or extended to an element (e.g., a driving transistor TR-D, a pixel transistor TR-P, or an organic light emitting device ED) constituting the display panel 100. The inorganic insulating pattern ILP may be spaced apart from each other in the first direction DR1, thereby preventing or substantially preventing an impact or a crack from being transmitted or extended in the first direction DR1. Therefore, the reliability of the display panel 100 may be improved.

[0089] The conductive patterns MTP may be respectively arranged in the gap regions defined between the inorganic insulating patterns ILP. For example, the conductive patterns MTP may be arranged to fill the gap regions. Therefore, each of the conductive patterns MTP may have a shape corresponding to a corresponding one of the gap regions. In the present embodiment, each of the conductive patterns MTP may be a linear structure extending in the second direction DR2.

[0090] In the present embodiment, the conductive patterns MTP may be arranged to be spaced apart from each other in the first direction DR1. Each of the conductive patterns MTP may be arranged to be in direct contact with a pair of adjacent corresponding inorganic insulating patterns ILP. For example, each of the conductive patterns MTP may be arranged to cover the opposite side surfaces of a pair of adjacent corresponding inorganic insulating patterns ILP and the top surface of the insulating substrate BS located between the pair of adjacent corresponding inorganic insulating patterns ILP. The inorganic insulating patterns ILP separated from each other may be physically connected to each other through the conductive patterns MTP.

[0091] In the present embodiment, at least a portion of the conductive pattern MTP may also be disposed to fill a gap region between the inorganic insulating pattern ILP and the base layer BL. Therefore, the crack dam CRD may be disposed to contact the base layer BL.

[0092] The conductive pattern MTP may be formed of a conductive material, or include a conductive material. For example, the conductive pattern MTP may be formed of the same material as the material of the control electrode CE of the pixel transistor TR-P, or include the same material as the material of the control electrode CE of the pixel transistor TR-P. Here, the conductive pattern MTP may be formed concurrently (e.g., simultaneously) with the process for the control electrode CE of the pixel transistor TR-P.

[0093] The conductive pattern MTP may be formed of the same material as that of the input electrode IE and the output electrode OE of the pixel transistor TR-P, or include the same material as that of the input electrode IE and the output electrode OE of the pixel transistor TR-P. Here, the conductive pattern MTP may be formed concurrently (e.g., simultaneously) by the same process as that for the input electrode IE and the output electrode OE of the pixel transistor TR-P.

[0094] Therefore, the conductive pattern MTP may be formed without an additional process, which may simplify the manufacturing process and reduce the process cost. However, the inventive concept is not limited to this example, and in certain embodiments, the conductive pattern MTP and the pixel transistor TR-P may be independently formed by different processes.

[0095] According to an embodiment of the inventive concept, since the gap region between the inorganic insulating patterns ILP is covered with the conductive pattern MTP, during the manufacturing process, particles may be prevented or substantially prevented from entering the gap region between the inorganic insulating patterns ILP. In addition, even when particles enter the gap region between the inorganic insulating patterns ILP during the manufacturing process, since the conductive pattern MTP covers the gap region, the process of forming the organic light-emitting device ED may be prevented or substantially prevented from being affected by the particles remaining in the gap region between the inorganic insulating patterns ILP. Therefore, the process reliability of the manufacturing process may be improved. This will be described in more detail below.

[0096] Figure 3A and Figure 3B is a cross-sectional view showing a portion of a display panel according to an embodiment of the inventive concept. For ease of explanation, Figure 3A and Figure 3B Shown with Figure 2C In the following, reference will be made to Figure 3A and Figure 3B A display panel according to an embodiment of the inventive concept is described. For the sake of brevity, the previous reference Figures 1 to 2C The described elements may be identified with the same reference numerals without repeating their repeated descriptions.

[0097] like Figure 3AAs shown in , the crack dam CRD-S1 may be disposed to be spaced apart from the base layer BL. The crack dam CRD-S1 may be spaced apart from an end of the base layer BL in the first direction DR1, thereby defining a gap region SS.

[0098] The crack dam CRD-S1 may include an inorganic insulating pattern ILP and a conductive pattern MTP-S disposed to fill a gap region between the inorganic insulating patterns ILP. The conductive pattern MTP-S may not be disposed in the gap region SS between the crack dam CRD-S1 and the base layer BL. The inorganic insulating pattern ILP of the crack dam CRD-S1 may be physically separated from the base layer BL.

[0099] Alternatively, if Figure 3B As shown in , the crack dam CRD-S2 may be inserted into the base layer BL-S. The base layer BL-S may extend to the edge EG of the insulating substrate BS, and the inorganic insulating pattern ILP-S of the crack dam CRD-S2 may be formed by removing some portions of the base layer BL-S.

[0100] The conductive pattern MTP-S of the crack dam CRD-S2 may be configured to fill the gap region between the inorganic insulating patterns ILP-S. For example, the conductive pattern MTP-S may be formed to fill the removed portion of the base layer BL-S. Thus, the crack dam CRD-S2 and the base layer BL-S may be formed to constitute a single object.

[0101] According to an embodiment of the inventive concept, if a display panel is configured to include a plurality of insulating patterns spaced apart from each other and a plurality of conductive patterns disposed to fill gap regions between the insulating patterns, the structure of the crack dam CRD-S1 or CRD-S2 may be variously changed.

[0102] Figure 4A and Figure 4B is a cross-sectional view showing a region of a display panel according to an embodiment of the inventive concept. For ease of explanation, Figure 4A and Figure 4B Shown with Figure 2B In the following, reference will be made to Figure 4A and Figure 4B A display panel according to an embodiment of the inventive concept is described. For the sake of brevity, the previous reference Figures 1 to 3B The described elements may be identified with the same reference numerals without repeating their repeated descriptions.

[0103] like Figure 4A As shown in , the display panel 100-1 may include a crack dam CRD-1 disposed on a base layer BL-1. The base layer BL-1 may be disposed to substantially cover the entire top surface of the insulating substrate BS and may entirely overlap the display area DA and the peripheral area NDA.

[0104] The crack dam CRD-1 may be disposed adjacent to the ends of the first insulating layer 10 and the second insulating layer 20. The crack dam CRD-1 may include a plurality of inorganic insulating patterns ILP-1 and a plurality of conductive patterns MTP. The inorganic insulating patterns ILP-1 may be spaced apart from the ends of the first insulating layer 10 and the second insulating layer 20 in the first direction DR1. In addition, the inorganic insulating patterns ILP-1 may be spaced apart from each other in the first direction DR1, thereby defining a gap region therebetween.

[0105] Each of the inorganic insulating patterns ILP-1 may have a double-layer structure. For example, the inorganic insulating pattern ILP-1 may include a plurality of first layers P1 extending in the second direction DR2 and arranged in the first direction DR1, and a plurality of second layers P2 extending in the second direction DR2 and arranged in the first direction DR1. Each of the second layers P2 may be stacked on a corresponding one of the first layers P1.

[0106] The first layer P1 may be formed on the same layer as the first insulating layer 10. The first layer P1 may be formed of the same material as the first insulating layer 10, and may have the same thickness as the first insulating layer 10. The second layer P2 may be formed on the same layer as the second insulating layer 20. The second layer P2 may be formed of the same material as the second insulating layer 20, and may have the same thickness as the second insulating layer 20.

[0107] The conductive patterns MTP may be disposed to fill a gap region between the inorganic insulation patterns ILP- 1 . Each of the conductive patterns MTP may be disposed to connect an adjacent corresponding pair of the inorganic insulation patterns ILP- 1 to each other.

[0108] The conductive pattern MTP may be formed of a conductive material, or include a conductive material. For example, the conductive pattern MTP may include the same material as the input electrode IE and the output electrode OE of the pixel transistor TR-P. Here, the conductive pattern MTP may be formed concurrently (e.g., simultaneously) with the same process as the process for the input electrode IE and the output electrode OE of the pixel transistor TR-P. However, the inventive concept is not limited to this example, and in a particular embodiment, the conductive pattern MTP may be independently formed by a process different from the process for the input electrode IE and the output electrode OE of the pixel transistor TR-P.

[0109] In a specific embodiment, if Figure 4BAs shown in , the display panel 100-2 may include a crack dam CRD-2 including inorganic insulating patterns ILP1 and ILP2 disposed on different layers and a conductive pattern MTP. The inorganic insulating patterns ILP1 and ILP2 may include a first inorganic insulating pattern ILP1 disposed on an insulating substrate BS and a second inorganic insulating pattern ILP2 disposed on a base layer BL.

[0110] The first inorganic insulating pattern ILP1 may be disposed on the same layer as the base layer BL and may be spaced apart from an end of the base layer BL. Figure 2B The conductive patterns MTP may be provided to fill gap regions formed between the first inorganic insulating patterns ILP1 and between the base layer BL and the first inorganic insulating pattern ILP1, respectively.

[0111] The second inorganic insulating pattern ILP2 may have a double-layer structure. The second inorganic insulating pattern ILP2 may include a first layer P1 disposed on the same layer as the first insulating layer 10 and a second layer P2 stacked on the first layer P1 and disposed on the same layer as the second insulating layer 20. Figure 4A The conductive pattern MTP may be provided to fill gap regions formed between the second inorganic insulating patterns ILP2, between the first insulating layer 10 and the second inorganic insulating pattern ILP2, and between the second insulating layer 20 and the second inorganic insulating pattern ILP2, respectively.

[0112] As described with reference to the crack dam CRD-1 of the display panel 100-1 or the crack dam CRD-2 of the display panel 100-2, the crack dam may be provided at any level of the display panel 100-1 or 100-2, and this may stably prevent or substantially prevent impact or cracks from being transmitted or extended laterally in each layer. Therefore, the reliability of the display panel 100-1 or 100-2 may be improved.

[0113] FIG. 5A to FIG. 5C is a cross-sectional view showing a region of a display panel according to an embodiment of the inventive concept. For ease of explanation, FIG. 5A to FIG. 5C Shown with Figure 2B In the following, reference will be made to FIG. 5A to FIG. 5C A display panel according to an embodiment of the inventive concept is described. For the sake of brevity, the previous reference Figures 1 to 4B The described elements may be identified with the same reference numerals without repeating their repeated descriptions.

[0114] like Figure 5AAs shown in FIG. 1 , the display panel 100 - 3 may include an encapsulation layer TFE-1 extending onto the crack dam CRD. The crack dam CRD and the base layer BL may be disposed on the same layer. In this embodiment, the crack dam CRD may be disposed on the same layer as the base layer BL. Figure 2B The fracture bar CRD corresponds to that shown in .

[0115] When viewed in a plan view, the encapsulation layer TFE-1 may overlap the crack dam CRD. The organic layer OL1 of the encapsulation layer TFE-1 may overlap the crack dam CRD. Figure 2B , but the first and second inorganic layers IOL11 and IOL21 of the encapsulation layer TFE-1 may extend beyond the second dam portion DM2 to cover an end of the second insulating layer 20, an end of the first insulating layer 10, and a top surface of the crack dam CRD.

[0116] The top surface of the inorganic insulating pattern ILP and the top surface of the conductive pattern MTP may be in contact with the first inorganic layer IOL11. Since the inorganic insulating pattern ILP and the conductive pattern MTP are formed of an inorganic material, the first inorganic layer IOL11 in contact with the inorganic insulating pattern ILP and the conductive pattern MTP may be closely attached to the crack dam CRD. Therefore, delamination of the encapsulation layer TFE-1 on the crack dam CRD may be prevented or substantially prevented, thereby improving the encapsulation properties of the encapsulation layer TFE-1.

[0117] In a specific embodiment, if Figure 5B As shown in FIG. 1 , the display panel 100-4 may include an encapsulation layer TFE-2 extending onto the crack dam CRD-1. The crack dam CRD-1 may be disposed on the base layer BL-1 to have a stacked structure. In this embodiment, the crack dam CRD-1 may be disposed on the base layer BL-1 to have a stacked structure. Figure 4A The crack dam shown corresponds to CRD-1.

[0118] The encapsulation layer TFE-2 may include a first inorganic layer IOL12, a second inorganic layer IOL22, and an organic layer OL2. The organic layer OL2 may be Figure 4A , but the first inorganic layer IOL12 and the second inorganic layer IOL22 may extend to cover the top surface of the crack dam CRD-1 defined by the top surface of the second layer P2 and the top surface of the conductive pattern MTP. The inorganic insulating pattern ILP-1 and the conductive pattern MTP may have a top surface in contact with the first inorganic layer IOL12.

[0119] like Figure 5C As shown in FIG. 1 , the display panel 100-5 may include an encapsulation layer TFE-3 extending onto the crack dam CRD-2. The crack dam CRD-2 may include inorganic insulating patterns ILP1 and ILP2 disposed on different layers. In this embodiment, the crack dam CRD-2 may be Figure 4BThe fracture dam shown in CRD-2 corresponds.

[0120] The encapsulation layer TFE-3 may include a first inorganic layer IOL13, a second inorganic layer IOL23, and an organic layer OL3. The organic layer OL3 may be Figure 4B The first inorganic layer IOL13 and the second inorganic layer IOL23 correspond to the organic layer OL shown in FIG. 1 , but the first inorganic layer IOL13 and the second inorganic layer IOL23 may extend to cover the top surface of the crack dam CRD-2. The first inorganic layer IOL13 and the second inorganic layer IOL23 may be disposed to cover the first inorganic insulating pattern ILP1 and the second inorganic insulating pattern ILP2 and have a step shape on the crack dam CRD-2.

[0121] In the display panel 100-3, 100-4 or 100-5 according to the embodiment of the inventive concept, the encapsulation layer TFE-1, TFE-2 or TFE-3 may extend to the crack dam CRD, CRD-1 or CRD-2. The inorganic insulating pattern ILP, ILP-1, ILP1 or ILP2 and the conductive pattern MTP may be formed of an inorganic material, or include an inorganic material. Therefore, the first inorganic layer IOL11, IOL12 or IOL13 may be tightly (e.g., strongly) attached to the crack dam CRD, CRD-1 or CRD-2. Therefore, it may be possible to prevent or substantially prevent the encapsulation layer TFE-1, TFE-2 or TFE-3 from being delaminated on the crack dam CRD, CRD-1 or CRD-2, thereby improving the encapsulation properties of the encapsulation layer TFE-1, TFE-2 or TFE-3.

[0122] According to an embodiment of the inventive concept, the encapsulation layer TFE-1, TFE-2 or TFE-3 is provided to cover the crack dam CRD, CRD-1 or CRD-2, and the crack dam CRD, CRD-1 or CRD-2 may be formed without providing an additional area for the crack dam CRD, CRD-1 or CRD-2 outside the encapsulation layer TFE-1, TFE-2 or TFE-3. Therefore, the distance from the end of the insulating substrate BS to the encapsulation layer TFE-1, TFE-2 or TFE-3 may be reduced, and therefore, the area of ​​the peripheral area NDA may be reduced and the area of ​​the border area of ​​the display panel 100-3, 100-4 or 100-5 may be reduced.

[0123] FIG. 6A to FIG. 6C is a schematic perspective view illustrating a method of manufacturing a display panel according to an embodiment of the inventive concept. Fig. 7A is a cross-sectional view showing a region of a display panel according to a comparative example, Figure 7B is a cross-sectional view illustrating a region of a display panel according to an embodiment of the inventive concept.

[0124] The steps of forming a plurality of display panels 100-A, 100-B, 100-C, and 100-D from a mother substrate 1000 can be briefly shown in FIG. FIG. 6A to FIG. 6C middle. Fig. 7A Shown with Figure 2B The area shown in corresponds to the area, Figure 7B It is shown Figure 6C 6A to 6B are cross-sectional views of one of the display panels 100-A, 100-B, 100-C and 100-D. Figure 7B Describe some display panels. For the sake of brevity, previously referenced Figures 1 to 5C The described elements may be identified with the same reference numerals without repeating their repeated descriptions.

[0125] like Fig. 6A As shown in FIG. 1 , the mother substrate 1000 may include a plurality of crack dams CRD-A1, CRD-A2, CRD-B1, CRD-B2, CRD-C1, CRD-C2, CRD-D1, and CRD-D2 adjacent to a plurality of display areas DA1, DA2, DA3, and DA4. Each of the display areas DA1, DA2, DA3, and DA4 may be adjacent to the above-mentioned display area DA (e.g., see FIG. 1 ). Figure 1 The display areas DA1, DA2, DA3 and DA4 may be formed by the same process.

[0126] Each of the crack dams CRD-A1, CRD-A2, CRD-B1, CRD-B2, CRD-C1, CRD-C2, CRD-D1, and CRD-D2 may be disposed on (e.g., adjacent to) a corresponding one of the display areas DA1, DA2, DA3, and DA4. In the present embodiment, a pair of crack dams may be disposed adjacent to a corresponding one of the display areas DA1, DA2, DA3, and DA4.

[0127] The cutting line CTL may be defined between the display areas DA1, DA2, DA3, and DA4. For example, the cutting line CTL may be defined to determine the insulating substrate BS (eg, see Figure 2B ). The cutting line CTL may define an edge of each of the display areas DA1, DA2, DA3, and DA4.

[0128] The crack dams CRD-A1, CRD-A2, CRD-B1, CRD-B2, CRD-C1, CRD-C2, CRD-D1, and CRD-D2 may extend in an extending direction of the cutting line CTL adjacent thereto. The crack dams CRD-A1, CRD-A2, CRD-B1, CRD-B2, CRD-C1, CRD-C2, CRD-D1, and CRD-D2 may include first crack dams CRD-A1, CRD-B1, CRD-C1, and CRD-D1 extending in the second direction DR2 and second crack dams CRD-A2, CRD-B2, CRD-C2, and CRD-D2 extending in the first direction DR1. The cutting line CTL extending in the second direction DR2 may be located between two relative first crack dams among the first crack dams CRD-A1, CRD-B1, CRD-C1, and CRD-D1, and the cutting line CTL extending in the first direction DR1 may be located between two relative second crack dams among the second crack dams CRD-A2, CRD-B2, CRD-C2, and CRD-D2.

[0129] Then, if Figure 6B and Figure 6C As shown in FIG. 1 , the mother substrate 1000 may be cut along cutting lines CTL to form a plurality of display panels 100-A, 100-B, 100-C, and 100-D. The display areas DA1, DA2, DA3, and DA4 may be spaced apart from each other along the cutting lines CTL interposed therebetween.

[0130] The laser module LM may be used to perform cutting of the mother substrate 1000. The laser module LM may be configured to irradiate a laser beam LS onto the mother substrate 1000 along a cutting line CTL, and the irradiation process may be used to separate the mother substrate 1000 into display panels 100-A, 100-B, 100-C, and 100-D including display areas DA1, DA2, DA3, and DA4, respectively.

[0131] Here, when the mother substrate 1000 is cut along the cutting line CTL, an impact may be applied to each of the display areas DA1, DA2, DA3, and DA4. For example, the impact may be transmitted from the cutting line CTL toward the display areas DA1, DA2, DA3, and DA4. However, according to an embodiment of the inventive concept, the propagation of such an impact may be prevented or reduced by the crack dams CRD-A1, CRD-A2, CRD-B1, CRD-B2, CRD-C1, CRD-C2, CRD-D1, and CRD-D2 formed along the cutting line CTL. Therefore, it may be possible to prevent or substantially prevent an impact that may occur along the cutting line CTL during the cutting process, or the resulting cracks from being transmitted or extended to the display areas DA1, DA2, DA3, and DA4, thereby improving the process reliability of the manufacturing process.

[0132] According to an embodiment of the inventive concept, it is possible to reduce the area of ​​the peripheral region or the frame region of each of the display panels 100-A, 100-B, 100-C, and 100-D. Fig. 7A and Figure 7B A comparative display panel 100-CE and a display panel 100-A according to a comparative embodiment are compared with each other. Figure 7B As shown in FIG. 1 , the display panel 100-A is constructed to have Figure 2B The features of the display panel 100 are substantially the same as the features of Fig. 7A As shown in , the comparative display panel 100 -CE is configured to have substantially the same features as those of the display panel 100 -A, except for differences related to the structure of the crack dam CRD-C.

[0133] like Fig. 7A As shown in FIG. 1 , in a comparative display panel 100 -CE according to a comparative embodiment, the crack dam CRD-C may include an inorganic insulating pattern ILP and an organic insulating pattern OLP. The inorganic insulating pattern ILP may be covered by the organic insulating pattern OLP.

[0134] In order to reduce the width of the margin area MGA defined between the crack dam CRD-C and the end of the insulating substrate BS, as shown by the arrow, the laser beam LS from the laser module LM is irradiated onto the area close to the crack dam CRD-C. In this case, the laser beam LS may easily damage the organic insulation pattern OLP. In addition, if the laser beam LS is irradiated onto the organic insulation pattern OLP, a contamination material such as carbide may be easily generated from a portion of the organic insulation pattern OLP. Therefore, in the comparative display panel 100-CE, in order to prevent or substantially prevent the organic insulation pattern OLP from being damaged, the margin area MGA should be set to have a sufficiently large width.

[0135] On the contrary, Figure 7B As shown in , the crack dam CRD of the display panel 100 -A may include a conductive pattern MTP instead of the organic insulation pattern OLP. The inorganic insulation pattern ILP may be covered by the conductive pattern MTP, and a gap area between the inorganic insulation patterns ILP may be filled with the conductive pattern MTP.

[0136] In the case where the laser beam LS from the laser module LM is irradiated onto the region adjacent to the crack dam CRD to reduce the width of the margin area MGA as indicated by the arrow, the conductive pattern MTP of the display panel 100-A may have relatively high tolerance to the laser beam LS compared to the organic insulating pattern OLP. Therefore, even when the laser beam LS is irradiated onto the region adjacent to the crack dam CRD, the crack dam CRD may be stably maintained. Therefore, the cutting process may be performed to effectively reduce the width of the margin area MGA, and this may enable the display panel 100-A to have a narrow frame area compared to the comparative display panel 100-CE.

[0137] According to an embodiment of the inventive concept, since the gap region between the inorganic insulating patterns ILP is filled with the conductive pattern MTP, contamination materials (e.g., dust or particles) generated from the insulating substrate BS in the cutting process using the laser beam LS may be prevented or substantially prevented from entering the gap region between the inorganic insulating patterns ILP. Therefore, process reliability may be improved in the process of manufacturing a display panel.

[0138] FIG. 8A to FIG. 8F is a cross-sectional view showing a method of manufacturing a display panel according to an embodiment of the inventive concept. FIG. 8A to FIG. 8F Each of the Figure 2B In the following, reference will be made to FIG. 8A to FIG. 8F A method of manufacturing a display panel according to an embodiment of the inventive concept is described.

[0139] like Fig. 8A As shown in , an initial base layer BL-I may be formed on an insulating substrate BS. The initial base layer BL-I may be formed of an insulating material, or include an insulating material. The initial base layer BL-I may be formed of an inorganic material, and may be formed by a deposition process.

[0140] like Figure 8B As shown in FIG. 1 , the preliminary base layer BL-I may be patterned to form a base layer BL and a plurality of inorganic insulation patterns ILP. The inorganic insulation patterns ILP may be spaced apart from each other to form gap regions OP.

[0141] like Figure 8C As shown in , a semiconductor pattern SP and a first insulating layer 10 may be formed on a base layer BL. The semiconductor pattern SP may be formed by patterning a semiconductor material. The first insulating layer 10 may be provided on the base layer BL to cover the semiconductor pattern SP. When viewed in a plan view, the first insulating layer 10 may be formed to be spaced apart from the inorganic insulating pattern ILP. The first insulating layer 10 may be formed of an inorganic material and may be formed by a deposition process.

[0142] like Fig.8D and Fig. 8E As shown in , a conductive layer CLL may be formed on the first insulating layer 10, and the conductive layer CLL may be patterned to form a control electrode CE and a plurality of conductive patterns MTP. The conductive layer CLL may be formed to cover the first insulating layer 10 and the inorganic insulating pattern ILP. The conductive layer CLL may be formed by depositing or coating a conductive material on the first insulating layer 10.

[0143] The control electrode CE and the conductive pattern MTP may be formed concurrently (e.g., simultaneously) by the same process. For example, the control electrode CE and the conductive pattern MTP may be formed using a single common mask. The conductive pattern MTP may be formed of the same material as that of the control electrode CE and may have the same layer structure as that of the control electrode CE.

[0144] The conductive pattern MTP in combination with the inorganic insulating pattern ILP may constitute a crack dam CRD. In an embodiment, since the crack dam CRD is formed using the same process as that used to form the base layer BL or the control electrode CE, the crack dam CRD may be easily formed without increasing the number of masks or process steps. This may simplify the manufacturing process and reduce the process cost.

[0145] Then, if Figure 8F As shown in , a circuit layer DP-CL, a display device layer DP-OLED, and an encapsulation layer TFE may be sequentially formed to form the display panel 100. Each of the circuit layer DP-CL, the display device layer DP-OLED, and the encapsulation layer TFE may be formed by one of known techniques, and a detailed description thereof will be omitted.

[0146] As described above, before forming the circuit layer DP-CL, the display device layer DP-OLED, and the encapsulation layer TFE, the gap region OP between the inorganic insulating patterns ILP may be filled with the conductive pattern MTP. Therefore, even if contamination material remains in the gap region OP between the inorganic insulating patterns ILP, because when forming the circuit layer DP-CL, the display device layer DP-OLED, and the encapsulation layer TFE, the remaining contamination material is covered with the conductive pattern MTP, it is possible to prevent or substantially prevent the contamination material from damaging the elements of the display panel. This can improve the process reliability of the manufacturing process.

[0147] In addition, as described above, since the cell and the crack dam CRD are formed using the existing process of forming the cell, there is no need to perform an additional process for forming the crack dam CRD. This can simplify the manufacturing process and reduce the process cost.

[0148] 9A to 9F is a cross-sectional view showing a method of manufacturing a display panel according to an embodiment of the inventive concept. 9A to 9F Each of the Figure 4A In the following, reference will be made to 9A to 9F Describes a method for manufacturing a display panel (ie, Figure 4A A method for display panel 100-1).

[0149] like Fig. 9A As shown in FIG. 1 , a base layer BL-1 may be formed on an insulating substrate BS. The base layer BL-1 may be formed by depositing an inorganic material on the insulating substrate BS. Fig. 8A The method for forming the initial base layer BL-I is basically the same as the method for forming the base layer BL-1.

[0150] Then, if Fig. 9B As shown in FIG. 1 , a semiconductor pattern SP, a preliminary first insulating layer 10 -I, a control electrode CE, and a preliminary second insulating layer 20 -I may be sequentially formed on a base layer BL- 1. The semiconductor pattern SP may be formed by patterning a semiconductor material.

[0151] An initial first insulating layer 10-I may be formed on the base layer BL-1 to cover the semiconductor pattern SP. The initial first insulating layer 10-I may be formed to substantially cover the entire top surface of the base layer BL-1. The initial first insulating layer 10-I may be formed by depositing an inorganic material on the base layer BL-1.

[0152] The control electrode CE may be formed on the initial first insulating layer 10-I. The control electrode CE may be formed by depositing a conductive material and patterning the conductive material. Fig.8D and Fig. 8E The method for forming the control electrode CE is basically the same as the method for forming the control electrode CE.

[0153] The initial second insulating layer 20-I may be formed on the initial first insulating layer 10-I to cover the control electrode CE. The initial second insulating layer 20-I may be formed to substantially cover the entire top surface of the initial first insulating layer 10-I. The initial second insulating layer 20-I may be formed by depositing an inorganic material on the initial first insulating layer 10-I.

[0154] Next, if Fig. 9C As shown in FIG, the initial first insulating layer 10-I and the initial second insulating layer 20-I may be patterned to form an inorganic insulating pattern ILP-1, a first insulating layer 10, and a second insulating layer 20. The first insulating layer 10 and the second insulating layer 20 may be formed by forming contact holes CH in the initial first insulating layer 10-I and the initial second insulating layer 20-I.

[0155] The inorganic insulating patterns ILP-1 may be formed to be spaced apart from each other with gap regions OP interposed therebetween. The inorganic insulating pattern ILP-1 may include a first layer P1 formed from an initial first insulating layer 10-I and a second layer P2 formed from an initial second insulating layer 20-I.

[0156] The inorganic insulating pattern ILP-1, the first insulating layer 10 and the second insulating layer 20 may be formed concurrently (e.g., simultaneously) by the same process. Therefore, the gap region OP and the contact hole CH may be formed concurrently (e.g., simultaneously) using a single mask. In addition, the first layer P1 and the second layer P2 may be aligned with each other in the third direction DR3.

[0157] Then, if Fig.9D and Fig.9E As shown in , a conductive layer CLL-1 may be formed on the second insulating layer 20, and then the conductive layer CLL-1 may be patterned to form an input electrode IE, an output electrode OE, and a conductive pattern MTP. The conductive layer CLL-1 may be formed by depositing or coating a conductive material on the second insulating layer 20. The conductive layer CLL-1 may be formed by forming a single layer or stacking multiple layers. The conductive layer CLL-1 may be formed to fill the gap region OP and the contact hole CH.

[0158] The conductive layer CLL-1 may be patterned to form an input electrode IE, an output electrode OE, and a conductive pattern MTP. The input electrode IE, the output electrode OE, and the conductive pattern MTP may be formed concurrently (e.g., simultaneously) using a single common mask. Therefore, the crack dam CRD-1 may be easily formed without an additional process for forming the conductive pattern MTP.

[0159] Next, if Fig.9F As shown in , the display device layer DP-OLED and the encapsulation layer TFE may be sequentially formed to form the display panel 100-1. Each of the display device layer DP-OLED and the encapsulation layer TFE may be formed by one of known techniques, and a detailed description thereof will be omitted.

[0160] As described above, before forming the display device layer DP-OLED, the gap region OP between the inorganic insulating patterns ILP-1 may be filled with the conductive pattern MTP. Therefore, even if contamination material remains in the gap region OP between the inorganic insulating patterns ILP-1, since the remaining contamination material is covered with the conductive pattern MTP when forming the display device layer DP-OLED or the encapsulation layer TFE, it is possible to prevent or substantially prevent the contamination material from damaging the elements of the display panel. This can improve the process reliability of the manufacturing process.

[0161] Furthermore, as described above, since the cell and the crack dam CRD-1 are formed using the existing process of forming the cell, there is no need to perform an additional process for forming the crack dam CRD-1. This can simplify the manufacturing process and reduce the process cost.

[0162] According to an embodiment of the inventive concept, a crack dam may be formed in a display panel to prevent or substantially prevent an impact applied to the outside of the display panel from being transferred to a display region. Thus, the reliability of a display device may be improved.

[0163] According to an embodiment of the inventive concept, since the organic pattern is omitted from the crack dam, the crack dam can be prevented or substantially prevented from being broken during the cutting process. Therefore, the area of ​​the margin region for protecting the crack dam can be reduced, thereby reducing the area of ​​the frame region of the display panel.

[0164] While example embodiments of the inventive concepts have been particularly shown and described, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the spirit and scope of the appended claims and their equivalents.

Claims

1. A display panel, comprising: An insulating substrate having a display area and a peripheral area adjacent to the display area; A plurality of insulating layers, located on the insulating substrate; A pixel, located on the display area, the pixel comprising a thin film transistor and an organic light emitting device connected to the thin film transistor; as well as a crack dam located on the peripheral region and spaced apart from the pixel, the crack dam being adjacent to one of the side surfaces of the insulating substrate extending in the first direction, The crack dam includes: a plurality of insulating patterns extending in the first direction and spaced apart from each other in a second direction intersecting the first direction; and a plurality of conductive patterns filling gap regions between the plurality of insulating patterns. Wherein, the plurality of conductive patterns are electrically insulated from the thin film transistor.

2. The display panel according to claim 1, wherein: The plurality of conductive patterns extend in the first direction and are spaced apart from each other in the second direction, and Each of the plurality of conductive patterns is configured to connect adjacent insulating patterns to each other.

3. The display panel according to claim 1, wherein: The thin film transistor comprises: Semiconductor patterning; a control electrode spaced apart from and overlapping the semiconductor pattern in a plan view; an input electrode spaced apart from the control electrode in the plan view and coupled to a portion of the semiconductor pattern; and an output electrode spaced apart from the control electrode in the plan view and coupled to an opposite portion of the semiconductor pattern, The plurality of conductive patterns include a material that is the same as a material of at least one of the control electrode, the input electrode, and the output electrode.

4. The display panel according to claim 3, wherein: The plurality of insulating layers include: a first insulating layer, located between the semiconductor pattern and the control electrode; and A second insulating layer is located between the control electrode and the input electrode, The plurality of insulating patterns are located on the same layer as at least one of the first insulating layer and the second insulating layer.

5. The display panel according to claim 4, wherein: Each of the plurality of insulating patterns has a double-layered structure.

6. The display panel according to claim 1, further comprising a base layer located between the thin film transistor and the insulating substrate, in, The base layer includes at least one of a barrier layer and a buffer layer, and The plurality of insulating patterns are located on the same layer as the base layer.

7. The display panel according to claim 6, wherein: The plurality of insulation patterns are spaced apart from the base layer in the second direction.

8. The display panel according to claim 6, wherein: The plurality of insulation patterns are connected to at least a portion of the base layer.

9. The display panel according to claim 1, wherein: The plurality of insulating patterns include: a plurality of first insulation patterns spaced apart from each other in the second direction; and A plurality of second insulation patterns are spaced apart from each other in the second direction and are located on a different layer from the plurality of first insulation patterns.

10. The display panel according to claim 1, further comprising an encapsulation layer located on the display area and configured to cover the pixel, in, The encapsulation layer extends to cover the crack dam and contacts the plurality of insulating patterns and the plurality of conductive patterns.

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