Nonvolatile storage device and method of operating the same

Abstract

A nonvolatile memory device comprises: a memory cell array comprising a plurality of memory cells; a page buffer for performing a plurality of read operations and storing results of the read operations, wherein each of the read operations comprises at least one read operation for a selected memory cell among the plurality of memory cells; a multi-read manager for determining the number of read operations for each of the plurality of read operations and controlling the page buffer to perform the read operations; and a data identifier for identifying a data state of a bit of the selected memory cell based on the results of the read operations, wherein the multi-read manager determines that the number of read operations for at least one of the read operations is different from the number of read operations for other read operations among the read operations.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority benefit of Korean Patent Application No. 10-2018-0003446 filed on January 10, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference in its entirety. Technical Field

[0003] The inventive concept relates to a memory device, and more particularly, to a nonvolatile memory device capable of performing multi-sense. Background Art

[0004] Semiconductor memory devices can be implemented by using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), and indium phosphide (InP). Semiconductor memory devices can be volatile memory devices or non-volatile memory devices. Volatile memory devices retain stored data when powered, but the data is lost when the power is interrupted. Non-volatile memory devices do not lose stored data when the power is interrupted.

[0005] Non-volatile memory devices may include read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrical EPROM (EEPROM), flash memory devices, phase-change random access memory (RAM) (PRAM), magnetoresistive RAM (MRAM), and ferroelectric RAM (FRAM). The flash memory device may be a NOR type or a NAND type flash memory. Summary of the invention

[0006] According to an exemplary embodiment of the present invention, a nonvolatile memory device is provided, comprising: a memory cell array including a plurality of memory cells; a page buffer for performing a plurality of read operations and storing results of the plurality of read operations, wherein each of the read operations includes at least one read operation for a selected memory cell among the plurality of memory cells; a multi-read manager for determining the number of read operations for each of the plurality of read operations and controlling the page buffer to perform the read operations; and a data identifier for identifying a data state of a bit of the selected memory cell based on the results of the read operations, wherein the multi-read manager determines that the number of read operations for at least one read operation among the plurality of read operations is different from the number of read operations for other read operations among the plurality of read operations.

[0007] According to an exemplary embodiment of the present invention, a nonvolatile memory device is provided, comprising: a memory cell array comprising a plurality of memory cells; a page buffer configured to perform a read operation on a selected memory cell among the plurality of memory cells, wherein the read operation comprises a plurality of read operations; a multi-read manager configured to control the page buffer to perform a first read operation for performing a plurality of first read operations based on a first read voltage set and a second read operation for performing a plurality of second read operations based on a second read voltage set; and a data identifier configured to identify a data state of a bit of the selected memory cell based on a result of the first read operation and a result of the second read operation, and to store the result in a latch set, wherein the number of the first read operations is different from the number of the second read operations.

[0008] According to an exemplary embodiment of the present invention, there is provided a method for operating a nonvolatile memory device including a plurality of memory cells connected to a plurality of bit lines, the method comprising: determining a number of read operations for each of a plurality of read operations, wherein each of the read operations performs at least one read operation on a memory cell selected from among a plurality of memory cells by using a set of read voltages; sequentially performing a plurality of read operations on a memory cell selected from among the plurality of memory cells based on the number of read operations; and identifying a data state of a bit of the selected memory cell based on results of the plurality of read operations, wherein the number of read operations corresponding to at least one read operation among the plurality of read operations is different from the number of read operations for other read operations among the plurality of read operations.

[0009] According to an exemplary embodiment of the present invention, there is provided a nonvolatile storage system, comprising: a memory controller configured to determine a number of read operations corresponding to each of a plurality of read operations; and a nonvolatile storage device configured to perform a plurality of read operations and identify a data state of a bit of a selected storage cell based on results of the plurality of operations, wherein each of the plurality of read operations performs at least one read operation on a storage cell selected from among a plurality of storage cells, and wherein the memory controller determines that the number of read operations corresponding to at least one read operation among the plurality of read operations is different from the number of read operations corresponding to other read operations among the plurality of read operations. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other features and advantages of the present inventive concept will be more clearly understood by describing in detail exemplary embodiments of the present inventive concept with reference to the accompanying drawings, in which:

[0011] Figure 1 is a block diagram illustrating a nonvolatile memory system according to an exemplary embodiment of the inventive concept;

[0012] Figure 2 is a block diagram illustrating a nonvolatile memory device according to an exemplary embodiment of the inventive concept;

[0013] Figure 3 is a block diagram illustrating a nonvolatile memory device according to an exemplary embodiment of the inventive concept;

[0014] Figure 4 is a flowchart of an operation of a nonvolatile memory system according to an exemplary embodiment of the inventive concept;

[0015] Figure 5 is a circuit diagram illustrating a memory block included in a memory cell array according to an exemplary embodiment of the inventive concept;

[0016] Figure 6 is a circuit diagram illustrating a memory block included in a memory cell array according to an exemplary embodiment of the inventive concept;

[0017] Figure 7 According to an exemplary embodiment of the present invention Figure 6 A three-dimensional diagram of a storage block;

[0018] Figure 8 is a diagram showing a cell spread according to an exemplary embodiment of the inventive concept;

[0019] Fig.9A and Fig. 9B is a diagram illustrating an operation of a nonvolatile memory device according to an exemplary embodiment of the inventive concept;

[0020] Fig. 10A and Fig. 10B is a diagram illustrating an operation of a nonvolatile memory device according to an exemplary embodiment of the inventive concept;

[0021] Fig.11 is a waveform diagram illustrating a change in a level of a readout node according to an exemplary embodiment of the inventive concept;

[0022] Fig.12 is a timing diagram illustrating a read operation according to an exemplary embodiment of the inventive concept;

[0023] Fig.13A , Fig. 13B and Fig. 13C is a diagram illustrating a method of selecting data when the number of read operations is '3' according to an exemplary embodiment of the inventive concept;

[0024] Fig.14A and Fig. 14Bis a diagram illustrating a method of selecting data when the number of read operations is '2' according to an exemplary embodiment of the inventive concept;

[0025] Fig.15 is a flowchart of an operation of a nonvolatile memory system according to an exemplary embodiment of the inventive concept;

[0026] Fig.16 is a diagram illustrating a nonvolatile memory system according to an exemplary embodiment of the inventive concept;

[0027] Fig.17 is a block diagram illustrating a nonvolatile memory device according to an exemplary embodiment of the inventive concept; and

[0028] Fig.18 is a block diagram illustrating application of a nonvolatile memory device to a solid state drive (SSD) system according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0029] Figure 1 is a block diagram illustrating a nonvolatile memory system 1 according to an exemplary embodiment of the inventive concept.

[0030] refer to Figure 1The nonvolatile memory system 1 may include a memory controller 20 and a nonvolatile memory device 10. According to an exemplary embodiment of the inventive concept, each of the host HOST, the memory controller 20 and the nonvolatile memory device 10 may be provided as a chip, a data package, a module, etc. Additionally, the memory controller 20 and the non-volatile memory device 10 may be package on package (PoP), ball grid array (BGA), chip scale package (CSP), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), die in waffle pack, die in wafer form, chip on board (COB), ceramic dual in-line package (CERDIP), plastic standard quad flat package (MQFP), thin quad flat package (TQFP), small outline IC (SOIC), shrink small outline package (SSOP), thin small outline package (TSOP), system in package (SIP), etc. Package, SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), Wafer-Level Processed Stack Package (WSP), etc.

[0031] The memory controller 20 may control the nonvolatile memory device 10 in response to a write request or a read request received from the host HOST. For example, the memory controller 20 may transmit a command CMD and an address ADDR to the nonvolatile memory device 10 in response to a write request or a read request received from the host HOST. The address ADDR transmitted by the memory controller 20 to the nonvolatile memory device 10 may be a physical address in the nonvolatile memory device 10. The memory controller 20 may exchange data with the nonvolatile memory device 10. For example, when the command CMD is a write command CMD_w, the nonvolatile memory device 10 may write the data DATA received from the memory controller 20 to the memory cell array 140. When the command CMD is a read command CMD_r, the nonvolatile memory device 10 may output the data DATA stored at the address ADDR received from the memory controller 20 to the memory controller 20.

[0032] The nonvolatile memory device 10 may include a multi-read manager 110, a data identifier 120, a page buffer 130, and a memory cell array 140. The multi-read manager 110 may control the page buffer 130 to perform multi-read for identifying a certain state of a selected memory cell corresponding to a read command CMD_r received from the memory controller 20. Multi-read may refer to a plurality of sensing operations performed to identify any one data state stored in the selected memory cell. Multi-read may be referred to as an on-chip-valley search. A plurality of read operations may be performed to identify any one data state stored in the memory cell, and each of the plurality of read operations may include a plurality of read operations based on a set of sensing voltages. The multi-read manager 110 may determine the number of read operations for each of the plurality of read operations. In addition, the multi-read manager 110 may determine an order for performing the plurality of read operations.

[0033] According to an exemplary embodiment of the inventive concept, the multi-readout manager 110 may determine that the number of read operations corresponding to at least one of the plurality of read operations is different from those corresponding to the remaining read operations. In other words, the number of read operations corresponding to the first read operation may be different from the number of read operations corresponding to the second read operation. For example, the multi-readout manager 110 may distinguish the plurality of read operations from each other based on a reference voltage and respectively determine different numbers of read operations for the distinguished read operations. The reference voltage may be set to the value of the reference voltage. Figure 8 A description thereof is given below.

[0034] According to an exemplary embodiment of the inventive concept, the multi-readout manager 110 may determine an order for executing the plurality of read operations based on the determined number of read operations. For example, the multi-readout manager 110 may determine an order for executing the plurality of read operations such that the read operation corresponding to the determined minimum number of read operations is executed last. Fig.15 A description thereof is given below.

[0035] The data identifier 120 may perform a process for selecting optimal data from among the multiple pieces of data stored in the page buffer 130 due to the multiple readout. In order to select the optimal data, the data identifier 120 may include a unit counter and may refer to the count result provided from the unit counter. In other words, the data identifier 120 may control the page buffer 130 to select and output the data closest to the lowest point from among the multiple pieces of data due to the multiple readout. FIG. 13A to FIG. 14B A detailed description of the operation of the data identifier 120 is given below.

[0036] The page buffer 130 may include a write driver and a sense amplifier. During a write operation, the page buffer 130 may pass a bit line voltage corresponding to data to be written to a bit line of the memory cell array 140. During a read operation or a verify operation, the page buffer 130 may read out data stored in a selected memory cell through a bit line. The page buffer 130 may include a plurality of latch sets connected to one or two bit lines.

[0037] The memory cell array 140 may include a plurality of memory cells. For example, the plurality of memory cells may be flash memory cells. Hereinafter, an exemplary embodiment of the inventive concept will be described assuming that the plurality of memory cells are NAND flash memory cells. However, the inventive concept is not limited thereto, and in other exemplary embodiments, the plurality of memory cells may be resistive memory cells like resistive RAM (RRAM), phase change RAM (PRAM), or magnetic RAM (MRAM).

[0038] The memory cell array 140 may be a three-dimensional (3D) memory cell array. The 3D memory cell array may include an active region arranged on a silicon substrate and a circuit associated with the operation of the memory cell. The circuit may be formed monolithically on or in a silicon substrate with at least one physical level of the memory cell array. The term "monolithic" may refer to a structure in which the circuit is stacked on a layer of a lower level of the memory cell array. The 3D memory cell array includes NAND strings arranged in a vertical direction so that at least one memory cell is located above another memory cell. At least one memory cell may include a charge trapping layer. However, the inventive concept is not limited thereto, and in other exemplary embodiments, the memory cell array 140 may be a two-dimensional (2D) memory cell array.

[0039] U.S. Patent Nos. 7,679,133, 8,553,466, 8,654,587, and 8,559,235 and U.S. Patent Application Publication No. 2011 / 0233648 disclose configurations of 3D memory arrays including multiple levels, wherein word lines and / or bit lines are shared among the multiple levels. The disclosures of these patent documents are incorporated herein by reference in their entirety. In addition, U.S. Patent Application Publication No. 2014-0334232 and U.S. Patent No. 8,488,381 are incorporated herein by reference in their entirety.

[0040] According to the present embodiment, each memory cell included in the memory cell array 140 may be a multi-level cell (MLC) storing two or more bits of data. For example, the memory cell may be an MLC storing two bits of data. In another example, the memory cell may be a triple-level cell (TLC) for storing 3 bits of data or a quad-level cell (QLC) for storing 4 bits of data. However, the inventive concept is not limited thereto. For example, some memory cells included in the memory cell array 140 may be single-level cells (SLC) for storing 1 bit of data, and the remaining memory cells may be MLCs.

[0041] Figure 2 1 is a block diagram showing a nonvolatile memory device according to an exemplary embodiment of the present invention. Figure 1 The same or similar descriptions are given to those described above.

[0042] refer to Figure 2 , the nonvolatile memory device 10 may include a control logic 100 , a page buffer 130 , a memory cell array 140 , a voltage generator 150 , a row decoder 160 , and an input / output circuit 170 .

[0043] The control logic 100 may include a multi-readout manager 110 and a data identifier 120. The control logic 100 may be based on a slave memory controller (e.g., Figure 1 20) receives the command CMD_w / CMD_r and the address ADDR to output various control signals for writing data to the memory cell array 140 or reading data from the memory cell array 140.

[0044] The multi-read manager 110 may respond to a request from a memory controller (e.g., Figure 120) receives a read command CMD_r to output a multi-read control signal Ctrl_MS to the page buffer 130, and the page buffer 130 can perform multi-reading on the selected memory cell in response to the multi-read control signal Ctrl_MS. According to an exemplary embodiment of the inventive concept, the multi-read control signal Ctrl_MS may include information about the number of read operations for each of the multiple read operations. According to an exemplary embodiment of the inventive concept, the multi-read control signal Ctrl_MS may include information about the order for performing the multiple read operations.

[0045] The page buffer 130 may include a plurality of latch sets LS1 to LSn, and each of the plurality of latch sets LS1 to LSn may perform sensing and latching for performing a multi-sense operation. For example, the page buffer 130 may perform a sense operation through a plurality of bit lines BL. In other words, each of the plurality of latch sets LS1 to LSn may perform a plurality of sense operations under the control of the control logic 100 to identify the state of the data stored in the selected memory cell. Next, each of the plurality of latch sets LS1 to LSn may store the data read out through the plurality of sense operations under the control of the control logic 100 and select any one of the data. Each of the plurality of latch sets LS1 to LSn may perform a multi-sense to identify the state of the data stored in the memory cell. According to an exemplary embodiment of the inventive concept, the plurality of latch sets LS1 to LSn may perform a different number of sense operations for each of the plurality of read operations based on the multi-sense control signal Ctrl_MS provided from the multi-sense manager 110. Each of the plurality of latch sets LS1 to LSn may select or output optimal data among the read-out pieces of data under the control of the control logic 100 .

[0046] The voltage generator 150 may generate various types of voltages for performing write, read, and erase operations with respect to the memory cell array 140 based on the voltage control signal Ctrl_vol. For example, the voltage generator 150 may generate a word line voltage VWL, such as a program voltage (or a write voltage), a read voltage, a pass voltage (or an unselected word line voltage), a verification voltage, or a recovery voltage.

[0047] The row decoder 160 may select some word lines WL in response to the row address X-ADDR. The row decoder 160 transfers a word line voltage to the word line WL. During a programming operation, the row decoder 160 may apply a programming voltage and a verification voltage to the selected word line WL and apply a program inhibition voltage to the unselected word line WL. During a read operation, the row decoder 160 may apply a read voltage to the selected word line WL and apply a read inhibition voltage to the unselected word line WL. During a recovery operation, the row decoder 160 may apply a recovery voltage to the selected word line WL. In addition, the row decoder 160 may select some string selection lines SSL or some ground selection lines GSL in response to the row address X-ADDR.

[0048] The input / output circuit 170 may receive data from an external device (eg, a memory controller) and store the input data in the memory cell array 140. In addition, the input / output circuit 170 may read data from the memory cell array 140 and output the read data to an external device.

[0049] Figure 3 1 is a block diagram illustrating a nonvolatile memory device according to an exemplary embodiment of the inventive concept. Figure 1 and Figure 2 Descriptions the same or similar to those given above.

[0050] refer to Figure 3 , the nonvolatile memory device 10 may include a multi-read manager 110, a data identifier 120, and a page buffer 130, wherein the multi-read manager 110 may include a read operation number determiner 111 (e.g., a NoS determiner) and a read operation order determiner 112 (e.g., a read order determiner). The read operation number determiner 111 may determine the number of read operations for each of a plurality of read operations. Each of the plurality of read operations may include a plurality of read operations based on a read voltage set. According to an exemplary embodiment of the inventive concept, the read operation number determiner 111 may determine the number of read operations for each of the plurality of read operations based on a read voltage set or a voltage level of a read voltage corresponding to the read voltage set. For example, the read operation number determiner 111 may determine the number of read operations by comparing a reference voltage with the read voltage set or a read voltage corresponding to the read voltage set. To accomplish this, the read operation number determiner 111 may include a storage device to store the reference voltage and the number of read operations corresponding thereto. According to an exemplary embodiment of the inventive concept, the memory controller 20 may update a reference voltage and the number of read operations corresponding thereto through a read command CMD_r.

[0051] For example, when the voltage level of the read voltage set is equal to or less than the first reference voltage, the read operation number determiner 111 may determine the first number as the number of read operations. When the voltage level of the read voltage set is greater than the first reference voltage and equal to or less than the second reference voltage, the read operation number determiner 111 may determine the second number as the number of read operations. When the voltage level of the read voltage set is greater than the second reference voltage, the read operation number determiner 111 may determine the third number as the number of read operations. In addition, the read operation number determiner 111 may determine that the first number and the third number are greater than the second number.

[0052] In another example, when the voltage level of the read voltage set is equal to or less than the first reference voltage, the read operation number determiner 111 may determine the first number as the number of read operations. When the voltage level of the read voltage set is greater than the first reference voltage and equal to or less than the second reference voltage, the read operation number determiner 111 may determine the second number as the number of read operations. When the voltage level of the read voltage set is greater than the second reference voltage and equal to or less than the third reference voltage, the read operation number determiner 111 may determine the third number as the number of read operations. When the voltage level of the read voltage set is greater than the third reference voltage, the read operation number determiner 111 may determine the fourth number as the number of read operations. In addition, the read operation number determiner 111 may determine that the first number is greater than the second number and the third number and that the fourth number is greater than the third number.

[0053] During a multi-read operation, the page buffer 130 may latch the read node at different development time points. For example, the read voltage set may refer to voltage levels at different time points at which the read node is latched.

[0054] The read operation sequence determiner 112 may determine the sequence for performing the plurality of read operations. According to an exemplary embodiment of the inventive concept, the read operation sequence determiner 112 may determine the sequence for performing the plurality of read operations based on the number of read operations. For example, the read operation sequence determiner 112 may determine the sequence for performing the plurality of read operations as follows: finally performing the first read operation corresponding to the minimum number of read operations among the plurality of read operations, and sequentially performing the plurality of read operations other than the first read operation in ascending or descending order according to the voltage level of the corresponding read voltage set. In other words, sequentially performing the plurality of read operations other than the first read operation, and then performing the first read operation.

[0055] The multi-readout manager 110 may transmit a multi-readout control signal Ctrl_MS including information about the determined number of read operations and information about an order in which read operations are performed to the page buffer 130. The page buffer 130 is controlled to perform multi-readout in response to the multi-readout control signal Ctrl_MS.

[0056] The page buffer 130 may perform multi-sense and store the result of the multi-sense in the first to Nth latch sets LS1 to LSn. In an example where the number of read operations determined by the multi-sense manager 110 is four (4), each of the first to Nth latch sets LS1 to LSn may include a first latch for storing data read by the first read operation, a second latch for storing data read by the second read operation, a third latch for storing data read by the third read operation, and a fourth latch for storing data read by the fourth read operation. The page buffer 130 may transmit multiple data obtained by the multi-sense to the data identifier 120 as a multi-sense result Rst_MS. When the number of read operations determined by the multi-sense manager 110 is greater than four (4), each of the first to Nth latch sets LS1 to LSn may include more than four latches.

[0057] The data identifier 120 may include a cell counter 121 and a read result selector 122. The cell counter 121 may perform cell counting based on the multi-readout result Rst_MS and output a count result Cnt to the read result selector 122. The read result selector 122 may select optimal data as read data from among multiple pieces of data included in the multi-readout result Rst_MS based on the count result Cnt.

[0058] For example, when the determined number of read operations is two (2), the read result selector 122 compares the number of ON cells counted by using the first latch with the number of OFF cells counted by using the second latch. In this way, the read result selector 122 determines the read data indicating the data state about the selected memory cell from among the data stored in the first latch and the second latch. FIG. 13A to FIG. 13C A detailed description thereof is given below.

[0059] For example, when the determined number of read operations is three (3), the read result selector 122 calculates a first cell count by comparing the result counted by the first latch with the result counted by the second latch, calculates a second cell count by comparing the result counted by the second latch with the result counted by the third latch, and compares the first cell count with the second cell count. In this way, the read result selector 122 determines read data indicating a data state about the selected memory cell from among the data included in the first to third latches. Fig.14A and Fig. 14B A detailed description thereof is given below.

[0060] For example, when the determined number of read operations is four (4), the read result selector 122 compares the results counted by the first to fourth latches with each other, thereby determining read data indicating the data state regarding the selected memory cell from among the data included in the first to fourth latches.

[0061] The data identifier 120 may output information Info_Sel regarding the determined read data to the page buffer 130 , and the page buffer 130 may output data corresponding to the information Info_Sel as a read result Rst_Rd to the input / output circuit 170 .

[0062] Figure 4 is a flowchart of an operation of a nonvolatile memory system according to an exemplary embodiment of the inventive concept.

[0063] refer to Figure 2 and Figure 4 , when the nonvolatile memory device 10 receives the read command CMD_r (operation S110), the multi-read manager 110 may determine the number of read operations for each of the plurality of read operations (operation S120). The multi-read manager 110 may determine the order in which the plurality of read operations are performed based on the determined number of read operations (operation S130). The multi-read manager 110 may control the page buffer 130 to sequentially perform the plurality of read operations for the selected memory cell based on the determined number of read operations and the order in which the plurality of read operations are performed (operation S140). The data identifier 120 may receive the multi-read result Rst_MS from the page buffer 130, and determine the read data for each of the plurality of read operations based on the multi-read result Rst_MS (operation S150). The nonvolatile memory device 10 may identify the data state of one bit of the selected memory cell based on the read data of the plurality of read operations (operation S160).

[0064] Figure 5is a circuit diagram illustrating a memory block included in a memory cell array according to an exemplary embodiment of the inventive concept.

[0065] refer to Figure 5 , memory cell arrays (e.g., Figure 2 The memory cell array 140 in the memory cell array 140 may be a memory cell array of a horizontal NAND flash memory and may include a plurality of memory blocks. Each memory block BLKa may include n (n is an integer equal to or greater than 2) cell strings STR, in which a plurality of memory cells MC (e.g., MC1-MCn) are connected in series on bit lines BL0 to BLm-1. For example, Figure 5 An example is shown in which each cell string STR includes eight or more memory cells MC.

[0066] In having Figure 5 In the NAND flash memory device of the structure shown in , an erase operation is performed block by block and a program operation is performed page by page, where a page corresponds to word lines WL0 to WL7 when each cell string STR includes eight memory cells MC. Figure 5 An example is shown in which n pages corresponding to n word lines WL1 to WLn are arranged in each block. Figure 1 and Figure 2 The nonvolatile memory device 10 may include a plurality of memory cell arrays having the same structure and performing the same operation as the memory cell array 140 described above.

[0067] Figure 6 is a circuit diagram illustrating a memory block included in a memory cell array according to an exemplary embodiment of the inventive concept.

[0068] refer to Figure 6 , memory cell arrays (e.g., Figure 2 The memory cell array 140 in the embodiment may be a memory cell array of a vertical NAND flash memory and may include a plurality of memory blocks. Each memory block BLK0 may include a plurality of NAND strings NS11 to NS33, a plurality of word lines WL1 to WL8, a plurality of bit lines BL1 to BL3, a plurality of ground selection lines GSL1 to GSL3, a plurality of string selection lines SSL1 to SSL3, and a common source line CSL. Here, the number of NAND cell strings, the number of word lines, the number of bit lines, the number of ground selection lines, and the number of cell string selection lines may be changed according to exemplary embodiments of the inventive concept.

[0069] NAND cell strings NS11, NS21, and NS31 are provided between a first bit line BL1 and a common source line CSL, NAND cell strings NS12, NS22, and NS32 are provided between a second bit line BL2 and a common source line CSL, and NAND cell strings NS13, NS23, and NS33 are provided between a third bit line BL3 and a common source line CSL. Each NAND cell string (e.g., NAND cell string NS11) may include a cell string selection transistor SST, a plurality of memory cells MC1 to MC8, and a ground selection transistor GST connected in series.

[0070] NAND cell strings commonly connected to one bit line BL constitute one column. For example, NAND cell strings NS11, NS21, and NS31 commonly connected to the first bit line BL1 may correspond to the first column, NAND cell strings NS12, NS22, and NS32 commonly connected to the second bit line BL2 may correspond to the second column, and NAND cell strings NS13, NS23, and NS33 commonly connected to the third bit line BL3 may correspond to the third column.

[0071] The NAND cell strings connected to one cell string selection line SSL constitute one row. For example, the NAND cell strings NS11, NS12, and NS13 connected to the first cell string selection line SSL1 correspond to the first row, the NAND cell strings NS21, NS22, and NS23 connected to the second cell string selection line SSL2 correspond to the second row, and the NAND cell strings NS31, NS32, and NS33 connected to the third cell string selection line SSL3 correspond to the third row.

[0072] The cell string selection transistors SST are connected to the corresponding cell string selection lines SSL1 to SSL3. A plurality of memory cells MC1 to MC8 are connected to the corresponding word lines WL1 to WL8. The ground selection transistors GST are connected to the corresponding ground selection lines GSL1 to GSL3. The cell string selection transistors SST are connected to their corresponding bit lines BL1 to BL3, and the ground selection transistors GST are connected to the common source line CSL.

[0073] Word lines at the same height (e.g., the first word line WL1) are commonly connected to each other, cell string selection lines SSL1 to SSL3 are separated from each other, and ground selection lines GSL1 to GSL3 are also separated from each other. For example, in the case of programming a memory cell MC1 connected to the first word line WL1 and belonging to NAND cell strings NS11, NS12, and NS13, the first word line WL1 and the first cell string selection line SSL1 are selected. The ground selection lines GSL1 to GSL3 may also be commonly connected to each other.

[0074] Figure 7 According to an exemplary embodiment of the present inventive concept, Figure 6 A three-dimensional diagram of the storage block BLK0.

[0075] refer to Figure 7 , formed in a memory cell array (eg, Figure 2 Each memory block included in the memory cell array 140 in FIG. Figure 6 Each memory block is shown to include two selection lines GSL and SSL, eight word lines WL1 to WL8 , and three bit lines BL1 to BL3 , but the number of individual elements may be greater or less than the above stated number.

[0076] The substrate SUB has a first conductivity type (e.g., p-type), wherein a common source line CSL extending in a first direction (e.g., Y-axis direction) and doped with impurities having a second conductivity type (e.g., n-type) is provided on the substrate SUB. A plurality of insulating films IL extending in the first direction are sequentially provided in a third direction (e.g., Z-direction) in a region of the substrate SUB between two common source lines CSL adjacent to each other. The plurality of insulating films IL are separated from each other by a specific distance in the third direction. For example, the plurality of insulating films IL may include an insulating material such as silicon oxide.

[0077] A plurality of pillars P are provided on a substrate SUB. For example, a plurality of pillars P are sequentially arranged in a first direction in a region of the substrate SUB between two adjacent common source lines CSL and the plurality of pillars P penetrate through a plurality of insulating films IL in the first direction. For example, the plurality of pillars P may penetrate through a plurality of insulating films IL and contact the substrate SUB. A surface layer S of each pillar P may include a silicon-based material having a first conductivity type and function as a channel region. An inner layer I of each pillar P may include an insulating material such as silicon oxide or an air gap.

[0078] In the region between two adjacent common source lines CSL, a charge storage layer CS is provided along the exposed surface of the insulating film IL, the plurality of pillars P, and the substrate SUB. The charge storage layer CS may include a gate insulating layer (e.g., a "tunneling insulating layer"), a charge trapping layer, and a blocking insulating layer. For example, the charge storage layer CS may have an oxide-nitride-oxide (ONO) structure. In addition, in the region between two adjacent common source lines CSL, a gate electrode GE including select lines GSL and SSL and word lines WL1 to WL8 is provided on the exposed surface of the charge storage layer CS.

[0079] Drains or drain contacts DR are provided on the plurality of pillars P, respectively. For example, the drain or drain contact DR may include a silicon-based material doped with impurities having a second conductivity type. Bit lines BL1 to BL3 extending in a second direction (e.g., X direction) and arranged at a distance from each other in the first direction are provided on the drain DR.

[0080] Figure 8 is a diagram illustrating cell distribution according to an exemplary embodiment of the inventive concept. Figure 8 A method of reading a QLC capable of storing 4 bits of data per cell page by page can be shown. Figure 8 The horizontal axis of the graph represents the threshold voltage level of the cells, and the vertical axis of the graph represents the number of cells.

[0081] refer to Figure 2 and Figure 8 In order to read the least significant bit (LSB) page, the first read operation RD1, the fifth read operation RD5, the ninth read operation RD9, and the twelfth read operation RD12 may be performed according to the order of performing the read operations determined by the multi-read manager 110. For example, the multi-read manager 110 may read the LSB page in the order of the first read operation RD1, the ninth read operation RD9, the twelfth read operation RD12, and the fifth read operation RD5, and the first read operation RD1 may be first provided to the word line of the selected memory cell. The ON / OFF state of the first read operation RD1 may be read and stored in any one of the plurality of latches. Logic "1" may be latched as a result of reading a memory cell (e.g., an ON cell) having a lower voltage than the first read operation RD1, and logic "0" may be latched as a result of reading a memory cell (e.g., an OFF cell) having a threshold voltage equal to or higher than that of the first read operation RD1. Thereafter, a fifth read operation RD5, a ninth read operation RD9, and a twelfth read operation RD12 may be sequentially provided to the word line of the selected memory cell. For each of the fifth read operation RD5, the ninth read operation RD9, and the twelfth read operation RD12, a previously latched logic value is maintained for a memory cell read as an ON cell, and a previously latched logic value may be toggled for a memory cell read as an OFF cell. After completing such a process, the result of reading the LSB page may be output.

[0082] To read the first middle bit (CSB1) page, the second read operation RD2, the sixth read operation RD6, the tenth read operation RD10, and the thirteenth read operation RD13 may be performed according to the order of performing the read operations determined by the multi-sense manager 110. To read the second middle bit (CSB2) page, the third read operation RD3, the seventh read operation RD7, and the fourteenth read operation RD14 may be performed according to the order of performing the read operations determined by the multi-sense manager 110. In addition, to read the most significant bit (MSB) page, the fourth read operation RD4, the eighth read operation RD8, the eleventh read operation RD11, and the fifteenth read operation RD15 may be performed according to the order of performing the read operations determined by the multi-sense manager 110.

[0083] In addition, each of the first to fifteenth read operations RD1 to RD15 may be performed based on a read voltage set including a plurality of read voltages having different voltage levels. In this case, the multi-read manager 110 may apply read voltage sets corresponding to the first to fifteenth read operations RD1 to RD15, respectively, to the selected memory cells based on the number of read operations that are different from each other. For example, the threshold voltage level may include a first region Region1 that is less than or equal to a first reference voltage Vref1, a second region Region2 that is greater than the first reference voltage Vref1 and less than or equal to a second reference voltage Vref2, a third region Region3 that is greater than the second reference voltage Vref2 and less than or equal to a third reference voltage Vref3, and a fourth region Region4 that is greater than the third reference voltage Vref3. The multi-read manager 110 may determine a different number of read operations for each of the regions Region1-Region4. When the memory cell array 140 degrades, the degree of degradation in each region may be different according to the programmed threshold voltage. According to an exemplary embodiment of the inventive concept, according to the degree of degradation of a specific area, the multi-read manager 110 determines that the number of times multi-reads are performed in a severely degraded area is relatively large and determines that the number of times multi-reads are performed in a non-severely degraded area is relatively small, and therefore, the read operation can be efficiently performed.

[0084] although Figure 8 A case related to QLC is shown, but the inventive concept is not limited thereto. For example, exemplary embodiments of the inventive concept may also be applied to SLC, MLC, and TLC.

[0085] Fig.9A and Fig. 9B is a diagram illustrating the operation of a nonvolatile memory device according to an exemplary embodiment of the inventive concept. For example, Fig.9A and Fig. 9BAn embodiment is shown in which the multi-sense manager 110 divides the threshold voltage level into three regions and determines a different number of read operations for each region.

[0086] refer to Figure 2 , Figure 8 and Fig.9A , the multi-read manager 110 may determine the number of read operations for the first to third read operations RD1 to RD3 corresponding to the first region Region1 and the second region Region2 to be “3”, determine the number of read operations for the fourth to eighth read operations RD4 to RD8 corresponding to the third region Region3 to be “2”, and determine the number of read operations for the ninth to fifteenth read operations RD9 to RD15 corresponding to the fourth region Region4 to be “3”.

[0087] Fig. 9B It shows the basis Fig.9A A cell scatter diagram of multiple read operations for an LSB page and multiple read operations for an MSB page performed according to the number of read operations determined by an embodiment of the present invention. For the LSB page, the multi-read manager 110 may control the page buffer 130 so that three (3) read operations are performed for a first read operation RD1 included in the first region Region1, two (2) read operations are performed for a fifth read operation RD5 included in the third region Region3, and three (3) read operations are performed for each of a ninth read operation RD9 and a twelfth read operation RD12 included in the fourth region Region4.

[0088] For the MSB page, the multi-read manager 110 can control the page buffer 130 so that two (2) read operations are performed for each of the fourth read operation RD4 and the eighth read operation RD8 included in the third region Region3, and three (3) read operations are performed for each of the eleventh read operation RD11 and the fifteenth read operation RD15 included in the fourth region Region4.

[0089] Fig. 10A and Fig. 10B is a diagram illustrating the operation of a nonvolatile memory device according to an exemplary embodiment of the inventive concept. For example, Fig. 10A and Fig. 10B An embodiment is shown in which the multi-sense manager 110 divides the threshold voltage level into four regions and determines a different number of read operations for each region.

[0090] refer to Figure 2 , Figure 8 and Fig. 10A, the multi-read manager 110 may determine the number of read operations for the first read operation RD1 corresponding to the first region Region1 to be “4”, determine the number of read operations for the second and third read operations RD2 and RD3 corresponding to the third region Region2 to be “3”, determine the number of read operations for the fourth to eighth read operations RD4 to RD8 corresponding to the third region Region3 to be “2”, and determine the number of read operations for the ninth to fifteenth read operations RD9 to RD15 corresponding to the fourth region Region4 to be “3”.

[0091] Fig. 10B It shows the basis Fig. 10A The cell scatter diagram of the multiple read operations for the LSB page and the multiple read operations for the MSB page performed according to the number of read operations determined by the embodiment. For the LSB page, the multi-read manager 110 may control the page buffer 130 so that four (4) read operations are performed for the first read operation RD1 included in the first region Region1, two (2) read operations are performed for the fifth read operation RD5 included in the third region Region3, and three (3) read operations are performed for each of the ninth read operation RD9 and the twelfth read operation RD12 included in the fourth region Region4.

[0092] For the MSB page, the multi-read manager 110 can control the page buffer 130 so that two (2) read operations are performed for each of the fourth read operation RD4 and the eighth read operation RD8 included in the third region Region3, and three (3) read operations are performed for each of the eleventh read operation RD11 and the fifteenth read operation RD15 included in the fourth region Region4.

[0093] Fig.11 is a waveform diagram illustrating a change in a level of a sensing node according to an exemplary embodiment of the inventive concept.

[0094] refer to Fig.11 , the change of the level of the readout node according to the threshold voltage level of the memory cell and the result of latching according to the development time point can be shown. The period from time point T0 to time point T1 will be referred to as the precharge period, the period from time point T1 to time point T2 will be referred to as the development period, and the period after time point T2 will be referred to as the latch period.

[0095] In the precharge period, the bit line voltage VBL can be charged to the first voltage level V1, and the read node can be charged to the read node voltage VSO. At the time point T1 when the development period starts, the charge charged in the read node can be moved to the bit line. When there is a strong OFF cell with a threshold voltage relatively higher than the read voltage, the change in the level of the read node can be relatively small. The change in the potential of the read node of the strong OFF cell in the development period is indicated by the dotted line C0. For example, the potential of the read node of the strong OFF cell only drops in the development period.

[0096] When there is a strong ON cell with a threshold voltage relatively lower than the read voltage, the change in the level of the read node can be relatively large. The change in the potential of the read node of the strong ON cell in the development period is indicated by the first curve C1. For example, the potential of the read node of the strong ON cell drops to the first voltage level V1 in the development period. Strong OFF cells or strong ON cells may not be significantly affected by small changes in the development period. The change in the potential of the read node of the storage cell whose threshold voltage is located around the read voltage is indicated by the second to fourth curves C2, C3 and C4 respectively. The second curve C2 can show the development trend of the storage cell with a threshold voltage slightly lower than the read voltage, the curve C3 can show the development trend of the storage cell with a threshold voltage almost similar to the read voltage, and the fourth curve C4 can show the development trend of the storage cell with a threshold voltage slightly higher than the read voltage.

[0097] According to the multi-read operation, a first latch signal LTCH_1 for latching the read node of the storage unit can be provided. The first latch signal LTCH_1 can move the latch time point to an earlier time point based on the time point T2. When the read node is latched by the first latch signal LTCH_1, the latches for the strong OFF unit C0 and the strong ON unit C1 can be set to the logic values ​​corresponding to the OFF unit and the ON unit, respectively. However, the storage unit with a relatively low threshold voltage corresponding to the second curve C2 can be latched as the logic value corresponding to the ON unit. In addition, the storage units corresponding to the third and fourth curves C3 and C4 can be latched as the logic values ​​corresponding to the OFF unit by the first latch signal LTCH_1.

[0098] When the read-out node is latched by the second latch signal LTCH_2, as in the case of using the first latch signal LTCH_1, logic "0" and logic "1" may be latched for the strong OFF cell C0 and the strong ON cell C1. However, a memory cell having a threshold voltage corresponding to the second curve C2 may be latched as a logic value corresponding to an ON cell. Additionally, in the case of a memory cell corresponding to the third curve C3, a capture level V2 in which logic "0" and logic "1" are not clearly distinguished may be latched by the second latch signal LTCH_2. A memory cell corresponding to the fourth curve C4 may be latched as a logic value corresponding to an OFF cell by the second latch signal LTCH_2.

[0099] When the read node is latched by the third latch signal LTCH_3, logic "0" and logic "1" may be latched for the strong OFF cell C0 and the strong ON cell C1 as in the case of using the first latch signal LTCH_1. However, all memory cells having threshold voltages corresponding to the second and third curves C2 and C3 may be latched as logic values ​​"1" corresponding to the ON cell phase "1". In addition, the memory cell corresponding to the fourth curve C4 may be latched as logic values ​​"0" corresponding to the OFF cell by the third latch signal LTCH_3.

[0100] By latching the state of the read node as a logic value at different development time points in the method described above to identify any one state, a read voltage can be provided to the word line at different levels according to the development time point. The read voltage set can refer to a plurality of different voltage levels of the read node according to the latching time point according to the method described above, or a plurality of voltage levels at different levels provided to the word line for reading.

[0101] Fig.12 1 is a timing diagram showing a read operation according to an exemplary embodiment of the present invention. Fig.11 The same or similar descriptions are given to those described above.

[0102] refer to Figure 2 and Fig.12 , the fifth read operation RD5 and the ninth read operation RD9 may be performed to perform multiple readouts on the MSB page. Fig.12In the embodiment of the present invention, the multi-read manager 110 may determine that the number of read operations corresponding to the fifth read operation RD5 is "2" and the number of read operations corresponding to the ninth read operation RD9 is "3". In the fifth read operation RD5, the bit line and the read node are precharged, and the read voltage corresponding to the fifth read operation RD5 may be provided to the word line of the selected memory cell. When the precharging of the bit line and the read node is completed, a development operation in which the potential of the read node changes according to the state of the memory cell may occur in the page buffer 130. In addition, the state of the selected memory cell may be latched by sequentially providing latch signals LTCH_1 and LTCH_2 at different development time points. After the selected memory cell is latched, the latched data may be stored in the page buffer 130 in a plurality of latches provided in a plurality of latch sets LS1 to LSn.

[0103] Next, in the ninth read operation RD9, the bit line and the read node are precharged, and the read voltage corresponding to the ninth read operation RD9 can be provided to the word line of the selected memory cell. When the precharge of the bit line and the read node is completed, a development operation in which the potential of the read node changes according to the state of the memory cell may occur in the page buffer 130. In addition, the state of the selected memory cell can be latched by sequentially providing latch signals LTCH_1, LTCH_2, and LTCH_3 at different development time points. After latching the selected memory cell, the latched data can be stored in the page buffer 130 in the plurality of latches provided in the plurality of latch sets LS1 to LSn.

[0104] The data identifier 120 may perform an operation for comparing and selecting data latched in each latch included in the plurality of latch sets LS1 to LSn. For example, the cells may be counted by comparing the data latched by the first latch signal LTCH_1 with the data latched by the second latch signal LTCH_2. Next, the number of storage cells may be counted by comparing the data latched by the second latch signal LTCH_2 with the data latched by the third latch signal LTCH_3. The number of counted cells may be compared with each other, thereby selecting any one of the data sets latched by the latch signals LTCH_1, LTCH_2, and LTCH_3, respectively.

[0105] FIG. 13A to FIG. 13C is a diagram illustrating a method of selecting data when the number of read operations is "3" according to an exemplary embodiment of the inventive concept. For example, Fig.13A A method of selecting data when the threshold voltage of a memory cell read out by multi-reading is located on the left side of the lowest point is described. Fig.13AThe lowest point in may correspond to the region indicated by (3). Fig. 13B A method of selecting data when the threshold voltage of a memory cell read out by multi-reading is located around the lowest point will be described. Fig. 13B The lowest point in may correspond to the region indicated by (2). Fig. 13C A method of selecting data when the threshold voltage of a memory cell read out by multi-reading is located on the right side of the lowest point is described. Fig. 13C The lowest point in may correspond to the region indicated by (1).

[0106] refer to Fig.13A and Fig. 13B , the threshold voltage level of the memory cell stored in the latch set can be indicated based on the multiple reads for identifying the two states S1 and S2 of the memory cell. In other words, Fig.13A and Fig. 13B Each provides a scatter plot of the positions of the threshold voltages of memory cells when the threshold voltages of the memory cells are read at different development time points or when they are read by read voltages of different levels.

[0107] Under the same read voltage conditions, when the state of the read-out node is latched as a logic level by the first latch signal LTCH_1, the results of reading and latching can match the read-out voltage at level (1), when the state of the read-out node is latched as a logic level by the second latch signal LTCH_2, the results of reading and latching can match the read-out voltage at level (2), and when the state of the read-out node is latched as a logic level by the third latch signal LTCH_3, the results of reading and latching can match the read-out voltage at level (3).

[0108] The memory cells whose threshold voltage is between level (1) and level (2) can be counted by comparing the first latch corresponding to level (1) and the second latch corresponding to level (2). For example, the data identifier 120 can perform an exclusive OR logic OR (XOR) operation on the data latched in each of the first latch and the second latch, thereby counting the number Cnt1 of the first memory cells whose threshold voltage is between level (1) and level (2). The data identifier 120 can perform an XOR operation on the data latched in each of the second latch and the third latch to count the number Cnt2 of the second memory cells whose threshold voltage is between level (2) and level (3).

[0109] When counting the numbers Cnt1 and Cnt2 of the storage cells, the data identifier 120 may compare the counted numbers of the storage cells. Fig.13AIn the embodiment of , when it is determined that the number Cnt1 of the first storage cells is greater than the number Cnt2 of the second storage cells, the data identifier 120 may select a third latch set corresponding to level (3) and determine that the data stored in the third latch set is the optimal data. Fig. 13B In the embodiment of , when it is determined that the number Cnt1 of the first storage cells is equal to the number Cnt2 of the second storage cells or the difference therebetween is less than or equal to the reference value, the data identifier 120 may select the second latch set corresponding to level (2) and determine that the data stored in the second latch set is the optimal data. Fig. 13C In the embodiment, when it is determined that the number Cnt1 of the first storage cells is less than the number Cnt2 of the second storage cells, the data identifier 120 may select the first latch set corresponding to level (1) and determine that the data stored in the first latch set is the optimal data.

[0110] Fig.14A and Fig. 14B is a diagram illustrating a method of selecting data when the number of read operations is "2" according to an exemplary embodiment of the inventive concept. For example, Fig.14A A method of selecting data when the threshold voltage of a memory cell read out by multi-reading is located on the left side of the lowest point is shown, and Fig. 14B A method of selecting data when the threshold voltage of a memory cell read out by multi-reading is located on the right side of the lowest point is shown. Fig.14A and Fig. 14B In the embodiment of the present invention, the threshold voltage level of the memory cell stored in the set of latches can be indicated based on the multiple reads for identifying the two states S1 and S2 of the memory cell.

[0111] Under the same read voltage condition, when the state of the read node is latched as a logic level by the first latch signal LTCH_1, the result of reading and latching can match the read voltage at level (1), and when the state of the read node is latched as a logic level by the second latch signal LTCH_2, the result of reading and latching can match the read voltage at level (2).

[0112] Among the memory cells, first memory cells having a threshold voltage higher than level (1) can be counted by using the first latch, and second memory cells having a threshold voltage lower than level (2) can be counted by using the second latch. The data identifier 120 can generate the count Cnt by performing an XOR operation on the first memory cell and the second memory cell.

[0113] The data identifier 120 may compare the count Cnt with a reference bit (or value) A. Fig.14AIn the embodiment of , when it is determined that the count Cnt is less than the reference bit A, the data identifier 120 may select the second latch corresponding to the level (2) and determine the data stored in the second latch as the optimal data. Fig. 14B In the embodiment of FIG. 1 , when it is determined that the count Cnt is greater than the reference bit A, the data identifier 120 may select the first latch corresponding to the level (1) and determine the data stored in the first latch as the optimal data.

[0114] Fig.15 is a flow chart of the operation of a nonvolatile storage system according to an exemplary embodiment of the present inventive concept. For example, Fig.15 is shown for sequentially performing multiple read operations Figure 4 Flow chart of operation S140.

[0115] refer to Figure 2 and Fig.15 , the nonvolatile memory device 10 may sequentially perform a plurality of read operations other than the read operation corresponding to the minimum number of read operations (operation S141). For example, the nonvolatile memory device 10 may sequentially perform a plurality of read operations other than the read operation corresponding to the minimum number of read operations in ascending or descending order according to the level of the read voltage. Cell counts for read operations that have been performed may be performed in parallel by the data identifier 120 while other read operations are being performed. After completing read operations other than the read operation corresponding to the minimum number of read operations, the nonvolatile memory device 10 may perform a read operation corresponding to the minimum number of read operations (operation S142). At this time, cell counts for read operations other than the read operation corresponding to the minimum number of read operations may be completed. After completing the read operation corresponding to the minimum number of read operations, the nonvolatile memory device 10 may perform cell counts for read operations corresponding to the minimum number of read operations (operation S143).

[0116] Because the last cell count performed corresponds to the read operation corresponding to the minimum number of read operations, the time taken for the last cell count is also the shortest. According to an exemplary embodiment of the inventive concept, the cell count for the read operation corresponding to the minimum number of read operations is performed last, and thus the overall read time can be reduced.

[0117] Fig.16 1 is a diagram showing a nonvolatile storage system according to an exemplary embodiment of the present invention. Fig.15 The same or similar descriptions are given to those described above.

[0118] refer to Figure 2 and Fig.16, the multi-read manager 110 may control the page buffer 130 to finally perform the fifth read operation RD5 having the smallest number of read operations among the plurality of read operations RD1, RD5, RD9, and RD12 for the LSB page. The first cell count CC1 corresponding to the first read operation RD1 (of 4 reads) may be performed by the data identifier 120 when the ninth read operation RD9 is performed by the page buffer 130. The ninth cell count CC9 corresponding to the read operation RD9 (of 3 reads) may be performed by the data identifier 120 when the twelfth read operation RD12 is performed by the page buffer 130. The twelfth cell count CC12 corresponding to the read operation RD12 (of 3 reads) may be performed by the data identifier 120 when the fifth read operation RD5 is performed by the page buffer 130. Therefore, the first cell count CC1, the ninth cell count CC9, and the twelfth cell count CC12 may not affect the overall read time. In addition, because the fifth read operation RD5 corresponds to the minimum number of read operations, the elapsed time t4 of the fifth cell count CC5 can be shorter than the elapsed times t1, t2, and t3 of the first cell count CC1, the ninth cell count CC9, and the twelfth cell count CC12, respectively. Therefore, according to an exemplary embodiment of the inventive concept, the read operation corresponding to the minimum number of read operations is performed last to complete the last cell count that affects the read time as quickly as possible, thereby reducing the overall read time. It will be further understood that the elapsed times t2 and t3 can be shorter than the elapsed time t1.

[0119] although Fig.16 Only a read operation for the LSB page is shown, but the description thereof can also be applied to the first middle bit CSB1, the second middle bit CSB2, and the MSB.

[0120] Fig.17 1 is a block diagram showing a nonvolatile memory device according to an exemplary embodiment of the present invention. Figure 1 The same or similar descriptions are given to those described above.

[0121] refer to Fig.17 , the nonvolatile memory system 1a may include a memory controller 20a and a nonvolatile memory device 10a. The memory controller 20a may include a multi-read manager 110a, and the nonvolatile memory device 10a may include a data identifier 120a, a page buffer 130a, and a memory cell array 140a. The operations of the multi-read manager 110a, the data identifier 120a, the page buffer 130a, and the memory cell array 140a may be similar to Figure 1The operations of the multi-readout manager 110, the data identifier 120, the page buffer 130, and the memory cell array 140 of the nonvolatile memory device 10a are or are the same as those described above. Therefore, descriptions that are the same as or similar to those given above may be omitted. The multi-readout manager 110a may be included in the memory controller 20a. The multi-readout manager 110a may generate a multi-readout control signal Ctrl_MS based on a read request from the host HOST and output the multi-readout control signal Ctrl_MS to the nonvolatile memory device 10a. The nonvolatile memory device 10a may perform multi-readout on the memory cell array 140a based on the multi-readout control signal Ctrl_MS.

[0122] Fig.18 is a block diagram illustrating application of a nonvolatile memory device to a solid state drive (SSD) system according to an exemplary embodiment of the inventive concept.

[0123] refer to Fig.18 , the SSD system 3000 may include a host 3100 and an SSD 3200. The SSD 3200 exchanges a signal SGL with the host 3100 through a signal connector and receives power PWR via a power connector. The SSD 3200 may include an SSD controller 3210, an auxiliary power supply 3220, and a plurality of flash memory devices 3230, 3240, and 3250. The plurality of flash memory devices 3230, 3240, and 3250 may communicate with the SSD controller 3210 via a plurality of channels Ch1 to Chn. Here, the SSD 3200 may be connected to the host 3100 by using a signal connector. Figures 1 to 17 The SSD 3200 is implemented according to the embodiment shown in FIG.

[0124] For example, Figure 2 The nonvolatile memory device 10 may be applied to at least one of the flash memory devices 3230, 3240, and 3250. Therefore, when performing a read operation, the number of read operations for at least one of the flash memory devices 3230, 3240, and 3250 may be determined differently, and the order in which the read operations are performed may be determined based on the determined number of read operations. Therefore, the efficiency of the read operation may be improved.

[0125] The nonvolatile memory device according to the exemplary embodiment of the inventive concept may be installed or applied not only to the SSD 3200 but also to a memory card system, a computing system, a universal flash storage (UFS), etc. In addition, the method of operating a nonvolatile memory device according to the exemplary embodiment of the inventive concept may be applied to various types of electronic systems on which a nonvolatile memory is installed.

[0126] While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concept as defined by the appended claims.

Claims

1. A non-volatile storage device, comprising: A memory cell array comprising a plurality of memory cells; a page buffer for performing a plurality of read operations and storing results of the plurality of read operations, wherein each of the plurality of read operations includes at least one readout operation for a selected memory cell among the plurality of memory cells; The control logic is configured as: determining a number of read operations for each of the plurality of read operations and controlling the page buffer to perform the plurality of read operations; and identifying a data state of a bit of the selected memory cell based on results of the plurality of read operations, wherein the control logic determines that the number of read operations for at least one of the plurality of read operations is different from the number of read operations for other read operations among the plurality of read operations, The page buffer performs the read operation by using a read voltage, and the control logic determines the number of read operations based on a voltage level range corresponding to a voltage level of the read voltage among a plurality of read level ranges.

2. The nonvolatile storage device according to claim 1, wherein: When the voltage level of the read voltage is equal to or less than a first reference voltage, the control logic determines the number of the read operations to be a first number, When the voltage level of the read voltage is greater than the first reference voltage and equal to or less than a second reference voltage, the control logic determines the number of the read operations to be a second number, and When the voltage level of the read voltage is greater than the second reference voltage, the control logic determines the number of the read operations to be a third number.

3. The nonvolatile storage device according to claim 2, wherein: The first number and the third number are greater than the second number.

4. The nonvolatile storage device according to claim 1, wherein: When the voltage level of the read voltage is equal to or less than a first reference voltage, the control logic determines the number of the read operations to be a first number, When the voltage level of the read voltage is greater than the first reference voltage and equal to or less than a second reference voltage, the control logic determines the number of the read operations to be a second number, When the voltage level of the read voltage is equal to or less than a third reference voltage, the control logic further determines the number of the read operations to be a third number, and When the voltage level of the read voltage is greater than the third reference voltage, the control logic determines the number of the read operations to be a fourth number.

5. The nonvolatile storage device according to claim 4, wherein: The first number is greater than the second number and the third number, and The fourth number is greater than the third number.

6. The nonvolatile memory device according to claim 1, wherein: The control logic determines an order for performing the plurality of read operations based on the number of the read operations.

7. The nonvolatile memory device according to claim 6, wherein: The control logic controls the page buffer to finally perform a first read operation among the plurality of read operations, wherein the first read operation has a smallest number of read operations.

8. The non-volatile memory device according to claim 7, in, The control logic controls the page buffer to sequentially perform a plurality of read operations except the first read operation in an ascending order or a descending order according to voltage levels of read voltages corresponding to the plurality of read operations except the first read operation.

9. The nonvolatile memory device according to claim 7, wherein: After the page buffer completes the first read operation, the control logic performs a first cell count corresponding to the first read operation, and The first cell count is shorter in time than each of a plurality of cell counts respectively corresponding to a plurality of read operations other than the first read operation.

10. The nonvolatile memory device according to claim 1, wherein: The page buffer includes a set of latches for storing results of the plurality of read operations, and The page buffer performs the read operation at least once at each of different development time points, and stores a result of the read operation in a plurality of latches included in the latch set.

11. The nonvolatile memory device according to claim 10, wherein: The latch set includes: a first latch configured to store data read out by a first read operation among the read operations; a second latch configured to store data read out by a second read operation among the read operations; a third latch configured to store data read out through a third read operation among the read operations; and The fourth latch is configured to store data read out through a fourth read operation among the read operations.

12. The nonvolatile memory device according to claim 11, wherein: The control logic controls the page buffer to store the read data in the first latch, the second latch, the third latch and the fourth latch by performing at least one of the first read operation, the second read operation, the third read operation and the fourth read operation according to the number of read operations for each of the multiple read operations.

13. The nonvolatile memory device according to claim 11, wherein: When the number of the read operations is two, the control logic compares a count generated by performing an XOR calculation on the number of OFF cells counted by using the first latch and the number of ON cells counted by using the second latch with a reference bit, and determines a data state of one of the selected memory cells from the data included in the first latch and the second latch.

14. The nonvolatile memory device according to claim 11, wherein: When the number of the read operations is three, the control logic calculates a first cell count by comparing the first latch with the second latch, calculates a second cell count by comparing the second latch with the third latch, and compares the first cell count with the second cell count, thereby determining a data state of one of the selected memory cells from the data included in the first latch, the second latch, and the third latch.

15. The nonvolatile memory device according to claim 11, wherein: When the number of the read operations is four, the control logic determines a data state of one of the selected memory cells from data included in the first latch, the second latch, the third latch, and the fourth latch by comparing the first latch, the second latch, the third latch, and the fourth latch with each other.

16. A non-volatile storage device comprising: A memory cell array comprising a plurality of memory cells; a page buffer configured to perform a read operation on a selected memory cell among the plurality of memory cells, wherein the read operation includes a plurality of read operations; The control logic is configured as: controlling the page buffer to perform a first read operation for performing a plurality of first read operations based on a first set of read voltages and a second read operation for performing a plurality of second read operations based on a second set of read voltages; and identifying a data state of a bit of a selected memory cell based on a result of the first read operation and a result of the second read operation, and storing the result in a set of latches, wherein the number of the first read operations is different from the number of the second read operations, wherein the control logic determines an order for performing the first and second read operations based on the number of read operations, and The control logic controls the page buffer to perform the first read operation last, wherein the first read operation has a minimum number of read operations.

17. The nonvolatile memory device according to claim 16, wherein: The control logic determines the number of the first sensing operations based on whether the first set of sensing voltages has a higher voltage level than a first reference voltage, and The control logic determines a number of the second sensing operations based on whether the second set of sensing voltages has a higher voltage level than the first reference voltage.

18. The nonvolatile memory device according to claim 16, wherein: The control logic controls the page buffer to perform a third read operation to perform a plurality of third read operations based on a third set of read voltages, The control logic identifies a data state of a bit of the selected memory cell based on a result of the first read operation, a result of the second read operation, and a result of the third read operation, and The number of the third readout operations is different from at least one of the number of the first readout operations and the number of the second readout operations.

19. The nonvolatile memory device according to claim 16, wherein: The control logic controls the page buffer to perform a third read operation and a fourth read operation, and, When the number of first read operations for the first read operation is less than each of the number of second read operations for the second read operation, the number of third read operations for the third read operation, and the number of fourth read operations for the fourth read operation, the control logic controls the page buffer to perform the first read operation last.

20. The nonvolatile memory device according to claim 19, wherein: When the first read operation, the second read operation, the third read operation and the fourth read operation are completed, the control logic respectively performs a first unit count, a second unit count, a third unit count and a fourth unit count, and The first cell count performed after the first read operation is completed takes a shorter time than each of the second cell count, the third cell count, and the fourth cell count.

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