Package embedded structure for semiconductor device and manufacturing method

Abstract

A semiconductor package is disclosed, comprising a second leadframe assembly stacked above a first leadframe assembly, each leadframe assembly including a die pad, a plurality of leads, and a semiconductor die attached to the die pad and electrically connected to the leads. Spacers separate the leadframe assemblies from one another. A single molding compound is embedded within a portion of the first leadframe assembly, a portion of the second leadframe assembly, and the spacers. Portions of the leads of the two leadframe assemblies are uncovered by the molding compound to form terminals of the semiconductor package. One side of the two die pads is uncovered by the molding compound.

Description

Technical Field

[0001] The present application relates to semiconductor device packaging, and more particularly to a stacked assembly for packaging semiconductor devices. Background Art

[0002] Stacking is a technique for stacking multiple semiconductor dies (chips) or multiple semiconductor packages on top of each other to reduce the overall package footprint and size. In the case of the stacked chip stacking technique, two semiconductor dies are attached to each other in a stacked arrangement using bonding wires leading to the dies. The stacked chip arrangement with wire bonding connections is then molded to form the final package. However, with the stacked chip stacking method, both dies are completely encapsulated by the molding compound, which limits the thermal performance of the final solution. Moreover, dedicated wire bonding design rules are required to form the bonding wire connections to the stacked die arrangement. In the case of the stacked package stacking technique, two fully completed semiconductor packages are stacked on top of each other. That is, each semiconductor package has been molded, trimmed, and formed before stacking. The completed packages are then bonded to each other in a stacked arrangement. However, with the stacked package stacking method, both packages are completely molded, and the dies are completely embedded in the corresponding molding compound, which again limits the thermal performance of the final solution.

[0003] Therefore, there is a need for an improved stack assembly for packaging semiconductor devices. Summary of the Invention

[0004] According to an embodiment of a semiconductor package, the semiconductor package includes a first lead frame assembly and a second lead frame assembly stacked above the first lead frame assembly. The first lead frame assembly includes a first die pad, a first plurality of leads, and a first semiconductor die attached to the first die pad and electrically connected to the first plurality of leads. The second lead frame assembly includes a second die pad, a second plurality of leads, and a second semiconductor die attached to the second die pad and electrically connected to the second plurality of leads. A spacer separates the first and second lead frame assemblies from each other. A single molding compound embeds a portion of the first lead frame assembly, a portion of the second lead frame assembly, and the spacer. A portion of the first plurality of leads and a portion of the second plurality of leads are not covered by the molding compound to form terminals of the semiconductor package. A side of the first die pad facing away from the first semiconductor die and a side of the second die pad facing away from the second semiconductor die are not covered by the molding compound.

[0005] According to an embodiment of a method for manufacturing a semiconductor package, the method includes: providing a plurality of first lead frame assemblies, each first lead frame assembly including a first die pad, a first plurality of leads, and a first semiconductor die attached to the first die pad and electrically connected to the first plurality of leads; stacking a second lead frame assembly above each of the first lead frame assemblies, each second lead frame assembly including a second die pad, a second plurality of leads, and a second semiconductor die attached to the second die pad and electrically connected to the second plurality of leads; providing spacers between the first lead frame assemblies and the second lead frame assemblies; embedding a portion of each first lead frame assembly, a portion of each second lead frame assembly, and each spacer in a single molding compound so that a portion of each of the first plurality of leads and a portion of each of the second plurality of leads are not covered by the molding compound to form terminals of a corresponding semiconductor package, and so that a side of each first die pad facing away from an adjacent first semiconductor die and a side of each second die pad facing away from an adjacent second semiconductor die are not covered by the molding compound; and singulating the corresponding semiconductor packages into individual packages.

[0006] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The elements of the drawings are not necessarily to scale with respect to each other. Like reference numerals indicate corresponding similar parts. Features of the various illustrated embodiments may be combined unless they exclude each other. Embodiments are depicted in the drawings and described in detail in the following description.

[0008] Figure 1A A cross-sectional view of an embodiment of a molded semiconductor package having a package-in-place structure is shown.

[0009] Figure 1B A top view of the lead frame footprint at the bottom side of a molded semiconductor package is shown.

[0010] Figures 2 to 8 and Figures 13 to 16 Corresponding cross-sectional views of additional embodiments of molded semiconductor packages having package-in-place structures are shown.

[0011] Figures 9A to 9D 、 FIG. 10A to FIG. 10C and Figures 11A to 11E An embodiment of a method of manufacturing a molded semiconductor package is shown.

[0012] Figure 12A and Figure 12B An alternative approach to fabricating a molded semiconductor package is shown. DETAILED DESCRIPTION

[0013] The embodiments described herein provide a package-embedded structure that utilizes the benefits of stacked chip and stacked package stacking technology. The package-embedded structure is achieved by stacking two lead frame assemblies on each other, each lead frame assembly having a die pad, leads, and at least one semiconductor die attached to the die pad and electrically connected to the leads. Spacers separate the lead frame assemblies from each other to prevent short circuits in the bonding wires between the stacked lead frame assemblies. The spacers and portions of the lead frame assemblies are then embedded in a single molding compound via a common molding process. The die pads of the lead frame assemblies are not covered by the molding compound on opposite sides of the final package to provide double-sided heat dissipation. In addition to improved thermal management, the package-in-package structure provides higher component density, does not require design rule changes for chip-to-package interconnects (die attach and wire bonding), reduces the complexity associated with 3D semiconductor packaging, combines two typical IC packaging finishing processes (such as molding, deburring, lead plating, etc.) into a single process with less material usage, utilizes a carrier that eliminates lead bounce during wire bonding, and enables package-level molding that can be reused during the manufacturing process.

[0014] Figure 1A A cross-sectional view of an embodiment of a molded semiconductor package having a package-in-place structure is shown, and Figure 1B A top view of the lead frame footprint at the bottom side of the package is shown.

[0015] The molded semiconductor package includes a first leadframe assembly 100 and a second leadframe assembly 102 stacked above the first leadframe assembly 100. Each leadframe assembly 100, 102 includes a die pad 104, 106 for attaching at least one semiconductor die 108, 110, and includes leads 112, 114 that provide means for external electrical connection to the respective die 108, 110. Each die 108, 110 can be connected to the respective leads 112, 114 by wires 116, 118, such as by wire bonding or tape automated bonding. The semiconductor dies 108, 110 are attached to the respective die pads 104, 106 using standard die attach material, and wire bond connections 116, 118 are formed between the dies 108, 110 and the respective leads 112, 114 to form the leadframe assemblies 100, 102.

[0016] Before the package is molded, the second lead frame assembly 102 is stacked over the first lead frame assembly 100. Also, spacers 120 are provided for separating the lead frame assemblies 100, 102 from each other. Figure 1A and Figure 1BIn the embodiment, the semiconductor die 110 of the second lead frame assembly 102 is arranged above the semiconductor die 108 of the first lead frame assembly 100 and is vertically aligned with it. According to this embodiment, the spacer 120 separates the upper semiconductor die 110 from the lower semiconductor die 108. In the case where the dies 108, 110 are arranged one above the other but are not vertically aligned, or one die is not arranged above the other die (i.e., does not overlap the other die in the vertical direction), the spacer 120 is still provided as structural support to facilitate die stacking. Typically, the spacer 120 is provided as structural support before the molding process to enable die stacking and ensure sufficient electrical isolation between the bond wire connections 116, 118 of the stacked lead frame assemblies 100, 102. In this way, a subsequent molding process can be performed to embed the portion of the first lead frame assembly 100, the portion of the second lead frame assembly 102, and the spacer 120.

[0017] For the reasons described above, the spacer 120 is electrically insulating. Preferably, but not necessarily, the spacer 120 is a good thermal conductor. Some examples of spacer materials are adhesive or polymer beads, films, or pastes with thermally conductive and electrically insulating fillers. These are examples only and should not be considered limiting.

[0018] With the second leadframe assembly 102 stacked above the first leadframe assembly 100 and a spacer 120 provided to separate the leadframe assemblies 100, 102 from one another, this arrangement undergoes a conventional molding process, during which portions of the first leadframe assembly 100, portions of the second leadframe assembly 102, and the spacer 120 are embedded in a single molding compound 122. That is, the same molding compound 122 integrally embeds portions of the leadframe assemblies 100, 102, and the spacer 120. Thus, two separately molded packages are not stacked one on top of the other to form a resulting package-in-a-package structure, and no physical molding compound interface exists between the two leadframe assemblies 100, 102. Instead, the package-in-a-package structure embodiments described herein utilize a single molding compound 122 having an overall continuous structure to embed the spacer 120 and partially embed the leadframe assemblies 100, 102 via a conventional molding process. The spacer 120 can comprise the same or a different material than the molding compound 122.

[0019] A side 124 of the die pad 104 of the first leadframe assembly 100 that faces away from the semiconductor die 108 attached to the die pad 104 is not covered by the mold compound 122. Similarly, a side 126 of the die pad 106 of the second leadframe assembly 102 that faces away from the semiconductor die 110 attached to the die pad 106 is also not covered by the mold compound 122. With this configuration, the molded semiconductor package provides double-sided heat dissipation.

[0020] A portion of the leads 112 of the first leadframe assembly 100 is not covered by the mold compound 122 to form a first set of terminals 128 of the semiconductor package. Similarly, a portion of the leads 114 of the second leadframe assembly 102 is not covered by the mold compound 122 to form a second set of terminals 130 of the semiconductor package. The terminals 128, 130 provide points of external electrical contact for the semiconductor dies 108, 110 embedded in the common mold compound 122.

[0021] The terminals 128, 130 formed by the leads 112, 114 of the lead frame assemblies 100, 102 can have different configurations. In this embodiment, the first set of terminals 128 are located within the outline of the molded semiconductor package and are flush with the bottom surface 132 of the molded semiconductor package. The second set of terminals 130 extend from one or more sides of the semiconductor package beyond the outline of the molded semiconductor package. According to a specific example, one of the lead frame assemblies 100 / 102 has a quad flat no-lead (QFN) or dual flat no-lead (DFN) configuration, and the other lead frame assembly 102 / 100 has a quad flat package (QFP) or dual small outline package (DSO) configuration. Flat no-lead package configurations such as QFN and DFN connect the IC at the bottom to the surface of a printed circuit board (PSB) or similar substrate without through-holes. QFP and DSO configurations are also surface mount technologies, but the terminals (leads) extend from one or more sides of the package instead of from the bottom surface.

[0022] exist Figure 1A and Figure 1B In the embodiment shown in FIG. 1 , the first lead frame assembly 100 has a QFN or DFN configuration, and the second lead frame assembly 102 has a QFP or DSO configuration. The leads 112 of the first lead frame assembly 100 are not covered by the mold compound 122 at the bottom surface 132 of the molded semiconductor package. The leads 114 of the second lead frame assembly 102 protrude from the mold compound 122 at one or more sides 134 of the semiconductor package and bend in a direction toward the bottom surface 132 of the package.

[0023] Figure 2 Another embodiment of a first lead frame assembly 100 having a QFN or DFN configuration and a second lead frame assembly 102 having a QFP or DSO configuration is shown. Figure 2 The embodiment shown in Figure 1A and Figure 1B However, the difference is that the leads 114 of the second lead frame assembly 102 are bent in a direction toward a top surface 136 opposite the bottom surface 132 of the semiconductor package.

[0024] Figure 3 Another embodiment of a first lead frame assembly 100 having a QFN or DFN configuration and a second lead frame assembly 102 having a QFP or DSO configuration is shown. Figure 3 The embodiment shown in Figure 2 However, the difference is that the ends of the leads 114 of the second lead frame assembly 102 point inwardly toward the package rather than outwardly.

[0025] Figure 4 Another embodiment of a first lead frame assembly 100 having a QFN or DFN configuration and a second lead frame assembly 102 having a QFP or DSO configuration is shown. Figure 4 The embodiment shown in Figure 3 However, the difference is that the ends of some of the leads 114 of the second lead frame assembly 102 point inwardly toward the package, and the ends of other leads 114 of the second lead frame assembly 102 point outwardly.

[0026] Figure 5 An embodiment is shown in which both lead frame assemblies 100, 102 have a QFN or DFN configuration. According to this embodiment, the leads 112 of the first lead frame assembly 100 are not covered by the molding compound 122 at a bottom surface 132 of the molded semiconductor package, and the leads 114 of the second lead frame assembly 102 are not covered by the same molding compound at a top surface 136 of the package opposite the bottom surface 132.

[0027] Figure 6 An embodiment is shown in which both lead frame assemblies 100, 102 have a QFP or DSO configuration. According to this embodiment, the leads 112 of the first lead frame assembly 100 protrude from the mold compound 122 at one or more sides 134 of the molded semiconductor package and are bent in a direction toward the bottom surface 132 of the package. The leads 114 of the second lead frame assembly 102 also protrude from the mold compound at one or more sides 134 of the semiconductor package, but are bent in a direction toward a top surface 136 of the semiconductor package, opposite the bottom surface 132.

[0028] Figure 7 Another embodiment is shown where both lead frame assemblies 100 , 102 have a QFP or DSO configuration. Figure 7 The embodiment shown in Figure 6 The embodiment shown in is similar. However, the difference is that Figure 6 As shown, the ends of the leads 112 of the first leadframe assembly 100 point inwardly toward the molded semiconductor package rather than outwardly.

[0029] Figure 8Another embodiment is shown where both lead frame assemblies 100 , 102 have a QFP or DSO configuration. Figure 8 The embodiment shown in Figure 6 The embodiment shown in is similar. However, the difference is that Figure 6 As shown, the ends of the leads 114 of the second leadframe assembly 102 point inwardly toward the molded semiconductor package, rather than outwardly. Additional QFP terminal (lead) configurations are also contemplated and depend on the corresponding conductor trace layout of the board / PCB to which the molded semiconductor package is to be attached.

[0030] As previously described herein, a molded semiconductor package is manufactured by stacking a second lead frame assembly 102 above a first lead frame assembly 100 and providing a spacer 120 prior to a common molding process for separating the lead frame assemblies 100, 102 from one another. After the lead frame assemblies 100, 102 are stacked and separated from one another by the spacer 120, portions of the first lead frame assembly 100, portions of the second lead frame assembly 102, and the spacer 120 are embedded in a single molding compound 122. A specific embodiment of manufacturing the molded semiconductor package is described below.

[0031] Figures 9A to 9D Shows the formation Figure 1A and Figure 1B One embodiment of a first lead frame assembly 100 is shown in FIG.

[0032] exist Figure 9A In the embodiment of the present invention, a first leadframe strip 200 is provided with a carrier 202 temporarily attached to the bottom of the first leadframe strip 200. The carrier 202 provides support during subsequent wire bonding and common molding processes. The first leadframe strip 200 includes a plurality of first die pads 204 and a plurality of first leads 206 interconnected to each other via a frame 208. Each die pad 204 and a surrounding set of leads 206 form an individual leadframe 210, which are interconnected by the frame 208, for example, via so-called tie bars or similar structures. The leadframe strip is typically formed from a flat metal sheet, for example, by stamping or etching. The metal sheet is typically exposed to a chemical etchant, which removes areas not covered by the photoresist. After the etching process, the etched frames are singulated (separated) into leadframe strips. Each leadframe strip includes a plurality of unit leadframes, each having the die pad and lead configuration described herein.

[0033] exist Figure 9B , a first semiconductor die 212 is attached to each of the first die pads 204 of the first lead frame strip 200. Any standard die attach process may be used, such as soldering, sintering, gluing, etc.

[0034] exist Figure 9C , each of the first semiconductor dies 212 is electrically connected to a set of first leads 206 surrounding a first die pad 204 to which the dies 212 are attached. For example, the first dies 212 can be connected to the corresponding set of first leads 206 by electrical conductors 214, such as wire bonds, metal clips, metal ribbons, or the like.

[0035] exist Figure 9D In the embodiment, the first lead frame strip 200 is singulated into individual first lead frame components 216 by any standard singulation process such as laser cutting, jet cutting, sawing, etc. Figure 9D Not shown, but a spacer material may be applied to the exposed major surface of each first semiconductor die 212 .

[0036] FIG. 10A to FIG. 10C Shows the formation Figure 1A and Figure 1B One embodiment of the second lead frame assembly 102 is shown in FIG.

[0037] exist Figure 10A In the embodiment, a second lead frame strip 300 is provided, which includes a plurality of second die pads 302 and a plurality of second leads 304 interconnected to each other by a frame 306. A portion of the frame 306 is not Figure 10A As described above, each die pad 302 and a surrounding set of leads 304 form a lead frame 308, which are interconnected through the frame 306, for example via tie bars or similar structures. Figure 10A , a second semiconductor die 310 is attached to each of the second die pads 302 of the second lead frame strip 300. Any standard die attach process may be used, such as soldering, sintering, gluing, etc.

[0038] exist Figure 10B , each of the second semiconductor dies 310 is electrically connected to a set of second leads 304 surrounding a second die pad 302 to which the dies 310 are attached. For example, the second dies 310 can be connected to the corresponding set of second leads 304 by electrical conductors 312, such as wire bonds, metal clips, metal ribbons, or the like.

[0039] exist Figure 10C, spacers 314 are applied to the exposed major surface of each second semiconductor die 310 of the second leadframe strip 300. As previously described, the spacers 314 are provided prior to the molding process as structural support to enable die stacking and to ensure adequate electrical isolation between the wirebond connections 214 of the first leadframe assembly 216 and the wirebond connections 312 of the second leadframe strip 300. Preferably, but not necessarily, the spacers 314 are good thermal conductors. Some examples of spacers 314 are adhesive or polymer beads, films, or pastes with thermally conductive and electrically insulating fillers. These are examples only and should not be considered limiting.

[0040] Figures 9A to 9D and FIG. 10A to FIG. 10C The process shown in can be reversed because Figure 1A and Figure 1B The second lead frame assembly 102 shown in FIG. 1 may be as shown in FIG. Figures 9A to 9D is processed as shown, and Figure 1A and Figure 1B The first lead frame assembly 100 shown in FIG. 10A to 10C Utilizing this method, a plurality of second lead frame assemblies will remain attached to one another as part of a single lead frame strip, and the corresponding first lead frame strips will be singulated into individual first lead frame assemblies. Typically, Figures 1A to 8 Any of the QFN / DFN / QFP / DSO configurations shown in Figures 9A to 9D as well as FIG. 10A to FIG. 10C In each case, one leadframe strip remains intact and the other leadframe strip is singulated into individual leadframe assemblies in preparation for subsequent processing that produces multiple packaged nested structures molded using a common process.

[0041] Figures 11A to 11E shows that by processing Figures 9A to 9D and FIG. 10A to FIG. 10C The process shown in FIG. 1 is implemented to form the first lead frame assembly 216 and the second lead frame strip 300. Figure 1A and Figure 1B An embodiment of a molded semiconductor package is shown in FIG. Again, as described above, Figures 11A to 11E The processing shown in can be easily applied to any of the QFN / DFN / QFP / DSO configurations described in this article.

[0042] exist Figure 11A, after providing the spacers 314 between the first leadframe assembly 216 and the second leadframe strip 300, the second leadframe strip 300 is aligned with the first leadframe assembly 216 such that each second semiconductor die 310 is disposed over one of the first semiconductor die 212. The second semiconductor die 310 may or may not be vertically aligned with the corresponding first semiconductor die 212.

[0043] exist Figure 11B In the embodiment of the present invention, the stacked arrangement of lead frame assemblies is placed in a standard molding tool 400 and subjected to a conventional molding process, during which a portion of each first lead frame assembly 216, a portion of each second lead frame assembly attached to a complete lead frame strip 300, and the spacers 314 are embedded in a single molding compound 402. That is, the same molding compound 402 integrally embeds a portion of each first lead frame assembly 216, a portion of each second lead frame assembly attached to a complete lead frame strip 300, and the spacers 314. Thus, two separately molded packages are not stacked one on top of the other to form the resulting package-in-place structure. Instead, in a conventional molding process, a single molding compound 402 having a continuous construction as a whole embeds the spacers 314 and partially embeds the lead frame assemblies. Any standard molding compound can be used.

[0044] Also in Figure 11B , the upper leadframe assembly 216 is shown pre-singulated to allow the mold compound 402 to flow in and around the sides of the resulting package embedding structure. Furthermore, the bottom leadframe assemblies remain attached to each other in strip form to facilitate a common molding process. That is, the leadframe assemblies of a group remain interconnected by the frame during embedding in a single mold compound 402.

[0045] exist Figure 11C In the embodiment of the present invention, the resulting molded package inlay structure 404 is removed from the molding tool 400 and remains connected by the frame 306 of the lower lead frame strip 300.

[0046] exist Figure 11D In the embodiment of the present invention, after being embedded in the single mold compound 402, the carrier 202 temporarily attached to the first lead frame assembly 216 is removed. As described above, the carrier 202 provides support during the previous wire bonding and common embedding processes. The carrier 202 can be reused to provide support during the manufacture of a new set of subsequent instances of semiconductor packages.

[0047] exist Figure 11EIn FIG. 4 , a molded package inlay structure 404 formed by a conventional molding process is singulated into individual packages 406. Any standard molded package singulation process may be used, such as trimming and forming, laser cutting, jet cutting, sawing, etc. The molded package inlay structure 404 is singulated by cutting through the frame 306 interconnecting the lower lead frame assembly. If the mold compound 402 is formed on the section of the frame 306 to be cut, the mold compound 402 is also cut through in this area to singulate the molded package inlay structure 404.

[0048] Also in Figure 11E In the conventional process steps, the portion of each lead 206, 304 not covered by the mold compound 402 can be deburred and plated. Any standard deburring process can be used to remove burrs that occur during the conventional molding process. Any standard plating process can be used to plate the exposed portions of the leads 206, 304, for example, using Sn, Sn alloys, NiPdAu, Ni alloys, Au, Au alloys, etc. The plating layer on the leads 206, 304 can include one or more metal layers using non-oxidizing metals or metal alloy materials. Individual packages 406 can also be marked in the conventional process steps.

[0049] Figure 12A and Figure 12B Shown Figure 11A and Figure 11B An alternative to the illustrated embodiment. Instead of the QFN / DFN based lead frame assembly with a temporary carrier being placed on the bottom of the stacked arrangement and the QFP / DSO based lead frame strip being placed on the top, the order is reversed. That is, the QFP / DSO based lead frame strip is placed on the bottom of the stacked arrangement and the QFN / DFN based lead frame assembly with a temporary carrier is placed on the top of the stacked arrangement. Figure 12B As shown, the stacked arrangement is then inserted into a molding tool and subjected to a common molding process to embed the portion of each first lead frame assembly 216, the portion of each second lead frame assembly attached to the complete lead frame strip 300, and the spacer 314 into a single molding compound 402. The resulting molded arrangement of the packaged embedded structure can then be subjected to, for example, Figures 11C to 11E Common process steps are shown.

[0050] As previously mentioned, the terminals formed by the leads of individual lead frame assemblies can have different configurations. For example, one group of lead frame assemblies can have a QFN or DFN configuration, while another group of lead frame assemblies can have a QFP or DSO configuration. In other cases, all leads can have the same configuration, such as QFN, DFN, QFP, or DSO.

[0051] As also previously described, the die included in one group of lead frame assemblies can be disposed above and vertically aligned with corresponding semiconductor dies included in another group of lead frame assemblies. In other cases, the dies are not vertically aligned and / or one die is not disposed above another die. In each case, a spacer is provided prior to the molding process as structural support to enable die stacking and to ensure adequate electrical isolation between the bond wire connections of the stacked lead frame assemblies.

[0052] Figure 13 Another embodiment of a molded semiconductor package is shown in which a lower leadframe assembly 100 includes a single semiconductor die 108 a and an upper leadframe assembly 102 includes two semiconductor dies 110 a, 110 b, neither of which is vertically aligned with the single semiconductor die 108 a of the lower leadframe assembly 100. Spacers 120 provide separation between the semiconductor dies 110 a, 110 b of the upper leadframe assembly 102 and the single semiconductor die 108 a of the lower leadframe assembly 100. Although the lower leadframe assembly 100 is shown as having a QFN / DFN lead configuration and the upper leadframe assembly 102 is shown as having a QFP / DSO lead configuration, the lead configurations may be reversed or even identical.

[0053] Figure 14 Shown above combined Figure 1A and Figure 1B Yet another embodiment of the molded semiconductor package. Figure 14 The embodiment shown in Figure 13 . However, the difference is that the upper lead frame assembly 102 includes a single semiconductor die 110a, and the lower lead frame assembly 100 includes two semiconductor dies 108a, 108b, neither of which is vertically aligned with the semiconductor die 110a of the upper lead frame assembly 102. The spacer 120 again provides separation between the two semiconductor dies 108a, 108b of the lower lead frame assembly 100 and the single semiconductor die 110a of the upper lead frame assembly 102. As described above, although the lower lead frame assembly 100 is shown as having a QFN / DFN lead configuration and the upper lead frame assembly 102 is shown as having a QFP / DSO lead configuration, the lead configurations can be reversed or even the same. Other die / spacer configurations are also contemplated. Generally, the spacer 120 is provided to separate the lead frame assemblies 100, 102 from each other and to avoid shorting of the bond wires between the stacked lead frame assemblies 100, 102.

[0054] Figure 15 Another embodiment of a molded semiconductor package is shown. Figure 15 The embodiment shown in Figure 13However, the difference is that the semiconductor dies 110a, 110b are attached to separate die pads 204a, 204b.

[0055] Figure 16 Another embodiment of a molded semiconductor package is shown. Figure 15 The embodiment shown in Figure 14 However, the difference is that the semiconductor dies 110a, 110b are attached to separate die pads 204a, 204b.

[0056] Spatially relative terms such as "under," "beneath," "lower," "above," and "upper" are used for convenience in the description to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the device in addition to orientations that differ from those shown in the accompanying drawings. In addition, terms such as "first," "second," and the like are also used to describe various elements, regions, portions, and the like, and are not intended to be limiting. Throughout the description, similar terms refer to similar elements.

[0057] As used herein, the terms "having," "comprising," "including," and the like are open-ended terms that indicate the presence of referenced elements or features, but do not exclude additional elements or features. The articles "a," "an," and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0058] With the above range of variations and applications in mind, it should be understood that the present invention is not limited by the foregoing description, nor by the accompanying drawings, but rather is limited only by the following claims and their legal equivalents.

Claims

1. A semiconductor package, comprising: a first leadframe assembly comprising a first die pad, a first plurality of leads, and a first semiconductor die attached to the first die pad and electrically connected to the first plurality of leads; a second leadframe assembly stacked above the first leadframe assembly such that no intervening leadframe assembly is interposed between the first leadframe assembly and the second leadframe assembly, the second leadframe assembly comprising a second die pad, a second plurality of leads, and a second semiconductor die attached to the second die pad and electrically connected to the second plurality of leads; an electrically insulating spacer separating the first lead frame assembly and the second lead frame assembly from each other; as well as a molding compound embedding portions of the first lead frame assembly, portions of the second lead frame assembly, and the electrically insulating spacer, wherein the first plurality of leads are physically separated and electrically isolated from the second plurality of leads, wherein a side of the first die pad facing away from the first semiconductor die is exposed from the molding compound, and A side of the second die pad facing away from the first semiconductor die is exposed from the molding compound.

2. The semiconductor package according to claim 1, wherein The electrically insulating spacer is interposed between the first semiconductor die and the second semiconductor die.

3. The semiconductor package according to claim 1, wherein The electrically insulating spacer comprises a different material than the mold compound.

4. The semiconductor package according to claim 1, wherein The first plurality of leads are uncovered by the molding compound at a bottom surface of the semiconductor package, and wherein the second plurality of leads protrude from the molding compound at one or more sides of the semiconductor package and bend in a direction toward the bottom surface.

5. The semiconductor package according to claim 1, wherein The first plurality of leads are not covered by the molding compound at the bottom surface of the semiconductor package, and wherein the second plurality of leads protrude from the molding compound at one or more sides of the semiconductor package and bend in a direction toward a top surface of the semiconductor package opposite to the bottom surface. The semiconductor package according to claim 1 , wherein: The first plurality of leads are not covered by the molding compound at a bottom surface of the semiconductor package, and wherein the second plurality of leads are not covered by the molding compound at a top surface of the semiconductor package opposite the bottom surface.

7. The semiconductor package according to claim 1, wherein The first plurality of leads protrude from the molding compound at one or more side surfaces of the semiconductor package and bend in a direction toward a bottom surface of the semiconductor package, and wherein the second plurality of leads protrude from the molding compound at the one or more side surfaces of the semiconductor package and bend in a direction toward a top surface of the semiconductor package opposite to the bottom surface.

8. The semiconductor package according to claim 1, wherein One of the lead frame assemblies has a quad flat no-lead (QFN) or dual flat no-lead (DFN) configuration, and wherein the other of the lead frame assemblies has a quad flat package (QFP) or dual small outline (DSO) configuration.

9. The semiconductor package according to claim 1, wherein The first lead frame assembly and the second lead frame assembly each have a quad flat no-lead (QFN) or dual flat no-lead (DFN) configuration.

10. The semiconductor package according to claim 1, wherein The first lead frame assembly and the second lead frame assembly each have a quad flat package (QFP) or dual small outline (DSO) configuration.

11. The semiconductor package according to claim 1, wherein The electrically insulating spacer is an adhesive.

12. The semiconductor package according to claim 1, wherein The electrically insulating spacer comprises polymer beads, films or pastes with thermally conductive and electrically insulating fillers.

13. The semiconductor package according to claim 1, wherein The second semiconductor die is disposed over the first semiconductor die, and wherein the electrically insulating spacer separates the second semiconductor die from the first semiconductor die.

14. A method of manufacturing a semiconductor package, the method comprising: providing a plurality of first lead frame assemblies, each of the plurality of first lead frame assemblies comprising a first die pad, a first plurality of leads, and a first semiconductor die attached to the first die pad and electrically connected to the first plurality of leads; stacking a plurality of second lead frame assemblies over each of the first lead frame assemblies, each second lead frame assembly including a second die pad, a second plurality of leads, and a second semiconductor die attached to the second die pad and electrically connected to the second plurality of leads; providing an electrically insulating spacer between the first lead frame assembly and the second lead frame assembly; embedding a portion of each first leadframe assembly, a portion of each second leadframe assembly, and each electrically insulating spacer in a single molding compound such that a portion of each of the first plurality of leads and a portion of each of the second plurality of leads are uncovered by the molding compound to form terminals of a corresponding semiconductor package, and such that a side of each first die pad facing away from an adjacent first semiconductor die and a side of each second die pad facing away from an adjacent second semiconductor die are uncovered by the molding compound; as well as The respective semiconductor packages are singulated into individual packages.

15. The method according to claim 14, wherein During embedding in the molding compound, the first lead frame assembly or the second lead frame assembly remains interconnected by a frame.

16. The method according to claim 15, further comprising: Cutting through the frame singulates the respective semiconductor packages into the individual packages.

17. The method according to claim 14, further comprising: temporarily attaching the first lead frame assembly or the second lead frame assembly to a carrier that provides support during embedding in the mold compound; as well as After the embedding the carrier is removed.

18. The method according to claim 14, further comprising: In common process steps, the portion of each of the first plurality of leads and the portion of each of the second plurality of leads not covered by the mold compound are deburred and plated.

19. The method according to claim 14, wherein Stacking a second lead frame assembly over each of the first lead frame assemblies includes: providing a lead frame strip comprising said first die pads interconnected to one another by a frame; attaching a first semiconductor die to each of the first die pads; electrically connecting each of the first semiconductor dies to the first plurality of leads surrounding the first die pad to which the first semiconductor die is attached; and After providing the electrically insulating spacer between the first leadframe assembly and the second leadframe assembly, the leadframe strip is aligned with the plurality of second leadframe assemblies such that each second semiconductor die is disposed over one of the first semiconductor dies.

20. The method according to claim 19, wherein The first leadframe assembly has a quad flat no-lead (QFN) or dual flat no-lead (DFN) configuration, and wherein the second leadframe assembly has a quad flat package (QFP) or dual small outline (DSO) configuration.

21. A method of manufacturing a semiconductor package, the method comprising: providing a first leadframe assembly comprising a first die pad, a first plurality of leads, and a first semiconductor die attached to the first die pad and electrically connected to the first plurality of leads; providing a second lead frame assembly stacked above the first lead frame assembly such that no intervening lead frame assembly is interposed between the first lead frame assembly and the second lead frame assembly, the second lead frame assembly including a second die pad, a second plurality of leads, and a second semiconductor die attached to the second die pad and electrically connected to the second plurality of leads; separating the first lead frame assembly and the second lead frame assembly from each other using an electrically insulating spacer; as well as After separating the first lead frame assembly and the second lead frame assembly from each other using the electrically insulating spacer, embedding a portion of the first lead frame assembly, a portion of the second lead frame assembly, and the electrically insulating spacer in a molding compound, wherein the first plurality of leads are physically separated and electrically isolated from the second plurality of leads, wherein a side of the first die pad facing away from the first semiconductor die is exposed from the molding compound, and A side of the second die pad facing away from the first semiconductor die is exposed from the molding compound.

22. The method according to claim 21, wherein The electrically insulating spacer is interposed between the first semiconductor die and the second semiconductor die.

23. The method according to claim 21, wherein Separating the first and second leadframe assemblies from each other using the electrically insulating spacer includes placing the second leadframe assembly over the first leadframe assembly such that the electrically insulating spacer separates the second semiconductor die from the first semiconductor die.

24. The method according to claim 21, wherein Separating the first and second leadframe assemblies from each other using the electrically insulating spacer includes vertically aligning the second semiconductor die with the first semiconductor die such that the electrically insulating spacer is interposed between the second and first semiconductor die.

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