Integrated Circuit Devices

Abstract

An integrated circuit device is provided. An integrated circuit device includes a substrate and a device isolation film on the substrate. An active region of the substrate is defined by the device isolation film on the substrate and has a first width in a horizontal direction. A gate electrode is on the active region and has a second width in a horizontal direction that is equal to or less than the first width of the active region. The integrated circuit device includes an insulating spacer on the device isolation film and the active region.

Description

Technical Field

[0001] The present disclosure relates to integrated circuit devices, and more particularly, to integrated circuit devices including gate electrodes for implementing analog semiconductor devices. Background Art

[0002] As the integration of integrated circuit devices gradually increases with the development of the electronics industry, it is beneficial to provide a design that improves the reliability of integrated circuit devices in a reduced area. Specifically, a display driver integrated circuit (DDI) for driving a display device such as a liquid crystal display device (LCD) or a plasma display panel (PDP) is being developed. The DDI includes a high-voltage transistor that can operate at a high voltage of about 8 volts (V) to about 200V. The high-voltage transistor included in a driver device such as a DDI may have an improved lightly doped drain (MLDD) structure, a field lightly doped drain (FLDD) structure, or a double diffused drain (DDD) structure. However, a high-voltage transistor with such a structure may suffer from a hump phenomenon. Summary of the invention

[0003] The present invention is conceived to provide an integrated circuit device that can have desired performance and provide excellent reliability in a small / minimum area within a highly reduced area, because the integrated circuit device reduces the occupied area of ​​the high voltage transistor and suppresses / prevents the reduction of the threshold voltage by suppressing / preventing the formation of an undesirable edge channel near the interface between the device isolation region and the active region in the high voltage transistor, thereby suppressing the hump phenomenon.

[0004] According to some embodiments of the present invention, an integrated circuit device is provided, which includes a substrate and a device isolation film on the substrate. The active area of ​​the substrate may be defined by the device isolation film on the substrate and may have a first width in the horizontal direction. The integrated circuit device may include a pair of source / drain regions in the active area. The integrated circuit device may include a gate electrode located on a portion of the active area between the paired source / drain regions. The gate electrode may have a second width equal to or less than the first width of the active area in the horizontal direction. The integrated circuit device may include an insulating spacer, the insulating spacer including a first spacer portion on the device isolation film and a second spacer portion on the active area. The first spacer portion and the second spacer portion may be on a first sidewall and a second sidewall of the gate electrode, respectively. The integrated circuit device may include an insulating film, the insulating film including a gate insulating portion between the active area and the gate electrode.

[0005] According to some embodiments of the present invention, an integrated circuit device is provided, which includes a substrate including a trench region defining an active region of the substrate. The active region may have a first width in a first horizontal direction. The integrated circuit device may include a device isolation film in the trench region. The integrated circuit device may include a gate electrode above the active region. The gate electrode may have a second width in the first horizontal direction that is equal to or less than the first width of the active region. The integrated circuit device may include an insulating spacer above the active region and the device isolation film. The insulating spacer may be on a sidewall of the gate electrode. The integrated circuit device may include a pair of source / drain regions in the active region. The pair of source / drain regions may be spaced apart from each other. The gate electrode may overlap a portion of the active region between the pair of source / drain regions. The integrated circuit device may include an insulating film on the active region and the device isolation film. The insulating film may include a gate insulating portion between the active region and the gate electrode. A vertical axis extending through a boundary between an uppermost surface of the active region and the device isolation film in a vertical direction perpendicular to the first horizontal direction may be aligned with one of the sidewalls of the gate electrode, or may extend through the insulating spacer.

[0006] According to some embodiments of the present inventive concept, an integrated circuit device is provided, which includes a substrate, the substrate including a first active region and a second active region adjacent to each other and spaced apart from each other in a first horizontal direction. The integrated circuit device may include a device isolation region between the first active region and the second active region. The integrated circuit device may include a plurality of first impurity diffusion regions in the first active region. The integrated circuit device may include a plurality of second impurity diffusion regions in the second active region. The integrated circuit device may include a first gate electrode above the first active region. The first gate electrode may have a width equal to or less than a width of the first active region in the first horizontal direction. The integrated circuit device may include a first insulating spacer on a sidewall of the first gate electrode and on the device isolation region. The integrated circuit device may include a second gate electrode above the second active region. The second gate electrode may have a width equal to or less than a width of the second active region in the first horizontal direction. The integrated circuit device may include a second insulating spacer on a sidewall of the second gate electrode and on the device isolation region. The separation distance between the first active region and the second active region in the first horizontal direction may be constant along a second horizontal direction perpendicular to the first horizontal direction. In addition, the distance between the first gate electrode and the second gate electrode in the first horizontal direction may be equal to or greater than the separation distance.

[0007] The integrated circuit device conceived according to the present invention can reduce the occupied area of ​​the transistor, can have the desired performance in a small / minimum area within a reduced area by suppressing the occurrence of the hump phenomenon caused by the formation of an undesirable edge channel near the interface between the device isolation region and the active region in the transistor, and can provide excellent reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments of the present inventive concept will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0009] Figure 1A is a plan layout diagram of main components of an integrated circuit device according to some embodiments of the present inventive concept, Figure 1B is along Figure 1A A cross-sectional view taken along line X-X', Figure 1C is along Figure 1A A cross-sectional view taken along the line Y-Y';

[0010] Figure 2 is a cross-sectional view showing an integrated circuit device according to some embodiments of the inventive concept;

[0011] Figure 3A is a plan layout diagram of main components of an integrated circuit device according to some embodiments of the present inventive concept, Figure 3B is along Figure 3A A cross-sectional view taken along the line Y-Y';

[0012] Figure 4A is a plan layout diagram of main components of an integrated circuit device according to some embodiments of the present inventive concept, Figure 4B is along Figure 4A A cross-sectional view taken along the line Y-Y';

[0013] Figure 5 is a plan layout diagram showing an example configuration of an integrated circuit device according to some embodiments of the inventive concept;

[0014] Fig. 6A , 6B , 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 11A, 11B, 12A, 12B, 13A, 13B, 14A, 14B, 15A, 15B, 16A and 16B are cross-sectional views illustrating operations (e.g., sequential processes) of a method of manufacturing an integrated circuit device according to some embodiments of the inventive concept. Specifically, Fig. 6A , 7A , 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A and 16A are respectively shown according to the process sequence and along Figure 1AThe cross-sectional view of the structure corresponding to the cross-sectional view taken along the line XX', Figure 6B , 7B , 8B, 9B, 10B, 11B, 12B, 13B, 14B, 15B and 16B are respectively shown according to the process sequence and along Figure 1A The cross-section taken along the line Y-Y' corresponds to the cross-sectional view of the structure. Figure 7C It is shown Fig. 7A and 7B A top view of the planar structure of some components shown, Fig. 10C It is shown Fig. 10A and 10B A top view of the planar structure of some of the components shown;

[0015] Fig.17A It shows the manufacturing Figure 2 A cross-sectional view of an exemplary method of an integrated circuit device is shown, Fig. 17B It is shown Fig.17A A top view of the planar structure of some of the components shown; and

[0016] Fig.18 is a schematic block diagram of a display device according to some embodiments of the inventive concept. DETAILED DESCRIPTION

[0017] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. Throughout the specification, the same components will be denoted by the same reference numerals, and repeated descriptions thereof may be omitted.

[0018] Figure 1A is a plan layout diagram of main components of an integrated circuit device according to some embodiments of the present inventive concept, Figure 1B is along Figure 1A A cross-sectional view taken along line X-X', Figure 1C is along Figure 1A A cross-sectional view taken along line Y-Y'.

[0019] Reference Figures 1A to 1C , the integrated circuit device 100 includes a transistor TR1 formed on a substrate 110, and a well 112 is formed in the substrate 110. The transistor TR1 may be a high voltage transistor configured to operate at a high voltage of about 8V to about 200V.

[0020] The substrate 110 includes a trench region T1. An active region AC may be defined in the substrate 110 by the trench region T1 and a device isolation film 114 in (eg, filling) the trench region T1. The active region AC has a first width WA1 in the Y direction (first horizontal direction).

[0021] The substrate 110 may include a semiconductor substrate. In some embodiments, the substrate 110 may include a semiconductor such as silicon (Si) or germanium (Ge). In some embodiments, the substrate 110 may include a compound semiconductor such as SiGe, silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP).

[0022] A pair of source / drain regions 116 are formed in the active region AC, and the pair of source / drain regions 116 are surrounded by the well 112. The well 112 may include an impurity doped region of a first conductivity type, such as a p-type. The pair of source / drain regions 116 may include an impurity doped region of a second conductivity type, such as an n-type, opposite to the first conductivity type. A high-concentration doped region 116H is formed in the upper portion of each of the pair of source / drain regions 116. The pair of source / drain regions 116 and the high-concentration doped region 116H may each be doped to have the same conductivity type, and the impurity concentration in the high-concentration doped region 116H may be greater than the impurity concentration in each of the pair of source / drain regions 116.

[0023] The gate electrode 130 is formed above the active region AC and between a pair of source / drain regions 116. The gate electrode 130 may be arranged to vertically overlap only the active region AC without including a portion vertically overlapping with the device isolation film 114. Therefore, the sidewalls of the gate electrode 130 may be referred to herein as “not vertically overlapping” the device isolation film 114 because the gate electrode 130 may be confined within the perimeter / boundary of the uppermost surface of the active region AC. In the Y direction (first horizontal direction), the widest / maximum width WG1 of the gate electrode 130 may be equal to or less than the first width WA1 of the active region AC. Although Figures 1A to 1C An example is shown in which the maximum width WG1 of the gate electrode 130 is equal to the first width WA1, but the present inventive concept is not limited to Figures 1A to 1C For example, in Figure 1A In the top view shown, the widest / maximum width WG1 of the gate electrode 130 may be smaller than the first width WA1 of the active area AC within a range (eg, perimeter) of the gate electrode 130 without the gate electrode 130 departing from (eg, not extending beyond) the active area AC.

[0024] like Figure 1C As shown, the gate electrode 130 may not extend beyond (e.g., may not cover) the boundary (e.g., boundary line / interface) between the device isolation film 114 and the top (e.g., topmost / uppermost) surface of the active region AC in the Y direction. More specifically, the gate electrode 130 may be confined within the perimeter / boundary of the uppermost surface of the active region AC. Figure 1CIn the embodiment, the opposite sidewalls of the gate electrode 130 may be vertically aligned with a portion (eg, the uppermost portion) of the boundary between the device isolation film 114 and the top surface of the active region AC. Figure 1C In the embodiment, each of imaginary vertical extension lines L1 and L2 (eg, vertical axes) extending from opposite side walls of the gate electrode 130 toward the substrate 110 may pass through a boundary between the device isolation film 114 and the top surface of the active region AC.

[0025] In the integrated circuit device 100 , in the top surface of the active region AC between the pair of source / drain regions 116 , the shortest / minimum horizontal distance from the boundary between the active region AC and the device isolation film 114 to each of the imaginary vertical extension lines L1 and L2 may be substantially zero (0).

[0026] The high-concentration doping region 130D may be formed in the upper portion of the gate electrode 130. The high-concentration doping region 130D may be doped with impurities of the second conductivity type. The high-concentration doping region 130D and the high-concentration doping region 116H may include the same impurity ions, and the high-concentration doping region 116H is formed in the upper portion of each of the pair of source / drain regions 116.

[0027] The integrated circuit device 100 may include an insulating spacer 140 on the sidewall of the gate electrode 130 (eg, covering the sidewall of the gate electrode 130). The insulating spacer 140 may include a first spacer portion 140A and a second spacer portion 140B. Figure 1C As shown, the second spacer portion 140B is arranged on the device isolation film 114 and on the sidewall of the gate electrode 130 (eg, covers at least a portion of the sidewall of the gate electrode 130). Figure 1B As shown, the gate electrode 130 is disposed above the active region AC and on the sidewall of the gate electrode 130 (eg, covers at least a portion of the sidewall of the gate electrode 130). Figure 1A As shown, the first spacer portion 140A may be integrally connected to the second spacer portion 140B. A first vertical length (eg, vertical height) HL1 of the first spacer portion 140A may be smaller than a second vertical length (eg, vertical height) HL2 of the second spacer portion 140B.

[0028] The insulating film pattern 120P may be inserted / interposed between the active region AC and the gate electrode 130. Therefore, the insulating film pattern 120P may extend parallel to the main surface / main surface (e.g., the uppermost surface) of the substrate 110. The insulating film pattern 120P may include a gate insulating portion 120GD, a first extended insulating portion 120E1, and a second extended insulating portion 120E2 that are integrally connected to each other. The gate insulating portion 120GD may be inserted / interposed between the channel region CH of the active region AC and the gate electrode 130, the first extended insulating portion 120E1 may be inserted / interposed between the first spacer portion 140A and the active region AC, and the second extended insulating portion 120E2 may be inserted / interposed between the second spacer portion 140B and the active region AC. The insulating film pattern 120P may include a silicon oxide film, but is not limited thereto.

[0029] The thickness of the gate insulating portion 120GD may be substantially equal to the thickness of the first extension insulating portion 120E1. The thickness of the first extension insulating portion 120E1 may be different from the thickness of the second extension insulating portion 120E2. In some embodiments, the thickness of the first extension insulating portion 120E1 may be greater than the thickness of the second extension insulating portion 120E2. Figure 1B As shown in the area marked by the dotted circle AX1 in FIG. 1 , the insulating film pattern 120P may have a step (e.g., a step portion) ST1. The step ST1 may be interposed between the gate insulating portion 120GD and the second extended insulating portion 120E2 (e.g., a transition may be provided between the gate insulating portion 120GD and the second extended insulating portion 120E2), and the step ST1 is on a vertical extension line (e.g., a vertical axis) of the interface between the second spacer portion 140B and the gate electrode 130.

[0030] An interlayer dielectric 160 is formed on the substrate 110, and the interlayer dielectric 160 overlaps (e.g., covers) each of the device isolation film 114, the gate electrode 130, and the pair of source / drain regions 116. A gate contact plug 172 and a plurality of source / drain contact plugs 174 may extend in the interlayer dielectric 160 (e.g., extend through the interlayer dielectric 160). The interlayer dielectric 160 may include an oxide film, a nitride film, or a combination thereof. The gate contact plug 172 may be connected to the gate electrode 130 via a first metal silicide film 152 formed on the high-concentration doped region 130D of the gate electrode 130. A plurality of source / drain contact plugs 174 may be respectively connected (e.g., electrically connected) to the pair of source / drain regions 116 via a second metal silicide film 154 formed on the high-concentration doped region 116H of the source / drain region 116.

[0031] In some embodiments, each of the first metal silicide film 152 and the second metal silicide film 154 may include titanium (Ti) silicide, cobalt (Co) silicide, or nickel (Ni) silicide, but is not limited thereto. In some embodiments, each of the gate contact plug 172 and the plurality of source / drain contact plugs 174 may include a stacked structure including a conductive barrier film and a metal plug. The conductive barrier film may include Ti, titanium nitride (TiN), or a combination thereof, and the metal plug may include tungsten (W), but is not limited thereto.

[0032] Generally, in a high voltage transistor operating at a high voltage of about 8V to about 200V, when the gate electrode extends horizontally above the top surface of the active region or even above the top surface of the device isolation film defining the active region, and thus extends across the vertical axis passing through the interface between the active region and the device isolation film, because the well doping concentration is lower near the interface between the active region and the device isolation film than in other regions due to dopant segregation, even when a voltage lower than the threshold voltage is applied to the gate electrode, inversion is likely to occur near the interface. As a result, an edge channel may be formed near the interface at a voltage lower than the threshold voltage, thereby causing a hump phenomenon. When the hump phenomenon occurs, the threshold voltage of the transistor is reduced due to the parasitic transistor formed at the edge of the gate electrode, and the leakage current increases at a voltage lower than the threshold voltage. In particular, a fatal current dispersion failure may be caused in an analog semiconductor device, thereby possibly causing incorrect operation of the transistor.

[0033] However, in reference Figures 1A to 1C In the described integrated circuit device 100, since the gate electrode 130 does not horizontally extend beyond the vertical axis passing through the boundary between the active region AC and the device isolation film 114 in the vertical direction Z perpendicular to the horizontal directions X and Y, the boundary region between the active region AC and the device isolation film 114 may not be affected by the voltage applied to the gate electrode 130. Therefore, an edge channel is not formed in the edge region, and thus the hump phenomenon may not be caused.

[0034] In addition, in reference Figures 1A to 1C In the described integrated circuit device 100, since the gate electrode 130 is arranged above the active region AC so as not to vertically overlap with the device isolation film 114, the area occupied by one transistor TR1 on the substrate 110 is reduced, so that a structure that is advantageous for device scaling down can be provided, and a transistor TR1 that allows desired performance to be achieved with a small / minimum area within a highly reduced area can be provided. Moreover, in the manufacture of the integrated circuit device 100, since the layout design can be simplified and there is no need to apply complex design rules, the productivity of the process of manufacturing the integrated circuit device 100 can be improved.

[0035] Figure 2 are cross-sectional views illustrating integrated circuit devices according to some embodiments of the inventive concept. Figure 2 shows that along with Figure 1A The cross section taken along the line XX' corresponds to the modified structure of the part. Figure 2 In the Figures 1A to 1C The same reference numerals are used to represent the same elements / components and their repeated descriptions.

[0036] Reference Figure 2 , the integrated circuit device 200 has Figures 1A to 1C The integrated circuit device 100 shown in FIG. 2 may have a similar (or even substantially the same) configuration. However, the transistor TR2 of the integrated circuit device 200 may include an insulating film pattern 120Q between the active region AC and the gate electrode 130. The insulating film pattern 120Q may have the same configuration as the reference 1. Figures 1A to 1C The insulating film pattern 120P described above has a similar (or even substantially the same) configuration. However, in the insulating film pattern 120Q, as shown in FIG. Figure 2 As shown in the area marked by the dotted circle AX2 in FIG. 1 , the step ST2 between the gate insulating portion 120GD and the second extension insulating portion 120E2 may be arranged at a position spaced apart from the gate electrode 130. The step ST2 may be disposed closer to the device isolation film 114 than the interface between the second spacer portion 140B and the gate electrode 130.

[0037] The second spacer portion 140B may overlap (eg, may cover) the step ST2 , and may include a bottom surface 140BS on which a step having a shape corresponding to the step ST2 is formed.

[0038] According to reference Figure 2 The integrated circuit device 200 is similar to the one described in reference Figures 1A to 1C The described integrated circuit device 100 can suppress a hump phenomenon due to an edge channel formed in a boundary region between the active region AC and the device isolation film 114, because the gate electrode 130 does not cross a vertical axis aligned with the boundary between the active region AC and the device isolation film 114 in the vertical direction Z (which is perpendicular to the horizontal directions X and Y). In addition, because the gate electrode 130 does not vertically overlap the device isolation film 114, an area occupied by one transistor TR2 on the substrate 110 is reduced, thereby providing a structure that can be advantageous for device scaling down.

[0039] Figure 3A and 3B is a diagram showing an integrated circuit device according to some embodiments of the present inventive concept, specifically, Figure 3A is a plan layout diagram of the main components of the integrated circuit device 300, Figure 3B is along Figure 3A A cross-sectional view taken along the line Y-Y'. Figure 3A and 3B In the Figures 1A to 1C The same reference numerals are used to represent the same elements / components and their repeated descriptions.

[0040] Reference Figure 3A and 3B , the integrated circuit device 300 has Figures 1A to 1C The integrated circuit device 100 shown in FIG. 1 has a similar (or even substantially the same) configuration. However, in the Y direction (first horizontal direction), the widest / maximum width WG3 of the gate electrode 330 of the transistor TR3 of the integrated circuit device 300 is smaller than the first width WA1 of the active region AC. The gate electrode 330 does not overlap / cover the boundary between the device isolation film 114 and the top surface of the active region AC. Figure 3A In the top view shown, in the Y direction (first horizontal direction), opposite sidewalls of the gate electrode 330 may be spaced apart from a boundary between the device isolation film 114 and the top surface of the active region AC and may be located within the perimeter / range of the active region AC.

[0041] In the active region AC between the pair of source / drain regions 116, the shortest / minimum horizontal distance G3 from the boundary between the top surface of the active region AC and the device isolation film 114 to each of imaginary vertical extension lines (e.g., vertical axes) L31 and L32 extending from the sidewall of the gate electrode 330 toward the substrate 110 may be greater than 0. In some embodiments, the shortest / minimum horizontal distance G3 from the boundary between the top surface of the active region AC and the device isolation film 114 to each of the imaginary vertical extension lines L31 and L32 may be selected from a range greater than about 0 and equal to or less than about 0.3 micrometers (μm).

[0042] The first spacer portion 140A of the insulating spacer 140 between the pair of source / drain regions 116 may overlap (eg, may cover) a boundary between the active region AC and the device isolation film 114 .

[0043] The high-concentration doping region 330D may be formed in an upper portion of the gate electrode 330. More detailed configurations (eg, aspects) of the gate electrode 330 and the high-concentration doping region 330D are similar to those described with reference to FIG. Figures 1A to 1C The configurations described with respect to the gate electrode 130 and the high-concentration doped region 130D are similar (or even substantially the same).

[0044] According to reference Figure 3A and 3BThe described integrated circuit device 300 can suppress a hump phenomenon due to an edge channel formed in a boundary region between the active region AC and the device isolation film 114 because the gate electrode 330 does not cross a vertical axis aligned with the boundary between the active region AC and the device isolation film 114. In addition, since the gate electrode 330 does not vertically overlap the device isolation film 114, an area occupied by one transistor TR3 on the substrate 110 is reduced, thereby providing a structure that can be advantageous for device scaling down.

[0045] Figure 4A and 4B is a diagram showing an integrated circuit device according to some embodiments of the present invention. Specifically, Figure 4A is a plan layout diagram of the main components of the integrated circuit device 400, Figure 4B is along Figure 4A A cross-sectional view taken along the line Y-Y'. Figure 4A and 4B In the Figures 1A to 1C The same reference numerals are used to represent the same elements / components and their repeated descriptions.

[0046] Reference Figure 4A and 4B , the integrated circuit device 400 has Figures 1A to 1C 1. The integrated circuit device 400 may have a similar (or even substantially the same) configuration as the integrated circuit device 100 shown in FIG. However, the transistor TR4 of the integrated circuit device 400 includes a gate electrode 430. In the Y direction (first horizontal direction), at least a portion of the gate electrode 430 may be arranged to vertically overlap only the active region AC without vertically overlapping the device isolation film 114. In the Y direction (first horizontal direction), the widest / maximum width WG4 of the gate electrode 430 may be equal to or less than the first width WA1 of the active region AC.

[0047] In the Y direction (first horizontal direction), one of the opposite ends of the gate electrode 430 may not vertically overlap with the boundary between the device isolation film 114 and the top surface of the active region AC (e.g., may not cover the boundary). In addition, in the Y direction (first horizontal direction), one of the opposite side walls S41 of the gate electrode 430 may be located at a position horizontally spaced apart from the boundary between the device isolation film 114 and the top surface of the active region AC in a direction away from the device isolation film 114. Therefore, in the Y direction (first horizontal direction), one of the side walls S41 of the gate electrode 430 may be located within the perimeter / range of the active region AC in a top view. The other of the opposite ends of the gate electrode 430 may vertically overlap with (e.g., may cover) the boundary between the device isolation film 114 and the top surface of the active region AC. In addition, in the Y direction (first horizontal direction), the other side wall S42 of the opposite side walls of the gate electrode 430 may be located at a position horizontally spaced apart from the boundary between the device isolation film 114 and the top surface of the active region AC in the direction away from the active region AC. Therefore, in the Y direction (first horizontal direction), the other side wall S42 of the gate electrode 430 may be located above the device isolation film 114 outside the perimeter / range of the active region AC in a top view.

[0048] In the integrated circuit device 400, the shortest / minimum horizontal distance G4 from the boundary between the top surface of the active region AC and the device isolation film 114 to the imaginary vertical extension line (e.g., vertical axis) L42 extending from one side wall S41 of the gate electrode 430 toward the substrate 110 may be greater than 0, and the active region AC is between a pair of source / drain regions 116. In some embodiments, the shortest / minimum horizontal distance G4 from the boundary between the top surface of the active region AC and the device isolation film 114 to the imaginary vertical extension line L42 may be selected from a range greater than about 0 and equal to or less than about 0.3 μm. In addition, the vertical axis parallel to the imaginary vertical extension line L42 and extending through the boundary between the top surface of the active region AC and the device isolation film 114 may also extend through the first spacer portion 140A of the insulating spacer 140.

[0049] In the first spacer portion 140A of the insulating spacer 140 between the pair of source / drain regions 116, a portion / region on one sidewall S41 of the gate electrode 430 (e.g., covering one sidewall S41 of the gate electrode 430) may vertically overlap (e.g., may cover) the boundary between the active region AC and the device isolation film 114, and a portion / region on the other sidewall S42 of the gate electrode 430 (e.g., covering the other sidewall S42 of the gate electrode 430) may at least not vertically overlap (e.g., may at least not cover the uppermost portion of the boundary between the active region AC and the device isolation film 114). A portion / region of the first spacer portion 140A on the other sidewall S42 of the gate electrode 430 (e.g., covering the other sidewall S42 of the gate electrode 430) may be arranged above the device isolation film 114 to vertically overlap the device isolation film 114 while not vertically overlapping the top surface of the active region AC.

[0050] The high-concentration doping region 430D may be formed in an upper portion of the gate electrode 430. More detailed configurations (eg, aspects) of the gate electrode 430 and the high-concentration doping region 430D are similar to those described with reference to FIG. Figures 1A to 1C The configurations described with respect to the gate electrode 130 and the high-concentration doped region 130D are similar (or even substantially the same).

[0051] According to reference Figure 4A and 4B The described integrated circuit device 400 can suppress a hump phenomenon due to an edge channel formed in a boundary region between the active region AC and the device isolation film 114, because at least a portion of the gate electrode 430 does not cross a vertical axis aligned with the boundary between the active region AC and the device isolation film 114. In addition, since an area where the gate electrode 430 vertically overlaps the device isolation film 114 can be reduced / minimized, an area occupied by one transistor TR4 on the substrate 110 can be reduced, thereby providing a structure that can be advantageous for device scaling down.

[0052] Figure 5 1 is a plan layout diagram showing an example configuration of an integrated circuit device according to some embodiments of the present inventive concept. Figure 5 In the Figures 1A to 1C The same reference numerals are used to represent the same elements / components and their repeated descriptions.

[0053] Reference Figure 5, the integrated circuit device 500 includes a first active region AC1 and a second active region AC2 defined in a substrate 110. A first transistor TR5A and a second transistor TR5B are formed on the first active region AC1 and the second active region AC2, respectively. Each of the first transistor TR5A and the second transistor TR5B may be a high voltage transistor operating at a high voltage of about 8V to about 200V.

[0054] Each of the first transistor TR5A and the second transistor TR5B may have a Figures 1A to 1C The transistor TR1 is described as having a similar (or even substantially identical) construction.

[0055] The first active region AC1 and the second active region AC2 are defined by a device isolation film 114 formed on the substrate 110 and are spaced apart from each other in the Y direction (first horizontal direction) with an isolation region 114S of the device isolation film 114 therebetween.

[0056] The first active region AC1 and the second active region AC2 may be formed to extend side by side in the X direction (second horizontal direction) crossing (e.g., perpendicular to) the Y direction (first horizontal direction). The width 114W of the isolation region 114S of the device isolation film 114 in the Y direction (first horizontal direction) may be constant (i.e., uniform) between the first active region AC1 and the second active region AC2 along the X direction (second horizontal direction).

[0057] The first gate electrode 530A is formed on the first active region AC1, and the second gate electrode 530B is formed on the second active region AC2. Figures 1A to 1C The first gate electrode 530A may be disposed over the first active region AC1 so as not to vertically overlap with (e.g., not to cover) the boundary between the first active region AC1 and the device isolation film 114. The second gate electrode 530B may be disposed over the second active region AC2 so as not to vertically overlap with (e.g., not to cover) the boundary between the second active region AC2 and the device isolation film 114. Each of the first gate electrode 530A and the second gate electrode 530B may not include a portion vertically overlapping with the isolation region 114S.

[0058] In the Y direction (first horizontal direction), the widest / maximum width WG51 of the first gate electrode 530A and the widest / maximum width WG52 of the second gate electrode 530B may be equal to or smaller than the width WA51 of the first active region AC1 and the width WA52 of the second active region AC2, respectively.

[0059] In the Y direction (first horizontal direction), the shortest / minimum distance between the first gate electrode 530A and the second gate electrode 530B may be equal to or greater than the width 114W of the isolation region 114S of the device isolation film 114 in the Y direction (first horizontal direction).

[0060] The first transistor TR5A may include a first insulating spacer 540A on a sidewall of the first gate electrode 530A (e.g., covering the sidewall of the first gate electrode 530A). The second transistor TR5B may include a second insulating spacer 540B on a sidewall of the second gate electrode 530B (e.g., covering the sidewall of the second gate electrode 530B). Each of the first insulating spacer 540A and the second insulating spacer 540B may have a thickness similar to that of the reference electrode 530A. Figures 1A to 1C The insulating spacers 140 are depicted with similar (or even identical) construction.

[0061] The first insulating spacer 540A may include a portion vertically overlapping (e.g., covering) a boundary between the first active region AC1 and the device isolation film 114, a portion vertically overlapping (e.g., covering) the device isolation film 114, and a portion vertically overlapping (e.g., covering) an impurity diffusion region constituting a pair of source / drain regions 116 of the first transistor TR5A. The second insulating spacer 540B may include a portion vertically overlapping (e.g., covering) a boundary between the second active region AC2 and the device isolation film 114, a portion vertically overlapping (e.g., covering) the device isolation film 114, and a portion vertically overlapping (e.g., covering) an impurity diffusion region constituting a pair of source / drain regions 116 of the second transistor TR5B.

[0062] Similar to reference Figures 1A to 1C The described insulating spacer 140, each of the first insulating spacer 540A and the second insulating spacer 540B may have a vertical length (Z-direction length) above the isolation region 114S of the device isolation film 114 that is different from its vertical length (Z-direction length) above the impurity diffusion region constituting a pair of source / drain regions 116.

[0063] Similar to reference Figures 1A to 1C Each of the transistor TR1, the first transistor TR5A and the second transistor TR5B described above may include an insulating film pattern 120P (see FIG. Figure 1B and 1C ). The thickness of the insulating film pattern 120P above the isolation region 114S of the device isolation film 114 may be different from its thickness above the impurity diffusion region constituting the pair of source / drain regions 116. For example, the thickness of the insulating film pattern 120P above the isolation region 114S of the device isolation film 114 may be greater than its thickness above the impurity diffusion region constituting the pair of source / drain regions 116.

[0064] according to Figure 5 In the integrated circuit device 500 shown, since the first gate electrode 530A and the second gate electrode 530B respectively included in the first transistor TR5A and the second transistor TR5B adjacent to each other do not extend over the isolation region 114S of the device isolation film 114, the separation distance between the first gate electrode 530A and the second active region AC2, and the separation distance between the second gate electrode 530B and the first active region AC1 can be sufficiently ensured. Therefore, the following problems can be effectively suppressed / prevented: such as the adverse effect on the electrical characteristics of the second transistor TR5B due to the leakage current from the first gate electrode 530A, or the adverse effect on the electrical characteristics of the first transistor TR5A due to the leakage current from the second gate electrode 530B.

[0065] Although it has been described that each of the first transistor TR5A and the second transistor TR5B has the same Figures 1A to 1C An example of a structure similar (or even identical) to the transistor TR1 of the integrated circuit device 100 is described to give an example of a structure similar (or even identical) to the transistor TR1 of the integrated circuit device 100 Figure 5 The integrated circuit device 500 is shown in the figure, but the present invention is not limited to Figure 5 For example, Figure 5 Each of the first transistor TR5A and the second transistor TR5B of the integrated circuit device 500 shown may have a Figures 1A to 4B A selected one of the structures of the transistors TR1, TR2, TR3 and TR4 of the integrated circuit devices 100, 200, 300 and 400 shown, and / or structures variously modified and changed therefrom, without departing from the spirit and scope of the inventive concept.

[0066] 6A to 16B 1 is a cross-sectional view illustrating operations (eg, sequential processes) of a method of manufacturing an integrated circuit device according to some embodiments of the present inventive concept. Figures 6A to 16B Among them, Fig. 6A , 7A , 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A and 16A are respectively shown in the process sequence and along Figure 1A The cross-section taken along the line XX' corresponds to a cross-sectional view of the structure. Figure 6B , 7B , 8B, 9B, 10B, 11B, 12B, 13B, 14B, 15B and 16B are respectively shown in the process sequence and along Figure 1A The cross-section taken along the line Y-Y' corresponds to the cross-sectional view of the structure. Figure 7C It is shown Fig. 7A and 7B A top view of the planar structure of some components shown, Fig. 10C It is shown Fig. 10A and 10B The plan view of the planar structure of some components shown. Figures 6A to 16B Description Manufacturing Figures 1A to 1C An exemplary method of the integrated circuit device 100 is shown. Figures 6A to 16B In the Figures 1A to 1C The same reference numerals are used to denote the same elements / components, respectively, and their repeated descriptions are given.

[0067] Reference Fig. 6A and 6B , the substrate 110 is doped with impurity ions to form a well 112 having a first conductivity type. In some embodiments, when the first conductivity type is p-type, boron (B) ions may be implanted into the substrate 110 to form the well 112, but the inventive concept is not limited thereto.

[0068] Next, a trench region T1 is formed in the substrate 110 by partially etching the substrate 110 , and a device isolation film 114 is formed in the trench region T1 (eg, fills the trench region T1 ). An active region AC may be defined in the substrate 110 by the trench region T1 and the device isolation film 114 .

[0069] In some embodiments, in order to form the trench region T1 in the substrate 110, a hard mask pattern may be formed on the substrate 110, and the substrate 110 may be etched by using the hard mask pattern as an etching mask. The hard mask pattern may have a structure in which an oxide film and a nitride film are stacked in the stated order. The device isolation film 114 may include a silicon oxide film. In order to form the device isolation film 114, a chemical vapor deposition (CVD) process may be used.

[0070] Reference Fig. 7A and 7B A mask pattern M1 is formed on the substrate 110, and the mask pattern M1 has a pair of openings MH exposing a portion of the active region AC. Next, by using the mask pattern M1 as an ion implantation mask, impurity ions DP1 of a second conductivity type opposite to the first conductivity type are implanted into a portion of the active region AC exposed by the pair of openings MH, thereby forming a pair of source / drain regions 116 having the second conductivity type in the well 112.

[0071] In some embodiments, the impurity ions DP1 may include phosphorus (P) ions. In the active region AC, a region between the pair of source / drain regions 116 may be a channel region CH.

[0072] Figure 7C is a top view showing the planar structure of the mask pattern M1 in more detail. Figure 7CIn the Fig. 7A and 7B Planar structures of some components shown. For better understanding, portions of the active area AC vertically overlapping with (eg, covered with) the mask pattern M1 are marked by dotted lines.

[0073] Reference Figures 7A to 7C , a pair of openings MH formed in the mask pattern M1 may be spaced apart from each other in the X direction (the second horizontal direction) with the channel region CH of the active region AC therebetween.

[0074] Reference Fig. 8A and 8B , the mask pattern M1 is Fig. 7A and 7B The pair of source / drain regions 116 formed in the resultant product / structure are removed, and then an insulating film 120 overlapping (eg, covering) the active region AC and the device isolation film 114 is formed.

[0075] In some embodiments, the insulating film 120 may include a silicon oxide film. To form the insulating film 120, a CVD process, or a combination of a thermal oxidation process and a CVD process may be used.

[0076] In some embodiments, the thickness TH1 of the insulating film 120 on the channel region CH may be about 400 angstroms. to about In some embodiments, the insulating film 120 may be formed on the substrate 110 to a uniform thickness.

[0077] Reference Fig.9A and 9B , the gate electrode 130 is formed on the insulating film 120 , and the gate electrode 130 vertically overlaps (eg, covers) the channel region CH.

[0078] In the Y direction (first horizontal direction), the widest / maximum width WG1 of the gate electrode 130 may be equal to or smaller than the first width WA1 of the active region AC defined by the device isolation film 114 (see FIG. Figure 1A ). The gate electrode 130 may not include a portion vertically overlapping the device isolation film 114. The gate electrode 130 may be formed to vertically overlap only the active region AC.

[0079] The sidewalls of the gate electrode 130 may include a pair of first sidewalls S1 and S2 and a pair of second sidewalls S3 and S4. The pair of first sidewalls S1 and S2 may be arranged on the interface between the device isolation film 114 and the active region AC at opposite ends of the gate electrode 130 along the Y direction (first horizontal direction). The pair of second sidewalls S3 and S4 may be arranged on the active region AC at opposite ends of the gate electrode 130 along the X direction (second horizontal direction).

[0080] like Fig. 9B As shown, each of imaginary vertical extension lines (e.g., vertical axes) L1 and L2 extending from a pair of first side walls S1 and S2 of the gate electrode 130 toward the substrate 110 may pass through a boundary between the device isolation film 114 and the top surface of the active region AC. That is, each of the pair of first side walls S1 and S2 may be vertically aligned with the boundary between the device isolation film 114 and the top surface of the active region AC.

[0081] In order to form the gate electrode 130, the conductive layer is Fig. 8A and 8B An insulating film 120 is formed on the entire surface of the resultant product / structure therein, and the conductive layer is then patterned by a photolithography process, thereby leaving a gate electrode 130 on the insulating film 120. In some embodiments, the gate electrode 130 may include doped polysilicon.

[0082] Reference Fig. 10A and 10B , a mask pattern M2 is formed, the mask pattern M2 overlapping (eg, covering) the gate electrode 130 , and a portion of the insulating film 120 exposed around the gate electrode 130 .

[0083] Fig. 10C is shown in more detail forming a reference Fig. 10A and 10B A top view of the process of describing the mask pattern M2. Fig. 10C In the Fig. 10A and 10B The planar structure of some components shown. Fig. 10C , for better understanding, a pair of source / drain regions 116 overlapping with (eg, covered with) the insulating film 120, and a gate electrode 130 overlapping with (eg, covered with) the mask pattern M2 are marked by dotted lines.

[0084] Reference Figures 10A to 10C, in the X direction (the second horizontal direction), the width WMX1 of the mask pattern M2 may be substantially equal to the width of the gate electrode 130. In the Y direction (the first horizontal direction), the mask pattern M2 may have a width WMY1 sufficient to overlap (e.g., cover) the top surface of the gate electrode 130, the pair of first side walls S1 and S2 of the gate electrode 130, and the insulating film 120 exposed around the pair of first side walls S1 and S2 / on the top surface of the gate electrode 130, the pair of first side walls S1 and S2 of the gate electrode 130, and the insulating film 120 exposed around the pair of first side walls S1 and S2. In the Y direction (the first horizontal direction), the width WMY1 of the mask pattern M2 may be greater than the width of the gate electrode 130. In the X direction (second horizontal direction), the mask pattern M2, although on the top surface of the gate electrode 130 (e.g., covers the top surface of the gate electrode 130), may not be on the pair of second side walls S3 and S4 of the gate electrode 130 (e.g., may not cover the pair of second side walls S3 and S4 of the gate electrode 130). In some embodiments, the mask pattern M2 may include a photoresist pattern, but is not limited thereto.

[0085] Reference Fig.11A and 11B , by using the mask pattern M2 as an etching mask, the insulating film 120 exposed around the mask pattern M2 is etched up to a predetermined / certain thickness, thereby forming an insulating film pattern 120P in which a portion of the insulating film 120 is reduced in height, and the portion of the insulating film 120 overlaps (e.g., covers) a pair of source / drain regions 116.

[0086] A portion of the insulating film 120 located between the channel region CH of the active region AC and the gate electrode 130 may be retained as a gate insulating portion 120GD, and the gate insulating portion 120GD may be retained. Fig. 8A and 8B The insulating film 120 has an initial thickness TH1 as shown. The portion of the insulating film 120 that vertically overlaps (e.g., covers) the device isolation film 114 adjacent to a pair of first side walls S1 and S2 of the gate electrode 130, that is, the portion of the insulating film 120 that is located on the extension line of the gate electrode 130 along the Y direction (the first horizontal direction) (e.g., protrudes beyond the gate electrode 130 along the Y direction (the first horizontal direction)) can be retained as a first extended insulating portion 120E1, and the first extended insulating portion 120E1 also maintains the initial thickness TH1 of the insulating film 120 similar to the gate insulating portion 120GD. In addition, the portion of the insulating film 120 that vertically overlaps (e.g., covers) a pair of source / drain regions 116 can be retained as a second extended insulating portion 120E2, and the second extended insulating portion 120E2 has a thickness TH2 that is smaller than the initial thickness TH1 of the insulating film 120.

[0087] The gate insulating portion 120GD, the first extension insulating portion 120E1, and the second extension insulating portion 120E2 constituting the insulating film pattern 120P may be integrally connected to each other, and the gate insulating portion 120GD may have a thickness substantially equal to that of the first extension insulating portion 120E1. The thickness of the first extension insulating portion 120E1 may be about 4 times to about 10 times the thickness of the second extension insulating portion 120E2. In some embodiments, the second extension insulating portion 120E2 may have a thickness of about to about For example, the second extension insulating portion 120E2 may have a thickness of about Thickness.

[0088] Reference Fig. 12A and 12B , the mask pattern M2 is Fig.11A and 11B The resulting product / structure is removed, and then an insulating spacer 140 is formed on the sidewall of the gate electrode 130 (eg, covering the sidewall of the gate electrode 130 ).

[0089] like Figure 1A As shown, the insulating spacer 140 may have a rectangular / ring shape surrounding the gate electrode 130. The insulating spacer 140 may include a first spacer portion 140A disposed on the device isolation film 114 and on a pair of first sidewalls S1 and S2 among the sidewalls of the gate electrode 130 (e.g., covering the pair of first sidewalls S1 and S2), and a second spacer portion 140B disposed on the active region AC and on a pair of second sidewalls S3 and S4 among the sidewalls of the gate electrode 130 (e.g., covering the pair of second sidewalls S3 and S4).

[0090] The first spacer portion 140A is integrally connected to the second spacer portion 140B, and a first vertical length HL1 of the first spacer portion 140A is smaller than a second vertical length HL2 of the second spacer portion 140B.

[0091] In some embodiments, an imaginary vertical extension line (eg, vertical axis) L1 extending from an interface between the first spacer portion 140A and the gate electrode 130 toward the substrate 110 may pass through a portion of the top surface of the active region AC contacting the device isolation film 114 .

[0092] Reference Fig.13A and 13B, a mask pattern M3 is formed on the entire surface of the resulting product / structure in which the insulating spacer 140 is formed. The mask pattern M3 may include a first hole MH31 exposing the top surface of the gate electrode 130, and a plurality of second holes MH32 respectively above a pair of source / drain regions 116, the plurality of second holes MH32 exposing the second extended insulating portion 120E2 of the insulating film pattern 120P. In some embodiments, the mask pattern M3 may include a photoresist pattern.

[0093] Next, the second conductive type impurity ions DP2 are implanted into the gate electrode 130 and the pair of source / drain regions 116 at a relatively high concentration through the first hole MH31 and the plurality of second holes MH32. As a result, a high-concentration doped region 130D may be formed in an upper portion of the gate electrode 130, and a high-concentration doped region 116H may be formed in an upper portion of each of the pair of source / drain regions 116. The impurity concentration in the high-concentration doped region 116H may be greater than the impurity concentration in other regions of each of the pair of source / drain regions 116. In some embodiments, the impurity ions DP2 implanted into the gate electrode 130 and the pair of source / drain regions 116 may include phosphorus (P) ions.

[0094] Although the impurity ions DP2 are injected into the gate electrode 130 through the first hole MH31, since the first extended insulating portion 120E1 having a relatively larger thickness than the second extended insulating portion 120E2, and the first spacer portion 140A of the insulating spacer 140 are on the interface between the active region AC and the device isolation film 114 and its periphery (e.g., covering the interface and its periphery) in the stated order, the first extended insulating portion 120E1 and the first spacer portion 140A serve as a blocking film that blocks / prevents impurities from diffusing into the substrate 110, thereby making it possible to block / prevent impurity ions from undesirably diffusing into the active region AC. Therefore, since it is possible to block / prevent an undesirable impurity diffusion region from being formed at the edge of a portion of the active region AC between a pair of source / drain regions 116, which edge is adjacent to the device isolation film 114, it is possible to suppress / prevent problems such as a short circuit of the pair of source / drain regions 116 via the edge of the active region AC.

[0095] In addition, although the impurity ions DP2 are injected into a pair of source / drain regions 116 through the plurality of second holes MH32, the second extended insulating portion 120E2 on the pair of source / drain regions 116 (e.g., covering the pair of source / drain regions 116) can protect the substrate 110, thereby suppressing / preventing damage to the surface of the substrate 110.

[0096] Reference Fig.14A and 14B , the mask pattern M3 is Fig.13Aand 13B The resultant product / structure is removed, and then a mask pattern M4 is formed over the substrate 110. The mask pattern M4 may include a first hole MH41 exposing a portion of the top surface of the gate electrode 130, a plurality of second holes MH42 over a pair of source / drain regions 116, and the plurality of second holes MH42 expose the second extended insulating portion 120E2 of the insulating film pattern 120P. In some embodiments, the mask pattern M4 may include an oxide film, a nitride film, or a combination thereof.

[0097] Next, by using the mask pattern M4 as an etching mask, the portion of the second extension insulating portion 120E2 of the insulating film pattern 120P exposed by the plurality of second holes MH42 is removed, thereby exposing the high-concentration doped region 116H through the plurality of second holes MH42. As a result, an opening 120H exposing the high-concentration doped region 116H on each of the pair of source / drain regions 116 may be formed in the second extension insulating portion 120E2 of the insulating film pattern 120P.

[0098] Reference Fig.15A and 15B Through the silicide / self-aligned silicide process, a first metal silicide film 152 is formed on the top surface of the gate electrode 130 exposed by the first hole MH41 of the mask pattern M4, and a second metal silicide film 154 is formed on the top surface of the high-concentration doped region 116H exposed by the multiple second holes MH42 of the mask pattern M4.

[0099] In some embodiments, each of the first metal silicide film 152 and the second metal silicide film 154 may include titanium (Ti) silicide, cobalt (Co) silicide, or nickel (Ni) silicide, but is not limited thereto.

[0100] During the silicide / self-aligned silicide process for forming the first metal silicide film 152 and the second metal silicide film 154, since the first extended insulating portion 120E1 having a relatively greater thickness than the second extended insulating portion 120E2, and the first spacer portion 140A of the insulating spacer 140 overlap (e.g., cover) the interface between the active region AC and the device isolation film 114 and its surroundings in the stated order, the first extended insulating portion 120E1 and the first spacer portion 140A may be used as a barrier film to block / prevent the atmospheric gas of the silicide / self-aligned silicide process from penetrating into the active region AC. Therefore, the metal silicide film may be suppressed / prevented from being formed on an undesired portion of the active region AC. For example, the boundary between the uppermost surface of the active region AC and the device isolation film 114 may not contain metal silicide because the boundary may be protected by the first extended insulating portion 120E1 and the first spacer portion 140A. Therefore, since an undesirable metal silicide film can be suppressed / prevented from being formed at an edge of a portion of the active region AC adjacent to the device isolation film 114, problems such as short circuiting of a pair of source / drain regions 116 via the edge of the active region AC can be suppressed / prevented.

[0101] Reference Fig.16A and 16B , by Fig.15A and 15B The mask pattern M4 is removed from the resulting product / structure, the first extension insulating portion 120E1 and the second extension insulating portion 120E2 of the insulating film pattern 120P, the gate electrode 130, the first metal silicide film 152, and the second metal silicide film 154 are exposed, and then an interlayer dielectric 160 located on the above components (e.g., covering the above components) is formed. The interlayer dielectric 160 may include an oxide film, a nitride film, or a combination thereof.

[0102] Next, a plurality of contact holes 160H are formed through the interlayer dielectric 160 to expose the first metal silicide film 152 and the second metal silicide film 154, and then the plurality of contact holes 160H are partially or completely filled with a conductive material to form a gate contact plug 172 and a plurality of source / drain contact plugs 174. In some embodiments, each of the gate contact plug 172 and the plurality of source / drain contact plugs 174 may include a stacked structure including a conductive barrier film and a metal plug. The conductive barrier film may include Ti, TiN, or a combination thereof, and the metal plug may include tungsten (W), but is not limited thereto.

[0103] So far, although we have referred to Figures 6A to 16B Describes the manufacturing Figures 1A to 1C The method of the integrated circuit device 100 shown in FIG. 1 may be fabricated based on references without departing from the spirit and scope of the present invention. Figures 6A to 16B Integrated circuit devices having various structures modified and changed as described above.

[0104] Fig.17A and 17B It shows the manufacturing Figure 2 FIG. 2 is a diagram of an example method of an integrated circuit device 200 shown in FIG. Fig.17A is a cross-sectional view showing some processes of manufacturing an integrated circuit device 200, Fig. 17B It is shown Fig.17A A top view of the planar structure of some of the components shown. Fig. 17B In FIG. 1 , for better understanding, a pair of source / drain regions 116 and a gate electrode 130 are marked by dotted lines.

[0105] Reference Fig.17A and 17B , in order to manufacture Figure 2 The integrated circuit device 200 shown can be used with reference to Figures 6A to 16B However, instead of having reference Figures 10A to 10C The mask pattern M2 having the described structure may form a mask pattern M21.

[0106] In the X direction (the second horizontal direction), the mask pattern M21 may have a width WMX2 greater than a width of the gate electrode 130. In the X direction (the second horizontal direction), the mask pattern M21 may be formed on opposite sidewalls of the gate electrode 130 (e.g., formed to cover the opposite sidewalls of the gate electrode 130). The mask pattern M21 may include a photoresist pattern, but is not limited thereto.

[0107] After the mask pattern M21 is formed, the mask pattern M21 is used as an etching mask to Fig.11A and 11B In a similar manner to that described above, the insulating film 120 (see FIG. 1 ) is exposed around the mask pattern M21. Fig. 10A and 10B ) may be etched up to a certain / predetermined thickness, thereby forming a height insulating film pattern 120Q in which a portion of the insulating film 120 is reduced, the portion overlapping (eg, covering) a pair of source / drain regions 116.

[0108] Then, the mask pattern M21 may be removed, and then the reference Figures 12A to 16B Described process, thereby manufacturing Figure 2 An integrated circuit device 200 is shown.

[0109] To manufacture Figure 3A and 3B The integrated circuit device 300 shown can be used with reference to Figures 6A to 16BThe method described is similar to the method described in Ref. Fig.9A and 9B In the process described above, instead of the gate electrode 130, a Figure 3A and 3B The gate electrode 330 is shown. Next, the reference Figures 10A to 16B Described process, thereby manufacturing Figure 3A and 3B An integrated circuit device 300 is shown.

[0110] To manufacture Figure 4A and 4B The integrated circuit device 400 shown can be used with reference to Figures 6A to 16B The method described is similar to the method described in Ref. Fig.9A and 9B In the process described above, instead of the gate electrode 130, a Figure 4A and 4B The gate electrode 430 is shown. Next, the reference Figures 10A to 16B Described process, thereby manufacturing Figure 4A and 4B An integrated circuit device 400 is shown.

[0111] To manufacture Figure 5 In the integrated circuit device 500 shown in FIG. 1 , the first transistor TR5A and the second transistor TR5B adjacent to each other can be connected to the reference Figures 6A to 16B The method described above is similar to that of forming on the substrate 110 .

[0112] Fig.18 is a schematic block diagram of a display device 1000 according to some embodiments of the inventive concept.

[0113] Reference Fig.18 , the display device 1000 includes a display driver integrated circuit (DDI) 1100 .

[0114] The DDI 1100 may include a controller 1110, a power supply circuit 1120, a driver block (e.g., driver device(s)) 1130, and a storage block (e.g., storage device(s)) 1140. The controller 1110 may receive and decode a command applied from a main processing unit (MPU) 1200, and may control each block of the DDI 1100 to implement an operation according to the command. The power supply circuit 1120 may generate a driving voltage in response to the control of the controller 1110. In response to the control of the controller 1110, the driver block 1130 may drive the display panel 1300 by using the driving voltage generated by the power supply circuit 1120. The display panel 1300 may be a liquid crystal display panel or a plasma display panel. The storage block 1140 may temporarily store a command input to the controller 1110, or a control signal output from the controller 1110, or may store required data. The storage block 1140 may include a memory such as a random access memory (RAM) or a read-only memory (ROM). The power supply circuit 1120 and the driver block 1130 may each include a reference Figures 1A to 5 One of the integrated circuit devices 100, 200, 300, 400, and 500 described, each of the integrated circuit devices 100, 200, 300, 400, and 500 includes a high voltage transistor. The controller 1110 and the storage block 1140 may each include a low voltage transistor that operates at a lower voltage than the high voltage transistor of each of the integrated circuit devices 100, 200, 300, 400, and 500.

[0115] Although the exemplary embodiments of the inventive concept have been described in detail, the inventive concept is not limited to the exemplary embodiments herein and may be modified and altered in various ways by a person of ordinary skill in the art without departing from the spirit and scope of the inventive concept. For example, although the exemplary embodiments of the inventive concept have been described by taking a high voltage transistor as an example, the inventive concept may be applied to a low voltage transistor.

[0116] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

[0117] This application claims the benefit of Korean Patent Application No. 10-2018-0000899 filed on January 3, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. An integrated circuit device comprising: substrate; a device isolation film on the substrate, wherein an active area of ​​the substrate is defined by the device isolation film on the substrate and comprises a first width in a horizontal direction; a pair of source / drain regions in the active region; a gate electrode over a portion of the active region between the pair of source / drain regions, the gate electrode comprising a second width in the horizontal direction, the second width being smaller than the first width of the active region; an insulating spacer, comprising a first spacer portion on the device isolation film and a second spacer portion on the active region, wherein the first spacer portion and the second spacer portion are respectively on a first sidewall and a second sidewall of the gate electrode; as well as an insulating film including a gate insulating portion between the active region and the gate electrode, wherein the first side wall of the gate electrode includes one of a pair of first side walls at opposite ends of the gate electrode in the horizontal direction, and wherein a pair of vertical axes respectively aligned vertically with the pair of first side walls intersects a boundary region between the device isolation film and a top surface of the active region, wherein a first vertical length of the first spacer portion is less than a second vertical length of the second spacer portion, The insulating film further comprises: a first extending insulating portion integrally connected to the gate insulating portion and interposed between the first spacer portion and the device isolation film in a vertical direction; as well as a second extending insulating portion integrally connected to the gate insulating portion and interposed between the second spacer portion and the active region in the vertical direction, and The thickness of the first extending insulating portion in the vertical direction is greater than the thickness of the second extending insulating portion in the vertical direction.

2. The integrated circuit device according to claim 1, The first side wall and the second side wall of the gate electrode are perpendicular to each other.

3. The integrated circuit device according to claim 1, Wherein the first spacer portion is integrally connected to the second spacer portion. 4 . The integrated circuit device according to claim 1 , wherein the insulating film further includes a stepped portion including a transition portion between the gate insulating portion and the second extension insulating portion.

5. The integrated circuit device according to claim 1, further comprising: an interlayer dielectric on the paired source / drain regions and the second extended insulating portion; as well as A plurality of conductive contact plugs penetrate the interlayer dielectric and are electrically connected to the pairs of source / drain regions.

6. An integrated circuit device comprising: a substrate including a trench region defining an active area of ​​the substrate, the active area comprising a first width in a first horizontal direction; a device isolation film in the trench region; a gate electrode above the active region, the gate electrode comprising a second width in the first horizontal direction, the second width being smaller than the first width of the active region; an insulating spacer, above the active region and the device isolation film, wherein the insulating spacer is on a sidewall of the gate electrode; a pair of source / drain regions in the active region, the pair of source / drain regions being spaced apart from each other, wherein the gate electrode overlaps a portion of the active region between the pair of source / drain regions; as well as an insulating film on the active region and the device isolation film, the insulating film including a gate insulating portion between the active region and the gate electrode, wherein a vertical axis extending through a boundary between an uppermost surface of the active region and the device isolation film in a vertical direction perpendicular to the first horizontal direction extends through the insulating spacer, wherein a vertical length of a first portion of the insulating spacer above the device isolation film is smaller than a vertical length of a second portion of the insulating spacer above one of the paired source / drain regions, The insulating film further comprises: a first extending insulating portion integrally connected to the gate insulating portion and on the device isolation film; as well as a second extending insulating portion integrally connected to the gate insulating portion and on the paired source / drain regions, The thickness of the first extending insulating portion in the vertical direction is greater than the thickness of the second extending insulating portion in the vertical direction.

7. The integrated circuit device according to claim 6, The sidewall of the gate electrode comprises: a pair of first side walls at opposite ends of the gate electrode along the first horizontal direction; as well as a pair of second side walls at opposite ends of the gate electrode along a second horizontal direction crossing the first horizontal direction, and Each of the pair of first sidewalls and each of the pair of second sidewalls overlap the uppermost surface of the active region.

8. The integrated circuit device according to claim 6, the second extended insulating portion includes a plurality of openings over corresponding regions of the pair of source / drain regions, wherein the integrated circuit device further comprises metal silicide on the corresponding regions of the pair of source / drain regions, The boundary between the uppermost surface of the active region and the device isolation film does not contain metal silicide.

9. The integrated circuit device according to claim 6, The sidewall of the gate electrode comprises: a pair of first side walls at opposite ends of the gate electrode along the first horizontal direction; as well as a pair of second side walls at opposite ends of the gate electrode along a second horizontal direction crossing the first horizontal direction, wherein the insulating spacer is on each of the pair of first side walls and on each of the pair of second side walls, and The device isolation film continuously extends around the insulating spacer.

10. An integrated circuit device comprising: a substrate including a first active region and a second active region adjacent to and spaced apart from each other in a first horizontal direction; a device isolation region between the first active region and the second active region; a plurality of first impurity diffusion regions in the first active region; a plurality of second impurity diffusion regions in the second active region; a first gate electrode over the first active region, the first gate electrode comprising a width in the first horizontal direction that is less than a width of the first active region; a first insulating spacer on a sidewall of the first gate electrode and on the device isolation region; a first insulating film including a first gate insulating portion between the first active region and the first gate electrode; a second gate electrode over the second active region, the second gate electrode comprising a width in the first horizontal direction that is less than a width of the second active region; as well as a second insulating spacer on a sidewall of the second gate electrode and on the device isolation region, wherein a separation distance between the first active region and the second active region in the first horizontal direction is constant along a second horizontal direction perpendicular to the first horizontal direction, and wherein a distance between the first gate electrode and the second gate electrode in the first horizontal direction is greater than the separation distance, and wherein a first portion of the first insulating spacer and a second portion of the second insulating spacer overlap a top surface of the device isolation region, wherein a first vertical length of a portion of the first insulating spacer and the second insulating spacer above the device isolation region is smaller than a second vertical length of other portions of the first insulating spacer and the second insulating spacer above the plurality of first impurity diffusion regions and the plurality of second impurity diffusion regions, The first insulating film further comprises: a first extending insulating portion integrally connected to the first gate insulating portion and on the device isolation region; as well as a second extension insulating portion integrally connected to the first gate insulating portion and on the plurality of first impurity diffusion regions, The thickness of the first extending insulating portion in a vertical direction perpendicular to the first horizontal direction and the second horizontal direction is greater than the thickness of the second extending insulating portion in the vertical direction.

11. The integrated circuit device according to claim 10, further comprising: a second insulating film including a second gate insulating portion between the second active region and the second gate electrode, The second insulating film further comprises: a third extending insulating portion integrally connected to the second gate insulating portion and on the device isolation region; and a fourth extension insulating portion integrally connected to the second gate insulating portion and on the plurality of second impurity diffusion regions, The thickness of the third extending insulating portion in the vertical direction is greater than the thickness of the fourth extending insulating portion in the vertical direction.

12. The integrated circuit device according to claim 10, wherein a first vertical axis extending in the vertical direction through a boundary between the first active region and the device isolation region extends through the first insulating spacer, wherein the sidewall of the first gate electrode includes four sidewalls, wherein the first insulating spacer is on each of the four sidewalls of the first gate electrode, and A second vertical axis extending through a boundary between the second active region and the device isolation region in the vertical direction extends through the second insulating spacer.

13. The integrated circuit device according to claim 10, The device isolation region continuously extends around the first insulating spacer and the second insulating spacer.

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