Circuit and method for digital-to-analog conversion using three-level unit

Abstract

The present invention provides a circuit and method for digital-to-analog conversion using a plurality of three-level cells, wherein the plurality of three-level cells independently provide positive electricity, negative electricity or floating. The circuit includes a preprocessing circuit and a shift circuit. The preprocessing circuit is configured to receive thermometer code data generated from signed binary data, and to generate a shift count for shifting a cell pointer pointing to one of the three-level cells in the plurality of three-level cells from the thermometer code data to perform dynamic element matching (DEM). The shift circuit is configured to store the cell pointer and shift the stored cell pointer according to the shift count. The shifted cell pointer is shifted in a direction depending on the sign of the binary data in proportion to the absolute value of the binary data.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0007892 filed on January 22, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The present disclosure relates to digital-to-analog conversion, and more particularly, to circuits and methods for digital-to-analog conversion using three-level cells. Background Art

[0004] A digital-to-analog converter (DAC) can be used in a variety of applications. A DAC can include multiple cells having the same structure, and can generate analog output signals based on signals output by these cells in response to a digital input signal. For example, a DAC can include a two-stage or dual-stage cell that can provide two or more different outputs in response to a control signal, or can include a multi-stage cell that can provide three or more different outputs in response to a control signal. Although a DAC including a multi-stage cell has many advantages over a two-stage or dual-stage cell, due to the characteristics of a cell that provides three or more different outputs, it may be necessary to compensate for nonlinearities within the cell. Summary of the invention

[0005] The present disclosure relates to digital-to-analog conversion and provides a circuit and method for performing digital-to-analog conversion using a three-level cell.

[0006] According to one aspect of the present disclosure, a circuit for digital-to-analog conversion using a plurality of three-level cells is provided, wherein the plurality of three-level cells independently provide positive electricity, negative electricity or floating. The circuit includes: (a) a preprocessing circuit configured to receive thermometer code data generated from signed binary data, and to generate a shift count for shifting a cell pointer pointing to one of the three-level cells from the thermometer code data for dynamic element matching (DEM); and (b) a shift circuit configured to store the cell pointer and shift the stored cell pointer according to the shift count. The shifted cell pointer is shifted in a direction depending on the sign of the binary data and in proportion to the absolute value of the binary data.

[0007] According to another aspect of the present disclosure, there is provided a circuit for performing digital-to-analog conversion using m three-level cells, the m three-level cells independently providing positive power, negative power or floating, wherein m is an integer greater than 1. The circuit comprises: (a) a preprocessing circuit, the preprocessing circuit comprising a first logic circuit, the first logic circuit outputting a shift count for shifting a cell pointer pointing to one of the m three-level cells by performing a bitwise operation on 2m-bit thermometer code data generated from signed binary data, so as to perform dynamic element matching (DEM); and (b) a shifting circuit, the shifting circuit comprising a latch and a first shifter, the latch storing the cell pointer, the first shifter being configured to shift the cell pointer stored in the latch according to the shift count. The output of the first shifter is consistent with the cell pointer stored in the latch shifted in a direction depending on the sign of the signed binary data in proportion to the absolute value of the signed binary data.

[0008] According to another aspect of the present disclosure, there is provided a method for performing digital-to-analog conversion using a plurality of three-level cells, wherein the plurality of three-level cells independently provide positive electricity, negative electricity, or floating. The method comprises: (a) receiving thermometer code data generated from signed binary data; (b) generating a shift count for shifting a cell pointer pointing to one of the plurality of three-level cells from the thermometer code data for dynamic element matching (DEM); and (c) shifting the cell pointer according to the shift count and storing the cell pointer. The shifted cell pointer is shifted in a direction depending on the sign of the binary data in proportion to the absolute value of the binary data.

[0009] According to another aspect of the present disclosure, a digital-to-analog converter having an analog generator circuit and a dynamic element matching circuit is provided. The analog generator circuit includes m voltage generator circuits, a differential amplifier, an integrator circuit, and a single-ended output amplifier, wherein m is an integer greater than 1. The dynamic element matching circuit: (a) generates an m-bit signed binary code representing a signed digital value, and (b) for each bit of the m-bit signed binary code and based on the absolute value and sign of the signed digital value, selects a voltage generator circuit from the m voltage generator circuits that generates both a first signal applied to a first input terminal of the differential amplifier and a second signal applied to a second input terminal of the differential amplifier. The differential amplifier amplifies the voltage difference between the first signal applied to the first input terminal and the second signal applied to the second input terminal for each bit of the m-bit signed binary code to generate an amplified differential output. The integrator circuit integrates the amplified differential output for each bit of the m-bit signed binary code to generate an integrated differential signal. The single-ended output amplifier converts the integrated differential signal into a single-ended analog signal having a voltage value representing the signed digital value among 2m+1 voltage values. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a block diagram illustrating a digital-to-analog converter (DAC) according to an example embodiment of the present disclosure;

[0012] Figure 2 is a diagram showing an exemplary embodiment according to the present disclosure Figure 1 A circuit diagram of an example of an analog generator;

[0013] FIG. 3A to FIG. 3C is a diagram of a related art showing a comparative example of controlling four units according to a given input sequence;

[0014] Figure 4A and Figure 4B It shows FIG. 3A to FIG. 3C A graph of the performance of a comparative example of the related art;

[0015] Figure 5 is a diagram showing an example of controlling four units according to a given input sequence according to an example embodiment of the present disclosure;

[0016] Fig. 6A and Figure 6B is a graph illustrating the performance of dynamic element matching (DEM) according to an example embodiment of the present disclosure;

[0017] Figure 7 is a diagram showing an exemplary embodiment according to the present disclosure Figure 1 data and Figure 2 A table of examples of control signals;

[0018] Fig. 8A and Figure 8B is a diagram showing an exemplary embodiment according to the present disclosure Figure 1 A diagram of an example of a preprocessing circuit;

[0019] Fig. 9 is a diagram showing an exemplary embodiment according to the present disclosure Figure 1 A block diagram of an example of a shift circuit;

[0020] Fig.10 is a flow chart illustrating a method of performing digital-to-analog conversion using a three-level unit according to an example embodiment of the present disclosure;

[0021] Fig.11 is a diagram showing an exemplary embodiment according to the present disclosure Fig.10 A flowchart of an example of operation S60; and

[0022] Fig.12 is a block diagram illustrating an analog-to-digital converter including a DAC according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] Figure 1 1 is a block diagram showing a digital-to-analog converter (DAC) 10 according to an exemplary embodiment of the present disclosure. The DAC 10, which is a delta-sigma DAC, can output an output signal OUT as an analog signal by converting an input signal IN as a digital signal. Figure 1 As shown, the DAC 10 may include a delta-sigma modulator 200 , a thermometer encoder 400 , a dynamic element matching (DEM) block 600 , and an analog generator 800 .

[0024] The delta-sigma modulator 200 may be referred to as an oversampling delta-sigma modulator, and may generate binary data (or binary code) BIN by oversampling the input signal IN. In some embodiments, the delta-sigma modulator 200 may interpolate the oversampled signal. The delta-sigma modulator 200 may provide the binary data BIN to the thermometer encoder 400. In some embodiments, the binary data BIN may be signed data.

[0025] The thermometer encoder 400 may convert the binary data BIN received from the delta-sigma modulator 200 into thermometer code data T_CD. The thermometer code data T_CD may have k bits (where k is an integer greater than or equal to 1) and may be represented as consecutive bits with "0" and / or consecutive bits with "1". The thermometer code data T_CD may be referred to as unary code data, and in some embodiments, as Figure 7 As shown, the number of “1” included in the thermometer code data T_CD may be proportional to the binary data BIN. The thermometer encoder 400 may provide the thermometer code data T_CD to the DEM block 600.

[0026] The DEM block 600 may generate the cell control data C_CT from the thermometer code data T_CD received from the thermometer encoder 400. The DEM block 600 may perform the DEM as an operation to compensate for the nonlinearity of the DAC 10 (i.e., the nonlinearity of the m cells C1, C2, . . . and Cm included in the analog generator 800 (where m is an integer greater than or equal to 1)). FIG. 3A to FIG. 3C As described, as an example of DEM, a data weighted average (DWA) may be adopted, in which a plurality of cells contributing to the analog output are uniformly selected to calculate the average value of the errors occurring in the cells. A two-level or dual-level cell in response to a control signal having two different states generates two outputs corresponding to two levels and thus has linearity, and therefore may only need to improve the nonlinearity between cells. On the other hand, a multi-level cell in response to a control signal having more than three different states may have nonlinearity within the cell, and therefore, not only may it be necessary to improve the nonlinearity between cells, but also may need to improve the nonlinearity within the cell. Compared with a DAC including a two-level or dual-level cell, a DAC 10 including a three-level cell may include a smaller number of cells, and therefore, may have a reduced area and power consumption. In addition, in a DAC 10 including a three-level cell, the three-level cell provides floating according to an input 0, and therefore, the influence of noise that may be generated in the cell may be reduced. Similarly, although the DAC 10 including a three-level cell has various advantages, as described above, it may be necessary to improve the nonlinearity between cells.

[0027] As described below, according to an exemplary embodiment of the present disclosure, the DEM block 600 can provide improved linearity and can have a simple structure. Due to the simple structure of the DEM block 600, the power consumption and area of ​​the DAC 10 can be reduced, and thus the practicality of the DAC 10 can be increased. Although it will be assumed hereinafter that each of the m units C1, C2, ... and Cm is a three-level unit, the exemplary embodiments of the present disclosure are not limited thereto.

[0028] The DEM block 600 may manage a cell pointer pointing to one of the m cells C1, C2, ... and Cm of the analog generator 800. The DEM block 600 may generate cell control data C_CT to select the cell pointed to by the cell pointer, and may shift the cell pointer based on the thermometer code data T_CD. The cell control data C_CT may include information about an output provided by each of the m cells C1, C2, ... and Cm. In the present specification, the cell control data C_CT will be described as including m values, each value having one of "-1", "0" and "+1" for the m cells C1, C2, ... and Cm as three-level cells. In some embodiments, the cell control data C_CT may include a control signal directly applied to the m cells C1, C2, ... and Cm, or control data applied to the m cells C1, C2, ... and Cm may be generated from the cell control data C_CT in the analog generator 800. As Figure 1 As shown, the DEM block 600 may include a pre-processing circuit 620 and a shift circuit 640 .

[0029] The preprocessing circuit 620 may generate a shift count CNT and a cell code data C_CD from the thermometer code data T_CD received from the thermometer encoder 400. The shift count CNT may be used to shift the cell pointer in the shift circuit 640. In some embodiments, the shift circuit 640 may unidirectionally shift the cell pointer cyclically or circularly, and the shift count CNT may correspond to the shift amount of the cell pointer. In addition, as described below with reference to Fig. 8A and Figure 8B As described, the shift count CNT may have m bits, and in a similar manner to the thermometer code, the shift count CNT may have as many "1"s as the number corresponding to the shift amount.

[0030] The preprocessing circuit 620 may generate a shift count CNT so that the cell pointer is shifted in a direction that depends on the sign of the binary data BIN in proportion to the absolute value of the binary data BIN. In some embodiments, when the binary data BIN is a positive number, the cell pointer may be shifted to the right, i.e., toward the least significant bit (LSB), and when the binary data BIN is a negative number, the cell pointer may be shifted to the left, i.e., toward the most significant bit (MSB). In some embodiments, when the binary data BIN is a positive number, the cell pointer may be shifted to the left, i.e., toward the MSB, and when the binary data BIN is a negative number, the cell pointer may be shifted to the right, i.e., toward the LSB. As described below with reference to Fig. 6A and Figure 6BAs described above, when the shift direction is changed according to the sign of the binary data BIN, better nonlinear improvement characteristics can be obtained, and using only one unit pointer can enable a simpler structure to be implemented. Figure 5 etc. describe an example of the operation of the pre-processing circuit 620 to generate the shift count CNT.

[0031] The preprocessing circuit 620 may generate the unit code data C_CD from the thermometer code data T_CD. In some embodiments, the preprocessing circuit 620 may generate the m-bit unit code data C_CD from the 2m-bit thermometer code data T_CD (i.e., k=2m). The unit code data C_CD may correspond to the unit control data C_CT, and the unit control data C_CT may be generated by shifting the unit code data C_CD based on the unit pointing. In some embodiments, the unit control data C_CT may correspond to the thermometer code data T_CD one-to-one. That is, although one value of the 2m-bit thermometer code data T_CD may correspond to multiple values ​​of the m-bit unit code data C_CD, the preprocessing circuit 620 may allow one value of the thermometer code data T_CD to correspond to one value among the multiple values ​​of the unit code data C_CD. In this specification, in a similar manner to the unit control data C_CT, the unit code data C_CD will be described as including m values, each value having one of "-1", "0" and "+1".

[0032] The shift circuit 640 may receive a shift count CNT and a cell code data C_CD from the preprocessing circuit 620, and may generate cell control data C_CT. The shift circuit 640 may store a cell pointer to be used to generate the cell control data C_CT, and may shift the stored cell pointer according to the shift count CNT. In some embodiments, the shift circuit 640 may bidirectionally cyclically or annularly shift the cell pointer according to the shift count CNT. As a result, the cell pointer may be shifted in different directions according to the sign of the binary data BIN. The shift circuit 640 may generate the cell control data C_CT by shifting the cell code data C_CD according to the stored cell pointer, and may shift the cell pointer used in the shift according to the shift count CNT and store the shifted cell pointer. Fig. 9 An example of the shift circuit 640 is described.

[0033] The analog generator 800 may receive the cell control data C_CT from the DEM block 600 and may generate an output signal OUT. Figure 1 As shown, the analog generator 800 may include m units C1, C2, . . . and Cm and an adder 820.

[0034] The m cells C1, C2, ..., Cm may have the same structure and may be operated independently of each other according to a control signal. Each of the m cells C1, C2, ..., Cm as a three-level cell may provide one of positive power, negative power, and floating (or non-output) as an output in response to a control signal. Figure 2 As described, each of the m cells C1, C2, ..., Cm can be designed so that the magnitude of the positive and negative electricity to be provided is consistent. In this specification, each of the m cells C1, C2, ..., Cm will be described as providing negative electricity when the corresponding value of the cell control data C_CT including m values ​​is "-1", providing floating when the corresponding value is "0", and providing positive electricity when the corresponding value is "+1".

[0035] The adder 820 can generate an output signal OUT by summing the outputs of the m units C1, C2, ..., Cm. Therefore, the output signal OUT can have "2m+1" different magnitudes from a magnitude corresponding to the m units C1, C2, ..., Cm all providing positive electricity to a magnitude corresponding to the m units C1, C2, ..., Cm all providing negative electricity. Figure 2 An example of the simulation generator 800 is described.

[0036] Figure 2 is a diagram showing an exemplary embodiment according to the present disclosure Figure 1 The circuit diagram of an example of the analog generator 800 is shown in FIG. Figure 1 As described, Figure 2 The analog generator 800' may receive the unit control data C_CT from the DEM block 600 and may generate the output signal OUT as an analog signal according to the unit control data C_CT. Figure 2 As shown, the analog generator 800' may include m units C1', C2', ... and Cm' and an adder 820'. Figure 1 describe Figure 2 .

[0037] The control signal may be generated from the cell control data C_CT including m values ​​(each value having "-1", "0" or "+1"). For example, the m-bit first control signal P may determine whether each of the m cells C1', C2', ... and Cm' provides positive electricity to the adder 820', the second control signal N may determine whether each of the m cells C1', C2', ... and Cm' provides negative electricity to the adder 820', and the third control signal Z may determine whether each of the m cells C1', C2', ... and Cm' provides floating to the adder 820'. The two bits corresponding to each other of the first control signal P and the second control signal N cannot have a value of "1" at the same time, and when the corresponding bits of the first control signal P and the second control signal N are both "0", the third control signal Z may have a value of "1". In this specification, a cell corresponding to "+1" or "-1" may be referred to as a selected cell. In some embodiments, the unit control data C_CT may include at least one of the first control signal P, the second control signal N, and the third control signal Z, and when the unit control data C_CT includes two or less of the first control signal P, the second control signal N, and the third control signal Z, the remaining (one or more) control signals not included may be generated from the control signal received from the analog generator 800'.

[0038] Each of the m units C1', C2', ... and Cm' may include two current sources and six switches. For example, the first unit C1' may include a first current source CS1, a second current source CS2, and three pairs of switches, the first current source CS1 supplies current Ix from a positive power supply voltage VCC, the second current source CS2 draws the current Ix to a ground voltage (or a negative power supply voltage), and each pair of switches includes two switches connected in series between the first current source CS1 and the second current source CS2. Each of the six switches may be electrically connected at both ends thereof according to a control signal having "1". For example, when the first bit P[1] of the first control signal P in the first unit C1' is "1", the current Ix may be provided to a node connected to a non-inverting input terminal of the first amplifier 822 included in the adder 820' by the first current source CS1, and the current Ix may be drawn from a node connected to an inverting input terminal of the first amplifier 822 by the second current source CS2. When the first bit N[1] of the second control signal N in the first cell C1' is "1", the current Ix may be provided to the node connected to the inverting input terminal of the first amplifier 822 through the first current source CS1, and the current Ix may be drawn from the node connected to the non-inverting input terminal of the first amplifier 822 through the second current source CS2. When the first bit Z[1] of the third control signal Z is "1", the current Ix may flow from the positive power supply voltage VCC to the ground voltage due to the first current source CS1 and the second current source CS2. Figure 2 As shown, a specific voltage VCM may be applied to the nodes to which the two switches controlled by the first bit Z[1] of the third control signal Z are connected. The second cell C2' operates with respect to the second bit P[2] of the first control signal P, the second bit N[2] of the second control signal N, and the second bit Z[2] of the third control signal Z in a manner similar to how the first cell C1' operates with respect to the first bit P[1] of the first control signal P, the first bit N[1] of the second control signal N, and the first bit Z[1] of the third control signal Z. In addition, the mth cell Cm' operates with respect to the mth bit P[m] of the first control signal P, the mth bit N[m] of the second control signal N, and the mth bit Z[m] of the third control signal Z in a manner similar to how the first cell C1' operates with respect to the first bit P[1] of the first control signal P, the first bit N[1] of the second control signal N, and the first bit Z[1] of the third control signal Z.

[0039] The adder 820' may include a first amplifier 822, a second amplifier 824, and capacitors C21 and C22. The first amplifier 822 may have an inverting input terminal and a non-inverting input terminal, and may be used as an integrator together with the capacitors C21 and C22. Therefore, a signal corresponding to the power obtained by summing the positive and negative electricity provided to the inverting input terminal and the non-inverting input terminal of the first amplifier 822 by the m units C1', C2', ... and Cm' may be provided to the second amplifier 824. The second amplifier 824 may generate a single-ended signal from a differential signal, and may generate an output signal OUT having a size corresponding to the signal difference output by the first amplifier 822.

[0040] In the following, for the convenience of description, it is assumed that Figure 1 The analog generator 800 includes four three-level cells (i.e., m=4). In addition, it will be assumed that the thermometer code data T_CD is 8 bits (i.e., k=8), and it will be assumed that the cell code data C_CD and the cell control data C_CT include four values, each of which has one of "-1", "0" and "+1". However, it should be understood that the exemplary embodiments of the present disclosure may also be applied to an analog-to-digital converter including more than five three-level cells.

[0041] FIG. 3A to FIG. 3C is a related art diagram showing a comparative example of controlling four cells C1 , C2 , C3 , and C4 according to a given input sequence. Figure 4A and Figure 4B It shows FIG. 3A to FIG. 3C A graph of the performance of a comparative example of the related art. In detail, Figure 3A A comparative example without using a DEM is shown. Figure 3B and Figure 3CComparative examples of applying DEM in different ways are shown. Figure 4A The graph shows the FIG. 3A to FIG. 3C The cumulative sum of the errors in the frequency domain that appear in each comparison example is, Figure 4B The graph shows that according to FIG. 3A to FIG. 3C The power spectral density (PSD) of each comparison example. FIG. 3A to FIG. 3C In the comparison example, the signed binary data BIN can be input in the order of "-1, -2, 0, 2, 1, -2, 1", which will be omitted below. FIG. 3A to FIG. 3C Redundant description of .

[0042] refer to Figure 3A , when DEM is not applied, some cells may be used with high frequency. Figure 3A As shown, at least one cell including the fourth cell C4 is selected according to the value of the binary data BIN which is not 0. Therefore, the usage frequency of the fourth cell C4 may be high, and because the error of the fourth cell C4 is mainly accumulated, the accumulated sum of the errors does not converge.

[0043] refer to Figure 3B , you can select the cells corresponding to "-1" or "+1" in sequence. Figure 3B As shown, one cell pointer (↑) can be used, and the cell pointer can be shifted unidirectionally (i.e., to the right) according to the absolute value of the binary data BIN. Therefore, cells can be uniformly selected by shifting the cell pointer; however, when the shift is repeated, the cumulative sum of the errors does not converge to a specific value.

[0044] refer to Figure 3C , two unit pointers (↑, ↓) can be used according to the sign of the binary data BIN, and the two unit pointers (↑, ↓) can be shifted independently of each other. That is, Figure 3C As shown, the negative cell pointer (↑) can be shifted to the right according to the negative binary data BIN, and the positive cell pointer (↓) can be shifted to the right according to the positive binary data BIN. Figure 3C A DAC of a comparative example may include an overlapping circuit for storing two cell pointers (↑, ↓) and shifting the two cell pointers (↑, ↓).

[0045] refer to Figure 4A ,according to FIG. 3A to FIG. 3C The cumulative sum of errors of each comparative example may have a high value at a low frequency, and its form may be different from white noise having a uniform value in the entire frequency band. Figure 4B ,according to FIG. 3A to FIG. 3C The PSD in each comparative example may have a form different from the first noise shaping.

[0046] Figure 5 is a diagram illustrating an example of controlling four cells C1 , C2 , C3 , and C4 according to a given input sequence according to an example embodiment of the present disclosure. Fig. 6A and Figure 6B is a graph showing the performance of a DEM according to an exemplary embodiment of the present disclosure. In detail, Figure 5 Shows that when the image FIG. 3A to FIG. 3C In the comparison example, the four cells C1, C2, C3 and C4 are controlled when the signed binary data BIN is input in the order of "-1, -2, 0, 2, 1, -2, 1". Fig. 6A and Figure 6B The graphs of FIG. 1 and FIG. 2 respectively show the cumulative sum of errors and the PSD of the DEM according to an exemplary embodiment of the present disclosure.

[0047] refer to Figure 5 According to an exemplary embodiment of the present disclosure, one unit pointer may be used and the unit pointer may be shifted in a direction depending on the sign of the binary data BIN. Figure 5 As shown, the cell pointer (↑) can be shifted right by 1 bit according to the binary data BIN of "-1", and the cell pointer (↑) can be shifted right by 2 bits according to the binary data BIN of "-2". In addition, the cell pointer (↑) can be maintained according to the binary data BIN of "0". Next, the cell pointer (↑) can be shifted left by 2 bits according to the binary data BIN of "2", and the cell pointer (↑) can be shifted left by 1 bit according to the binary data BIN of "1". Then, the cell pointer (↑) can be shifted right by 2 bits according to the binary data BIN of "-2", and the cell pointer (↑) can be shifted left by 1 bit according to the binary data BIN of "1".

[0048] refer to Fig. 6A , the cumulative sum of errors that can be provided by the DEM according to the exemplary embodiment of the present disclosure is similar in form to white noise having a uniform value in the entire frequency band. Figure 6B , the DEM according to the exemplary embodiment of the present disclosure can provide a PSD having substantially the same form as the first noise shaping. Therefore, the DEM according to one or more exemplary embodiments of the present disclosure can not only provide a PSD having substantially the same form as the first noise shaping. FIG. 3A to FIG. 3C The comparison example shows better performance and can be used compared to the one using two unit pointers. Figure 3C A simpler structure for the comparative example.

[0049] Figure 7 is a diagram showing an exemplary embodiment according to the present disclosure Figure 1 data and Figure 2 The following table shows an example of the control signal. Figure 7 In the example of , the binary data BIN may have a value from "-4" to "4".

[0050] refer to Figure 7 , the thermometer code data T_CD may have 8 bits and may have a number of "1"s continuously from the LSB in proportion to the binary data BIN. For example, a value of "00000000" of the thermometer code data T_CD may correspond to a value of "-4" of the binary data BIN, a value of "00001111" of the thermometer code data T_CD may correspond to a value of "0" of the binary data BIN, and a value of "11111111" of the thermometer code data T_CD may correspond to a value of "4" of the binary data BIN.

[0051] like Figure 7 As shown, the cell code data C_CD may have nine values ​​corresponding to nine different values ​​of the thermometer code data T_CD. In some embodiments, Figure 1 The pre-processing circuit 620 can generate from the thermometer code data T_CD Figure 7 The unit code data C_CD shown in FIG. Figure 1 As described in, for example, the cell control data C_CT can be generated by shifting the cell code data C_CD according to the cell pointer.

[0052] In some embodiments, the selection mode of the cell supplying positive power and the selection mode of the cell supplying negative power may be different according to the thermometer code data T_CD (or binary data BIN). Figure 7 As in the cell code data C_CD, according to the binary data BIN of "-1", the fourth value C_CD[4] of the cell code data C_CD corresponding to the fourth cell C4 may be "-1", and according to the binary data BIN of "1", the first value C_CD[1] of the cell code data C_CD corresponding to the first cell C1 may be "+1". Therefore, the direction of selecting a cell from the cell pointer can be determined by the cell code data C_CD. That is, by Figure 7 The unit code data C_CD, such as Figure 5 As shown, at least one cell to the right of the cell pointer (↑) may be selected according to negative binary data BIN, and at least one cell to the left of the cell pointer (↑) may be selected according to positive binary data BIN.

[0053] The cell code data C_CD includes four values, each of which has one of "-1", "0" and "+1", and therefore, can be represented by two or more 4-bit data. Figure 7 As shown, it can be achieved by respectively Figure 2The unit code data C_CD is represented by at least one of the first code signal P', the second code signal N' and the third code signal Z' corresponding to the first control signal P, the second control signal N and the third control signal Z. The shift of the unit code data C_CD caused by the shift circuit 640 may refer to the shift of at least one of the three first to third code signals P', N' and Z'.

[0054] Fig. 8A and Figure 8B is a diagram showing an exemplary embodiment according to the present disclosure Figure 1 620. Fig. 8A The table of shift count CNT output by the preprocessing circuit 620a in Figure 8B The table of shift count CNT output by the preprocessing circuit 620b in FIG. Figure 1 As described, Fig. 8A The pre-processing circuit 620a and Figure 8B The pre-processing circuit 620b may receive 2m-bit thermometer code data T_CD (ie, k=2m), and may generate a shift count CNT from the thermometer code data T_CD. Figure 7 describe Fig. 8A and Figure 8B , and will omit Fig. 8A and Figure 8B Redundant description of .

[0055] refer to Figure 7 , the 4-bit first code signal P' can be consistent with the upper 4 bits of the thermometer code data T_CD. In addition, the second code signal N' can be consistent with the bits obtained by inverting the lower 4 bits of the thermometer code data T_CD. The third code signal Z' can be consistent with the bits obtained by inverting the first code signal P' when the binary data BIN is a positive number, and can be consistent with the lower 4 bits of the thermometer code data T_CD when the binary data BIN is a negative number. Using this method, although not in Fig. 8A and Figure 8B As shown in FIG. 1 , however, the pre-processing circuits 620 a and 620 b may generate the first code signal P′ and the third code signal Z′ from the thermometer code data T_CD.

[0056] refer to Fig. 8A, the preprocessing circuit 620a may include a multiplexer 624a. The multiplexer 624a is an m-bit 2:1 multiplexer, and may output one of the lower m bits T_CD[m:1] of the thermometer code data T_CD and the upper m bits T_CD[2m:m+1] of the thermometer code data T_CD as the shift count CNT according to the (m+1)th bit T_CD[m+1] of the thermometer code data T_CD. When m is 4, the (m+1)th bit T_CD[m+1] of the thermometer code data T_CD may correspond to Figure 7 "T_CD[5]", and when the (m+1)th bit T_CD[m+1] of the thermometer code data T_CD is "1", the binary data BIN can be a positive number, however, when the (m+1)th bit T_CD[m+1] of the thermometer code data T_CD is "0", the binary data BIN can be zero or a negative number.

[0057] like Fig. 8A As shown in the table, the number of "1" included in the shift count CNT can represent the shift amount of the cell pointer. Therefore, the cell pointer can be shifted in proportion to the absolute value of the binary data BIN in the direction determined according to the sign of the binary data BIN. For example, although a shift count CNT of "0001" can be generated according to the binary data BIN of "1", a shift count CNT of "0111" can be generated according to the binary data BIN of "-1". Because the cell pointer is cyclically or circularly shifted by 4 bits, the shift count CNT of "0001" and the shift count CNT of "0111" can represent a shift of 1 in opposite directions to each other. In addition, a shift count CNT of "1111" can be generated according to the binary data BIN of "0", and the shift count CNT of "1111" can have the same effect as not shifting the cell pointer (i.e., a shift count CNT of "0000") by cyclically or circularly shifting the cell pointer by 4.

[0058] refer to Figure 8B , the pre-processing circuit 620b may include a multiplexer 624b. Fig. 8A Compared with the pre-processing circuit 620a, Figure 8B The multiplexer 624b can output one of the lower m bits T_CD[m:1] of the thermometer code data T_CD and the upper m bits T_CD[2m:m+1] of the thermometer code data T_CD as the shift count CNT according to the mth bit T_CD[m] of the thermometer code data T_CD. Figure 8B As shown in the table, the shift count CNT of "0000" can be generated based on the binary data BIN of "0".

[0059] Fig. 9is a diagram showing an exemplary embodiment according to the present disclosure Figure 1 A block diagram of an example of a shift circuit 640 is shown in FIG. Figure 1 As described, Fig. 9 The shift circuit 640′ may receive the shift count CNT and the cell code data C_CD from the pre-processing circuit 620, and may generate the cell control data C_CT. Fig. 9 As shown, the shift circuit 640 ′ may include a cell pointer shifter 642 , a latch 644 , and a cell code shifter 646 .

[0060] The latch 644 may store a current cell pointer P_CUR for shifting the cell code data C_CD, and may output the stored current cell pointer P_CUR. The cell pointer shifter 642 may generate a new cell pointer P_NEW for shifting the next cell code data C_CD by shifting the current cell pointer P_CUR according to the shift count CNT, and may provide the new cell pointer P_NEW to the latch 644. In addition, the cell code shifter 646 may generate cell control data C_CT by shifting the cell code data C_CD according to the current cell pointer P_CUR. The cell pointer shifter 642 and the cell code shifter 646 may have any shifter structure. For example, as a non-limiting example, the cell pointer shifter 642 and the cell code shifter 646 may have a structure of a barrel shifter, a logarithmic shifter, etc.

[0061] Fig.10 is a flow chart showing a method of digital-to-analog conversion using a three-level cell according to an example embodiment of the present disclosure. Fig.10 As shown, the method of digital-to-analog conversion may include a plurality of operations S20, S40, S60 and S80. In some embodiments, Fig.10 The method can be Figure 1 The DAC 10 performs, and will be referred to below Figure 1 describe Fig.10 .

[0062] In operation S20, an operation of modulating a digital input may be performed. For example, the delta-sigma modulator 200 may generate binary data (or binary code) BIN by oversampling an input signal IN as a digital signal.

[0063] In operation S40, an operation of generating a thermometer code may be performed. For example, the thermometer encoder 400 may convert the binary data BIN into the thermometer code data T_CD. In some embodiments, as described above with reference to Figure 1 As described, the thermometer code data T_CD may include as many "1"s as are proportional to the binary data BIN.

[0064] In operation S60, DEM may be performed. For example, the DEM block 600 may use a cell pointer pointing to one of the three-level cells in the plurality of three-level cells, and may determine a shift direction of the cell pointer according to a sign of the binary data BIN. Fig.11 An example of operation S60 is described.

[0065] In operation S80, an operation of generating an analog signal may be performed. For example, the analog generator 800 may include m units C1, C2, ..., and Cm, and each of the plurality of three-level units may provide one of positive power, negative power, and floating according to the unit control data C_CT received from the DEM block 600 (or a control signal generated from the unit control data C_CT). The adder 820 of the analog generator 800 may generate an output signal OUT as an analog signal by summing the positive power and negative power provided from the m units C1, C2, ..., and Cm.

[0066] Fig.11 is a diagram showing an exemplary embodiment according to the present disclosure Fig.10 Flow chart of an example of operation S60. Fig.10 As described in Fig.11 In operation S60', DEM can be performed. Fig.11 As shown, Fig.11 The operation S60′ may include a plurality of operations S61, S63, S65, S67 and S69, and will be referred to below. Figure 1 describe Fig.11 .

[0067] In operation S61 , an operation of receiving a thermometer code may be performed. For example, the pre-processing circuit 620 of the DEM block 600 may receive thermometer code data T_CD from the thermometer encoder 400 .

[0068] In operation S63, an operation of generating a shift count may be performed. The shift count is used to shift the cell pointer, and, for example, the pre-processing circuit 620 may generate the shift count CNT from the thermometer code data T_CD.

[0069] In operation S65, an operation of generating a unit code may be performed. The unit code, i.e., data for controlling the m units included in the analog generator 800, may include information about the output of the m units. For example, the preprocessing circuit 620 may generate the unit code data C_CD from the thermometer code data T_CD, and the preprocessing circuit 620 may generate the unit code data C_CD so that the mode of selecting the unit varies according to the sign of the binary data BIN.

[0070] In operation S67, an operation of shifting the cell code according to the cell pointer may be performed. For example, the shift circuit 640 may store the cell pointer, and may generate the cell control data C_CT by shifting the cell code data C_CD according to the stored cell pointer.

[0071] In operation S69, an operation of shifting a cell pointer according to a shift count and storing the cell pointer may be performed. For example, the shift circuit 640 may shift a cell pointer for shifting the cell code data C_CD according to the shift count CNT and may store the shifted cell pointer.

[0072] Fig.12 2 is a block diagram showing an analog-to-digital converter 20 including a DAC according to an exemplary embodiment of the present disclosure. The DAC according to the exemplary embodiment of the present disclosure can be used independently to convert a digital signal into an analog signal, or as Fig.12 As shown in , it can be used to convert analog signals into digital signals.

[0073] refer to Fig.12 The analog-to-digital converter 20 may have a delta-sigma structure and may generate a digital output signal D_OUT by converting an analog input signal A_IN. The analog-to-digital converter 20 may include a summing circuit 21, an integrating circuit 23, a quantizing circuit 25, a DAC 27, and a digital filter 29.

[0074] The summing circuit 21 may generate an error signal ERR corresponding to the difference between the analog input signal A_IN and the DAC output signal A_OUT. The integrating circuit 23 may generate an integrated output signal I_OUT by accumulating the error signal ERR, and the quantizing circuit 25 may generate a quantized signal Q_OUT by quantizing the integrated output signal I_OUT. The digital filter 29 may generate a digital output signal D_OUT by filtering (e.g., low-pass filtering) the quantized signal Q_OUT.

[0075] DAC 27 can generate DAC output signal A_OUT as an analog signal by converting quantization signal Q_OUT as a digital signal. As described above, according to the exemplary embodiment of the present disclosure, DAC 27 can provide improved linearity through a simple structure, and thus, analog-to-digital converter 20 can have reduced cost and improved performance.

[0076] As traditional in the art, embodiments can be described and shown by blocks that perform one or more described functions.These blocks, which may be referred to as units or modules, etc. in this article, are physically implemented by analog and / or digital circuits such as logic gates, integrated circuits, microprocessors, microcontrollers, storage circuits, passive electronic components, active electronic components, optical components, hard-wired circuits, etc., and can be optionally driven by firmware and / or software.These circuits can, for example, be specifically implemented in one or more semiconductor chips, or on substrate supports such as printed circuit boards, etc. The circuit constituting the block can be performed by dedicated hardware or by a processor (for example, one or more programmed microprocessors and associated circuits) or by a combination of dedicated hardware for performing some functions of the block and a processor for performing other functions of the block.Without departing from the scope of the present disclosure, each block of the embodiment can be physically divided into more than two interacting and discrete blocks.Similarly, without departing from the scope of the present disclosure, the block of the embodiment can be physically combined into more complex blocks.

[0077] While the present disclosure has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A circuit for performing digital-to-analog conversion using a plurality of three-level units, wherein the plurality of three-level units independently provide positive power, negative power or floating, the circuit comprising: a pre-processing circuit configured to receive thermometer code data generated from the signed binary data and to generate from the thermometer code data a shift count for shifting a cell pointer pointing to one of the plurality of three-level cells for dynamic element matching; as well as a shift circuit configured to store the cell pointer and shift the cell pointer according to the shift count, wherein The cell pointer is shifted in a direction depending on the sign of the signed binary data in proportion to the absolute value of the signed binary data, wherein: the value represented by the signed binary data identifies the number of "1"s within the thermometer code data, The shift circuit is configured to shift the cell pointer according to the number of "1"s in the shift count, and The preprocessing circuit is configured to generate the shift count from an upper half of the thermometer code data when the signed binary data is a positive number, and to generate the shift count from a lower half of the thermometer code data when the signed binary data is a negative number.

2. The circuit of claim 1, wherein: The pre-processing circuit is configured to generate unit code data from the thermometer code data, and The shift circuit is configured to generate cell control data provided to the plurality of three-level cells by shifting the cell code data according to the cell pointer.

3. The circuit of claim 2, wherein: The preprocessing circuit is configured to generate the unit code data including the first code data, the second code data or the third code data, and Each of the plurality of three-level cells provides the positive power according to the first code data, provides the negative power according to the second code data, and provides the floating according to the third code data.

4. The circuit according to claim 3, wherein: The pre-processing circuit is configured to generate the first code data using upper half bits of the thermometer code data.

5. The circuit according to claim 3, wherein: The pre-processing circuit is configured to generate the second code data by inverting lower half bits of the thermometer code data.

6. The circuit according to claim 3, wherein: The preprocessing circuit is configured to generate the third code data by inverting the upper half bits of the thermometer code data when the signed binary data is a positive number, and to generate the third code data using the lower half bits of the thermometer code data when the signed binary data is zero or a negative number.

7. The circuit according to claim 2, further comprising: an analog generator comprising the plurality of three-level cells and a summing circuit for summing the power provided by the plurality of three-level cells, wherein The plurality of three-level cells are configured to supply current to the summing circuit using the positive power, to draw current from the summing circuit using the negative power, or to float a terminal connected to the summing circuit according to the cell control data.

8. A circuit for performing digital-to-analog conversion using m three-level units, wherein the m three-level units independently provide positive power, negative power or floating, wherein m is an integer greater than 1, and the circuit comprises: a pre-processing circuit, the pre-processing circuit comprising a first logic circuit configured to output a shift count for shifting a cell pointer pointing to one of the m three-level cells for dynamic element matching by performing a bit-by-bit operation on 2m-bit thermometer code data generated from signed binary data; as well as A shift circuit comprising a latch and a first shifter, the latch storing the cell pointer, the first shifter being configured to shift the cell pointer stored in the latch according to the shift count, wherein The output of the first shifter is consistent with the cell pointer stored in the latch shifted in a direction depending on the sign of the signed binary data in proportion to the absolute value of the signed binary data, wherein: the value represented by the signed binary data identifies the number of "1"s within the thermometer code data, The first shifter is configured to shift the unit pointer according to the number of "1"s in the shift count, and The first logic circuit is configured to output the upper m bits of the thermometer code data when the least significant bit of the upper m bits of the thermometer code data is "1", and to output the lower m bits of the thermometer code data when the least significant bit is "0".

9. The circuit of claim 8, wherein: The pre-processing circuit further includes a second logic circuit configured to generate unit code data by performing a bit-by-bit operation on the thermometer code data, and The shift circuit further includes a second shifter configured to output cell control data provided to the m three-level cells by shifting the cell code data according to the cell pointer stored in the latch.

10. The circuit of claim 9, wherein: The second logic circuit is configured to generate the unit code data including at least one of m-bit first code data, m-bit second code data, and m-bit third code data, and Each of the m three-level cells provides the positive power according to the first code data, provides the negative power according to the second code data, and provides the floating according to the third code data.

11. The circuit according to claim 10, wherein: The second logic circuit is configured to output upper m bits of the thermometer code data as the first code data.

12. The circuit according to claim 10, wherein: The second logic circuit is configured to output the second code data by inverting lower m bits of the thermometer code data.

13. The circuit according to claim 10, wherein: The second logic circuit is configured to output the third code data by inverting the upper m bits of the thermometer code data when the least significant bit of the upper m bits of the thermometer code data is "1", and to output the lower m bits of the thermometer code data as the third code data when the least significant bit is "0".

14. The circuit of claim 10, further comprising: An analog generator, comprising the m three-level units and a summing circuit for summing the power provided by the m three-level units, wherein The m three-level cells are configured to supply current to the summing circuit using the positive power, to draw current from the summing circuit using the negative power, or to float a terminal connected to the summing circuit according to the cell control data.

15. A method for performing digital-to-analog conversion using a plurality of three-level units, wherein the plurality of three-level units independently provide positive electricity, negative electricity or floating, the method comprising: receiving thermometer code data generated from signed binary data; generating a shift count from the thermometer code data for shifting a cell pointer pointing to one of the plurality of three-level cells for dynamic element matching; and The cell pointer is shifted according to the shift count and the cell pointer is stored, wherein The cell pointer is shifted in a direction depending on the sign of the signed binary data in proportion to the absolute value of the signed binary data, wherein: the value represented by the signed binary data identifies the number of "1"s within the thermometer code data, The shifting includes shifting the unit pointer according to the number of "1"s in the shift count, and Generating the shift count includes generating the shift count from the upper half bits of the thermometer code data when the signed binary data is a positive number, and generating the shift count from the lower half bits of the thermometer code data when the signed binary data is a negative number.

16. The method according to claim 15, further comprising: generating unit code data from the thermometer code data; as well as Before the cell pointer is shifted, cell control data provided to the plurality of three-level cells is generated by shifting the cell code data according to the cell pointer. 17 . The method of claim 16 , further comprising generating an analog signal by summing the positive power, the negative power, and the floating provided by the plurality of three-level cells according to the cell control data.

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