Package device, semiconductor device and method for manufacturing package device

Abstract

A packaging device comprises a circuit layer, at least one conductive segment, a packaging body and a redistribution layer. The conductive segment is disposed on the circuit layer and has a first surface and a second surface. The packaging body seals at least a portion of the conductive segment and has a first upper surface. A first portion of the first surface of the conductive segment and at least a portion of the second surface are disposed above the first upper surface of the packaging body. The redistribution layer is disposed on the packaging body, the first portion of the first surface of the conductive segment and the second surface of the conductive segment.

Description

Technical Field

[0001] The present disclosure relates to a package device and a manufacturing method thereof, and relates to a package device comprising a redistribution layer (RDL) disposed on a portion of a conductive segment, and a manufacturing method of the package device. Background Art

[0002] In some semiconductor packages, an interconnection component (e.g., a pillar or wire) is encased (e.g., completely encapsulated) by a molding compound during its manufacturing process. Therefore, a grinding process can be used to expose the interconnection component from the package. The grinding process can remove a portion of the encapsulation compound and a portion of the interconnection component, so that the upper surface of the interconnection component is exposed. Then, the RDL can be connected to the upper surface of the interconnection component. However, this grinding process can be expensive or time consuming. Summary of the invention

[0003] In some embodiments, a packaged device includes a circuit layer, at least one conductive segment, an encapsulant, and a redistribution layer. The conductive segment is disposed on the circuit layer and has a first surface and a second surface. The encapsulant seals at least a portion of the conductive segment and has a first upper surface. A first portion of the first surface of the conductive segment and at least a portion of the second surface are disposed above the first upper surface of the encapsulant. The redistribution layer is disposed on the encapsulant, the first portion of the first surface of the conductive segment, and the second surface of the conductive segment.

[0004] In some embodiments, a semiconductor device includes a circuit layer, a logic component, a package, a redistribution layer, a first conductive segment, and a second conductive segment. The logic component is disposed on the circuit layer. The package seals the logic component. The redistribution layer is disposed on the package. The first conductive segment connects the circuit layer and the redistribution layer. The second conductive segment connects the logic component and the redistribution layer. The first conductive segment and the second conductive segment are formed by a single bonding wire.

[0005] In some embodiments, a method for manufacturing a packaging device includes (a) forming a bonding wire having two first surfaces and including a connecting segment between the two first surfaces; (b) providing a packaging body to seal the bonding wire and expose a portion of the connecting segment of the bonding wire; (c) removing the connecting segment of the bonding wire to separate the bonding wire into two segments and form a second surface of each of the segments; and (d) removing a portion of the packaging body to expose a first portion of the first surface of each of the segments. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of some embodiments of the present disclosure are readily understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that various structures may not be drawn to scale, and the sizes of various structures may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 Cross-sectional views illustrating examples of packaging devices according to some embodiments of the present disclosure.

[0008] Figure 2 illustrate Figure 1 An enlarged view of area 1A is shown in FIG.

[0009] Figure 3 Instructions along the Figure 2 A cross-sectional view of line 1B-1B is shown in FIG.

[0010] Figure 4 Cross-sectional views illustrating examples of packaging devices according to some embodiments of the present disclosure.

[0011] Figure 5 illustrate Figure 4 An enlarged view of area 4A is shown in FIG.

[0012] Figure 6 Instructions along the Figure 5 A cross-sectional view of line 4B-4B shown in FIG.

[0013] Figure 7 Cross-sectional views illustrating examples of packaging devices according to some embodiments of the present disclosure.

[0014] Figure 8 illustrate Figure 7 An enlarged view of area 7A is shown in FIG.

[0015] Fig. 9 Instructions along the Figure 8 A cross-sectional view of line 7B-7B shown in FIG.

[0016] Fig.10 Cross-sectional views illustrating examples of packaging devices according to some embodiments of the present disclosure.

[0017] Fig.11 illustrate Fig.10 An enlarged view of area 10A is shown in FIG.

[0018] Fig.12 Instructions along the Fig.11 A cross-sectional view of line 10B-10B is shown in FIG.

[0019] Fig.13 Cross-sectional views illustrating examples of packaging devices according to some embodiments of the present disclosure.

[0020] Fig.14 Cross-sectional views illustrating examples of packaged devices (semiconductor devices) according to some embodiments of the present disclosure.

[0021] Fig.15 Cross-sectional views illustrating examples of packaged devices (semiconductor devices) according to some embodiments of the present disclosure.

[0022] Fig.16 Cross-sectional views illustrating examples of packaged devices (semiconductor devices) according to some embodiments of the present disclosure.

[0023] Fig.17 Cross-sectional views illustrating examples of packaged devices (semiconductor devices) according to some embodiments of the present disclosure.

[0024] Fig.18 Cross-sectional views illustrating examples of packaged devices (semiconductor devices) according to some embodiments of the present disclosure.

[0025] Fig.19 Cross-sectional views illustrating examples of packaged devices (semiconductor devices) according to some embodiments of the present disclosure.

[0026] Fig. 20 Cross-sectional views illustrating examples of packaged devices (semiconductor devices) according to some embodiments of the present disclosure.

[0027] Fig.21 One or more stages of an example of a method for manufacturing a packaged device according to some embodiments of the present disclosure are described.

[0028] Fig. 22 One or more stages of an example of a method for manufacturing a packaged device according to some embodiments of the present disclosure are described.

[0029] Fig.23 One or more stages of an example of a method for manufacturing a packaged device according to some embodiments of the present disclosure are described.

[0030] Fig.24One or more stages of an example of a method for manufacturing a packaged device according to some embodiments of the present disclosure are described.

[0031] Fig.25 One or more stages of an example of a method for manufacturing a packaged device according to some embodiments of the present disclosure are described.

[0032] Fig.26 One or more stages of an example of a method for manufacturing a packaged device according to some embodiments of the present disclosure are described.

[0033] Fig. 27 One or more stages of an example of a method for manufacturing a packaged device according to some embodiments of the present disclosure are described.

[0034] Fig.28 One or more stages of an example of a method for manufacturing a packaged device according to some embodiments of the present disclosure are described.

[0035] Fig.29 One or more stages of an example of a method for manufacturing a packaged device according to some embodiments of the present disclosure are described.

[0036] Fig.30 One or more stages of an example of a method for manufacturing a packaged device according to some embodiments of the present disclosure are described.

[0037] Fig.31 illustrate Fig.30 An enlarged view of area 30A is shown in FIG.

[0038] Fig.32 Instructions along the Fig.31 A cross-sectional view of line 30B-30B shown in FIG.

[0039] Fig.33 One or more stages of an example of a method for manufacturing a packaged device according to some embodiments of the present disclosure are described.

[0040] Fig.34 illustrate Fig.33 An enlarged view of area 33A is shown in FIG.

[0041] Fig.35 Instructions along the Fig.34 A cross-sectional view of line 33B-33B shown in FIG.

[0042] Fig.36 One or more stages of an example of a method for manufacturing a packaged device according to some embodiments of the present disclosure are described.

[0043] Fig.37 illustrate Fig.36 An enlarged view of area 36A is shown in FIG.

[0044] Fig.38 Instructions along the Fig.37 A cross-sectional view of line 36B-36B shown in FIG.

[0045] Fig.39 One or more stages of an example of a method for manufacturing a packaged device according to some embodiments of the present disclosure are described.

[0046] Fig.40 One or more stages of an example of a method for manufacturing a packaged device according to some embodiments of the present disclosure are described.

[0047] Fig.41 One or more stages of an example of a method for manufacturing a packaged device according to some embodiments of the present disclosure are described.

[0048] Fig.42 One or more stages of an example of a method for manufacturing a packaged device according to some embodiments of the present disclosure are described.

[0049] Fig.43 One or more stages of an example of a method for manufacturing a packaged device according to some embodiments of the present disclosure are described.

[0050] Fig.44 One or more stages of an example of a method for manufacturing a packaged device according to some embodiments of the present disclosure are described.

[0051] Fig.45 One or more stages of an example of a method for manufacturing a packaged device according to some embodiments of the present disclosure are described.

[0052] Fig.46 One or more stages of an example of a method for manufacturing a packaged device according to some embodiments of the present disclosure are described.

[0053] Fig.47 One or more stages of an example of a method for manufacturing a packaged device according to some embodiments of the present disclosure are described.

[0054] Fig.48 One or more stages of an example of a method for manufacturing a packaged device according to some embodiments of the present disclosure are described.

[0055] Fig.49 illustrate Fig.48 An enlarged view of area 48A is shown in FIG.

[0056] Fig.50 Instructions along the Fig.49 A cross-sectional view of line 48B-48B is shown in FIG.

[0057] Fig.51 One or more stages of an example of a method for manufacturing a packaged device according to some embodiments of the present disclosure are described.

[0058] Fig.52 illustrate Fig.51 An enlarged view of area 51A is shown in FIG.

[0059] Fig.53 Instructions along the Fig.52 A cross-sectional view of line 51B-51B shown in FIG.

[0060] Fig.54 One or more stages of an example of a method for manufacturing a packaged device according to some embodiments of the present disclosure are described.

[0061] Fig.55 illustrate Fig.54 An enlarged view of area 54A is shown in FIG.

[0062] Fig.56 Instructions along the Fig.55 A cross-sectional view of line 54B-54B is shown in FIG.

[0063] Fig.57 One or more stages of an example of a method for manufacturing a packaged device according to some embodiments of the present disclosure are described.

[0064] Fig.58 illustrate Fig.57 An enlarged view of area 57A is shown in FIG.

[0065] Fig.59 Instructions along the Fig.58 A cross-sectional view of line 57B-57B is shown in FIG.

[0066] Fig.60 One or more stages of an example of a method for manufacturing a packaged device according to some embodiments of the present disclosure are described.

[0067] Fig.61 illustrate Fig.60 An enlarged view of area 60A is shown in FIG.

[0068] Fig.62 Instructions along the Fig.61 A cross-sectional view of line 60B-60B is shown in FIG.

[0069] Fig.63 One or more stages of an example method of manufacturing a semiconductor device according to some embodiments of the present disclosure are described.

[0070] Fig.64 One or more stages of an example of a method for manufacturing a packaged device (semiconductor device) according to some embodiments of the present disclosure are described.

[0071] Fig.65One or more stages of an example of a method for manufacturing a packaged device (semiconductor device) according to some embodiments of the present disclosure are described.

[0072] Fig.66 One or more stages of an example of a method for manufacturing a packaged device (semiconductor device) according to some embodiments of the present disclosure are described.

[0073] Fig.67 One or more stages of an example of a method for manufacturing a packaged device (semiconductor device) according to some embodiments of the present disclosure are described.

[0074] Fig.68 One or more stages of an example of a method for manufacturing a packaged device (semiconductor device) according to some embodiments of the present disclosure are described.

[0075] Fig.69 One or more stages of an example of a method for manufacturing a packaged device (semiconductor device) according to some embodiments of the present disclosure are described.

[0076] Fig.70 One or more stages of an example of a method for manufacturing a packaged device (semiconductor device) according to some embodiments of the present disclosure are described.

[0077] Fig.71 One or more stages of an example of a method for manufacturing a packaged device (semiconductor device) according to some embodiments of the present disclosure are described.

[0078] Fig.72 One or more stages of an example of a method for manufacturing a packaged device (semiconductor device) according to some embodiments of the present disclosure are described.

[0079] Fig.73 One or more stages of an example of a method for manufacturing a packaged device (semiconductor device) according to some embodiments of the present disclosure are described.

[0080] Fig.74 One or more stages of an example of a method for manufacturing a packaged device (semiconductor device) according to some embodiments of the present disclosure are described.

[0081] Fig.75 One or more stages of an example of a method for manufacturing a packaged device (semiconductor device) according to some embodiments of the present disclosure are described.

[0082] Fig.76 One or more stages of an example of a method for manufacturing a packaged device (semiconductor device) according to some embodiments of the present disclosure are described.

[0083] Fig.77 One or more stages of an example of a method for manufacturing a packaged device (semiconductor device) according to some embodiments of the present disclosure are described.

[0084] Fig.78 One or more stages of an example of a method for manufacturing a packaged device (semiconductor device) according to some embodiments of the present disclosure are described.

[0085] Fig.79 One or more stages of an example of a method for manufacturing a packaged device (semiconductor device) according to some embodiments of the present disclosure are described.

[0086] Fig.80 One or more stages of an example of a method for manufacturing a packaged device (semiconductor device) according to some embodiments of the present disclosure are described. DETAILED DESCRIPTION

[0087] Common reference numerals are used throughout the drawings and detailed description to refer to the same or similar components. The embodiments of the present disclosure will be readily understood based on the following detailed description made in conjunction with the accompanying drawings.

[0088] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to illustrate certain aspects of the disclosure. Of course, these are just examples and are not intended to be restrictive. For example, in the following description, reference to the formation of a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted or formed or arranged, and may also include an embodiment in which an additional feature may be formed or arranged between the first feature and the second feature so that the first feature and the second feature may not be directly contacted. In addition, the disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0089] In a manufacturing process of a comparative packaged device, a grinding process may be used to expose an interconnect component (e.g., a pillar or wire) sealed by a packaging compound. A portion of the packaging compound and a portion of the interconnect component are removed so that the upper surface of the interconnect component is exposed from the packaging compound to be connected to the RDL. However, the removed portion of the packaging compound may form powder adhering to the upper surface of the interconnect component. In addition, if the RDL is connected to a single surface of the interconnect component, delamination is likely to occur between the RDL and the interconnect component.

[0090] The present disclosure provides a packaged device that can be manufactured without using an interconnect component and a grinding process for a packaging compound that seals the interconnect component. In some embodiments, the packaged device includes at least one conductive segment disposed on a circuit layer and having a first surface and a second surface; a package body that seals at least a portion of the conductive segment and has a first upper surface, wherein a first portion of the first surface of the conductive segment and at least a portion of the second surface are disposed above the first upper surface of the package body; and a redistribution layer disposed on the package body, a first portion of the first surface of the conductive segment, and a second surface of the conductive segment. At least some embodiments of the present disclosure provide a technique for manufacturing the packaged device.

[0091] Figure 1 A cross-sectional view illustrating a packaging device 1 according to some embodiments of the present disclosure. Figure 2 illustrate Figure 1 An enlarged view of area 1A is shown in FIG. Figure 3 Instructions along the Figure 2 The package device 1 includes a dielectric layer 11, a circuit layer 2, a package body 4, at least one conductive segment (e.g., a first conductive segment 3a and a second conductive segment 3b), an RDL 5, a passivation layer 12, at least one first under bump metallization (UBM) 13, and at least one second UBM 14. For illustration purposes, Figure 3 The passivation layer 12 is omitted.

[0092] The dielectric layer 11 has an upper surface 111 and a lower surface 112 opposite to the upper surface 111, and has at least one through hole 110, which penetrates the dielectric layer 11 and extends between the upper surface 111 and the lower surface 112. The dielectric layer 11 may include an organic dielectric material, such as benzocyclobutene (BCB), bismaleimidetriazine (BT), Ajinomoto build-up film (ABF), epoxy resin, polyimide (PI); or an inorganic dielectric material, such as SiO x 、SiN x 、TaO x , glass, silicon or ceramic. In some embodiments, the dielectric layer 11 may include a cured photoimageable dielectric (PID) material.

[0093] The circuit layer 2 is disposed on the upper surface 111 of the dielectric layer 11 and in the through hole 110 of the dielectric layer 11. For example, the circuit layer 2 may include at least one bump pad 24 disposed on the upper surface 111 of the dielectric layer 11, and at least one conductive via 26 disposed in the through hole 110 of the dielectric layer 11. In some embodiments, as Figures 1 to 3 As shown in , the circuit layer 2 may include a first metal layer 21, a second metal layer 22, and a third metal layer 23. The first metal layer 21 and the second metal layer 22 may be seed layers and include titanium, copper, nickel, tungsten, and / or platinum or alloys thereof, and may be formed by sputtering. The third metal layer 23 may include copper, tin, gold, silver, nickel, and / or palladium or alloys thereof, and may be formed by electroplating, electroless plating, or printing. The first UBM 13 may be disposed on a side of the conductive via 26 adjacent to the lower surface 112 of the dielectric layer 11. The first UBM 13 may include palladium and / or gold.

[0094] The package body 4, such as a packaging compound, is disposed on the upper surface 111 of the dielectric layer 11 and covers the circuit layer 2. The package body 4 has a first upper surface 41 and a second upper surface 42, and a lower surface 43 opposite to the first upper surface 41 and the second upper surface 42. The first upper surface 41 and the second upper surface 42 are not coplanar. For example, the first upper surface 41 is disposed above the second upper surface 42 (for example, the first upper surface 41 is farther from the lower surface 43 than the upper surface 42). In some embodiments, the first upper surface 41 is generally flat, and the second upper surface 42 is generally annular or semi-cylinder shaped. The second upper surface 42 intersects with the first upper surface 41 at two sides and is recessed from the first surface 41 to form a cavity 44. The lower surface 43 of the package body 4 is disposed on the upper surface 111 of the dielectric layer 11. In some embodiments, the material of the package body 4 may be the same as or similar to the material of the dielectric layer 11 .

[0095] In some embodiments, Figure 1As shown in , at least one conductive segment includes a first conductive segment 3a and a second conductive segment 3b separated from the first conductive segment 3a. The first conductive segment 3a and the second conductive segment 3b may be formed by a single bonding wire. For example, the first conductive segment 3a may include a first bonding portion (first bond portion) of the bonding wire (e.g., a ball bond), and the second conductive segment 3b may include a second bonding portion (second bond portion) of the bonding wire (e.g., a wedge bond or a tail bond). In some embodiments, the second conductive segment 3b may further include a stud portion 36 disposed on the circuit layer 2 to enhance the bonding with the circuit layer 2. However, in other embodiments, the stud portion 36 may be omitted. The first conductive segment 3a and the second conductive segment 3b may be disposed on the circuit layer 2 (e.g., each disposed on a corresponding bump pad 24) and penetrate the package 4. The package 4 seals at least a portion of the first conductive segment 3a. In some embodiments, the package body 4 further seals at least a portion of the second conductive segment 3 b , and the cavity 44 of the package body 4 is located between the first conductive segment 3 a and the second conductive segment 3 b .

[0096] The first conductive segment 3a has a first surface 31 and a second surface 32. The first surface 31 and the second surface 32 intersect each other. For example, the second surface 32 is a concave surface. The first surface 31 is generally an annular surface (in Figure 3 ), and extends from the periphery of the second surface 32. The first portion 311 of the first surface 31 is exposed from the package body 4 and is disposed above the first upper surface 41 of the package body 4. The second surface 32 is exposed from the package body 4, and at least a portion of the second surface 32 is disposed above the first upper surface 41 of the package body 4. In some embodiments, as Figure 1 and 2As shown in , the second surface 32 of the first conductive segment 3a (for example, the entire second surface 32) is disposed above the first upper surface 41 of the package body 4. The second upper surface 42 of the package body 4 is disposed below the second surface 32 of the first conductive segment 3a. The average roughness of the first surface 31 of the first conductive segment 3a is different from the average roughness of the second surface 32 of the first conductive segment 3a. In some embodiments, the average roughness of the first surface 31 of the first conductive segment 3a is less than the average roughness of the second surface 32 of the first conductive segment 3a. For example, the average roughness of the second surface 32 may be at least about 1.5 times, about 2 times, at least about 3 times, or at least about 5 times the average roughness of the first surface 31. For example, the average roughness of the first surface 31 may be less than about 20 nm, and the average roughness of the second surface 32 may be greater than about 40 nm. As Figure 1 and 2 As shown in FIG. 4 , a portion 34 of the first conductive segment 3a is exposed from the package body 4. The first portion 311 of the first surface 31 and the second surface 32 are surfaces of the exposed portion 34 of the first conductive segment 3a. The second conductive segment 3b also has a first surface 31 and a second surface 32, and includes an exposed portion 34. The first surface 31, the second surface 32 and the exposed portion 34 of the second conductive segment 3b are similar to the surfaces and portions of the first conductive segment 3a, and therefore are not repeated. The first conductive segment 3a and the second conductive segment 3b may include a conductive metal, such as tin, aluminum, gold, silver or copper or an alloy thereof. In some embodiments, the height of the first conductive segment 3a may be about 150 micrometers (μm) to about 500 μm. The maximum diameter of the first conductive segment 3a, such as the diameter of a portion of the first conductive segment 3a attached to the circuit layer 2, may be about 10 μm to about 50 μm. The aspect ratio (A / R) of the first conductive segment 3 a may be greater than about 10:1 (eg, may be about 11:1 or higher, about 12:1 or higher, or about 13:1 or higher).

[0097] The RDL 5 is disposed on the package body 4, the first portion 311 of the first surface 31 of the first conductive segment 3a disposed above the first upper surface 41 of the package body 4, and the second surface 32 of the first conductive segment 3a. Similarly, the RDL 5 is also disposed on the first portion 311 of the first surface 31 of the second conductive segment 3b disposed above the first upper surface 41 of the package body 4, and the second surface 32 of the second conductive segment 3b. Figure 1 and 2As shown in , the RDL 5 is disposed on both the first upper surface 41 and the second upper surface 42 of the package body 4. The RDL 5 covers the exposed portion 34 of the first conductive segment 3a and the exposed portion 34 of the second conductive segment 3b. The RDL 5 is disposed on the first portion 311 of the first surface 31 of the first conductive segment 3a and the second surface 32 of the first conductive segment 3a and is conformal thereto. Similarly, the RDL 5 may also be disposed on the first portion 311 of the first surface 31 of the second conductive segment 3b and the second surface 32 of the second conductive segment 3b and is conformal thereto. In some embodiments, both the first conductive segment 3a and the second conductive segment 3b are connected to the circuit layer 2 and the RDL 5. Similar to the circuit layer 2, the RDL 5 may also include a plurality of metal layers, including a fourth metal layer 51, a fifth metal layer 52, and a sixth metal layer 53. The fourth metal layer 51 and the fifth metal layer 52 may be seed layers and include titanium, copper, nickel, tungsten and / or platinum, or alloys thereof, and may be formed by sputtering. The sixth metal layer 53 may include copper, tin, gold, silver, nickel and / or palladium, or alloys thereof, and may be formed by electroplating, electroless plating, or printing.

[0098] The passivation layer 12 is disposed on the first upper surface 41 of the package body 4, the RDL 5, and the second upper surface 42 of the package body 4. The passivation layer 12 extends into the cavity 44 of the package body 4. At least a portion of the RDL 5 is exposed from the passivation layer 12 for external connection. The material of the passivation layer 12 may be the same as that of the dielectric layer 11. The second UBM 14 may be disposed on the exposed portion of the RDL 5. In some embodiments, the second UBM 14 includes a first layer 141 and a second layer 142. The first layer 141 includes nickel, and the second layer 142 includes palladium and / or gold.

[0099] In the package device 1, since at least a portion of the first portion 311 and the second surface 32 of the first surface 31 of the conductive segment (e.g., the first conductive segment 3a) is disposed above the first upper surface 41 of the package body 4, and since the RDL 5 is disposed on the first portion 311 and the second surface 32 of the first surface 31 of the first conductive segment 3a, the contact area between the RDL 5 and the first conductive segment 3a is large. Therefore, the circuit resistance can be reduced, and the possibility of delamination of the RDL 5 can be reduced. The height difference between the first upper surface 41 and the second upper surface 42 can further reduce the possibility of delamination of the RDL 5 and the possibility of delamination of the passivation layer 12. In addition, since the average roughness of the second surface 32 of the first conductive segment 3a is greater than the first surface 31 of the first conductive segment 3a, the RDL 5 can be easily adhered to the first conductive segment 3a.

[0100] Figure 4 A cross-sectional view illustrating a packaging device 1 a according to some embodiments of the present disclosure. Figure 5 illustrate Figure 4 An enlarged view of area 4A is shown in FIG. Figure 6 Instructions along the Figure 5 For illustration purposes, Figure 6 The passivation layer 12 is omitted.

[0101] The packaging device 1a is similar to Figures 1 to 3 , except that a portion of the second surface 32 of the first conductive segment 3a is disposed above the first upper surface 41 of the package body 4. Another portion of the second surface 32 of the first conductive segment 3a is disposed below the first upper surface 41 of the package body 4. Similarly, a portion of the second surface 32 of the second conductive segment 3b is disposed above the first upper surface 41 of the package body 4, and another portion of the second surface 32 of the second conductive segment 3b is disposed below the first upper surface 41 of the package body 4.

[0102] Figure 7 A cross-sectional view illustrating a packaging device 1 b according to some embodiments of the present disclosure. Figure 8 illustrate Figure 7 An enlarged view of area 7A is shown in FIG. Fig. 9 Instructions along the Figure 8 For illustration purposes, the cross-sectional view of line 7B-7B shown in FIG. Fig. 9 The passivation layer 12 is omitted.

[0103] Package device 1b is similar to Figures 1 to 3 The packaging device 1 shown in FIG. 1 is similar to the packaging device 1 shown in FIG. 1 , but with the following differences. Figures 7 to 9 As shown in FIG. 4 , the second upper surface 42 of the package body 4 is disposed above the first upper surface 41 of the package body 4. In addition, the first surface 31 (e.g., the entire first surface 31) of the first conductive segment 3a may be covered by the package body 4. The second surface 32 of the first conductive segment 3a is exposed from the package body 4 and connects the first upper surface 41 and the second upper surface 42 of the package body 4. For example, the first conductive segment 3a has the second surface 32 exposed from the package body 4, and Figure 1 and 2 The exposed portion 34 shown in Figures 7 to 9 The RDL 5 may be disposed on the second surface 32 of the first conductive segment 3a, the first upper surface 41 and the second upper surface 42 of the package body 4, but not on the first surface 31 of the conductive segment 3a.

[0104] Fig.10 A cross-sectional view illustrating a packaging device 1c according to some embodiments of the present disclosure. Fig.11 illustrate Fig.10 An enlarged view of area 10A is shown in FIG. Fig.12Instructions along the Fig.11 For illustration purposes, the cross-sectional view of line 10B-10B shown in FIG. Fig.12 The passivation layer 12 is omitted.

[0105] The packaged device 1c is similar to Figures 1 to 3 The packaging device 1 shown in FIG. 1 is similar to the packaging device 1 shown in FIG. 1 , but with the following differences. Figures 10 to 12 As shown in FIG, the first surface 31 (e.g., the entire first surface 31) of the first conductive segment 3a may be covered by the package body 4. The second surface 32 of the first conductive segment 3a is exposed from the package body 4 and connects the first upper surface 41 and the second upper surface 42 of the package body 4. For example, the first conductive segment 3a has the second surface 32 exposed from the package body 4, and Figure 1 and 2 The exposed portion 34 shown in Figures 10 to 12 The RDL 5 may be disposed on the second surface 32 of the first conductive segment 3a, the first upper surface 41 and the second upper surface 42 of the package body 4, but not on the first surface 31 of the conductive segment 3a.

[0106] Fig.13 A cross-sectional view of a packaging device 1d according to some embodiments of the present disclosure is shown. The packaging device 1d is similar to Figures 1 to 3 The packaging device 1 shown in Fig.13 The package device 1d in the embodiment further includes an additional RDL 5a and an additional passivation layer 12a. The additional RDL 5a is disposed on the passivation layer 12 and is electrically connected to the RDL 5. Similar to the RDL 5, the RDL 5a may also include multiple metal layers, including a fourth metal layer 51a, a fifth metal layer 52a, and a sixth metal layer 53a. The fourth metal layer 51a and the fifth metal layer 52a may be seed layers and include titanium, copper, nickel, tungsten and / or platinum, or alloys thereof, and may be formed by sputtering. The sixth metal layer 53a may include copper, tin, gold, silver, nickel and / or palladium, or alloys thereof, and may be formed by electroplating, electroless plating, or printing. The additional passivation layer 12a is disposed on the additional RDL 5a and the passivation layer 12, and at least a portion of the additional RDL 5a is exposed from the additional passivation layer 12a. The second UBM 14 is disposed on the exposed portion of the additional RDL 5a.

[0107] Fig.14 A cross-sectional view of a packaging device 1e according to some embodiments of the present disclosure is shown. The packaging device 1e is similar to Figures 1 to 3 The packaging device 1 shown in Fig.14The package device 1e further comprises an electronic component 6, an underfill 15, a packaging compound 16 and at least one upper solder connector 17. Fig.14 The packaged device 1e may also be referred to as a “semiconductor device”.

[0108] The electronic components 6 are arranged on the circuit layer 2. Fig.14 As shown in FIG. 1 , the electronic component 6 is disposed on the lower surface 112 of the dielectric layer 11 and is electrically connected to the circuit layer 2. For example, the electronic component 6 may be a semiconductor die. The electronic component 6 includes or is electrically connected to at least one conductive pillar 63 and at least one solder bump 64 sequentially disposed on the first surface 61 of the electronic component 6. The solder bump 64 is electrically connected to the first UBM 13 disposed on the conductive via 26 of the circuit layer 2.

[0109] The underfill 15 is disposed between the electronic component 6 and the dielectric layer 11 and covers the first surface 61 of the electronic component 6, the conductive pillars 63 and the solder bumps 64. The packaging compound 16 is disposed on the lower surface 112 of the dielectric layer 11 and covers the electronic component 6, the underfill 15 and the lower surface 112 of the dielectric layer 11. The upper solder connector 17 is disposed on the second UBM 14 and protrudes from the passivation layer 12.

[0110] Fig.15 A cross-sectional view of a packaged device (or semiconductor device) 1f according to some embodiments of the present disclosure is illustrated. Figures 1 to 3 , the package device 1f also includes a dielectric layer 11, a circuit layer 2, a package body 4, at least one conductive segment (e.g., a first conductive segment (or a third conductive segment) 3c and a second conductive segment (or a fourth conductive segment) 3d), an RDL 5, and a passivation layer 12. However, the package device 1f includes the first conductive segment 3c and the second conductive segment 3d instead of Figures 1 to 3 The first conductive section 3a and the second conductive section 3b of the package device 1 shown in FIG. Figures 1 to 3 The first UBM 13 and the second UBM 14 of the package device 1 shown in FIG. 1 are omitted in the package device 1f. In addition, the package device 1f may further include an additional circuit layer 2a, an electronic component 6a, at least one upper solder connector 17, a protective layer 18 and at least one lower solder connector 19.

[0111] The dielectric layer 11 and the circuit layer 2 are the same or similar Figures 1 to 3, and therefore are not described in detail. The additional circuit layer 2a is disposed on the lower surface 112 of the dielectric layer 11 and is electrically connected to the conductive via 26 of the circuit layer 2. The additional circuit layer 2a may also include a first metal layer 21a, a second metal layer 22a, and a third metal layer 23a. The first metal layer 21a and the second metal layer 22a may be seed layers and include titanium, copper, nickel, tungsten and / or platinum, or alloys thereof, and may be formed by sputtering. The third metal layer 23a may include copper, tin, gold, silver, nickel and / or palladium, or alloys thereof, and may be formed by electroplating, electroless plating, or printing.

[0112] The protective layer 18 is provided on the lower surface 112 of the dielectric layer 11 and covers the additional circuit layer 2a. At least a portion of the additional circuit layer 2a is exposed from the protective layer 18. The lower solder connector 19 is provided in the protective layer 18 and on the exposed portion of the additional circuit layer 2a.

[0113] The electronic component 6a is disposed on the circuit layer 2. For example, the electronic component 6a may be a logic component. However, in some other embodiments, the electronic component 6a may be other components. The electronic component 6a has a first surface 61 (e.g., an active surface) and a passive surface 62 opposite to the first surface 61. The electronic component 6a includes a conductive layer 65 disposed on the passive surface 62, and at least one bump pad 66 is disposed on the first surface 61. The electronic component 6a further includes at least one solder joint 67 disposed between the bump pad 66 and the corresponding conductive via 26. Therefore, the electronic component 6a can be electrically connected to the circuit layer 2 via the bump pad 66 and the solder joint 67.

[0114] The package body 4, such as a packaging compound, is disposed on the upper surface 111 of the dielectric layer 11 and covers the circuit layer 2 and the electronic component 6a. The package body 4 has a first upper surface 41 and a second upper surface 42, and a lower surface 43 opposite to the first upper surface 41 and the second upper surface 42. The first upper surface 41 and the second upper surface 42 are not coplanar. For example, the first upper surface 41 is disposed above the second upper surface 42. In some embodiments, the first upper surface 41 is substantially flat, and the second upper surface 42 is substantially annular or semi-cylindrical in shape. The second upper surface 42 intersects with the first upper surface 41 at both sides and is recessed from the first upper surface 41 to form a cavity 44. The lower surface 43 of the package body 4 is disposed on the upper surface 111 of the dielectric layer 11. In some embodiments, the material of the package body 4 may be the same as or similar to the material of the dielectric layer 11.

[0115] In some embodiments, Fig.15As shown in FIG. 1 , at least one conductive segment includes a first conductive segment 3c and a second conductive segment 3d separated from the first conductive segment 3c. The first conductive segment 3c and the second conductive segment 3d may be formed by a single bonding wire. For example, the first conductive segment 3c may include a first bonding portion of the bonding wire (e.g., a ball bond), and the second conductive segment 3d may include a second bonding portion of the bonding wire (e.g., a wedge bond or a tail bond). In some embodiments, the second conductive segment 3d may further include a stud portion (e.g., a stud portion) disposed on the circuit layer 2. Figure 1 36) to enhance the bonding with the circuit layer 2. However, as Fig.15 As shown in Figure 1 The stud portion 36 shown in FIG. Fig.15 . The first conductive segment 3c is disposed on the circuit layer 2 (for example, each disposed on a corresponding bump pad 24) and penetrates the package body 4. The second conductive segment 3d is disposed on the conductive layer 65 of the electronic component 6a and also penetrates the package body 4. The package body 4 seals at least a portion of the first conductive segment 3c. In some embodiments, the package body 4 also seals at least a portion of the second conductive segment 3d, and the cavity 44 of the package body 4 is located between the first conductive segment 3c and the second conductive segment 3d.

[0116] The first conductive segment 3c has a first surface 31 and a second surface 32. The first surface 31 and the second surface 32 intersect each other. For example, the second surface 32 is a concave surface, and the first surface 31 is substantially an annular surface extending from the periphery of the second surface 32. The first portion 311 of the first surface 31 is disposed above the first upper surface 41 of the package body 4 and exposed from the package body 4. The second surface 32 is exposed from the package body 4, and at least a portion of the second surface 32 is disposed above the first upper surface 41 of the package body 4. In some embodiments, as Fig.15 As shown in , the second surface 32 (e.g., the entire second surface 32) is disposed above the first upper surface 41 of the package body 4. The second upper surface 42 of the package body 4 is disposed below the second surface 32 of the first conductive segment 3c. The average roughness of the first surface 31 of the first conductive segment 3c is different from the average roughness of the second surface 32 of the first conductive segment 3c. In some embodiments, the average roughness of the first surface 31 of the first conductive segment 3c is less than the average roughness of the second surface 32 of the first conductive segment 3c. For example, the average roughness of the second surface 32 may be at least about 1.5 times, about 2 times, at least about 3 times, or at least about 5 times the average roughness of the first surface 31. For example, the average roughness of the first surface 31 may be less than about 20 nm, and the average roughness of the second surface 32 may be greater than about 40 nm. As Fig.15, a portion 34 of the first conductive segment 3c and a portion 34 of the second conductive segment 3d are exposed from the package body 4. The first portion 311 of the first surface 31 and the second surface 32 are surfaces of the exposed portion 34 of the first conductive segment 3c. The second conductive segment 3d also has a first surface 31 and a second surface 32. The first surface 31, the second surface 32 and the exposed portion 34 of the second conductive segment 3d are similar to the first surface 31, the second surface 32 and the exposed portion 34 of the first conductive segment 3c, and therefore are not described in detail. The first conductive segment 3c and the second conductive segment 3d may include a conductive metal, such as tin, aluminum, gold, silver or copper or an alloy thereof.

[0117] The RDL 5 is disposed on the package body 4, the first portion 311 of the first surface 31 of the first conductive segment 3c disposed above the first upper surface 41 of the package body 4, and the second surface 32 of the first conductive segment 3c. Similarly, the RDL 5 is also disposed on the first portion 311 of the first surface 31 of the second conductive segment 3d disposed above the first upper surface 41 of the package body 4, and the second surface 32 of the second conductive segment 3d. Fig.15 , the RDL 5 is disposed on both the first upper surface 41 and the second upper surface 42 of the package body 4. The RDL 5 covers the exposed portion 34 of the first conductive segment 3c and the exposed portion 34 of the second conductive segment 3d. The RDL 5 is disposed on and conforms to the first portion 311 of the first surface 31 of the first conductive segment 3c and the second surface 32 of the first conductive segment 3c. Similarly, the RDL 5 may also be disposed on and conforms to the first portion 311 of the first surface 31 of the second conductive segment 3d and the second surface 32 of the second conductive segment 3d. In some embodiments, the first conductive segment 3c connects the circuit layer 2 and the RDL 5, and the second conductive segment 3d connects the electronic component 6a and the RDL 5. For example, the second conductive segment 3d is connected to the conductive layer 65 of the electronic component 6a. Similar to the circuit layer 2, the RDL 5 may also include metal layers, including a fourth metal layer 51, a fifth metal layer 52, and a sixth metal layer 53. The fourth metal layer 51 and the fifth metal layer 52 may be seed layers and include titanium, copper, nickel, tungsten and / or platinum, or alloys thereof, and may be formed by sputtering. The sixth metal layer 53 may include copper, tin, gold, silver, nickel and / or palladium, or alloys thereof, and may be formed by electroplating, electroless plating or printing.

[0118] The passivation layer 12 is similar to Figures 1 to 3 At least a portion of the RDL 5 is exposed from the passivation layer 12 , and an upper solder connector 17 is provided in the passivation layer 12 and on the exposed portion of the RDL 5 .

[0119] In the packaged device (semiconductor device) 1f, since the second conductive segment 3d is connected to the passive surface 62 of the electronic component 6a, the second conductive segment 3d provides a heat dissipation function and an electrical grounding function. In the case where the electronic component 6a is a logic component, the solid structure of the logic component provides a strong reaction force during the formation of the bonding wire (e.g., the second conductive segment 3d), thereby enhancing the bonding between the second conductive segment 3d and the electronic component 6a.

[0120] Fig.16 A cross-sectional view of a packaged device (or semiconductor device) 1g according to some embodiments of the present disclosure is shown. The packaged device 1g is similar to Fig.15 The packaged device 1f shown in FIG. Fig.16 The package device 1g shown in FIG. 1 further includes an additional RDL 5a and an additional passivation layer 12a. The additional RDL 5a is disposed on the passivation layer 12 and is electrically connected to the RDL 5. The additional passivation layer 12a is disposed on the additional RDL 5a and the passivation layer 12, and at least a portion of the additional RDL 5a is exposed from the additional passivation layer 12a. The second UBM 14 is disposed on the exposed portion of the additional RDL 5a.

[0121] Fig.17 A cross-sectional view of a packaged device (or semiconductor device) 1h according to some embodiments of the present disclosure is shown. The packaged device 1h is similar to Fig.15 The packaged device 1f shown in FIG. Fig.17 The package device 1h shown in FIG. 4 further includes an underfill 15. The underfill 15 is disposed between the electronic component 6a and the circuit layer 2, and covers the first surface 61 of the electronic component 6a, the bump pad 66 and the solder joint 67. The underfill 15 is sealed in the package body 4.

[0122] Fig.18 A cross-sectional view of a packaged device (or semiconductor device) 1i according to some embodiments of the present disclosure is shown. The packaged device 1i is similar to Fig.15 The packaged device 1f shown in FIG. Fig.18 The electronic component 6a of the package device 1i shown in FIG. 1 further includes at least one bonding pad 68 disposed on the first surface 61 thereof and adhered to the outside of the dielectric layer 11 via an adhesive 69. Fig.18, the electronic component 6a includes a plurality of bonding pads 68. The adhesive 69 is disposed between the passive surface 62 of the electronic component 6a and the first surface 111 of the dielectric layer 11, and may cover a portion of the circuit layer 2. The second conductive segment 3d may be disposed on one of the plurality of bonding pads 68 of the electronic component 6a. In addition, the package device 1i may further include at least one additional bonding wire 3e, which connects the circuit layer 2 and another of the plurality of bonding pads 68 of the electronic component 6a.

[0123] Fig.19 A cross-sectional view of a packaged device (or semiconductor device) 1j according to some embodiments of the present disclosure is shown. The packaged device 1j is similar to Fig.15 The packaged device 1f shown in FIG. Fig.19 In addition to the package device 1j shown in FIG. 1 , the two electronic components 6a are separately (e.g., spaced apart from each other) disposed on the dielectric layer 11 and electrically connected to the circuit layer 2. In addition, the package device 1j further includes two second conductive segments 3d disposed on the two electronic components 6a, respectively. In some embodiments, the package device 1j may include more than two electronic components 6a and more than two second conductive segments 3d.

[0124] Fig. 20 A cross-sectional view of a packaged device (or semiconductor device) 1k according to some embodiments of the present disclosure is shown. The packaged device 1k is similar to Fig.15 The packaged device 1f shown in FIG. Fig. 20 The package device 1k shown in FIG. 1 includes two electronic components 6a sequentially arranged on the dielectric layer 11. The lower one of the two electronic components 6a is arranged on the dielectric layer 11 and is electrically connected to the circuit layer 2 via a bump pad 66 and a solder joint 67. The higher one of the two electronic components 6a is arranged on the lower one of the two electronic components 6a and is connected to the lower electronic component 6a via another bump pad 66a. The second conductive segment 3d is arranged on the higher one of the two electronic components 6a.

[0125] Figure 21 to Figure 47 Methods for manufacturing a packaged device according to some embodiments of the present disclosure are described. In some embodiments, the method is for manufacturing, for example, Figures 1 to 3 The packaging device of the packaging device 1 shown in FIG.

[0126] refer to Fig.21, providing a carrier 70. The carrier 70 may include, for example, a metal or glass material. The carrier 70 may optionally include a material layer or film disposed thereon, such as a thermal release material 701. Next, a first seed layer 71 and a second seed layer 72 are sequentially disposed on the thermal release material 701 of the carrier 70. The first seed layer 71 may include titanium, and the second seed layer may include copper. The first seed layer 71 and the second seed layer 72 may be formed by, for example, physical vapor deposition.

[0127] refer to Fig. 22 , a dielectric layer 11 is provided on the second seed layer 72. The dielectric layer 11 has an upper surface 111 and a lower surface 112 opposite to the upper surface 111, and the lower surface 112 is disposed on the second seed layer 72. The dielectric layer 11 may be a PID material, such as an epoxy resin or polyimide (PI) containing a photoinitiator, or a solder mask. Next, the dielectric layer 11 is exposed to a pattern of intense light. For example, a first mask 73a is disposed adjacent to the upper surface 111 of the dielectric layer 11 so as to cover a portion of the dielectric layer 11. Next, the dielectric layer 11 is exposed to a radiation source 74.

[0128] refer to Fig.23 , and then the dielectric layer 11 is developed by a developer. The dielectric layer 11 is patterned to form at least one through-hole 110, which penetrates the dielectric layer 11 and extends between the upper surface 111 and the lower surface 112. Then, a first metal layer 21 and a second metal layer 22 are sequentially disposed on the dielectric layer 11 and in the through-hole 110. The first metal layer 21 and the second metal layer 22 may be seed layers and include titanium, copper, nickel, tungsten and / or platinum, or alloys thereof, and may be formed by sputtering.

[0129] refer to Fig.24 , a first photoresist layer 75a is disposed on the second metal layer 22. Then, the first photoresist layer 75a is exposed to a strong light pattern. For example, a second photomask 73b is disposed adjacent to the first photoresist layer 75a so as to cover a portion of the first photoresist layer 75a. Then, the first photoresist layer 75a is exposed to the radiation source 74 or a different radiation source.

[0130] refer to Fig.25 , and then the first photoresist layer 75a is developed by a developer. The first photoresist layer 75a is patterned to expose a portion of the second metal layer 22. Then, a third metal layer 23 is formed in the first photoresist layer 75 and on the second metal layer 22. The third metal layer 23 may include copper, tin, gold, silver, nickel and / or palladium, or an alloy thereof, and may be formed by electroplating, electroless plating, or printing.

[0131] refer to Fig.26 , the first photoresist layer 75a is removed by, for example, stripping. Then, the portions of the first metal layer 21 and the second metal layer 22 that are not covered by the third metal layer 23 are removed by, for example, etching. Therefore, the circuit layer 2 is formed by and includes the first metal layer 21, the second metal layer 22, and the third metal layer 23. The circuit layer 2 may include at least one bump pad 24 disposed on the upper surface 111 of the dielectric layer 11 and at least one conductive via 26 disposed in the through hole 110 of the dielectric layer 11. In some embodiments, as Fig.26 As shown in FIG. 2 , the circuit layer 2 includes a first bump pad 24 a and a second bump pad 24 b .

[0132] refer to Fig. 27 , the stud portion 36 is disposed on and connected to the second bump pad 24b of the circuit layer 2. Next, a first bonding portion (e.g., ball bonding) of the bonding wire 30 is formed on and connected to the first bump pad 24a of the circuit layer 2 by using a capillary 76.

[0133] refer to Fig.28 , move the capillary 76 to the stud portion 36 on the second bump pad 24b, and form a second bonding portion (e.g., a wedge-shaped portion or a tail portion) of the bonding wire 30. The bonding wire 30 connects the first bump pad 24a and the second bump pad 24b, and is generally in the shape of a loop. The bonding wire 30 may include a conductive metal, such as tin, aluminum, gold, silver or copper, or an alloy thereof, and the stud portion 36 may also include a conductive metal, such as tin, aluminum, gold, silver or copper, or an alloy thereof. However, in other embodiments, the stud portion 36 may be omitted, and the bonding wire 30 may be directly connected to the second bump pad 24b. The bonding wire 30 has a first surface 301, which is generally annular in shape (e.g., Fig.32 Then, a plasma pretreatment is performed to clean and activate the surface of the dielectric layer 11.

[0134] refer to Fig.29, the carrier 70 and the components disposed thereon are disposed in the cavity of the mold 77. The bonding wire 30 is pressed so that the connection section 302 of the bonding wire 30 may be substantially straight and substantially parallel to the surface 771 of the mold 77. For example, a film 78 is disposed on the surface 771 of the mold 77. The film 78 may include an elastic polymer. The bonding wire 30 is pressed by the film 78 on the surface 771 of the mold 77 so that a portion 303 of the connection section 302 protrudes into the film 78. However, in other embodiments, the film 78 may be omitted, and the bonding wire 30 may be directly pressed by the mold 77. Then, an encapsulant material is provided in the cavity of the mold 77, and then the encapsulant material is cured to form the encapsulant 4. The encapsulant 4 may be an encapsulant compound, and is disposed on the upper surface 111 of the dielectric layer 11 and covers the circuit layer 2. In some embodiments, the material of the encapsulant 4 may be the same as or similar to the material of the dielectric layer 11. The package body 4 has a lower surface 43 disposed on the upper surface 111 of the dielectric layer 11 . The package body 4 seals the bonding wire 30 and exposes a portion 303 of the connecting section 302 .

[0135] refer to Fig.30 , and then the mold 77 and the film 78 are removed. Fig.31 illustrate Fig.30 An enlarged view of area 30A is shown in FIG. Fig.32 Instructions along the Fig.31 The cross-sectional view of line 30B-30B shown in FIG. Figures 30 to 32 As can be seen in FIG. 4 , a portion 303 of the connection section 302 of the bonding wire 30 is exposed from the package body 4 .

[0136] refer to Fig.33 , the connection section 302 of the bonding wire 30 is removed by, for example, etching. The bonding wire 30 is thus separated into two conductive sections, for example, the first conductive section 3a on the first bump pad 24a and the second conductive section 3b on the second bump pad 24b. Thus, the second surface 32 of the first conductive section 3a and the second surface 32 of the second conductive section 3b are formed. Fig.34 illustrate Fig.33 An enlarged view of area 33A is shown in FIG. Fig.35 Instructions along the Fig.34 The cross-sectional view of line 33B-33B shown in FIG. Figures 33 to 35, the first conductive segment 3a (and the second conductive segment 3b, which is similar to the first conductive segment 3a) have a first surface 31 and a second surface 32. For example, a portion of the first surface 301 of the bonding wire 30 forms the first surface 31 of the first conductive segment 3a, and another portion of the first surface 301 of the bonding wire 30 forms the first surface 31 of the second conductive segment 3b. The first surface 31 and the second surface 32 intersect each other. For example, the second surface 32 is a concave surface and is exposed from the package body 4. The first surface 31 is generally annular and extends from the periphery of the second surface 32. Since the first surface 31 of the first conductive segment 3a is formed by, for example, electroplating, and the second surface 32 of the first conductive segment 3b is formed by, for example, etching, the average roughness of the first surface 31 is different from the average roughness of the second surface 32. In some embodiments, the average roughness of the first surface 31 of the first conductive segment 3a is less than the average roughness of the second surface 32 of the first conductive segment 3a. For example, the average roughness of the second surface 32 may be at least about 1.5 times, about 2 times, at least about 3 times, or at least about 5 times the average roughness of the first surface 31. For example, the average roughness of the first surface 31 may be less than about 20 nm, and the average roughness of the second surface 32 may be greater than about 40 nm. Next, a portion of the package body 4 is removed by plasma treatment, for example using the plasma source 79.

[0137] refer to Fig.36 , after the plasma treatment, the portion of the package body 4 is removed. A first upper surface 41 of the package body 4 and a second upper surface 42 of the package body 4 (e.g., corresponding to the removed portion of the package body 4) are formed, and a first portion 311 of the first surface 31 of the first conductive segment 3a and a first portion 311 of the first surface 31 of the second conductive segment 3b are exposed from the package body 4. The first upper surface 41 and the second upper surface 42 of the package body 4 are not coplanar. For example, the first upper surface 41 is disposed above the second upper surface 42. In some embodiments, the first upper surface 41 is substantially flat, and the second upper surface 42 is substantially annular or disc-shaped. The second upper surface 42 intersects with the first upper surface 41 at both sides and is recessed from the first surface 41 to form a cavity 44. The cavity 44 is located between the first conductive segment 3a and the second conductive segment 3b. Fig.37 illustrate Fig.36 An enlarged view of area 36A is shown in FIG. Fig.38 Instructions along the Fig.37 A cross-sectional view of line 36B-36B shown in FIG. Figures 36 to 38 , the first portion 311 of the first surface 31 is exposed from the package body 4 and is disposed above the first surface 41 of the package body 4. The second surface 32 is exposed from the package body 4, and at least a portion of the second surface 32 is disposed above the first upper surface 41 of the package body 4. In some embodiments, as Fig.36 and 37 As shown in FIG. 1 , the second surface 32 (eg, the entire second surface 32) is disposed above the first upper surface 41 of the package body 4. The second upper surface 42 of the package body 4 is disposed below the second surface 32 of the first conductive segment 3a. Fig.36 and 37 As shown in FIG. 4 , a portion 34 of the first conductive segment 3a is exposed from the package body 4. The first portion 311 of the first surface 31 and the second surface 32 are surfaces of the exposed portion 34 of the first conductive segment 3a. The second conductive segment 3b also has a first surface 31 and a second surface 32 and includes an exposed portion 34. The first surface 31, the second surface 32 and the exposed portion 34 of the second conductive segment 3b are similar to the surfaces and portions of the first conductive segment 3a, and therefore are not described in detail.

[0138] refer to Fig.39 , a fourth metal layer 51 and a fifth metal layer 52 are disposed on the package body 4 and on the exposed portion 34 of each of the first conductive segment 3a and the second conductive segment 3b. The fourth metal layer 51 and the fifth metal layer 52 may be seed layers and include titanium, copper, nickel, tungsten and / or platinum, or alloys thereof, and may be formed by sputtering.

[0139] refer to Fig.40 , a second photoresist layer 75b is disposed on the fifth metal layer 52. Then, the second photoresist layer 75b is exposed to a strong light pattern. For example, a first photomask 73c is disposed adjacent to the second photoresist layer 75b so as to cover a portion of the second photoresist layer 75b. Then, the second photoresist layer 75b is exposed to the radiation source 74 or another radiation source.

[0140] refer to Fig.41 , and then the second photoresist layer 75b is developed by a developer. The second photoresist layer 75b is patterned to expose a portion of the fifth metal layer 52. Then, a sixth metal layer 53 is formed in the second photoresist layer 75b and on the fifth metal layer 52. The sixth metal layer 53 may include copper, tin, gold, silver, nickel and / or palladium, or an alloy thereof, and may be formed by electroplating, electroless plating, or printing.

[0141] refer to Fig.42 , the second photoresist layer 75b is removed by, for example, stripping. Then, the portions of the fourth metal layer 51 and the fifth metal layer 52 that are not covered by the sixth metal layer 53 are removed by, for example, etching. Thus, the RDL 5 is formed on the exposed portion 311 of the first surface 31 and the second surface 32 of each of the first conductive segment 3a and the second conductive segment 3b, and includes the fourth metal layer 51, the fifth metal layer 52, and the sixth metal layer 53. Fig.42As shown in , the RDL 5 is disposed on both the first upper surface 41 and the second upper surface 42 of the package body 4, and is disposed in the cavity 44 of the package body 4. The RDL 5 covers the exposed portion 34 of the first conductive segment 3a and the exposed portion 34 of the second conductive segment 3b. The RDL 5 is disposed on and conforms to the first portion 311 of the first surface 31 of the first conductive segment 3a and the second surface 32 of the first conductive segment 3a. Similarly, the RDL 5 may also be disposed on and conforms to the first portion 311 of the first surface 31 of the second conductive segment 3b and the second surface 32 of the second conductive segment 3b. In some embodiments, both the first conductive segment 3a and the second conductive segment 3b connect the circuit layer 2 and the RDL 5.

[0142] refer to Fig.43 , a passivation layer 12 is disposed on the package body 4 and covers the RDL 5. Then, the passivation layer 12 is exposed to a strong light pattern. For example, a second mask 73d is disposed adjacent to the passivation layer 12 so as to cover a portion of the passivation layer 12. Then, the passivation layer 12 is exposed to the radiation source 74 or another radiation source. The material of the passivation layer 12 can be the same as that of the dielectric layer 11.

[0143] refer to Fig.44 The passivation layer 12 is then developed by a developer to expose at least a portion of the RDL 5 for external connection. The passivation layer 12 is disposed on the first upper surface 41 of the package body 4, the RDL 5 and the second upper surface 42 of the package body 4. The passivation layer extends into the cavity 44 of the package body 4.

[0144] refer to Fig.45 , remove the carrier 70 and the thermal release material 701.

[0145] refer to Fig.46 , the first seed layer 71 and the second seed layer 72 are removed by, for example, etching.

[0146] refer to Fig.47 At least one first UBM 13 may be formed on one side of the conductive via 26 adjacent to the lower surface 112 of the dielectric layer 11. The first UBM 13 may include palladium and / or gold. At least one second UBM 14 may be formed on the exposed portion of the RDL 5. In some embodiments, the second UBM 14 includes a first layer 141 and a second layer 142. The first layer 141 includes nickel, and the second layer 142 includes palladium and / or gold. Next, a singulation process is performed, thereby forming a structure such as Figures 1 to 3 The packaging device 1 shown in FIG.

[0147] Figures 48 to 50 Methods for manufacturing a packaged device according to some embodiments of the present disclosure are described. In some embodiments, the method is for manufacturing, for example, Figures 4 to 6 The initial stage of the process described is the same or similar to Figure 21 to Figure 35 The stages described in . Fig.48 Depicted in Fig.35 The stage following the stage depicted in . Fig.49 illustrate Fig.48 An enlarged view of area 48A is shown in FIG. Fig.50 Instructions along the Fig.49 A cross-sectional view of line 48B-48B is shown in FIG.

[0148] refer to Figures 48 to 50 After the portion of the package body 4 is removed, a first upper surface 41 and a second upper surface 42 of the package body 4 are formed, and a first portion 311 of the first surface 31 of the first conductive segment 3a and a first portion 311 of the first surface 31 of the second conductive segment 3b are exposed from the package body 4. Fig.48 The removal of the package body 4 in the process described in Fig.36 In the process described in the figure, a portion of the second surface 32 of the first conductive segment 3a is removed, and thus a portion of the second surface 32 of the first conductive segment 3a is disposed above the first upper surface 41 of the package body 4. Another portion of the second surface 32 of the first conductive segment 3a is disposed below the first upper surface 41 of the package body 4. Similarly, a portion of the second surface 32 of the second conductive segment 3b is disposed above the first upper surface 41 of the package body 4, and another portion of the second surface 32 of the second conductive segment 3b is disposed below the first upper surface 41 of the package body 4. In the process described in the figure, Figures 48 to 50 The phase after the phase shown in Figure 39 to Figure 47 The stages described in Figures 4 to 6 The packaging device 1a shown in FIG.

[0149] Figure 51 to Figure 56 Methods for manufacturing a packaged device according to some embodiments of the present disclosure are described. In some embodiments, the method is for manufacturing, for example, Figures 7 to 9 The initial stage of the process described is the same or similar to Figure 21 to Figure 32 The stages described in . Fig.51 Depicted in Figures 30 to 32 The stage following the stage depicted in . Fig.52 illustrate Fig.51 An enlarged view of area 51A is shown in FIG. Fig.53 Instructions along the Fig.52 A cross-sectional view of line 51B-51B shown in FIG.

[0150] refer to Figures 51 to 53, before removing the connection section 302 of the bonding wire 30, a portion of the package body 4 is removed, thereby forming a first upper surface 41 of the package body 4. The portion of the package body 4 may be removed by, for example, plasma treatment. Figures 51 to 53 As shown in FIG. 4 , the first upper surface 41 of the package body 4 is disposed below the connection section 302 of the bonding wire 30, and the connection section 302 is exposed from the package body 4. The first upper surface 41 of the package body 4 may be substantially flat.

[0151] refer to Fig.54 , then the connecting section 302 of the bonding wire 30 is removed by, for example, etching. The bonding wire 30 is thus separated into two conductive sections, for example, a first conductive section 3a and a second conductive section 3b. A second surface 32 of the first conductive section 3a and a second surface 32 of the second conductive section 3b are formed. In addition, a second upper surface 42 of the package body 4 is formed between the first conductive section 3a and the second conductive section 3b. Fig.55 illustrate Fig.54 An enlarged view of area 54A is shown in FIG. Fig.56 Instructions along the Fig.55 The second upper surface 42 is generally annular or disc-shaped and is disposed above the first upper surface 41 of the package body 4. The second surfaces 32 of the first conductive segment 3a and the second conductive segment 3b connect the first upper surface 41 and the second upper surface 42 of the package body 4. Figures 54 to 56 As shown in FIG. 4 , the first surfaces 31 of the first conductive segment 3 a and the second conductive segment 3 b may be completely covered by the package body 4 .

[0152] The process described Figures 54 to 56 The phase after the phase shown in Figure 39 to Figure 47 The stages described in Figures 7 to 9 The packaged device 1b shown in FIG.

[0153] Figure 57 to Figure 62 Methods for manufacturing a packaged device according to some embodiments of the present disclosure are described. In some embodiments, the method is for manufacturing, for example, Figures 10 to 12 The initial stage of the process described is the same or similar to Figure 21 to Figure 32 The stages described in . Fig.57 Depicted in Figures 30 to 32 The stage following the stage depicted in . Fig.58 illustrate Fig.57 An enlarged view of area 57A is shown in FIG. Fig.59 Instructions along the Fig.58 A cross-sectional view of line 57B-57B is shown in FIG.

[0154] refer to Figures 57 to 59, before removing the connection section 302 of the bonding wire 30, a portion of the package body 4 is removed, thereby forming a first upper surface 41 of the package body 4. The portion of the package body 4 may be removed by, for example, plasma treatment. Figures 57 to 59 As shown in FIG. 4 , the package body 4 still covers a portion of the connecting section 302 of the bonding wire 30 .

[0155] refer to Fig.60 , then the connecting section 302 of the bonding wire 30 is removed by, for example, etching. The bonding wire 30 is thus separated into two conductive sections, for example, a first conductive section 3a and a second conductive section 3b. A second surface 32 of the first conductive section 3a and a second surface 32 of the second conductive section 3b are formed. In addition, a second upper surface 42 of the package body 4 is formed between the first conductive section 3a and the second conductive section 3b. Fig.61 illustrate Fig.60 An enlarged view of area 60A is shown in FIG. Fig.62 Instructions along the Fig.61 The second upper surface 42 is generally in the shape of a ring or a disk and is recessed from the first upper surface 41 of the package body 4. The second surfaces 32 of the first conductive segment 3a and the second conductive segment 3b connect the first upper surface 41 and the second upper surface 42 of the package body 4. Figures 60 to 62 As shown in FIG. 4 , the first surfaces 31 of the first conductive segment 3 a and the second conductive segment 3 b may be completely covered by the package body 4 .

[0156] The process described Figures 60 to 62 The phase after the phase shown in Figure 39 to Figure 47 The stages described in Figures 10 to 12 The packaging device 1c shown in FIG.

[0157] Figures 63 to 80 A method for manufacturing a packaged device (semiconductor device) according to some embodiments of the present disclosure is described. In some embodiments, the method is used to manufacture a packaged device (semiconductor device), such as Fig.15 The packaged device (semiconductor device) 1f shown in FIG.

[0158] refer to Fig.63, providing a carrier 70 including a thermal release material 701. A first seed layer 71 and a second seed layer 72 are sequentially disposed on the thermal release material 701 of the carrier 70. A dielectric layer 11 is provided on the second seed layer 72. The dielectric layer 11 has an upper surface 111 and a lower surface 112 opposite to the upper surface 111, and the lower surface 112 is disposed on the second seed layer 72. The dielectric layer 11 has at least one through-hole 110, which penetrates the dielectric layer 11 and extends between the upper surface 111 and the lower surface 112. A circuit layer 2 is formed on the second surface 111 of the dielectric layer 11 and in the through-hole 110, which includes a first metal layer 21, a second metal layer 22 and a third metal layer 23. The formation of the carrier 70, the thermal release material 701, the first seed layer 71, the second seed layer 72, the dielectric layer 11 and the circuit layer 2 may be the same or similar to Figure 21 to Figure 25 The stages described in .

[0159] refer to Fig.64 , connecting the electronic component 6a to the circuit layer 2. The electronic component 6a has a first surface 61 and a passive surface 62 opposite to the first surface 61. The electronic component 6a includes at least one bump pad 66 disposed on the first surface 61 and a conductive layer 65 disposed on the passive layer 62. The electronic component 6a further includes at least one solder joint 67, which is disposed between the bump pad 66 of the electronic component 6a and the corresponding conductive through hole 26 of the circuit layer 2. Therefore, the electronic component 6a can be electrically connected to the circuit layer 2 via the bump pad 66 and the solder joint 67.

[0160] refer to Fig.65 , a first bonding portion (eg, ball bonding) of the bonding wire 30 a is formed on and connected to the bump pad 24 of the circuit layer 2 by using the capillary 76 .

[0161] refer to Fig.66 , moving the capillary 76 to the conductive layer 65 on the passive surface 62 of the electronic component 6a, forming a second bonding portion (e.g., a wedge-shaped portion or a tail portion) of the bonding wire 30a. The bonding wire 30a connects the bump pad 24 and the conductive layer 65 of the electronic component 6a, and is generally in the shape of a loop. The bonding wire 30a may include a conductive metal, such as tin, aluminum, gold, silver, or copper, or an alloy thereof. In some other embodiments, the stud portion (e.g., Figure 1 The stud portion 36 shown in FIG. 1 may be provided on the conductive layer 65 of the electronic component 6a, and the bonding wire 30a may be connected to the conductive layer 65 via the stud portion 36 to enhance the bonding with the electronic component 6a. The bonding wire 30a has a first surface 301, which is generally annular. Fig.32 Next, a plasma pretreatment is performed to clean and activate the surface of the dielectric layer 11 .

[0162] refer to Fig.67, the carrier 70 and the components disposed thereon are disposed in the cavity of the mold 77. The bonding wire 30a is pressed so that the connection section 302 of the bonding wire 30 can be substantially straight and substantially parallel to the surface 771 of the mold 77. For example, a film 78 is disposed on the surface 771 of the mold 77. The film 78 may include an elastic polymer. The bonding wire 30a is pressed by the film 78 on the surface 771 of the mold so that a portion 303 of the connection section 302 protrudes into the film 78. However, in other embodiments, the film 78 may be omitted, and the bonding wire 30a may be directly pressed by the mold 77. Then, a packaging material is provided in the cavity of the mold 77, and then the packaging material is cured to form a package body 4. The package body 4 may be a packaging compound, and is disposed on the upper surface 111 of the dielectric layer 11 and covers the circuit layer 2. In some embodiments, the material of the package body 4 may be the same as or similar to the material of the dielectric layer 11. The package body 4 has a lower surface 43 disposed on the upper surface 111 of the dielectric layer 11. The package body 4 seals the bonding wire 30a.

[0163] refer to Fig.68 , and then the mold 77 and the film 78 are removed. As a result, a portion 303 of the connection section 302 of the bonding wire 30a is exposed from the package body 4.

[0164] refer to Fig.69, the connecting section 302 of the bonding wire 30a is removed by, for example, etching. The bonding wire 30a is thus separated into two conductive sections, such as a first conductive section 3c on the bump pad 24 and a second conductive section 3d on the electronic component 6a. Therefore, a second surface 32 of the first conductive section 3c and a second surface 32 of the second conductive section 3d are formed. The first conductive section 3c (and the second conductive section 3d, which are similar to the first conductive section 3c) have a first surface 31 and a second surface 32. For example, a portion of the first surface 301 of the bonding wire 30a forms the first surface 31 of the first conductive section 3c, and another portion of the first surface 301 of the bonding wire 30a forms the first surface 31 of the second conductive section 3d. The first surface 31 and the second surface 32 intersect each other. For example, the second surface 32 is a concave surface and is exposed from the package body 4. The first surface 31 is generally annular and extends from the periphery of the second surface 32. Since the first surface 31 of the first conductive segment 3c is formed by, for example, electroplating, and the second surface 32 of the first conductive segment 3c is formed by, for example, etching, the average roughness of the first surface 31 is different from the average roughness of the second surface 32. In some embodiments, the average roughness of the first surface 31 is less than the average roughness of the second surface 32. For example, the average roughness of the second surface 32 may be at least about 1.5 times, about 2 times, at least about 3 times, or at least about 5 times the average roughness of the first surface 31. For example, the average roughness of the first surface 31 may be less than about 20 nm, and the average roughness of the second surface 32 may be greater than about 40 nm. Next, a portion of the package body 4 is removed by plasma treatment, for example, using a plasma source 79.

[0165] refer to Fig.70 , after the plasma treatment, a portion of the package body 4 is removed. A first upper surface 41 and a second upper surface 42 of the package body 4 are formed, and a first portion 311 of the first surface 31 of the first conductive segment 3c and a first portion 311 of the first surface 31 of the second conductive segment 3d are exposed from the package body 4. The first upper surface 41 and the second upper surface 42 of the package body 4 are not coplanar. For example, the first upper surface 41 is disposed above the second upper surface 42. In some embodiments, the first upper surface 41 is substantially flat, and the second upper surface 42 is substantially annular or disc-shaped. The second upper surface 42 intersects with the first upper surface 41 at both sides and is recessed from the first surface 41 to form a cavity 44. The cavity 44 is located between the first conductive segment 3c and the second conductive segment 3d. The first portion 311 of the first surface 31 is exposed from the package body 4 and is disposed above the first surface 41 of the package body 4. The second surface 32 is exposed from the package body 4, and at least a portion of the second surface 32 is disposed above the first upper surface 41 of the package body 4. In some embodiments, as Fig.70As shown in FIG. 1 , the second surface 32 (eg, the entire second surface 32 ) is disposed above the first upper surface 41 of the package body 4 . The second upper surface 42 of the package body 4 is disposed below the second surface 32 of the first conductive segment 3 c . Fig.70 As shown in FIG. 4 , a portion 34 of the first conductive segment 3c is exposed from the package body 4. The first portion 311 of the first surface 31 and the second surface 32 are surfaces of the exposed portion 34 of the first conductive segment 3c. The second conductive segment 3d also has a first surface 31 and a second surface 32, and includes an exposed portion 34. The first surface 31, the second surface 32 of the second conductive segment 3d and the exposed portion 34 of the first surface 31, the second surface 32 and the exposed portion 34 are similar to the surfaces and the exposed portion of the first conductive segment 3c, and therefore are not described in detail.

[0166] refer to Fig.71 , a fourth metal layer 51 and a fifth metal layer 52 are disposed on the package body 4 and on the exposed portion 34 of each of the first conductive segment 3c and the second conductive segment 3d. The fourth metal layer 51 and the fifth metal layer 52 may be seed layers and include titanium, copper, nickel, tungsten and / or platinum, or alloys thereof, and may be formed by sputtering.

[0167] refer to Fig.72 , a third photoresist layer 75c is disposed on the fifth metal layer 52. The third photoresist layer 75c is then patterned to expose a portion of the fifth metal layer 52. Then, a sixth metal layer 53 is formed in the third photoresist layer 75c and on the fifth metal layer 52. The sixth metal layer 53 may include copper, tin, gold, silver, nickel and / or palladium, or an alloy thereof, and may be formed by electroplating, electroless plating, or printing.

[0168] refer to Fig.73 , the third photoresist layer 75c is removed by, for example, stripping. Then, the portions of the fourth metal layer 51 and the fifth metal layer 52 that are not covered by the sixth metal layer 53 are removed by, for example, etching. Thus, the RDL 5 is formed on the exposed portion 311 of the first surface 31 and the second surface 32 of each of the first conductive segment 3c and the second conductive segment 3d, and includes the fourth metal layer 51, the fifth metal layer 52, and the sixth metal layer 53. The formation of the RDL 5 may be the same as or similar to Figure 39 to Figure 41 The stages described in Fig.71As shown in , the RDL 5 is disposed on both the first upper surface 41 and the second upper surface 42 of the package body 4, and is disposed in the cavity 44 of the package body 4. The RDL 5 covers the exposed portion 34 of the first conductive segment 3c and the exposed portion 34 of the second conductive segment 3d. The RDL 5 is disposed on and conforms to the first portion 311 of the first surface 31 of the first conductive segment 3c and the second surface 32 of the first conductive segment 3c. Similarly, the RDL 5 may also be disposed on and conforms to the first portion 311 of the first surface 31 of the second conductive segment 3d and the second surface 32 of the second conductive segment 3d. In some embodiments, the first conductive segment 3c connects the circuit layer 2 and the RDL 5, and the second conductive segment 3d connects the conductive layer 65 of the electronic component 6a and the RDL 5.

[0169] refer to Fig.74 , a passivation layer 12 is disposed on the package body 4 and covers the RDL 5. Then, the passivation layer 12 is exposed to a strong light pattern. For example, a mask 73e is disposed adjacent to the passivation layer 12 so as to cover a portion of the passivation layer 12. Then, the passivation layer 12 is exposed to a radiation source 74.

[0170] refer to Fig.75 , and then the passivation layer 12 is developed by a developer, thereby forming a passivation layer 12, which exposes a portion of the RDL 5 for external connection. The passivation layer 12 is provided on the first upper surface 41 of the package body 4, the RDL 5 and the second upper surface 42 of the package body 4. The passivation layer 12 extends into the cavity 44 of the package body 4. The material of the passivation layer 12 can be the same as that of the dielectric layer 11. Then, at least one upper solder connector is provided in the passivation layer 12 and on the exposed portion of the RDL 5.

[0171] refer to Fig.76 , remove the carrier 70 and the thermal release material 701.

[0172] refer to Fig.77 , the first seed layer 71 and the second seed layer 72 are removed by, for example, etching. Then, an additional first metal layer 21a and an additional second metal layer 22a are disposed on the second surface 112 of the dielectric layer 11. The additional first metal layer 21a and the additional second metal layer 22a may be seed layers and include titanium, copper, nickel, tungsten and / or platinum, or alloys thereof, and may be formed by sputtering.

[0173] refer to Fig.78, forming a fourth photoresist 75d on the additional first metal layer 21a and the additional second metal layer 22a. Patterning the fourth photoresist layer 75d to expose a portion of the additional second metal layer 22a. Then, forming an additional third metal layer 23a in the fourth photoresist layer 75d and on the additional second metal layer 22a. The additional third metal layer 23a may include copper, tin, gold, silver, nickel and / or palladium, or an alloy thereof, and may be formed by electroplating, electroless plating or printing.

[0174] refer to Fig.79 , the fourth photoresist layer 75d is removed by, for example, stripping. Then, the portions of the additional first metal layer 21a and the additional second metal layer 22a that are not covered by the additional third metal layer 23a are removed by, for example, etching. Thus, an additional circuit layer 2a is formed on the second surface 112 of the dielectric layer 11 and is electrically connected to the circuit layer 2.

[0175] refer to Fig.80 A protective layer 18 is formed on the dielectric layer 11 and covers the additional circuit layer 2a. At least a portion of the additional circuit layer 2a is exposed from the protective layer 18. Then, at least one lower solder connector 19 is disposed in the protective layer 18 and on the exposed portion of the additional circuit layer 2a. Then, a singulation process is performed, thereby forming Fig.15 The packaging device 1f shown in FIG.

[0176] Unless otherwise specified, spatial descriptions such as "above", "below", "up", "left", "right", "lower", "top", "bottom", "vertical", "horizontal", "side", "above", "below", "upper", "on", "below", etc. are indicated relative to the orientation shown in the figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual implementations of the structures described herein may be spatially arranged in any orientation or manner, with the proviso that the advantages of the embodiments of the present disclosure are not deviated by such arrangements.

[0177] As used herein, the terms "substantially," "generally," "approximately," and "about" are used to describe and explain small variations. When used in conjunction with an event or circumstance, the terms may refer to situations in which the event or circumstance clearly occurred as well as situations in which the event or circumstance is very close to occurring. For example, when used in conjunction with a numerical value, the terms may refer to a range of variation of less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, two values ​​may be considered “substantially” the same or equal if the difference between them is less than or equal to ±10% of the average of the values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%).

[0178] Two surfaces may be considered coplanar or substantially coplanar if the displacement between the two surfaces is no greater than 5 μm, no greater than 2 μm, no greater than 1 μm, or no greater than 0.5 μm.

[0179] As used herein, the singular terms "a", "an", and "the" may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided "on" or "over" another component may encompass the case where the former component is directly on (e.g., in physical contact with) the latter component, as well as the case where one or more intervening components are located between the former component and the latter component.

[0180] As used herein, the terms "conductive," "electrically conductive," and "conductivity" refer to the ability to transmit an electric current. Conductive materials generally refer to those materials that exhibit little or no resistance to the flow of electric current. One measure of conductivity is Siemens / meter (S / m). Typically, a conductive material is one that has a conductivity greater than about 10 4 S / m (e.g. at least 10 5 S / m or at least 10 6 S / m). The conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the conductivity of a material is measured at room temperature.

[0181] In addition, amounts, ratios and other numerical values ​​are sometimes presented in this article in a range format. It should be understood that such a range format is for convenience and brevity, and should be flexibly understood to include not only the values ​​explicitly specified as range limits, but also all individual values ​​or sub-ranges contained within the range, as if each value and sub-range were explicitly specified.

[0182] Although the disclosure has been described and illustrated with reference to specific embodiments of the disclosure, these descriptions and illustrations are not restrictive. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the disclosure as defined by the appended claims. The description may not necessarily be drawn to scale. Due to manufacturing processes and tolerances, there may be differences between the artistic reproduction in the disclosure and the actual equipment. There may be other embodiments of the disclosure that are not specifically described. The description and drawings should be considered illustrative rather than restrictive. Modifications may be made to adapt specific situations, materials, material compositions, methods or processes to the goals, spirit and scope of the disclosure. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it should be understood that these operations may be combined, subdivided or reordered to form equivalent methods without departing from the teachings of the disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations on the disclosure.

Claims

1. A semiconductor device comprising: Circuit layer; A logic component, which is arranged on the circuit layer; a package encapsulating the logic component; A redistribution layer, which is disposed on the package body; A first conductive segment connecting the circuit layer and the redistribution layer, wherein a portion of the first conductive segment is exposed from the package body, and the redistribution layer covers the portion of the first conductive segment exposed from the package body; as well as a second conductive segment connecting the logic component and the redistribution layer, wherein a portion of the second conductive segment is exposed from the package body, and the redistribution layer covers the portion of the second conductive segment exposed from the package body; The package has a cavity located between the first conductive segment and the second conductive segment, and the redistribution layer extends into the cavity of the package. 2 . The semiconductor device according to claim 1 , wherein the logic component has an inactive surface and includes a conductive layer disposed on the inactive surface, and the second conductive segment is connected to the conductive layer of the logic component. 3 . The semiconductor device according to claim 1 , further comprising a passivation layer disposed on the package body and the redistribution layer, wherein the passivation layer extends into the cavity.

4. A method for manufacturing a packaging device, comprising: (a) forming a bonding wire having two first surfaces and including a connecting section between the two first surfaces; (b) providing a package to seal the bonding wire and expose a portion of the connection section of the bonding wire; (c) removing the connecting section of the bonding wire to separate the bonding wire into two conductive sections, and forming a second surface of each of the conductive sections; as well as (d) removing a portion of the package body to expose a first portion of the first surface of each of the conductive segments and forming a cavity of the package body between the two conductive segments. 5 . The method of claim 4 , wherein in (b), the method further comprises pressing the bonding wire so that the portion of the connection section of the bonding wire is exposed from the package body after (b). The method according to claim 5 , wherein in (b), the bonding wire is pressed by a mold. 7 . The method according to claim 5 , wherein in (b), the bonding line is pressed by a film on a mold surface. 8 . The method of claim 4 , wherein after (d), the method further comprises forming a redistribution layer on the first portion of the first surface and the second surface of each of the conductive segments. 9 . The method of claim 4 , wherein after (d), the method comprises forming a redistribution layer on the first surface and the second surface of each of the conductive segments and in the cavity of the package.

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