Display Panel

Abstract

The present invention relates to a display panel. The display panel includes: a first base substrate; a second base substrate facing the first base substrate; an insulating structure including a non-pad portion and a pad portion, the non-pad portion having an end aligned with the side surface of the second base substrate, and the pad portion having an end laterally recessed from the side surface of the second base substrate; pixels overlapping with a display area and arranged between the first base substrate and the second base substrate; signal lines located on the first base substrate and connected to the pixels; and a connecting pad, including a portion arranged in a connecting area, the connecting area being defined between the side surface of the second base substrate and the end of the pad portion. The signal line overlaps with the pad portion. The connecting pad contacts the signal line. The insulating structure is arranged between the first base substrate and the second base substrate, and overlaps with a non-display area outside the display area.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2018-0014662, filed on February 6, 2018, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0003] Example embodiments relate generally to display panels, and more particularly, to a display panel having a robust structure. Background Art

[0004] Typically, a display panel may be manufactured, and then a circuit board may be connected to the display panel, such as in a bezel area (or non-display area). For example, in a tape automated bonding (TAB) method, the circuit board may be bonded to the display panel using, for example, an anisotropic conductive film (ACF). However, it should be noted that various studies have been conducted on display panel design techniques for reducing the bezel area (or non-display area), and therefore, there is a need for an effective, economical technology that can improve structural integrity and reliably manufacture such a display device.

[0005] The above information disclosed in this section is only for understanding the background of the present inventive concept and therefore may contain information that does not constitute prior art. Summary of the invention

[0006] Some exemplary embodiments provide a display panel capable of improving electrical connection characteristics between a circuit board and a signal line.

[0007] Some exemplary embodiments provide a method of manufacturing a display panel capable of improving electrical connection characteristics between a circuit board and a signal line.

[0008] Additional aspects will be set forth in the detailed description which follows, and in part will be apparent from the disclosure, or may be learned by practice of the inventive concepts.

[0009] According to some exemplary embodiments, the display panel includes a first base substrate, a second base substrate, an insulating structure, a pixel, a signal line and a connecting pad. The second base substrate faces the first base substrate. The second base substrate includes a display area and a non-display area arranged outside the display area. The insulating structure includes a non-pad portion and a pad portion, the non-pad portion having an end aligned with the side surface of the second base substrate, and the pad portion having an end laterally recessed from the side surface of the second base substrate. The insulating structure is arranged between the first base substrate and the second base substrate and overlaps the non-display area. The pixel is arranged between the first base substrate and the second base substrate and overlaps the display area. The signal line is arranged on the first base substrate and electrically connected to the pixel. The signal line overlaps the pad portion. The connecting pad includes a portion arranged in a connection area defined between the side surface of the second base substrate and the end of the pad portion. The connecting pad contacts the signal line.

[0010] In some exemplary embodiments, an end of the signal line may be exposed from the insulating structure, and the exposed end of the signal line may be substantially aligned with a side surface of the first base substrate. The connection pad may contact the exposed end of the signal line.

[0011] In some exemplary embodiments, the insulating structure may include a plurality of organic layers.

[0012] In some exemplary embodiments, the pixel may include a first electrode, a second electrode insulated from the first electrode, a thin film transistor electrically connected to the first electrode and a signal line, and a liquid crystal layer disposed between the first electrode and the second electrode.

[0013] In some exemplary embodiments, the display panel may further include a color filter disposed between the first base substrate and the first electrode.

[0014] In some exemplary embodiments, a first organic layer closest to the signal line among the plurality of organic layers may include the same material as the color filter.

[0015] In some exemplary embodiments, the insulating structure may include a plurality of pad portions and a plurality of non-pad portions, the pad portion may be one of the plurality of pad portions, and the non-pad portion may be one of the plurality of non-pad portions. When viewed in a plan view, the plurality of pad portions and the plurality of non-pad portions may be arranged alternately.

[0016] In some exemplary embodiments, the display panel may include a spacer that overlaps the thin film transistor and maintains a gap in which the liquid crystal layer is disposed. A second organic layer of the plurality of organic layers that may be disposed on the first organic layer may include the same material as the spacer.

[0017] In some exemplary embodiments, the display panel may further include a black matrix partially overlapping the display area. The display area may include a transmission area overlapping the first electrode and a surrounding area overlapping the thin film transistor. The black matrix may overlap the surrounding area. The organic layer that may be arranged closest to the second base substrate among the plurality of organic layers may include the same material as the black matrix.

[0018] In some exemplary embodiments, the insulating structure may further include a plurality of inorganic layers. The thin film transistor may include a control electrode, a semiconductor pattern arranged on the control electrode, and an input electrode and an output electrode overlapping the semiconductor pattern and spaced apart from each other. A first inorganic layer among the plurality of inorganic layers that may be arranged closest to the signal line may directly cover the control electrode and the signal line.

[0019] In some exemplary embodiments, the plurality of organic layers may expose a portion of an upper surface of the first inorganic layer.

[0020] In some exemplary embodiments, the connection pad may contact an exposed portion of the upper surface of the first inorganic layer.

[0021] In some exemplary embodiments, a portion of an upper surface of the signal line may be exposed from the insulating structure, and the connection pad may contact the exposed portion of the upper surface of the signal line.

[0022] In some exemplary embodiments, the end of the non-pad portion may have a relatively flat surface compared to the end of the pad portion, and the end of the pad portion may have a groove shape.

[0023] In some exemplary embodiments, the signal line may be one of a plurality of signal lines, a first signal line and a second signal line among the plurality of signal lines may be separated from each other, the connecting pad may include a plurality of connecting pads, the plurality of connecting pads respectively overlap with the first signal line and the second signal line, the plurality of connecting pads may be separated from each other, and the connecting pad may expose a remaining portion of the upper surface of the first base substrate corresponding to the pad portion except for a portion of the upper surface of the first base substrate corresponding to the pad portion on which the plurality of connecting pads are arranged.

[0024] According to some exemplary embodiments, the display panel includes a first base substrate, a second base substrate, a pixel, a signal line, an insulating structure and a connection pad. The second base substrate faces the first base substrate and is separated from the first base substrate. The pixel is arranged between the first base substrate and the second base substrate. The signal line is arranged on the first base substrate and is electrically connected to the pixel. The insulating structure is arranged between the first base substrate and the second base substrate. The insulating structure includes a plurality of organic layers and a plurality of inorganic layers. The connection pad contacts the signal line and contacts a portion of the side surface of the insulating structure. The side surface of the insulating structure forms a step shape with each of the first base substrate and the second base substrate.

[0025] In some exemplary embodiments, the plurality of organic layers and the plurality of inorganic layers may include: a first inorganic layer adjacent to the signal line; a first organic layer disposed on the first inorganic layer; a second inorganic layer disposed on the first organic layer; a second organic layer disposed on the second inorganic layer; and a third organic layer disposed on the second organic layer. Ends of the plurality of organic layers and ends of the plurality of inorganic layers may form at least one stepped portion.

[0026] In some exemplary embodiments, an end portion of the first inorganic layer may be closer to a side surface of the first base substrate than an end portion of the first organic layer.

[0027] In some exemplary embodiments, at least a portion of the second inorganic layer may be exposed by the first and second organic layers, and at least a portion of the second inorganic layer exposed by the first and second organic layers may cover an end portion of the first organic layer.

[0028] In some exemplary embodiments, the first organic layer may have one of red, green, and blue.

[0029] In some exemplary embodiments, the third organic layer may have a black color.

[0030] In some exemplary embodiments, an end portion of the signal line may not be aligned with a side surface of the first base substrate and may be laterally recessed from the side surface of the first base substrate.

[0031] In some exemplary embodiments, the insulating material may be disposed in a space defined on an upper surface of the first base substrate between a side surface of the first base substrate and an end portion of the signal line.

[0032] In some exemplary embodiments, a portion of an upper surface of the signal line may be exposed by the insulating structure, and the connection pad may contact the exposed portion of the upper surface of the signal line.

[0033] In some exemplary embodiments, a portion of the upper surface of the signal line may be exposed by the insulating structure, a portion of the rear surface of the signal line may be separated from the upper surface of the first base substrate, and the connecting pad may contact the exposed portion of the upper surface of the signal line and the separated portion of the rear surface of the signal line.

[0034] The foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings, which are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the inventive concept and together with the description serve to explain the principles of the inventive concept.

[0036] Figure 1 is a perspective view illustrating a display device according to some exemplary embodiments.

[0037] Figure 2 is a plan view illustrating a display device according to some exemplary embodiments.

[0038] Figure 3 is an equivalent circuit diagram of a pixel according to some exemplary embodiments.

[0039] Figure 4 is a perspective view illustrating a display area of ​​a display panel according to some exemplary embodiments.

[0040] Figure 5 is a cross-sectional view illustrating a display area of ​​a display panel according to some exemplary embodiments.

[0041] Fig. 6A is a perspective view illustrating a side surface of a display panel according to some exemplary embodiments.

[0042] Figure 6B is a plan view illustrating a portion of a display panel according to some exemplary embodiments.

[0043] Fig. 7A , Figure 7B and Figure 7C is a cross-sectional view illustrating a non-display area of ​​a display panel according to some exemplary embodiments.

[0044] Fig. 8A and Figure 8B is a cross-sectional view illustrating a non-display area of ​​a display panel according to some exemplary embodiments.

[0045] Fig.9A , Fig. 9B , Fig. 9C and Fig.9D is a cross-sectional view illustrating a modified embodiment of an insulation structure in a non-display area of ​​a display panel according to some exemplary embodiments.

[0046] Fig. 10A , Fig. 10B , Fig. 10C and Fig. 10D is a cross-sectional view illustrating a modified embodiment of a signal line in a non-display area of ​​a display panel according to some exemplary embodiments.

[0047] Fig.11A , Fig. 11B and Fig. 11C is a cross-sectional view illustrating a non-display area of ​​a display panel according to some exemplary embodiments.

[0048] Fig. 12A , Fig. 12B , Fig. 12C , Fig.12D , Fig.12E , Fig.12F and Figure 12G are schematic diagrams illustrating a display panel at various stages of fabrication according to some exemplary embodiments. DETAILED DESCRIPTION

[0049] In the following description, for the purpose of illustration, many specific details are set forth to provide a thorough understanding of various exemplary embodiments. However, it is apparent that various exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other cases, well-known structures and devices are shown in the form of block diagrams to avoid unnecessary confusion of various exemplary embodiments. In addition, various exemplary embodiments may be different, but not necessarily exclusive. For example, the specific shape, configuration, and characteristics of an exemplary embodiment may be used or implemented in another exemplary embodiment without departing from the concept of the present invention.

[0050] Unless otherwise specified, the illustrated exemplary embodiments will be understood as providing exemplary features of different details of some exemplary embodiments. Therefore, unless otherwise specified, the various illustrated features, components, modules, layers, films, panels, regions, aspects, etc. (hereinafter individually or collectively referred to as "elements") may be combined, separated, interchanged and / or rearranged in other ways without departing from the concept of the present invention.

[0051] The use of cross hatching and / or shadows in the drawings is generally provided to make the boundaries between adjacent elements clear. Therefore, unless specified, the presence or absence of cross hatching or shadows does not express or indicate any preference or requirement for a specific material, material property, size, ratio, commonality between the illustrated elements, and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the drawings, for clarity and / or description purposes, the size and relative size of the elements can be exaggerated. In this way, the size and relative size of the corresponding elements are not necessarily limited to the size and relative size shown in the drawings. When the exemplary embodiment can be implemented differently, a specific process sequence different from the described sequence can be performed. For example, two processes described in succession can be performed substantially simultaneously, or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0052] When an element is referred to as being "on", "connected to" or "coupled to" another element, the element may be directly on the other element, directly connected to or coupled to the other element, or there may be intermediate elements. However, when an element is referred to as being "directly" "on", "directly connected to" or "directly coupled to" another element, there are no intermediate elements. Other terms and / or phrases used to describe the relationship between elements should be interpreted in a similar manner, for example, "between" versus "directly between", "adjacent" versus "directly adjacent", "on" versus "directly on", etc. In addition, the term "connected" may refer to physical, electrical and / or fluid connections. In addition, the DR1 axis, DR2 axis and DR3 axis are not limited to the three axes of a rectangular coordinate system, but may be interpreted in a broader sense. For example, the DR1 axis, DR2 axis and DR3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ. Unless the context clearly indicates otherwise, the term "or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0053] Although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0054] For descriptive purposes, spatially relative terms such as "below," "below," "below," "above," "above," "above," "side" (e.g., as in "sidewall"), and the like may be used herein to describe the relationship of one element to another element as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, an element described as being "below" or "beneath" other elements or features would subsequently be positioned "above" the other elements or features. Thus, the exemplary term "below" may encompass both above and below orientations. Furthermore, the device may be otherwise positioned (e.g., rotated 90 degrees or in other orientations), and therefore, the spatially relative descriptors used herein are interpreted accordingly.

[0055] The terms used herein are for the purpose of describing specific embodiments, and are not intended to be limiting. As used herein, the singular "one" and "the" are intended to also include plural forms, unless the context clearly states otherwise. In addition, when used in this specification, the terms "include" and / or "comprise" indicate that there are stated features, integral bodies, steps, operations, elements, parts and / or their groups, but do not exclude the presence or addition of one or more other features, integral bodies, steps, operations, elements, parts and / or their groups. It should also be noted that, as used herein, the terms "roughly", "approximately" and other similar terms are used as approximate terms and not as terms of degree, and are therefore used to explain the inherent deviations in the values ​​identified, measured, calculated and / or provided by those of ordinary skill in the art.

[0056] Various exemplary embodiments are described herein with reference to cross-sectional views, perspective views, plan views, and / or exploded illustrations, which are schematic illustrations of idealized exemplary embodiments and / or intermediate structures. As such, variations from the illustrated shapes may be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the exemplary embodiments disclosed herein should not be interpreted as limited to the shapes of the regions illustrated in the particular illustrations, but will include deviations in shape resulting from, for example, manufacturing. In this manner, the regions illustrated in the accompanying drawings are schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and are therefore not intended to be limiting.

[0057] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person of ordinary skill in the art to which this disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0058] As is common in the art, some exemplary embodiments are described and illustrated in the accompanying drawings with functional blocks, units and / or modules. It will be appreciated by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc., which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where blocks, units and / or modules are implemented by microprocessors or other similar hardware, software (e.g., microcode) can be used to program and control blocks, units and / or modules to perform the various functions discussed herein, and blocks, units and / or modules can be optionally driven by firmware and / or software. It is also contemplated that each block, unit and / or module can be implemented by dedicated hardware, or can be used as a combination of dedicated hardware to perform some functions and processors (e.g., one or more programmed microprocessors and related circuits) to perform other functions. Moreover, without departing from the concept of the present invention, each block, unit and / or module of some exemplary embodiments can be physically divided into two or more interacting and discrete blocks, units and / or modules. In addition, without departing from the concept of the present invention, the blocks, units and / or modules of some exemplary embodiments can be physically combined into more complex blocks, units and / or modules.

[0059] Various exemplary embodiments will now be described with reference to the accompanying drawings.

[0060] Figure 1 is a perspective view illustrating a display device according to some exemplary embodiments. Figure 2 is a plan view illustrating a display device according to some exemplary embodiments. Figure 3 is an equivalent circuit diagram of a pixel according to some exemplary embodiments. Figure 4 is a perspective view illustrating a display area of ​​a display panel according to some exemplary embodiments. Figure 5 is a cross-sectional view illustrating a display area of ​​a display panel according to some exemplary embodiments. Fig. 6A is a perspective view illustrating a side surface of a display panel according to some exemplary embodiments. Figure 6B is a plan view illustrating a portion of a display panel according to some exemplary embodiments.

[0061] refer to Figure 1 and Figure 2 , the display device DD includes a display panel DP, a gate driving unit (or gate driver) GDC, a data driving unit (or data driver) DDC, a main circuit board PB, and a signal controller SC. Even though not shown in the drawings, the display device DD may further include a chassis member or a mold member, and may further include a backlight unit according to the type of the display panel DP.

[0062] The display panel DP may be, but is not limited to, a liquid crystal display panel, a plasma display panel, an electrophoretic display panel, a micro-electromechanical system (MEMS) display panel, an electrowetting display panel, or the like.

[0063] The display panel DP may include a first display substrate 100 and a second display substrate 200 disposed on the first display substrate 100. Figure 1 Not shown in the figure, a gap may be formed between the first display substrate 100 and the second display substrate 200 .

[0064] like Figure 1 As shown, the display panel DP may display an image through the display surface DP-IS. The display surface DP-IS is parallel to a plane defined by the first direction axis DR1 and the second direction axis DR2. The display surface DP-IS may include a display area DA and a non-display area NDA. The non-display area NDA may be defined outside the display area DA. For example, the non-display area NDA may be defined along a boundary of the display surface DP-IS and may surround the display area DA.

[0065] The normal direction of the display surface DP-IS (e.g., the thickness direction of the display panel DP) is indicated by the third directional axis DR3. Hereinafter, the front surface (or upper surface) and the rear surface (or bottom surface) of each of the layers or units are defined by the third directional axis DR3 (or defined relative to the third directional axis DR3). However, as mentioned above, the first directional axis DR1, the second directional axis DR2, and the third directional axis DR3 illustrated in the various figures are merely examples, and the directions indicated by the first directional axis DR1, the second directional axis DR2, and the third directional axis DR3 may be relative concepts and may be changed to other directions. Hereinafter, the first direction to the third direction are directions indicated by the first directional axis DR1, the second directional axis DR2, and the third directional axis DR3, respectively, and are indicated by the same reference indicators as the first directional axis DR1, the second directional axis DR2, and the third directional axis DR3.

[0066] A display panel DP having a flat display surface DP-IS is illustrated as an example; however, exemplary embodiments are not limited thereto. In some exemplary embodiments, the display device DD may include a curved display surface or a three-dimensional (3D) display surface. A 3D display surface may include a plurality of display areas indicated by different directions.

[0067] The gate drive unit GDC and the data drive unit DDC may include circuit boards GCB and DCB and drive chips GC and DC, respectively. Each of the circuit boards GCB and DCB has a structure in which an insulating layer and a conductive layer are stacked. The conductive layer may include a plurality of signal lines. The gate drive unit GDC and the data drive unit DDC may be coupled to a side surface of the display panel DP so as to be electrically connected to the signal lines of the display panel DP. Since the gate drive unit GDC and the data drive unit DDC are coupled to the side surface of the display panel DP, the non-display area NDA may be reduced.

[0068] although Figure 1 The gate driving unit GDC and the data driving unit DDC are illustrated as being coupled to different side surfaces of the display panel DP, but the exemplary embodiments are not limited thereto. In some exemplary embodiments, one of the gate driving unit GDC and the data driving unit DDC may be omitted. In some exemplary embodiments, the gate driving unit GDC and the data driving unit DDC may be coupled to the same side surface of the display panel DP, or the gate driving unit GDC may be integrated on the display panel DP by an oxide silicon gate driver circuit (OSG) process, an amorphous silicon gate driver circuit (ASG) process, or any other suitable process.

[0069] The main circuit board PB may be connected to the circuit board DCB of the data driving unit DDC. The main circuit board PB may be electrically connected to the circuit board DCB of the data driving unit DDC through an anisotropic conductive film (ACF) or solder balls. The signal controller SC may be mounted on the main circuit board PB. The signal controller SC receives image data and control signals from, for example, an external graphic controller (not shown). The signal controller SC may provide control signals to the gate driving unit GDC and the data driving unit DDC.

[0070] In some exemplary embodiments, the display device DD may further include a main circuit board connected to the circuit board GCB of the gate driving unit GDC. In some exemplary embodiments, the driving chip DC of the data driving unit DDC may be mounted on the main circuit board PB.

[0071] Figure 1A shape is illustrated in which one data driving unit DDC among a plurality of data driving units DDC is spaced apart from one side surface of the display panel DP. A connection pad CP is arranged on the side surface of the display panel DP connected to the data driving unit DDC.

[0072] The connection pad CP may be provided in plural and may be spaced apart from each other along the first direction axis DR1. The connection pad CP may be connected to the pad DCB-P (see FIG. 1 ) disposed at the rear surface of the data driving unit DDC. Figure 8B ), to electrically connect the display panel DP and the data driving unit DDC. Each of the plurality of connection pads CP may be connected to a corresponding one of the signal lines PL-G and PL-D. The connection pads CP may also be applied to the connection portion between the gate driving unit GDC and the display panel DP. The connection pads CP may include a metal paste. The metal paste may include a mixture of a metal and an insulating material. The connection pads CP may include, for example, a silver paste.

[0073] The area in which the signal lines PL-G and PL-D are arranged may be defined as a pad portion PDA. An area separated from the pad portion PDA and in which the signal lines PL-G and PL-D are not arranged may be defined as a non-pad portion PDN. The connection pad CP and the display panel DP connected to the connection pad CP will be described in more detail later.

[0074] Figure 2 The diagram shows a planar arrangement of signal lines GL1 to GLn, DL1 to DLm, PL-G and PL-D and pixels PX11 to PXnm included in the display panel DP, where "n" and "m" are natural numbers greater than zero. It should be noted that "n" and "m" may be the same as or different from each other. The signal lines GL1 to GLn, DL1 to DLm, PL-G and PL-D may include a plurality of gate lines GL1 to GLn, a plurality of data lines DL1 to DLm, and auxiliary signal lines PL-G and PL-D.

[0075] The gate lines GL1 to GLn extend in the first direction DR1 and are arranged in the second direction DR2 (e.g., spaced apart from each other), and the data lines DL1 to DLm are insulated from and intersect the gate lines GL1 to GLn. In this way, the data lines DL1 to DLm extend in the second direction DR2 and are arranged in the first direction DR1.

[0076] The gate lines GL1 to GLn and the data lines DL1 to DLm may overlap the display area DA. The auxiliary signal lines PL-G and PL-D may overlap the non-display area NDA and may be connected to the gate lines GL1 to GLn and the data lines DL1 to DLm.

[0077] The first auxiliary signal lines PL-G connected to the gate lines GL1 to GLn may be arranged on the same layer as the gate lines GL1 to GLn. The first auxiliary signal lines PL-G and the gate lines GL1 to GLn connected to each other may constitute a single unitary body. The second auxiliary signal lines PL-D connected to the data lines DL1 to DLm may be arranged on a layer different from the layer on which the data lines DL1 to DLm are arranged. Each of the data lines DL1 to DLm may be electrically connected to a corresponding one of the second auxiliary signal lines PL-D through a contact hole CH, and the contact hole CH penetrates at least one insulating layer arranged between the second auxiliary signal line PL-D and the data lines DL1 to DLm.

[0078] In some exemplary embodiments, the contact hole CH may be omitted, and the data lines DL1 to DLm and the second auxiliary signal line PL-D may be arranged on the same layer. As described herein, the gate lines GL1 to GLn and the first auxiliary signal line PL-G are distinguished from each other; however, in some exemplary embodiments, the gate lines GL1 to GLn and the first auxiliary signal line PL-G connected to each other may be defined as one signal line. In this case, the gate lines GL1 to GLn and the first auxiliary signal line PL-G connected to each other may be defined as different parts of one signal line.

[0079] The signal lines GL1 to GLn, DL1 to DLm, PL-G, and PL-D may further include other signal lines (not shown). For example, the signal lines may further include signal lines (not shown) for electrically connecting the plurality of gate drive units GDC to each other and signal lines (not shown) for electrically connecting the plurality of gate drive units GDC to the main circuit board PB.

[0080] Each of the pixels PX11 to PXnm is connected to a corresponding one of the plurality of gate lines GL1 to GLn and a corresponding one of the plurality of data lines DL1 to DLm. Each of the pixels PX11 to PXnm may include a pixel driving circuit and a display element. Figure 2 1 and 2 are shown as being arranged in a matrix form as an example, but the exemplary embodiments are not limited thereto. In some exemplary embodiments, the pixels PX11 to PXnm may be arranged in a pentile form or any other suitable arrangement.

[0081] Figure 3An equivalent circuit diagram of a pixel PXij according to some exemplary embodiments is illustrated. The pixel PXij may include a thin film transistor TR (hereinafter referred to as a "transistor"), a liquid crystal capacitor Clc, and a storage capacitor Cst. The liquid crystal capacitor Clc may correspond to a display element, and the transistor TR and the storage capacitor Cst may constitute a pixel driving circuit. The number of transistors TR and storage capacitors Cst may vary according to an operation mode or design of a display panel DP (e.g., a liquid crystal display panel).

[0082] The liquid crystal capacitor Clc may store a pixel voltage output from the transistor TR. The arrangement of the liquid crystal directors contained in the liquid crystal layer LCL may be changed according to the amount of charge stored in the liquid crystal capacitor Clc. In other words, the liquid crystal directors may be controlled by an electric field formed, for example, between two electrodes of the liquid crystal capacitor Clc. Light incident to the liquid crystal layer LCL may be transmitted or blocked according to the arrangement of the liquid crystal directors.

[0083] The storage capacitor Cst is connected in parallel with the liquid crystal capacitor Clc. The storage capacitor Cst maintains the arrangement of the liquid crystal director for a certain period of time.

[0084] The transistor TR includes a control electrode GE connected to the i-th gate line GLi, an active portion AL overlapping the control electrode GE, an input electrode SE connected to the j-th data line DLj, and an output electrode DE spaced apart from the input electrode SE.

[0085] The liquid crystal capacitor Clc includes a pixel electrode PE and a common electrode CE. The storage capacitor Cst includes the pixel electrode PE and a portion of a storage line STL overlapping the pixel electrode PE.

[0086] Figure 4 The central portion of the display area DA according to some exemplary embodiments is partially illustrated. The display area DA may include a transmission area PXA and a peripheral area NPXA. The peripheral area NPXA may surround each of the transmission areas PXA and may correspond to a boundary area between the transmission areas PXA. The transmission areas PXA may be arranged in the same form as the pixels PX11 to PXnm.

[0087] The transmission area PXA may correspond to an area that substantially displays at least one color. The transmission area PXA may correspond to a transmission area in a transmission type display panel, or may correspond to an emitting area in an emitting display panel. The transmission areas PXA may be divided into a plurality of groups based on the color displayed by the transmission areas PXA. In other words, each of the transmission areas PXA may display one of the primary colors. The primary colors may include, for example, red, green, blue, and white; however, exemplary embodiments are not limited thereto.

[0088] A gap GP is defined between the first display substrate 100 and the second display substrate 200. Figure 2 The described signal lines GL1 to GLn, DL1 to DLm, PL-G, and PL-D may be included in one of the first display substrate 100 and the second display substrate 200 (or as a part of one of the first display substrate 100 and the second display substrate 200). The pixels PX11 to PXnm may be included in one of the first display substrate 100 and the second display substrate 200. Alternatively, some components of the pixels PX11 to PXnm may be included in the first display substrate 100, and other components of the pixels PX11 to PXnm may be included in the second display substrate 200. The pixels PX11 to PXnm may be arranged between the first base substrate BS1 of the first display substrate 100 and the second base substrate BS2 of the second display substrate 200.

[0089] like Figure 5 As shown, the i-th gate line GLi and the storage line STL are arranged on one surface of the first base substrate BS1 of the first display substrate 100. The control electrode GE is separated from the i-th gate line GLi. The i-th gate line GLi, the control electrode GE, and the storage line STL may include a metal (e.g., aluminum (Al), silver (Ag), copper (Cu), molybdenum (Mo), chromium (Cr), tantalum (Ta), or titanium (Ti)) or any alloy thereof; however, exemplary embodiments are not limited thereto. In some exemplary embodiments, the i-th gate line GLi, the control electrode GE, and the storage line STL may have a multilayer structure including, for example, a titanium layer and a copper layer.

[0090] The first base substrate BS1 may be a glass substrate or a plastic substrate. The first insulating layer 10 may be arranged on one surface of the first base substrate BS1 and may cover the control electrode GE and the storage line STL. The first insulating layer 10 may include at least one of an inorganic material or an organic material. For example, the first insulating layer 10 may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. In some exemplary embodiments, the first insulating layer 10 may have a multilayer structure including, for example, a silicon nitride layer and a silicon oxide layer.

[0091] The active portion AL overlapping the control electrode GE is disposed on the first insulating layer 10. The active portion AL may include a semiconductor layer SCL and an ohmic contact layer OCL. The semiconductor layer SCL is disposed on the first insulating layer 10, and the ohmic contact layer OCL is disposed on the semiconductor layer SCL.

[0092] The semiconductor layer SCL may include amorphous silicon or polycrystalline silicon. Alternatively, the semiconductor layer SCL may include a metal oxide semiconductor. The ohmic contact layer OCL may be doped with a dopant. The concentration of the dopant in the ohmic contact layer OCL may be higher than the concentration of the dopant in the semiconductor layer SCL. The ohmic contact layer OCL may include two parts separated from each other. In some exemplary embodiments, the ohmic contact layer OCL may have a single integral shape.

[0093] The output electrode DE and the input electrode SE are arranged on the active portion AL. The output electrode DE and the input electrode SE are spaced apart from each other. Each of the output electrode DE and the input electrode SE partially overlaps the control electrode GE.

[0094] The second insulating layer 20 is arranged on the first insulating layer 10 and covers the active portion AL, the output electrode DE and the input electrode SE. The second insulating layer 20 may include at least one of an inorganic material or an organic material. For example, the second insulating layer 20 may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer or an aluminum oxide layer. In some exemplary embodiments, the second insulating layer 20 may have a multilayer structure including, for example, a silicon nitride layer and a silicon oxide layer.

[0095] exist Figure 5 , the transistor TR having a staggered structure is illustrated as an example; however, the structure of the transistor TR is not limited thereto. In some exemplary embodiments, the transistor TR may have a planar structure.

[0096] The third insulating layer 30 is disposed on the second insulating layer 20. The third insulating layer 30 may be a single organic layer providing a flat surface. Figure 5 As can be seen in FIG. 1 , the third insulating layer 30 may include a plurality of color filters. The color filters may completely cover at least the transmission area PXA (see FIG. 1 ). Figure 4 ). Color filters of adjacent pixels may partially overlap each other in the peripheral area NPXA.

[0097] The color filter included in the third insulating layer 30 may overlap with the transmission area PXA. The color filter may include a color filter having at least two colors different from each other. Each color filter in the color filter may be an organic layer having red, green or blue. In some exemplary embodiments, the color filter may have four or more colors different from each other, and some of the adjacent color filters may have the same color. The color filter may be implemented as various embodiments and may not be limited to a specific embodiment.

[0098] The fourth insulating layer 40 is disposed on the third insulating layer 30. The fourth insulating layer 40 may be an inorganic layer covering the color filter. For example, the fourth insulating layer 40 may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. In some exemplary embodiments, the fourth insulating layer 40 may have a multilayer structure including, for example, a silicon nitride layer and a silicon oxide layer.

[0099] The pixel electrode PE is disposed on the fourth insulating layer 40. The pixel electrode PE is connected to the output electrode DE through a contact hole CH10 penetrating the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40. An alignment layer (not shown) covering the pixel electrode PE may be disposed on the fourth insulating layer 40.

[0100] The second base substrate BS2 of the second display substrate 200 may be a glass substrate or a plastic substrate. The black matrix BM is arranged on the bottom surface of the second base substrate BS2. The black matrix BM may have a shape similar to that of the surrounding area NPXA (see Figure 4 ) corresponding to the shape. The black matrix BM may be arranged to partially overlap the display area DA. In some exemplary embodiments, the black matrix BM may absorb light incident on the black matrix BM. Therefore, the black matrix BM may be a black organic layer.

[0101] At least one insulating layer covering the black matrix BM may be disposed on the bottom surface of the second base substrate BS2. The fifth insulating layer 50 providing a flat surface is exemplified in FIG. Figure 5 The fifth insulating layer 50 may include an organic material.

[0102] The common electrode CE is arranged on the bottom surface of the second base substrate BS2. A common voltage is applied to the common electrode CE. The value of the common voltage is different from the value of the pixel voltage. However, Figure 5 The cross section of the pixel PXij in FIG. 1 is illustrated only as an example. In some exemplary embodiments, the first display substrate 100 and the second display substrate 200 may be reversed.

[0103] For ease of description, a liquid crystal display panel in a vertical alignment (VA) mode will be described as an example; however, exemplary embodiments are not limited thereto. In some exemplary embodiments, the display panel DP may be a liquid crystal display panel in an in-plane switching (IPS) mode, a fringe field switching (FFS) mode, a plane-to-line switching (PLS) mode, a super vertical alignment (SVA) mode, a surface-stabilized vertical alignment (SS-VA) mode, or the like.

[0104] The spacer CS may be disposed between the first display substrate 100 and the second display substrate 200. The spacer CS maintains a gap GP (see FIG. 1 ) between the first display substrate 100 and the second display substrate 200. Figure 4). The spacer CS may include a photosensitive organic material. The spacer CS overlaps the peripheral area NPXA. The spacer CS may overlap the transistor TR.

[0105] Fig. 6A The pad portion PDA and the non-pad portion PDN defined along one side surface of the display panel DP according to some exemplary embodiments are illustrated. For ease of description and illustration, Figure 6B FIG. 1 shows a plan view in which the second base substrate BS2 and Fig. 6A Some components are omitted.

[0106] The display panel DP includes an insulating structure IS. Figure 5 The insulating layers 10 to 50, the spacers CS, and the black matrix BM of the pixel PXij described in the figure may extend into the non-display area NDA, and the insulating structure IS may include the insulating layers 10 to 50, the spacers CS, and the black matrix BM overlapping the non-display area NDA. Therefore, each of the layers of the insulating structure IS may include the same material as a corresponding one of the insulating layers 10 to 50, the spacers CS, and the black matrix BM as components of the pixel PXij.

[0107] Fig. 6A Organic layers are illustrated as some of the components included in the insulating structure IS. The organic layers of the insulating structure IS may include a bank member BL, a spacer CS, a fifth insulating layer 50, and a black matrix BM.

[0108] The dam member BL may include the same material as at least one of the color filters included in the third insulating layer 30. For example, the dam member BL may include the same material as the blue color filter.

[0109] An insulating structure IS may be disposed between the first base substrate BS1 and the second base substrate BS2 .

[0110] Since the insulating structure IS may overlap the non-display area NDA, the insulating structure IS may surround the edge of the display panel DP and may support a space formed between the first base substrate BS1 and the second base substrate BS2 .

[0111] The first and second base substrates BS1 and BS2 may respectively have side surfaces B1 and B2 defined along edges of the display panel DP.

[0112] The insulating structure IS includes a non-pad portion PDN having a non-pad end portion NS, which can be aligned with the side surface B2 of the second base substrate BS2. In addition, the insulating structure IS includes a pad portion PDA having a pad end portion PS that is laterally recessed from the side surface B2 of the second base substrate BS2 by a predetermined distance.

[0113] According to some exemplary embodiments, the insulating structure IS may include a plurality of pad portions PDA and a plurality of non-pad portions PDN. Figure 6B As shown, when viewed in a plan view, a plurality of pad portions PDA and a plurality of non-pad portions PDN may be alternately arranged in the insulating structure IS.

[0114] The pad portion PDA may overlap with a region in which the signal lines PL-G and PL-D are arranged. Fig. 6A Some of the signal lines PL of the signal lines PL-G and PL-D are illustrated in 6B and features and characteristics of the signal lines PL may be the same as those of the signal lines PL-G and PL-D.

[0115] A portion of the connection pad CP may be arranged in a connection area AS defined between the pad end portion PS and the side surfaces B1 and B2 of the first and second base substrates BS1 and BS2. Figure 6B As shown, the connection pad CP overlaps with the signal line PL and is in contact with the signal line PL.

[0116] A portion of the connection pad CP may overlap a portion of each of the side surfaces B1 and B2 of the first base substrate BS1 and the second base substrate BS2. According to some exemplary embodiments, a plurality of signal lines PL may be arranged to be spaced apart from each other in the pad portion PDA. When a plurality of signal lines PL are arranged, a plurality of connection pads CP respectively overlapping the signal lines PL may be arranged to be spaced apart from each other by a predetermined distance. Therefore, the upper surface of the first base substrate BS1 between the connection pads CP in the connection area AS may be exposed to the outside. According to some exemplary embodiments, since the connection pads CP respectively corresponding to the signal lines PL are spaced apart from each other, the connection pads CP may be electrically insulated from each other.

[0117] 7A to 7C is a cross-sectional view illustrating a non-display area NDA of a display panel DP according to some exemplary embodiments. For example, 7A to 7C Along Fig. 6A The invention is a cross-sectional view taken along section lines II', II-II' and III-III', and illustrates the non-pad portion PDN, an area of ​​the pad portion PDA where no signal line PL is arranged, and an area of ​​the pad portion PDA where the signal line PL is arranged.

[0118] The insulating structure IS includes a first insulating layer 10, a second insulating layer 20, a dam member BL, a fourth insulating layer 40, a spacer CS, a fifth insulating layer 50, and a black matrix BM. The second insulating layer 20 is arranged on the first insulating layer 10, and the dam member BL is arranged on the second insulating layer 20. The fourth insulating layer 40 is arranged on the dam member BL, and the fifth insulating layer 50 is arranged on the fourth insulating layer 40. The spacer CS may be arranged between the fourth insulating layer 40 and the fifth insulating layer 50, and the black matrix BM may be arranged between the fifth insulating layer 50 and the rear surface (e.g., bottom surface) of the second base substrate BS2. In some exemplary embodiments, the first insulating layer 10, the second insulating layer 20, and the fourth insulating layer 40 may be inorganic layers including inorganic materials, and the dam member BL, the spacer CS, the fifth insulating layer 50, and the black matrix BM may be organic layers including organic materials.

[0119] like Fig. 7A As shown, the non-pad end NS of the non-pad portion PDN of the insulating structure IS is substantially aligned with the side surfaces B1 and B2 of the base substrates BS1 and BS2. The side surfaces B1 and B2 aligned with each other and the non-pad end NS may be formed in a process of grinding the side surface of the cut display panel DP in the method of manufacturing the display panel, which will be described later. The non-pad portion PDN is an area where the signal line PL is not arranged, and therefore, in the cross section of the non-pad portion PDN, the signal line PL is not arranged on the first base substrate BS1.

[0120] like Figure 7B As shown, in the cross section of the pad portion PDA between the signal lines PL separated from each other, the pad end PS of the insulating structure IS can be laterally recessed from the side surfaces B1 and B2 of the base substrates BS1 and BS2 in the inner direction toward the display area DA to form a step shape.

[0121] like Figure 7C As shown, in the cross section of the signal line PL of the pad portion PDA, the pad end portion PS of the insulating structure IS may be laterally recessed from the side surfaces B1 and B2 of the base substrates BS1 and BS2 toward the inside adjacent to the display area DA to form a step shape. Figure 7C A cross section of a connection area AS including a signal line PL is illustrated, and thus, the signal line PL is disposed on the first base substrate BS1. An insulating structure IS is disposed on the signal line PL, and exposes a portion of the signal line PL.

[0122] One side surface of the display panel DP may include a reference Fig. 7A The multiple non-pad portions PDN described and referenced Figure 7B and Figure 7CThe plurality of pad portions PDA described above may be alternately arranged when viewed in a plan view.

[0123] According to some exemplary embodiments, the side surfaces B1 and B2, the non-pad end portion NS, and the pad end portion PS of the base substrates BS1 and BS2 are illustrated as flat surface shapes. However, the shapes of the side surfaces B1 and B2, the non-pad end portion NS, and the pad end portion PS may be modified according to manufacturing technology and / or tolerances. In other words, the side surfaces B1 and B2, the non-pad end portion NS, and the pad end portion PS may have uneven shapes and are not flat surface shapes.

[0124] Fig. 8A and Figure 8B 1 is a cross-sectional view illustrating a non-display area NDA of a display panel DP according to some exemplary embodiments. 6A to 7C The same or similar components will be referred to by the same or similar reference numerals or indicators, and descriptions of the same features as those mentioned above will be omitted.

[0125] like Fig. 8A As shown, a portion of the connection pad CP is arranged in Figure 7C A portion of the connection pad CP may overlap at least a portion of each of the side surfaces B1 and B2 of the base substrates BS1 and BS2.

[0126] A portion PLU of the upper surface of the signal line PL and an end PLS of the signal line PL are exposed by the insulating structure IS. The portion PLU of the upper surface of the signal line PL and the end PLS of the signal line PL exposed by the insulating structure IS are in contact with the connection pad CP. In some exemplary embodiments, the end PLS of the signal line PL may be substantially aligned with the side surface B1 of the first base substrate BS1; however, exemplary embodiments are not limited thereto.

[0127] like Figure 8B As shown, the connection pads CP can be electrically connected to the pads DCB-P of the circuit board DCB through an anisotropic conductive film (ACF). The anisotropic conductive film (ACF) can be replaced with solder paste, and the connection pads CP can be directly connected to the pads DCB-P of the circuit board DCB.

[0128] According to various exemplary embodiments, since the connection pads CP are arranged on the side surface of the display panel DP, the circuit boards GCB and / or DCB (see Figure 1) may be connected to the side surface of the display panel DP. Since the contact portion of the circuit board GCB and / or DCB with the display panel DP is limited on the side surface of the display panel DP, the area or size of the non-display area NDA may be reduced. In addition, the connection pad CP may be connected to a portion PLU of the upper surface of the signal line PL, and thus, the contact area between the signal line PL and the connection pad CP may be increased. As a result, the contact resistance of the circuit board GCB or DCB with the display panel DP may be reduced.

[0129] 9A to 9D 2 is a cross-sectional view illustrating a modified embodiment of the insulating structure IS in the non-display area NDA of the display panel DP according to some exemplary embodiments. 9A to 9D Various shapes of an insulation structure IS and a connection pad CP coupled to the insulation structure IS are illustrated. Fig.11A , Fig. 11B and Fig. 11C is a cross-sectional view showing a non-display area NDA of a display panel DP according to some exemplary embodiments. FIG. 6A to FIG. 8B The same or similar components will be referred to by the same or similar reference numerals or indicators, and descriptions of the same features as those mentioned above will be omitted.

[0130] like Fig.9A As shown, the pad end PS-1 of the insulating structure IS-1 has at least one step portion. For example, at least one of the ends of the inorganic layers 10-1, 20-1 and 40-1 and the organic layers BL-1, CS-1, 50-1 and BM-1 of the insulating structure IS-1 may be laterally recessed in the direction toward the display area DA from at least another of the ends of the inorganic layers 10-1, 20-1 and 40-1 and the organic layers BL-1, CS-1, 50-1 and BM-1. Therefore, when observed in a cross-sectional view, the inorganic layers 10-1, 20-1 and 40-1 and the organic layers BL-1, CS-1, 50-1 and BM-1 constituting the insulating structure IS-1 may include at least one or more step portions. The surface of the connecting pad CP-1 that is in direct contact with the pad end PS-1 of the insulating structure IS-1 may have a shape corresponding to the step shape of the pad end PS-1 of the insulating structure IS-1.

[0131] exist Fig.9AIn the embodiment, the side surfaces of the first insulating layer 10-1, the second insulating layer 20-1, the dam member BL-1 and the fourth insulating layer 40-1 are aligned with each other and are adjacent to the side surfaces B1 and B2 of the base substrates BS1 and BS2 (for example, recessed from the side surfaces B1 and B2 of the base substrates BS1 and BS2), and the side surfaces of the spacer CS-1 and the black matrix BM-1 are aligned with each other and are more recessed than the first insulating layer 10-1, the second insulating layer 20-1, the dam member BL-1 and the fourth insulating layer 40-1 in the direction toward the display area DA. In addition, the fifth insulating layer 50-1 may be more recessed than the spacer CS-1 and the black matrix BM-1 in the direction toward the display area DA. However, the step shape formed by the inorganic layers 10-1, 20-1 and 40-1 and the organic layers BL-1, CS-1, 50-1 and BM-1 is not limited to the above-mentioned step shape.

[0132] like Fig. 9B As shown, the pad end PS-2 of the insulating structure IS-2 may have a groove shape. For example, at least one of the inorganic layers 10-2, 20-2, and 40-2 of the insulating structure IS-2, and the ends of the organic layers BL-2, CS-2, and 50-2 and BM-2 has a groove shape. The groove shape may have an uneven shape at the pad end PS-2. Therefore, the pad end NS (see FIG. Fig. 7A ), the pad end portion PS-2 of the insulating structure IS-2 may have a relatively uneven surface. Compared with the pad end portion PS-2 of the insulating structure IS-2, the non-pad end portion NS may have a relatively flat surface.

[0133] The surface of the connection pad CP-2 directly contacting the pad end portion PS-2 of the insulation structure IS-2 may have a shape corresponding to the groove shape of the pad end portion PS-2 of the insulation structure IS-2.

[0134] Fig. 11B An example of the groove shape of the pad end PS-2 after performing an etching process on the pad end PS-2 of the insulating structure IS-2 in a real (or actual) manufacturing process is shown. However, the exemplary embodiments are not limited thereto. For example, the exemplary embodiments may include various uneven shapes of the pad end PS-2 that may be generated in an etching process or other manufacturing processes.

[0135] like Fig. 9CAs shown, at least one of the inorganic layers 10-3, 20-3, and 40-3 included in the insulating structure IS-3 may protrude from the organic layers BL-3, CS-3, 50-3, and BM-3. For example, the end ZS-3 of the first insulating layer 10-3 and the second insulating layer 20-3 may be substantially aligned with the side surface B1 of the first base substrate BS1-3 and the end PLS of the signal line PL. The plurality of organic layers BL-3, CS-3, 50-3, and BM-3 may expose a portion ZU-3 of the upper surface of the second insulating layer 20-3.

[0136] A portion 40-C of the fourth insulating layer 40-3 may be exposed by the dam member BL-3 and the spacer CS-3. The portion 40-C of the fourth insulating layer 40-3 may cover at least a portion of an end portion of the dam member BL-3.

[0137] like Fig. 9C As shown, the signal line PL is covered by the first insulating layer 10-3 and the second insulating layer 20-3 disposed on the first insulating layer 10-3. Therefore, a portion of the connection pad CP-3 contacts the exposed portion ZU-3 of the upper surface of the second insulating layer 20-3 and the end PLS of the signal line PL.

[0138] like Fig.9D As shown, the end ZS-4 of the first insulating layer 10-4 and the second insulating layer 20-4 is closer to the side surface B1 of the first base substrate BS1-4 than the end of the dam member BL-4. However, the end ZS-4 of the first insulating layer 10-4 and the second insulating layer 20-4 may be recessed from the side surface B1 of the first base substrate BS1-4 and may expose a portion PLU of the upper surface of the signal line PL.

[0139] A portion 40-D of the fourth insulating layer 40-4 may be exposed by the dam member BL-4 and the spacer CS-4. The portion 40-D of the fourth insulating layer 40-4 may cover at least a portion of an end portion of the dam member BL-4.

[0140] like Fig.9D As shown, at least one of the inorganic layers 10-4, 20-4 and 40-4 included in the insulating structure IS-4 may protrude from the organic layers BL-4, CS-4, 50-4 and BM-4. A portion of the connection pad CP-4 may contact the exposed portion PLU of the upper surface of the signal line PL, the end portion PLS of the signal line PL, and the exposed portion ZU-4 of the upper surface of the second insulating layer 20-4.

[0141] like 9A to 9DAs shown, in the method of manufacturing a display panel to be described later, the step portions and groove shapes of the inorganic layer and the organic layer and the shape of the inorganic layer covering at least a portion of the organic layer can be formed by the difference in material and thickness between the organic layer and the inorganic layer and / or the amount of plasma gas injected in the process of etching components of the insulating structure using plasma gas.

[0142] As used herein, the term "substantially aligned" may include a situation where the side surface of the insulating structure (e.g., insulating structure IS), the signal line (e.g., signal line PL), and the first base substrate and the second base substrate (e.g., first base substrate BS1 and second base substrate BS2) are coplanar with each other. In addition, the term "substantially aligned" may also include variations as a result of manufacturing technology and / or process tolerances. For example, the side surface (or end) of the signal line (e.g., signal line PL) may have a surface that is smoothed by a grinder YM (see Fig. 12C The corners of the curved side surfaces defining the signal line may be aligned with the corners of the side surfaces defining the insulating structure.

[0143] FIG. 10A to FIG. 10D is a cross-sectional view illustrating a modified embodiment of a signal line in a non-display area of ​​a display panel according to some exemplary embodiments. As mentioned previously, Fig.11A , Fig. 11B and Fig. 11C is a cross-sectional view showing a non-display area of ​​a display panel according to some exemplary embodiments. For example, Fig.11A and Fig. 11C 1 shows a modified embodiment that may occur in the process of polishing the signal line according to some exemplary embodiments. Fig. 8A The same or similar components will be referred to by the same or similar reference numerals or indicators, and descriptions of the same features as those mentioned above will be omitted.

[0144] like Fig. 10A As shown, the insulating structure IS may expose a portion PLU-A of the upper surface of the signal line PL-A on the first base substrate BS1. The end PLS-A of the signal line PL-A may be laterally recessed from the side surface B1 of the first base substrate BS1 in an inner direction toward the display area DA. Therefore, the end PLS-A of the signal line PL-A may not be aligned with the side surface B1 of the first base substrate BS1. In this way, a portion of the connection pad CP-5 may contact the portion PLU-A of the upper surface of the signal line PL-A and the end PLS-A of the signal line PL-A.

[0145] like Fig. 10BAs shown, the insulating structure IS may expose a portion PLU-B of the upper surface of the signal line PL-B on the first base substrate BS1. The insulating material MU may be arranged in a space OP defined between the side surface B1 of the first base substrate BS1 and the end PLS-B of the signal line PL-B. In this way, a portion of the connection pad CP-6 may contact the portion PLU-B of the upper surface of the signal line PL-B and the insulating material MU.

[0146] In a manufacturing method to be described later, the display panel may be cut, and then, the side surfaces of the first and second base substrates BS1 and BS2, the signal lines PL-B, and the insulating structure IS may be polished by a polishing machine YM (see Fig. 12C ) is polished. In this process, a portion of the end portion of the signal line PL-B may be removed by the rotational force of the polisher YM, and the inorganic layers 10, 20, and 40 of the insulating structure IS and the foreign materials of the organic layers BL, CS, 50, and BM may be arranged in the space OP, thereby forming the insulating material MU. The insulating material MU may be coupled to the connection pad CP-6. Fig. 11C An example is shown in which the insulating material MU generated in the real grinding process is arranged between the side surface B1 of the first base substrate BS1 and the end portion PLS-B of the signal line PL-B.

[0147] like Fig. 10C As shown, the end PLS-C of the signal line PL-C can be substantially aligned with the side surface B1 of the first base substrate BS1. The tip of the end PLS-C aligned with the side surface B1 of the first base substrate BS1 may include a protrusion PLP. The signal line PL-C may be in direct contact with the grinder YM during the grinding process, and therefore, the protrusion PLP may be formed. During the grinding process, friction may be generated between the end PLS-C of the signal line PL-C and the grinder YM by the rotational force of the grinder YM. In this way, a portion of the end PLS-C of the signal line PL-C may be plastically deformed to form the protrusion PLP. In addition, a portion of the connecting pad CP-7 may be in contact with a portion PLU-C of the upper surface of the signal line PL-C and the end PLS-C of the signal line PL-C.

[0148] like Fig. 10D As shown, the insulating structure IS may expose a portion PLU-D of an upper surface of the signal line PL-D on the first base substrate BS1. A portion of a rear surface PLB-D of the signal line PL-D may be spaced apart from the upper surface of the first base substrate BS1.

[0149] A portion of the connection pad CP-8 may contact a portion of the end surface PLS-D and an exposed portion PLU-D of the upper surface of the signal line PL-D and an exposed portion of the rear surface PLB-D of the signal line PL-D.

[0150] Fig.11A An example is shown in which a portion of the back surface PLB-D of the signal line PL-D is separated from the upper surface of the first base substrate BS1 by the rotational force of the grinder YM in the actual grinding process.

[0151] FIG. 12A to FIG. 12G is a schematic diagram illustrating a display panel at various stages of manufacture according to some exemplary embodiments. FIG. 12A to FIG. 12G A method for manufacturing a display device DD is described. Figures 1 to 8B The same components will be referred to by the same reference numerals or indicators, and descriptions of the same features as those described above will be omitted.

[0152] Fig. 12A is a perspective view illustrating a work panel WP used in a method of manufacturing a display panel DP according to some exemplary embodiments. Fig. 12B is a cross-sectional view illustrating a working panel WP used in a method of manufacturing a display panel DP according to some exemplary embodiments. Fig. 12C and Fig.12D The diagram is from Fig. 12B The cross-sectional view of the initial display panel DPA cut by the working panel WP is shown. FIG. 12E to FIG. 12G is a cross-sectional view illustrating an operation of connecting the connection pad CP to the display panel DP.

[0153] like Fig. 12A As shown, the same process may be performed on a plurality of unit regions DP-C defined in the working panel WP to form a display panel DP in each of the unit regions DP-C (see FIG. Figures 1 to 6B ). For example, the first working substrate 100-W and the second working substrate 200-W may be coupled to each other to form a working panel WP. The first working substrate 100-W in each unit area in the unit area DP-C may have a Figures 5 to 6B The first display substrate 100 described above has the same structure, and the second working substrate 200-W in each unit area in the unit area DP-C may have the same structure as the reference 1. Figures 5 to 6B The second display substrate 200 has the same structure as described above.

[0154] like Fig. 12BAs shown, the structures of the cell area DP-C may extend into the boundary area BA of the working panel WP so as to be connected to each other. The boundary area BA may overlap the non-display area NDA. The working panel WP may be formed along the boundary area BA by, for example, a scribing process. Fig. 12B The cutting line CL shown is cut, and therefore, the initial display panel DPA (each of the initial display panels DPA) Fig. 12C ) can be separated from each other.

[0155] and Fig. 6A Compared with the non-pad end NS of the non-pad portion PDN of the display panel DP, Fig. 12C The side surface of the initial display panel DPA shown may be uneven. The side surface of the initial display panel DPA is polished using a grinder YM (e.g., a grinding process). The end of the insulating structure IS, the end of the signal line PL, the side surface of the first base substrate BS1, and the side surface of the second base substrate BS2 may be substantially aligned with each other through a grinding process. The shape of the end of the signal line PL may change according to the grinding method (e.g., the rotation direction of the grinder YM). However, the end of the signal line PL and the side surface of the first base substrate BS1 may be substantially aligned with each other, regardless of the grinding method. Fig. 10C , Fig. 10D and Fig.11A The diagram shows Fig. 12C An example of an end portion of the signal line PL formed in the rotation direction of the grinder YM is shown.

[0156] As mentioned above, the term "substantially aligned" may include a situation where the ends of the insulating structure IS, the ends of the signal lines PL, the side surfaces of the first base substrate BS1, and the side surfaces 2 of the second base substrate BS2 are coplanar with each other. In addition, the term "substantially aligned" may also include variations as a result of manufacturing technology and / or process tolerances. For example, the side surface (or end) of the signal line PL may have a fine curved surface formed by a grinder YM. The corners defining the curved side surfaces of the signal line PL may be aligned with the corners defining the side surfaces of the insulating structure IS.

[0157] The insulating structure IS can prevent the ends of the signal lines PL from being damaged and / or deformed during the grinding process. This may be because the insulating structure IS supports the first display substrate 100 and the second display substrate 200 to prevent the side surface of the display panel DP from being damaged / deformed due to friction of the grinder YM.

[0158] FIG. 10A to FIG. 10D Various shapes of an end portion (eg, end portion PLS) of a signal line (eg, signal line PL) that can be formed through a grinding process are illustrated. Fig. 10A A shape is illustrated in which a portion of the signal line PL-A is removed by a grinding process. Fig. 10B A shape is illustrated in which the insulating material MU corresponding to the residue is arranged in the space OP formed by removing a portion of the signal line PL-B and is coupled to the connection pad CP-6. Fig. 10C A shape is illustrated in which the protrusion PLP of the signal line PL-C is formed by the friction force between the signal line PL-C and the grinder YM. Fig. 10D The diagram illustrates a shape in which a portion of the rear surface PLB-D of the signal line PL-D is separated from the upper surface of the first base substrate BS1 by direct contact between the grinder YM and the signal line PL-D, and the connection pad CP-8 is arranged in the space between the signal line PL-D and the first base substrate BS1.

[0159] like Fig.12D As shown, an etching process may be performed to remove the pad portion PDA of the insulating structure IS and the initial display panel DPA (see Figure 1 ) corresponding part. The etching process uses plasma gas PG. Plasma gas PG may mean an ionized gas state including ions, electrons and free radicals. Plasma gas PG may be generated by high temperature, strong electric field and / or radio frequency (RF) electromagnetic field. The organic layer and / or inorganic layer may be selectively etched according to the type of plasma gas PG.

[0160] The plasma gas PG for etching or removing the organic layers BL, CS, 50, and BM of the insulating structure IS may include argon (Ar), oxygen (O 2 ) and nitrogen oxides (N X O Y ). In addition, the plasma gas PG for etching or removing the inorganic layers 10, 20, and 40 of the insulating structure IS may include a chlorine-based gas (eg, BCl 3 ) and fluorocarbon-based gases (e.g., CF 4 , C 3 F 8 , C 4 F 8 or CHF 3 ). Therefore, the plasma gas PG may be selectively injected to remove the organic layers BL, CS, 50 and BM and / or the inorganic layers 10 , 20 and 40 .

[0161] The plasma gas PG for removing the organic layers BL, CS, 50, and BM and the plasma gas PG for removing the inorganic layers 10, 20, and 40 may be mixed with each other and may be injected to etch the insulating structure IS, and thus, a Fig.9A and / or Fig. 9B The insulation structures IS-1 and IS-2 have pad ends PS-1 and PS-2.

[0162] In some exemplary embodiments, only the plasma gas PG for removing the organic layers BL, CS, 50, and BM may be injected, or the flow rate of the plasma gas PG for removing the inorganic layers 10, 20, and 40 may be relatively reduced. In these cases, at least a portion of the inorganic layers 10, 20, and 40 may be exposed from the organic layers BL, CS, 50, and BM to remain at the pad end portion PS of the insulating structure IS. Fig. 9C and Fig.9D Examples of these situations are illustrated.

[0163] like Fig.12E and Fig.12F As shown, after the etching process, the connection pad CP may be arranged to correspond to the space defined by the side surfaces B1 and B2 of the base substrates BS1 and BS2 and the pad end PS of the insulating structure IS. Thereafter, an external pressure TL may be applied to the connection pad CP (for example, using an optical process) to contact the connection pad CP with the insulating structure IS. At this time, the connection pad CP may be formed of a metal paste, and therefore, the metal contained in the connection pad CP may be electrically contacted with the signal line PL through a capillary phenomenon (or force).

[0164] like Figure 12G As shown, a portion of the connection pad CP may be sintered by the laser LS, and thus, the connection pad CP connected to the plurality of signal lines PL may be divided into a plurality of connection pads CP spaced apart from each other, as shown in FIG. Fig. 6A As a result, electrical connection between the signal lines PL separated from each other can be prevented, and the connection pads CP can be connected to the signal lines PL, respectively. Fig. 6A As shown, the connection pads CP respectively overlapping the signal lines PL may expose a portion of the upper surface of the first base substrate BS1 and a portion of the rear surface of the second base substrate BS2 overlapping the first base substrate BS1 .

[0165] According to various exemplary embodiments, since the connection pads CP are arranged on the side surface of the display panel DP, the circuit boards GCB and / or DCB (see Figure 1 ) can be connected to the side surface of the display panel DP. Since the connection area between the circuit board GCB and / or DCB and the display panel DP is limited on the side surface of the display panel DP, the area or size of the non-display area NDA can be reduced. In addition, since the contact area between the connection pad CP and the signal line PL is fully guaranteed, the contact resistance between the display panel DP and the circuit board GCB or DCB can be reduced.

[0166] Although specific exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to such embodiments, but rather to the broader scope of the appended claims and to various obvious modifications and equivalent arrangements that will be apparent to those of ordinary skill in the art.

Claims

1. A display panel, include: a first base substrate; a second base substrate facing the first base substrate, the second base substrate including a display area and a non-display area arranged outside the display area; an insulating structure, arranged between the first base substrate and the second base substrate, extending from a layer overlapping the display area and overlapping the non-display area, the insulating structure comprising: a non-pad portion having an end portion extending from a side surface of the first base substrate to a side surface of the second base substrate and aligned with the side surface of the second base substrate; and a pad portion having an end portion laterally recessed from the side surface of the second base substrate; pixels, arranged between the first base substrate and the second base substrate and overlapping the display area; a signal line disposed on the first base substrate and connected to the pixel, the signal line partially overlapping the pad; and a connecting pad including a portion arranged in a connection area defined between the side surface of the second base substrate and the end of the pad portion, the connecting pad being in contact with the signal line, The end portion of the non-pad portion has a relatively flat surface compared to the end portion of the pad portion.

2. The display panel according to claim 1, in: An end portion of the signal line is exposed from the insulating structure, the exposed end portion of the signal line being aligned with the side surface of the first base substrate; and The connection pad contacts the exposed end portion of the signal line.

3. The display panel according to claim 1, in, The insulating structure includes a plurality of organic layers.

4. The display panel according to claim 3, wherein the pixel include: a first electrode; a second electrode insulated from the first electrode; a thin film transistor electrically connected to the first electrode and the signal line; as well as A liquid crystal layer is disposed between the first electrode and the second electrode.

5. The display panel according to claim 4, further comprising: include: A color filter is disposed between the first base substrate and the first electrode.

6. The display panel according to claim 5, in, A first organic layer among the plurality of organic layers, which is closest to the signal line, includes the same material as the color filter.

7. The display panel according to claim 6, in: The insulating structure includes a plurality of pad portions and a plurality of non-pad portions, the pad portion is one of the plurality of pad portions, and the non-pad portion is one of the plurality of non-pad portions; and The plurality of pad portions and the plurality of non-pad portions are alternately arranged when viewed in a plan view.

8. The display panel according to claim 6, further comprising: include: a spacer overlapping the thin film transistor and maintaining a gap, wherein the liquid crystal layer is arranged in the gap, The second organic layer disposed on the first organic layer among the plurality of organic layers includes a same material as the spacer.

9. The display panel according to claim 4, further comprising: include: a black matrix partially overlapping the display area, in: The display area includes a transmission area overlapping with the first electrode and a peripheral area overlapping with the thin film transistor; The black matrix overlaps the surrounding area, and An organic layer among the plurality of organic layers disposed closest to the second base substrate includes the same material as the black matrix.

10. The display panel according to claim 4, in: The insulating structure further comprises a plurality of inorganic layers; The thin film transistor comprises: Control electrode; a semiconductor pattern disposed on the control electrode; and an input electrode and an output electrode overlapping the semiconductor pattern and spaced apart from each other; and A first inorganic layer among the plurality of inorganic layers, which is arranged closest to the signal line, directly covers the control electrode and the signal line.

11. The display panel according to claim 10, in, The plurality of organic layers expose a portion of an upper surface of the first inorganic layer.

12. The display panel according to claim 11, in, The connection pad contacts the exposed portion of the upper surface of the first inorganic layer.

13. The display panel according to claim 1, in: A portion of an upper surface of the signal line is exposed from the insulating structure; and The connection pad contacts the exposed portion of the upper surface of the signal line.

14. The display panel according to claim 1, in: The end portion of the pad portion has a groove shape.

15. The display panel according to claim 1, in: The signal line is one of a plurality of signal lines; A first signal line and a second signal line of the plurality of signal lines are separated from each other; The connection pads include a plurality of connection pads, the plurality of connection pads overlap the first signal line and the second signal line respectively, and the plurality of connection pads are spaced apart from each other; and The connection pads expose a remaining portion of the upper surface of the first base substrate corresponding to the pad portion except for a portion of the upper surface of the first base substrate corresponding to the pad portion where the plurality of connection pads are arranged.

16. A display panel, include: a first base substrate; a second base substrate facing the first base substrate and spaced apart from the first base substrate, the second base substrate including a display area and a non-display area arranged outside the display area; pixels, arranged between the first base substrate and the second base substrate; a signal line disposed on the first base substrate and electrically connected to the pixel; an insulating structure disposed between the first base substrate and the second base substrate and extending from a layer overlapping the display area, the insulating structure including a plurality of organic layers and a plurality of inorganic layers, and having a non-pad portion and a pad portion, the non-pad portion having an end portion extending from a side surface of the first base substrate to a side surface of the second base substrate and aligned with the side surface of the second base substrate, the pad portion having an end portion laterally recessed from the side surface of the second base substrate; as well as A connecting pad is in contact with the signal line and with a portion of a side surface of the insulating structure, the side surface of the insulating structure forms a step shape with each of the first base substrate and the second base substrate, and the end of the non-pad portion has a relatively flat surface compared to the end of the pad portion.

17. The display panel according to claim 16, in: The plurality of organic layers and the plurality of inorganic layers include: a first inorganic layer adjacent to the signal line; a first organic layer disposed on the first inorganic layer; a second inorganic layer disposed on the first organic layer; a second organic layer disposed on the second inorganic layer; and a third organic layer disposed on the second organic layer; and End portions of the plurality of organic layers and end portions of the plurality of inorganic layers form at least one stepped portion.

18. The display panel according to claim 17, in, The end portion of the first inorganic layer is closer to the side surface of the first base substrate than the end portion of the first organic layer.

19. The display panel according to claim 17, in: At least a portion of the second inorganic layer is exposed by the first organic layer and the second organic layer; and The at least a portion of the second inorganic layer exposed by the first organic layer and the second organic layer covers the end portion of the first organic layer.

20. The display panel according to claim 17, in, The first organic layer has one of red, green and blue colors.

21. The display panel according to claim 17, in, The third organic layer has a black color.

22. The display panel according to claim 16, in, An end portion of the signal line is not aligned with the side surface of the first base substrate and is laterally recessed from the side surface of the first base substrate.

23. The display panel according to claim 22, in, An insulating material is arranged in a space defined on an upper surface of the first base substrate between the side surface of the first base substrate and the end portion of the signal line.

24. The display panel according to claim 16, in: A portion of the upper surface of the signal line is exposed by the insulating structure; and The connection pad contacts the exposed portion of the upper surface of the signal line.

25. The display panel according to claim 16, in: A portion of the upper surface of the signal line is exposed by the insulating structure; A portion of the rear surface of the signal line is spaced apart from the upper surface of the first base substrate; and The connection pad contacts the exposed portion of the upper surface of the signal line and the separated portion of the rear surface of the signal line.

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