High bandwidth memory device and system device having the same

Abstract

According to some embodiments, a high bandwidth memory device includes a base die and a plurality of memory dies stacked on the base die and electrically connected to the base die through a plurality of substrate through holes. The base die includes: a plurality of first input buffers configured to receive channel clock signals, channel commands / addresses, and channel data from a plurality of first bumps connected to the outside of the base die; a plurality of second input buffers configured to receive test clock signals, test commands / addresses, and test data from a plurality of second bumps connected to the outside of the base die; a monitoring unit; a plurality of first output buffers connected to the monitoring unit and configured to output monitoring data from the monitoring unit to the plurality of second bumps; and a plurality of paths from the plurality of first input buffers to the monitoring unit.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims the benefit of Korean Patent Application No. 10-2018-0028456 filed on March 12, 2018, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2018-0094449 filed on August 13, 2018, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] The inventive concept relates to a high bandwidth memory (HBM) device and a system device having the same. Background Art

[0004] A high bandwidth memory (HBM) device has a structure in which a plurality of memory dies and a base die (which may be described as a buffer die or a logic die) are stacked. The plurality of memory dies are stacked above the base die, and the plurality of memory dies receive commands / addresses (e.g., including command bits and address bits, and in some cases together with data bits) from the base die using substrate through-holes (e.g., through-silicon vias TSVs that pass through the plurality of memory dies), and input data from the base die or output data to the base die.

[0005] A system device with an HBM device may include an HBM device and a controller (e.g., a graphics processing unit (GPU) die, a central processing unit (CPU) die, or a system on chip (SoC), etc.). The base die of the HBM device receives commands / addresses sent from the controller, and inputs data from the controller or outputs data to the controller. When the system device is manufactured as a 2.5-dimensional (D) package, the base die and the controller of the HBM die are located above the interposer, and data and commands / addresses are transmitted through lines formed in the interposer. When the system device is manufactured as a 3D package, the HBM device is located above the controller, and the HBM device and the controller directly send data and commands / addresses.

[0006] However, the system device having the HBM device cannot monitor data or commands / addresses sent from the controller to the base die of the HBM device. Summary of the invention

[0007] The present disclosure relates to providing a high bandwidth memory (HBM) device and a system device having the HBM device, wherein the HBM device is capable of monitoring data or commands / addresses transmitted from a controller to a base die of the HBM device.

[0008] The scope of the inventive concept is not limited to the above-mentioned objects, and other unmentioned objects can be clearly understood by those skilled in the art from the following description.

[0009] According to some embodiments, a memory device includes a logic die and a plurality of memory dies stacked on a base die and electrically connected to the base die through a plurality of substrate through holes. The base die includes: a plurality of first input buffers configured to receive channel clock signals, channel commands / addresses, and channel data from a plurality of first bumps connected to the outside of the base die; a plurality of second input buffers configured to receive test clock signals, test commands / addresses, and test data from a plurality of second bumps connected to the outside of the base die; a monitoring unit; a plurality of first output buffers connected to the monitoring unit and configured to output monitoring data from the monitoring unit to the plurality of second bumps; and a plurality of paths from the plurality of first input buffers to the monitoring unit. The plurality of second bumps are connected to receive test clock signals, test commands / addresses, and test data from the outside of the base die during a first operating mode, and receive monitoring data from the plurality of first output buffers during a second operating mode.

[0010] According to some embodiments, a high-bandwidth memory device includes a base die and a memory die stack, wherein the memory die stack includes a plurality of memory dies stacked on the base die, the base die including a plurality of first input / output (I / O) terminals as command / address and data terminals and a plurality of second I / O terminals as direct access terminals. A method for a high-bandwidth memory device includes: receiving commands / addresses, clock signals, and data at a plurality of first I / O terminals; first, sending commands / addresses, clock signals, and data received by the plurality of first I / O terminals from the base die to the memory die stack; and then, through a circuit of the base die, sending at least a portion of one or more of the commands / addresses, clock signals, and data received by the group consisting of the plurality of first I / O terminals to the plurality of second I / O terminals.

[0011] According to some embodiments, a memory system device includes a system device substrate, a memory device, a controller and an interposer, wherein the memory device includes a base die and a group of memory die stacked on the system device substrate, the base die is electrically connected to the group of memory die through a substrate through hole, and the interposer is mounted on the system device substrate and has the memory device and the controller mounted thereon. The interposer electrically connects the memory device to the controller. The controller is configured to receive control signals and data signals as inputs to the memory system device, and based on the inputs, outputs a channel clock signal, a channel command / address and channel data to the memory device. The base die is configured to receive a channel clock signal, a channel command / address and channel data from the controller at a first group of input / output (i / o) terminals of the base die; send a channel clock signal, a channel command / address and channel data to the group of memory die; and send at least a portion of one or more of a channel clock signal, a channel command / address and channel data to a second group of i / o terminals of the base die through a monitoring unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a diagram illustrating a structure of a system device having a 2.5-dimensional (D) high bandwidth memory (HBM) device according to an exemplary embodiment of the present disclosure.

[0013] Figure 2 is a diagram illustrating a structure of a system device having a 3D HBM device according to an exemplary embodiment of the present disclosure.

[0014] Figure 3 is a diagram showing a configuration of a plurality of memory dies according to an exemplary embodiment of the present disclosure.

[0015] Figure 4A and Figure 4B is a diagram showing a configuration of a base die according to an exemplary embodiment of the present disclosure.

[0016] Figure 5 is a diagram illustrating a configuration of a through silicon via (TSV) circuit according to an exemplary embodiment of the present disclosure.

[0017] Figure 6 is a diagram illustrating a configuration of a monitoring unit according to an exemplary embodiment of the present disclosure.

[0018] Fig. 7A and Figure 7B is a truth table showing row and column commands according to an exemplary embodiment of the present disclosure.

[0019] Fig. 8A , Figure 8B , Fig.9A and Fig. 9Bis a timing chart for describing the operation of the monitoring unit according to an exemplary embodiment of the present disclosure.

[0020] Fig.10 is a diagram illustrating a configuration of a monitoring unit according to an exemplary embodiment of the present disclosure.

[0021] Fig.11 and Fig.12 is a timing chart for describing the operation of the monitoring unit according to an exemplary embodiment of the present disclosure.

[0022] Fig.13 is a diagram illustrating a configuration of a monitoring unit according to an exemplary embodiment of the present disclosure.

[0023] Fig.14 is a timing chart for describing the operation of the monitoring unit according to an exemplary embodiment of the present disclosure.

[0024] Fig.15 is a diagram illustrating a configuration of a monitoring unit according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] Hereinafter, a high bandwidth memory (HBM) device and a system device having the same according to exemplary embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0026] Figure 1 is a diagram illustrating a structure of a system device having a 2.5-dimensional (D) HBM device according to an exemplary embodiment of the inventive concept, and it illustrates the structure of the system device manufactured into a 2.5D package.

[0027] refer to Figure 1 , the system device 1000 may include the HBM device 100, the controller 200, the interposer 300, and the printed circuit board (PCB) 400. For example, the system device 1000 may be a semiconductor package including a plurality of semiconductor dies mounted on the printed circuit board (PCB) 400, which may be encapsulated by an encapsulant, and the printed circuit board (PCB) 400 may be a package substrate.

[0028] The HBM device 100 may include memory dies MD1 to MD4 and a base die BD (which may be referred to as (or may be) a buffer die or a logic die). The memory dies MD1 to MD4 and the base die BD may be stacked in a vertical direction, and the stacked memory dies MD1 to MD4 are located above the base die BD. Each die (also referred to as a chip or a semiconductor chip) may include an integrated circuit formed by a wafer. A first bump MB is formed between the stacked memory dies MD1 to MD4 and the base die BD, and a through silicon via (TSV) passing through the memory dies MD1 to MD4 may be formed between the first bumps MB. A first direct access (DA) bump dab, a first power supply bump pb1, and a first command / address bump and a data bump cadb1 may be arranged on the lower surface of the base die BD. The various bumps described herein may be referred to herein as interconnect terminals or connection terminals, which transmit signals or voltages to a die or substrate (or between them).

[0029] The second command / address and data bumps cadb2, the second power bumps pb2, and the first control signal and data bumps cdb may be arranged on the lower surface of the controller 200. The controller 200 may be a graphics processing unit (GPU) die, a central processing unit (CPU) die, a system on chip (SoC) die, or the like.

[0030] The first bump MB, the first DA bump dab, the first power bump pb1, the second power bump pb2, the first command / address and data bump cadb1, the second command / address and data bump cadb2, and the first control signal and data bump cdb may be micro bumps.

[0031] The second DA bump DAFB, the third power supply bump PBFB, and the second control signal and data bump CDFB may be arranged on the lower surface of the interposer 300. The interposer 300 may include a DA line da1 connecting the first DA bump dab with the second DA bump DAFB, a command / address line and a data line cad1 connecting the first command / address bump and data bump cadb1 with the second command / address bump and data bump cadb2, and a control signal and data line cd1 connecting the first control signal and data bump cdb with the second control signal and data bump CDFB. Although not shown, the interposer 300 may further include a power supply line connecting the first power supply bump pb1 with the third power supply bump PBFB and connecting the second power supply bump pb2 with the third power supply bump PBFB. The second DA bump DAFB, the third power supply bump PBFB, and the second control signal and data bump CDFB may be flip-chip die bumps.

[0032] The DA ball DAB, the power ball PB, and the control signal and data ball CDB can be arranged on the lower surface of the PCB 400. Through the PCB 400, the second DA bump DAFB can be connected to the DA ball DAB, the third power bump PBFB can be connected to the power ball PB, and the second control signal and data bump CDFB can be connected to the control signal and data ball CDB. The various bumps or balls described herein are connected to circuits within one or more tube cores to which the bumps are connected. For example, the power bump or ball is connected to a circuit element within a tube core that receives a power signal (e.g., a constant voltage signal), and the control signal and data bump or ball is connected to a circuit element within a tube core that receives a control signal and / or data.

[0033] Figure 2 is a diagram illustrating a structure of a system device having a 3D HBM device according to an exemplary embodiment of the inventive concept, and illustrates the structure of the system device manufactured into a 3D package.

[0034] refer to Figure 2 ,and Figure 1 Differently, the system device 1100 may not include the interposer 300. In addition, the base die BD of the HBM device 100 may be directly located on the upper surface of the controller 200. That is, the first DA bump dab, the first power bump pb1, and the first command / address bump and data bump cadb1 may be arranged on the upper surface of the controller 200.

[0035] The first DA bump dab and the second DA bump DAFB may be connected in the controller 200. The first power supply bump pb1 and the third power supply bump PBFB may be connected in the controller 200.

[0036] The controller 200 may receive the control signal and data applied through the second control signal and data bump CDFB and transmit the channel command / address and channel data to the first command / address bump cadb1 .

[0037] Figure 1 and Figure 2The controller 200 shown in the figure can process data in response to the control signal applied by the second control signal and the data bump CDFB, generate the processed data as channel data, and send the channel data and the channel command / address to the base die BD through the first channel command / address bump and the data bump cadb1. Therefore, the channel data and channel command / address described herein refer to the command / address and data output from the controller and sent to the memory die stack, for example, through the base die. In some cases, the channel signals (e.g., channel commands / addresses and channel data) described herein can be data for reading or writing the memory die for normal use, which is different from the test signal that can be sent from the controller to the base die for testing purposes.

[0038] Figure 1 and Figure 2 The base die BD shown in FIG. 1 may include various logic circuits for performing logic processing functions. In the DA test mode, the base die BD may receive a test command / address and test data applied through the first DA bump dab and output the test command / address and test data to a plurality of memory dies MD1 to MD4.

[0039] In addition, during monitoring operations, Figure 1 and Figure 2 The base die BD shown in can output a portion of the channel command / address and channel data applied through the first command / address bump and the data bump cadb1 through the first DA bump dab. The monitoring operation can be performed in the system-level test mode or the normal mode. In addition, the base die BD can output the channel command / address or channel data applied through the first command / address bump and the data bump cadb1 to the multiple memory dies MD1 to MD4 in the system-level test mode or the normal mode. Therefore, in the system-level test mode or the normal mode, at least a portion of the channel command / address or channel data sent from the controller 200 to the HBM device 100 can be output through the first DA bump dab, thereby being monitored externally in real time.

[0040] Figure 3is a diagram showing the construction of a plurality of memory dies according to an exemplary embodiment of the inventive concept. Each of the plurality of memory dies MD1 to MD4 may include two memory channels MCHa and MCHc, MCHb and MCHd, MCHe and MCHg, MCHf and MCHh, and each of the memory channels MCHa to MCHh may include a predetermined number of memory bodies (not shown). The memory channels MCHa, MCHb, MCHe and MCHf may be arranged on the left side of each of the memory dies MD1 to MD4, and the memory channels MCHc, MCHd, MCHg and MCHh may be arranged on the right side of each of the memory dies MD1 to MD4. Each of the memory channels MCHa to MCHh may be arranged to be vertically divided in the corresponding memory dies MD1 to MD4. The corresponding data terminals DQ1a to DQ4a, DQ1b to DQ4b, DQ1e to DQ4e or DQ1f to DQ4f, and the corresponding command / address terminals CATa, CATb, CATe or CATf may be included between the corresponding memory channels MCHa, MCHb, MCHe or MCHf arranged to be vertically divided; and the corresponding data terminals DQ1c to DQ4c, DQ1d to DQ4d, DQ1g to DQ4g or DQ1h to DQ4h, and the corresponding command / address terminals CATc, CATd, CATg or CATh may be included between the corresponding memory channels MCHc, MCHd, MCHg or MCHh arranged to be vertically divided. The first data group DG1 may be transmitted through the data terminals DQ1a, DQ1b, DQ1e and DQ1f, and the second data group DG2 may be transmitted through the data terminals DQ2a, DQ2b, DQ2e and DQ2f. Similarly, the third data group DG3 to the eighth data group DG8 can be transmitted through other data terminals DQ3a to DQ4h. The first command / address group CAG1 can be transmitted through the command / address terminals CATa, CATb, CATe and CATf, and the second command / address group CAG2 can be transmitted through the command / address terminals CATc, CATd, CATg and CATh.

[0041] Figure 3 Each data pin and command / address pin can be Figure 1 and 2 In addition, the lines vertically passing through the data terminals and the command / address terminals may be TSVs.

[0042] Assuming that n-bit data is input and output through each data terminal DQ1a to DQ4a...DQ1h to DQ4h, a total of 32n-bit data can be input and output through all data terminals. Assuming that k-bit data is input and output through each command / address terminal CATa to CATh, a total of 8k-bit command / address can be input and output through all command / address terminals.

[0043] like Figure 3 As shown, the lines corresponding to the second data group DG2 to the eighth data group DG8 can be constructed to be the same as the lines corresponding to the first data group DG1, and the lines corresponding to the second command / address group CAG2 can be constructed to be the same as the CAG1 lines corresponding to the first data group.

[0044] Figure 4A1 is a diagram showing the construction of a base die BD according to an exemplary embodiment of the inventive concept. The base die BD may include a physical (PHY) unit 10, a TSV circuit 20, a DA circuit 30, a monitoring unit 40, a clock signal (CK1) input buffer 32-1, a command / address (CA1) input buffer 32-2, a data (DQ1) input buffer 32-3, a clock signal (CK1) output buffer 34-1, a command / address (CA1) output buffer 34-2, and a data (DQ1) output buffer 34-3. The PHY unit 10 may include channel PHY units PHYa to PHYh, which are configured to receive a channel clock signal and a channel command / address, and input and output channel data of each memory channel MCHa to MCHh. Each channel PHY unit PHYa to PHYh may include a clock signal (CK2) input buffer 12-1, a command / address (CA2) input buffer 12-2, a data (DQ2) input buffer 12-3, a data (DQ2) output buffer 14, and a selection unit 16. The clock signal (CK2) input buffer 12-1, the command / address (CA2) input buffer 12-2, and the data (DQ2) input buffer 12-3 may be described as a plurality of input buffers, such as a plurality of first input buffers, and may include a first group of input buffers. The clock signal (CK1) input buffer 32-1, the command / address (CA1) input buffer 32-2, and the data (DQ1) input buffer 32-3 may be described as a plurality of input buffers, such as a plurality of second input buffers, and may include a second group of input buffers. The clock signal (CK1) output buffer 34-1, the command / address (CA1) output buffer 34-2, and the data (DQ1) output buffer 34-3 may be described as a plurality of output buffers. In some embodiments, the first group of input buffers 12-1, 12-2, and 12-3 may be generally described as a first group of buffers, and the plurality of output buffers 34-1, 34-2, and 34-3 and the second group of input buffers 32-1, 32-2, and 32-3 may be generally described as a second group of buffers. Please note, however, that the terms "first", "second", etc. in this document are used merely as naming conventions unless the context indicates otherwise, and thus these buffers and other items described using the names "first" or "second" may alternatively be named "second" or "first", or "third", "fourth", etc., based on the context being described.

[0045] The following will describe Figure 4A and Figure 4B The functions of the boxes shown in .

[0046] refer to Figures 1 to 4AWhen the DA enable signal DAEN is deactivated (the reverse DA enable signal DAENB is activated) in the system-level test mode or the normal mode, each channel PHY unit PHYa to PHYh can receive the corresponding channel clock signal CKa, CKb... or CKh, the corresponding channel command / address CAa, CAb... or CAh and the corresponding channel data DQa, DQb... or DQh applied from the controller through the first command / address block and the data block cadb1, and output the corresponding clock signal cka, ckb... or ckh, the corresponding command / address caa, cab... or cah and the corresponding data dqa, dqb... or dqh, or receive the corresponding data dqa, dqb... or dqh, and output the corresponding channel data DQa, DQb... or DQh. In addition, when the DA enable signal DAEN is activated in the DA test mode, each channel PHY unit PHYa to PHYh can receive the corresponding channel test clock signal tcka, tckb... or tckh, the corresponding channel test command / address tcaa, tcab... or tcah and the corresponding test data tdqa, tdqb... or tdqh output from the DA circuit unit 30, and output the corresponding clock signal cka, ckb... or ckh, the corresponding command / address caa, cab... or cah and the corresponding data dqa, dqb... or dqh to the TSV circuit unit 20, or receive the corresponding data dqa, dqb... or dqh output from the TSV circuit unit 20, and output the corresponding channel test data tdqa, tdqb... or tdqh to the DA circuit unit 30.

[0047] The clock signal input buffer 12-1 for each channel PHY unit PHYa to PHYh can buffer the corresponding channel clock signal CKa, CKb... or CKh, and generate the corresponding buffered channel clock signal ckba, ckbb... or ckbh. The command / address input buffer 12-2 can buffer the corresponding channel command / address CAa, CAb... or CAh, and generate the corresponding buffered channel command / address caba, cabb... or cabh. The data input buffer 12-3 can buffer the corresponding channel data DQa, DQb... or DQh, and generate the corresponding buffered channel data dqba, dqbb... or dqbh. The data output buffer 14 can receive the corresponding buffered channel data dqba, dqbb... or dqbh from the selection unit 16, and generate the corresponding channel data DQa, DQb... or DQh. Note that in the case of a base die BD, the term “buffered channel data” in this document is used as a naming convention to refer to data inside the output buffer associated with the base die BD described herein, which is different from channel data outside the output buffer (e.g., channel data transmitted through the bumps of the base die BD), which is not referred to as “buffered channel data”.

[0048] When the DA enable signal DAEN is deactivated, the selection unit 16 for each channel PHY unit PHYa to PHYh can select and send the corresponding buffered channel clock signal ckba, ckbb... or ckbh, the corresponding buffered channel command / address caba, cabb... or cabh and the corresponding buffered channel data dqba, dqbb... or dqbh to generate the corresponding clock signal cka, ckb... or ckh, the corresponding command / address caa, cab... or cah and the corresponding data dqa, dqb... or dqh. When the DA enable signal DAEN is activated, the selection unit 16 for each channel PHY unit (PHYa to PHYh) can select and send the corresponding channel test clock signal tcka, tckb... or tckh, the corresponding channel test command / address tcaa, tcab... or tcah and the corresponding channel test data tdqa, tdqb... or tdqh to generate the corresponding clock signal cka, ckb... or ckh, the corresponding channel command / address caa, cab... or cah and the corresponding data dqa, dqb... or dqh. In addition, when the DA enable signal DAEN is deactivated, the selection unit 16 for each channel PHY unit PHYa to PHYh can select and send the corresponding data dqa, dqb... or dqh to generate the corresponding buffered channel data dqba, dqbb... or dqbh, and when the DA enable signal DAEN is activated, the selection unit 16 for each channel PHY unit PHYa to PHYh can select and send the corresponding data dqa, dqb... or dqh to generate the corresponding channel test data tdqa, tdqb... or tdqh. For example, the selection unit 16 may be a circuit including a plurality of switching circuits for performing the above-mentioned selection, and these switching circuits may be controlled based on the DA enable signal DAEN signal (for example, when the DA enable signal DAEN is enabled, the TSV circuit 20 is connected to the DA circuit 30, and the TSV circuit 20 is disconnected from the input and output buffers 12-1, 12-2, 12-3 and 14 and the monitoring unit 40; when the DA enable signal DAEN is disabled, the TSV circuit 20 is disconnected from the DA circuit 30, and the TSV circuit 20 is connected to the input and output buffers 12-1, 12-2, 12-3 and 14 and the monitoring unit 40).

[0049] The TSV circuit 20 may align clock signals cka to ckh, commands / addresses caa to cah, and data dqa to dqh output from the PHY units PHYa to PHYh, and generate first to eighth data groups DG1 to DG8 and first and second command / address groups CAG1 and CAG2.

[0050] The clock signal input buffer 32-1 can buffer the test clock signal TCK and generate a buffered test clock signal tckbu. The command / address input buffer 32-2 can buffer the test command / address TCA and generate a buffered test command / address tcabu. The data input buffer 32-3 can buffer the test data TDQ and generate a buffered test data tdqbu.

[0051] When the DA enable signal DAEN is activated, the DA circuit 30 can receive the buffer test clock signal tckbu, the buffer test command / address tcabu and the buffer test data tdqbu, and output the corresponding channel test clock signal tcka, tckb... or tckh, the corresponding channel test command / address tcaa, tcab... or tcah, and the corresponding channel test data tdqa, tdqb... or tdqh to the selection unit 16 for each channel PHY unit PHYa to PHYh, and receive the corresponding channel test data tdqa, tdqb... or tdqh, and output the buffer test data tdqbu. When the buffer test clock signal tckbu, the buffer test command / address tcabu, and the buffer test data tdqbu are 1-bit, k-bit, and n-bit data, respectively, the DA circuit 30 may copy the 1-bit buffer test clock signal tckbu, the k-bit buffer test command / address tcabu, and the n-bit buffer test data tdqbu, and generate 8 1-bit buffer test clock signals tcka to tckh, 8 k-bit channel test commands / addresses tcaa to tcah, and 8 32n-bit channel test data tdqa to tdqh. When the 8 32-bit test data tdqa to tdqh are input from the selection unit 16, the DA circuit 30 may compare the 8 32n-bit channel test data tdqa to tdqh with the previously received n-bit buffer test data tdqb by n bits, and output the comparison result as the buffer test data tdqbu.

[0052] The clock signal output buffer 34-1 and the command / address output buffer 34-2 may buffer and output a portion of the monitoring data md. The clock signal output buffer 34-1 may be used to output a buffered test clock signal tckbu.

[0053] The data output buffer 34 - 3 may buffer and output the buffered test data tdqbu, or buffer and output another part of the monitoring data md.

[0054] The clock signal output buffer 34-1, the command / address output buffer 34-2, and the data output buffer 34-3 may constitute a monitoring data output unit 34 that outputs monitoring data md. The monitoring data output unit 34 may receive the monitoring data md through the first DA bump dab in a DA test mode.

[0055] When the DA enable signal DAEN is deactivated (the inverted DA enable signal DAENB is activated), the monitoring unit 40 may receive the buffered channel clock signals ckba to ckbh and the buffered channel commands / addresses caba to cabh generated from the PHY units PHYa to PHYh through a plurality of paths between the input buffers 12-1 and 12-2 and the monitoring unit 40, and generate the monitoring data md. The monitoring unit 40 may receive all or part of the buffered channel clock signal ckba and the buffered channel command / address caba applied to a specific channel (e.g., the memory channel MCHa), and generate the monitoring data md.

[0056] When the DA enable signal DAEN is activated, Figure 4A The base die BD shown in the figure can receive the test clock signal TCK, the test channel command / address TCA and the test channel data TDQ applied through the first DA bump dab, and generate the first data group DG1 to the eighth data group DG8 and the first command / address group CAG1 and the second command / address group CAG2, and receive the first data group DG1 to the eighth data group DG8 and generate the test data TDQ. In addition, when the DA enable signal DAEN is deactivated, the base die BD can receive the channel clock signals CKa to CKh, the channel commands / addresses CAa to CAh and the channel data DQa to DQh applied through the first command / address bump and the data bump cadb1, and generate the first data group DG1 to the eighth data group DG8 and the first command / address group CAG1 and the second command / address group CAG2 to output to the plurality of memory dies MD1 to MD4, and receive at least a portion of the channel clock signals CKa to CKh and the channel commands / addresses CAa to CAh, and generate the monitoring data md to be output through the first DA bump dab. Although not shown, when the DA enable signal DAEN is deactivated, the base die BD may generate at least a portion of the channel data DQa to DQh applied through the first command / address bump and the data bump cadb1 as the monitoring data md, and output the monitoring data md through the first DA bump dab. In addition, the base die BD may receive the first data group DG1 to the eighth data group DG8 output from the plurality of memory dies MD1 to MD4, and generate the channel data DQa to DQh. Figure 4B is a diagram showing a configuration of a base die BD according to an exemplary embodiment of the inventive concept, wherein the base die BD may include a monitoring unit 41 instead of Figure 4A A monitoring unit 40 of a base die BD is shown.

[0057] The following will describe Figure 4B The function of the monitoring unit 41 in the block shown.

[0058] When the DA enable signal DAEN is deactivated, the monitoring unit 41 may receive at least a portion of the buffered channel clock signals ckba to ckbh, the buffered channel commands / addresses caba to cabh, or the buffered channel data dqba to dqbh generated from the channel PHY units PHYa to PHYh, and generate monitoring data md. The monitoring unit 41 may receive all or a portion of the buffered channel clock signal ckba, the buffered channel commands / addresses caba, or the buffered channel data dqba applied to a specific channel (e.g., the memory channel MCHa), and generate monitoring data md.

[0059] also, Figure 4A and Figure 4B The base die BD shown in FIG. 1 can receive the first data group DG1 to the eighth data group DG8 and generate the monitoring data md through the first DA bump dab. The monitoring unit 40 or 41 can receive all or part of the buffer channel data dqba to dqbh output from the selection unit 16 and generate the monitoring data md through the first DA bump dab. Therefore, the first data group DG1 to the eighth data group DG8 output from the plurality of memory dies MD1 to MD4 can be monitored.

[0060] Therefore, as described above, the base die BD may include a first group of buffers (e.g., 12-1, 12-2, and 12-3) and a second group of buffers (e.g., 32-1, 32-2, 32-3, 34-1, 34-2, and 34-3), wherein the first group of buffers is connected to the first group of i / o terminals and is connected to receive a channel clock signal (e.g., CKa-CKh), a channel command / address (e.g., CAa-CAh), and a channel data (e.g., DQa-DQh) from the first group of i / o terminals, and the second group of buffers is connected to the second group of i / o terminals and is connected to send at least a portion of one or more of the channel clock signal (CKa-CKh), the channel command / address (e.g., CAa-CAh), and the channel data (e.g., DQa-DQh) to the second group of i / o terminals. The second group of buffers (e.g., 32-1, 32-2, 32-3, 34-1, 34-2, and 34-3, in particular, buffers 32-1, 32-2, and 32-3) may be further connected to receive a test clock signal (e.g., TCK), a test command / address (e.g., TCA), and test data (e.g., TDQ) from outside the base die. In addition, the base die BD may include circuits and be configured such that the second group of buffers receives the test clock signal, the test command / address, and the test data from outside the base die BD during a direct access test mode, and the second group of buffers receives (e.g., from the first group of buffers such as 12-1, 12-2, and 12-3) at least a portion of one or more of the channel clock signal, the channel command / address, and the channel data during a normal mode or a system level test mode.

[0061] Figure 5 1 is a block diagram showing the construction of a TSV circuit according to an exemplary embodiment of the inventive concept. The TSV circuit 20 may include a clock signal (ck) output buffer 22-1, a command / address (ca) output buffer 22-2, a data (dq) output buffer 22-3, a data (dq) input buffer 24, and a sorting unit 26.

[0062] The following will describe Figure 5 The functions of the boxes shown in .

[0063] The clock signal output buffer 22-1 can buffer clock signals cka to ckh and output buffered clock signals cba to cbh. The command / address output buffer 22-2 can receive command / address caa to cah and output buffered command / address aba to abh. The data output buffer 22-3 can receive data dqa to dqh and output buffered data dba to dbh. The data input buffer 24 can buffer the buffered data dba to dbh output from the sorting unit 26 and generate data dqa to dqh. The sorting unit 26 can arrange the buffered clock signals cba to cbh and the buffered commands / addresses aba to abh and generate the first command / address group CAG1 and the second command / address group CAG2, and arrange the buffered data dba to dbh and generate the first data group DG1 to the eighth data group DG8. In addition, the sorting unit 26 can arrange the first data group DG1 to the eighth data group DG8 and generate the buffered data dba to dbh. That is, the sorting unit 26 can generate the buffered clock signals cba, cbb, cbe and cbf, and the buffered commands / addresses aba, abb, abe and abf as the first command / address group CAG1, and generate the buffered clock signals cbc, cbd, cbg and cbh, and the buffered commands / addresses abc, abd, abg and abh as the second command / address group CAG2. In addition, the sorting unit 26 can classify the respective buffered data dba, dbb, dbe and dbf into four groups and generate the first data group DG1 to the fourth data group DG4, and classify the respective buffered data dbc, dbd, dbg and dbh into four groups and generate the fifth data group DG5 to the eighth data group DG8.

[0064] Figure 6 4 is a diagram showing the construction of a monitoring unit according to an exemplary embodiment of the present invention. The monitoring unit 40 may be a monitoring relay circuit that relays data from the input buffers 12-1, 12-2, and 12-3 to the output buffers 34-1, 34-2, and 34-3 (see FIG. 4 ). The relay data may be referred to as monitoring data. The monitoring unit 40 may include channel monitoring units CHMa to CHMh and a fourth selector SEL4. Each channel monitoring unit CHMa to CHMh may be a channel monitoring relay circuit, and the channel monitoring relay circuit may include a row monitoring unit RM, a column monitoring unit CM, and a third selector SEL3. For example, the row monitoring unit RM may be a circuit including an inverter I, a first trigger FF1 to a third trigger FF3, and a first selector SEL1. For example, the column monitoring unit CM may be a circuit including a fourth trigger FF4 to a sixth trigger FF6 and a second selector SEL2.

[0065] Figure 6, the buffered channel command / address caba applied to the channel monitoring unit CHMa may be constructed to have 6-bit row command / address r0a to r5a and 8-bit column command / address c0a to c7a. The corresponding channel command / address cabb, cabc... or cabh applied to each channel monitoring unit CHMb to CHMh may be constructed to have corresponding row command / address r0b to r5b, r0c to r5c... or r0h to r5h, and corresponding column command / address c0b to c7b, c0c to c7c... or c0h to c7h.

[0066] Inverter I can invert the buffer channel clock signal ckba and generate an inverted buffer channel clock signal ckbab. In response to the rising edge of the buffer channel clock signal ckba, the first flip-flop FF1 can input and generate row commands / addresses r0a to r5a. In response to the rising edge of the inverted buffer channel clock signal ckbab, the second flip-flop FF2 can generate the output signal of the first flip-flop FF1 as an odd row command / address rfa. In response to the rising edge of the inverted buffer channel clock signal ckbab, the third flip-flop FF3 can generate row commands / addresses r0a to r5a as even row commands / addresses rsa. In response to the rising edge of the buffer channel clock signal ckba, the fourth flip-flop FF4 can input and generate column commands / addresses c0a to c7a. In response to the rising edge of the inverted buffer channel clock signal ckbab, the fifth flip-flop FF5 can generate the output signal of the fourth flip-flop FF4 as an odd column command / address cfa. In response to the rising edge of the inverted buffer channel clock signal ckbab, the sixth flip-flop FF6 can generate the column command / address c0a to c7a as the even column command / address csa. In response to the first selection signal EOS, the first selector SEL1 can select the odd row command / address rfa or the even row command / address rsa, and generate the row output signal reoa. In response to the first selection signal EOS, the second selector SEL2 can select the odd column command / address cfa or the even column command / address csa, and generate the column output signal ceoa. In response to the second selection signal RCS, the third selector SEL3 can select the row output signal reoa or the column output signal ceoa, and generate the channel output signal rca. Each channel monitoring unit CHMb to CHMh can perform the same operation as the channel monitoring unit CHMa, and generate the corresponding channel output signal rcb, rcc... or rch. In response to the third selection signal CHS, the fourth selector SEL4 can select one of the channel output signals rca to rch, and generate the monitoring data md. The monitoring unit 40 may output a buffered channel clock signal ckba and monitoring data md.

[0067] Therefore, in some embodiments, the monitoring unit 40 is connected between the first group of buffers (e.g., one or more of the buffers 12-1, 12-2, and 12-3) and the second group of buffers (e.g., one or more of the buffers 32-1, 32-2, 32-3, 34-1, 34-2, and 34-3), and is configured to transmit signals output from the first group of buffers to the second group of buffers during a first operation mode (e.g., a system level test mode or a normal mode) of the memory device, and to prevent signals output from the first group of buffers from being transmitted to the second group of buffers during a second operation mode (e.g., a direct access mode) of the memory device. For example, the direct access mode may be a mode in which test information including a test clock signal, a test command / address, and test data is input to a plurality of second bumps (e.g., a test terminal) as direct access terminals. Figure 2 The direct access bump dab in the memory is sent to a plurality of memory dies (eg, Figure 2 The system level test mode or normal mode may be a mode in which a channel clock signal, a channel command / address, and channel data are input to a plurality of first bumps (e.g., Figure 2 The channel command / address bump and data bump cadb1 in FIG4 and a plurality of first input buffers (e.g., one or more of buffers 12-1, 12-2, and 12-3 in FIG4 ) are transmitted to a plurality of memory dies through the plurality of first bumps and the plurality of first input buffers to access the memory dies, while the channel clock signal, channel command / address, and channel data (e.g., monitoring data) are also transmitted through the monitoring unit 40 in FIG4 and a plurality of first output buffers (e.g., output buffers 34-1, 34-2, and 34-3 in FIG4 ) to be output from the base die BD at a plurality of second bumps (e.g., received by and transmitted from the base die BD). All of the plurality of second bumps can be used to input test information and to output monitoring data.

[0068] Fig. 7A is a row command truth table according to an exemplary embodiment of the inventive concept. Row commands / addresses R0 to R5 may be applied in response to rising and falling edges of the clock signal CK during two cycles. At the first rising edge of the clock signal CK, row signals R2 to R5 may be applied together with row signals R0 and R1 having a "low (L)" level and a "high (H)" level, respectively, indicating an activation command ACTIVATE. In addition, row signals R0 to R5 may be applied at the first falling edge, the second rising edge, and the second falling edge of the clock signal CK. The row signals included in the shaded area I may include a row address and a memory bank address.

[0069] Figure 7BColumn command truth table of an exemplary embodiment of the inventive concept. Column commands / addresses C0 to C7 may be applied in response to the rising and falling edges of the clock signal CK during one cycle. At the first rising edge of the clock signal CK, column signals C4 to C7 may be applied together with column signals C0 to C3, wherein the column signals C0 to C3 have a "high" level, a "low" level, and a "high" level, indicating a read command READ. At the first rising edge of the clock signal CK, column signals C4 to C7 may be applied together with column signals C0 to C3 having a "high" level, a "low" level, a "low" level, and a "low" level, respectively, indicating a write command WRITE. In addition, at the first falling edge of the clock signal CK, column signals C0 to C7 may be applied. The column signal included in the shaded area II may include a column address. At the first rising edge of the clock signal CK, column signals C3 to C7 may be applied together with column signals C0 to C2 having a "low" level, indicating a mode register setting command MODE REGISTER SET. In addition, at a first falling edge of the clock signal CK, the column signals C0 to C7 may be applied. The column signals included in the shaded area III may include a mode setting code.

[0070] Fig. 7A and Figure 7B Row and column command truth tables for HBM devices standardized by the Joint Electron Device Engineering Council (JEDEC) are shown. Fig. 7A and Figure 7B In the embodiment, the clock signal CK may be a channel clock signal, and the row commands / addresses R0 to R5 and the column commands / addresses C0 to C7 may be channel commands / addresses.

[0071] FIG. 8A to FIG. 9B is a timing diagram for describing the operation of the monitoring unit 40 according to an exemplary embodiment of the inventive concept.

[0072] refer to Figure 6 , Fig. 7A , Figure 7B , FIG. 8A to FIG. 9B, an activation command ACTIVATE (as a row command R COM) and a row address may be applied according to a row command truth table, and a read command READ (or a write command WRITE) (as a column command C COM) and a column address may be applied according to a column command truth table. In response to the rising and falling edges of the corresponding channel clock signals CKa, CKb... or CKh during one clock cycle, a first odd row command / address RF1 and a first even row command / address RS1 may be sequentially applied as row commands / addresses R0 to R5, and an odd column command / address CF and an even column command / address CS may be sequentially applied as column commands / addresses C0 to C7. In response to the rising and falling edges of the corresponding channel clock signals CKa, CKb... or CKh during the next clock cycle, a second odd command / address RF2 and a second even command / address RS2 may be sequentially applied as row commands / addresses R0 to R5. Each buffered channel clock signal ckba to ckbh may be generated by buffering a corresponding one of the channel clock signals CKa to CKh. Each buffered channel command / address caba to cabh may be generated by buffering a corresponding one of the channel commands / addresses CAa to CAh. FIG. 8A to FIG. 9B It is shown that it is assumed that the same buffer row commands / addresses r0 to r5 and the same buffer column commands / addresses c0 to c7 are applied as buffer channel commands / addresses caba to cabh.

[0073] Fig. 8A 1 is a timing diagram for describing the operation of the monitoring unit 40 when the first selection signal EOS has a “high” level, the second selection signal RCS has a “high” level, and the third selection signal CHS has a “high” level, a “high” level, and a “high” level so as to select the channel monitoring unit CHMa from the eight channel monitoring units CHMa to CHMh.

[0074] refer to Figure 6 and Fig. 8AIn response to the rising edge of the inverted buffered channel clock signal ckbab, the row monitoring unit RM of the channel monitoring unit CHMa may sequentially generate the first odd row command / address RF1 and the second odd row command / address RF2 as odd row command / address rfa, and sequentially generate the first even row command / address RS1 and the second even row command / address RS2 as even row command / address rsa. In response to the rising edge of the inverted buffered channel clock signal ckbab, the column monitoring unit CM of the channel monitoring unit CHMa may generate the odd column command / address CF as odd column command / address cfa, and generate the even column command / address CS as even column command / address csa. In response to the first selection signal EOS having a "high" level, each of the first selector SEL1 and the second selector SEL2 for the channel monitoring unit CHMa can generate the first odd row command / address RF1 and the second odd row command / address RF2 (which are odd row command / address rfa) as the row output signal reoa, and the odd column command / address CF (which are odd column command / address cfa) as the column output signal ceoa. In response to the second selection signal RCS having a "high" level, the third selector SEL3 for the channel monitoring unit CHMa can generate the first odd row command / address RF1 and the second odd row command / address RF2 (which are the row output signal reoa) as the channel output signal rca. By performing the same operation as the channel monitoring unit CHMa, each of the channel monitoring units CHMb to CHMh can generate a corresponding one of the channel output signals rcb to rch.

[0075] In response to the third selection signal CHS having a "high" level, a "high" level, and a "high" level, the fourth selector SEL4 can generate the first odd row command / address RF1 and the second odd row command / address RF2 (which are the channel output signal rca) as the monitoring data md. The monitoring unit 40 can generate the buffered channel clock signal ckba and the first row command / address RF1 and the second row command / address RF2 as the monitoring data md.

[0076] Figure 8B is a timing diagram for describing the operation of the monitoring unit 40 when the first selection signal EOS has a “low” level, the second selection signal RCS has a “high” level, and the third selection signal CHS has a “high” level, a “high” level, and a “high” level.

[0077] refer to Figure 6 and Figure 8B, since the first selection signal EOS has a "low" level, the first selector SEL1 and the second selector SEL2 can respectively generate the first even row command / address RS1 and the second even row command / address RS2 (which are even row command / address rsa) as the row output signal reoa, and can generate the even column command / address CS (which are even column command / address csa) as the column output signal ceoa. In response to the second selection signal RCS having a "high" level, the third selector SEL3 can generate the first even row command / address RS1 and the second even row command / address RS2 (which are the row output signal reoa) as the channel output signal rca. In response to the third selection signal CHS having a "high" level, a "high" level, and a "high" level, the fourth selector SEL4 can generate the first even row command / address RS1 and the second even row command / address RS2 (which are the channel output signal rca) as the monitoring data md. The monitoring unit 40 may generate the buffered channel clock signal ckba and the first and second even row commands / addresses RS1 and RS2 as monitoring data md.

[0078] Fig.9A is a timing diagram for describing the operation of the monitoring unit 40 when the first selection signal EOS has a “high” level, the second selection signal RCS has a “low” level, and the third selection signal CHS has a “high” level, a “high” level, and a “high” level.

[0079] refer to Figure 6 and Fig.9A , by referring to the above Fig. 8A The operation of the first selector SEL1 and the second selector SEL2 will be easily understood. In response to the second selection signal RCS having a "low" level, the third selector SEL3 can generate an odd column command / address CF (which is a column output signal ceoa) as a channel output signal rca. In response to the third selection signal CHS having a "high" level, a "high" level, and a "high" level, the fourth selector SEL4 can generate an odd column command / address CF (which is a channel output signal rca) as monitoring data md. The monitoring unit 40 can generate the buffered channel output clock signal ckba and the odd column command / address CF as monitoring data md.

[0080] Fig. 9B is a timing diagram for describing the operation of the monitoring unit 40 when the first selection signal EOS has a “low” level, the second selection signal RCS has a “low” level, and the third selection signal CHS has a “high” level, a “high” level, and a “high” level.

[0081] refer to Figure 6 and Fig. 9B , by referring to the above Figure 8B The operation of the first selector SEL1 and the second selector SEL2 will be easily understood. In response to the second selection signal RCS having a "low" level, the third selector SEL3 can generate an even column command / address CS (which is a column output signal ceoa) as a channel output signal rca. In response to the third selection signal CHS having a "high" level, a "high" level, and a "high" level, the fourth selector SEL4 can generate an even column command / address CS (which is a channel output signal rca) as monitoring data md. The monitoring unit 40 can generate the buffered channel clock signal ckba and the even column command / address CS as monitoring data md.

[0082] like FIG. 8A to FIG. 9B As shown above Figure 6 The monitoring unit 40 shown in the figure can receive the corresponding channel command / address CAa, CAb... or CAh (or the corresponding buffered channel command / address caba, cabb... or cabh) applied at a double data rate (DDR), which will be arranged at the center of the corresponding channel clock signal CKa, CKb... or CKh (or the corresponding buffered channel clock signal ckba, ckbb... or ckhb), and output the monitoring data md generated at a single data rate (SDR), which will be arranged at the edge of the corresponding channel clock signal CKa, CKb... or CKh (or the corresponding buffered channel clock signal ckba, ckbb... or ckbh).

[0083] References FIG. 8A to FIG. 9B The operation of outputting the channel clock signal CKa and the channel command / address CAa applied to the memory channel MCHa as the monitoring data md is described, but the corresponding channel clock signal CKb, CKc... or CKh and the corresponding channel command / address CAb, CAc... or CAh applied to the corresponding memory channel MCHb, MCHc... or MCHh can also be output as the monitoring data md by setting the third selection signal CHS differently. In addition, as shown below in combination Figures 10 to 12 As further described, in some embodiments, the output of the monitoring data md may be generated at a double data rate (DDR).

[0084] Fig.10is a diagram showing the construction of a monitoring unit according to an exemplary embodiment of the inventive concept. The monitoring unit 40' may include channel monitoring units CHMa' to CHMh' and a fourth selector SEL4. Each channel monitoring unit CHMa' to CHMh' may include a row monitoring unit RM', a column monitoring unit CM' and a third selector SEL3. The row monitoring unit RM' may include an inverter I, a first trigger FF1 and a third trigger FF3, and a first selector SEL1'. The column monitoring unit CM' may include a fourth trigger FF4 and a sixth trigger FF6, and a second selector SEL2'.

[0085] refer to Figure 6 The description will be easy to understand Fig.10 The reference numerals shown are Figure 6 Here, the functions of the first selector SEL1' and the second selector SEL2' will be described.

[0086] The first selector SEL1' can select and output the odd row command / address rfa as the row output signal reoa in response to the rising edge of the buffer channel clock signal ckba; or select and output the even row command / address rsa as the row output signal reoa in response to the falling edge of the buffer channel clock signal ckba.

[0087] The second selector SEL2' can select and output the odd column command / address cfa as the column output signal ceoa in response to the rising edge of the buffer channel clock signal ckba; or select and output the even column command / address csa as the column output signal ceoa in response to the falling edge of the buffer channel clock signal ckba.

[0088] The channel monitoring unit CHMa′ may generate a channel output signal rca, and each of the channel monitoring units CHMb′ to CHMh′ may perform the same operation as the channel monitoring unit CHMa′ and generate a channel output signal rcb, rcc . . . or rch.

[0089] Fig.11 and Fig.12 is used to describe an exemplary embodiment according to the inventive concept. Fig.10 An operation timing diagram of the operation of the monitoring unit 40' is shown in FIG.

[0090] Applies to FIG. 8A to FIG. 9B The assumptions of the operating timing diagrams shown can be applied to Fig.11 and Fig.12 Operation timing diagram.

[0091] Fig.112 is an operation timing diagram for describing the operation of the monitoring unit 40' when the second selection signal RCS is at a "high" level and the third selection signal CHS is at a "high" level, a "high" level and a "high" level so as to select the channel monitoring unit CHMa' from the eight channel monitoring units CHMa' to CHMh'.

[0092] refer to Fig.10 and Fig.11 , different from Fig. 8A In response to the rising edge of the buffered channel clock signal ckba, the row monitoring unit RM' of the channel monitoring unit CHMa' can sequentially generate the first odd row command / address RF1 and the second odd row command / address RF2 as the odd row command / address rfa. Fig. 8A As described above, in response to the rising edge of the inverted buffered channel clock signal ckbab, the row monitoring unit RM' of the channel monitoring unit CHMa' can sequentially generate the first even row command / address RS1 and the second even row command / address RS2 as the even row command / address rsa. The first selector SEL1' of the row monitoring unit RM' of the channel monitoring unit CHMa' can select the odd row command / address rfa in response to the rising edge of the buffered channel clock signal ckba, select the even row command / address rsa in response to the falling edge of the buffered channel clock signal ckba, and sequentially generate the first odd row command / address RF1, the first even row command / address RS1, the second odd row command / address RF2, and the second even row command / address RS2 as the row output signal reoa.

[0093] refer to Fig.10 and Fig.11 , different from Fig. 8A In response to the rising edge of the buffered channel clock signal ckba, the column monitoring unit CM' of the channel monitoring unit CHMa' can generate the odd column command / address CF as the odd column command / address cfa. In addition, similar to Fig. 8A According to the description, the column monitoring unit CM' of the channel monitoring unit CHMa' can generate the even column command / address CS as the even column command / address csa. The second selector SEL' of the column monitoring unit CM' of the channel monitoring unit CHMa' can select the odd column command / address cfa in response to the buffered channel clock signal ckba with a "high" level, select the even column command / address csa in response to the buffered channel clock signal ckba with a "low" level, and sequentially generate the odd column command / address cfa and the even column command / address csa as the column output signal ceoa.

[0094] Similar to Fig. 8AThe channel monitoring units CHMb' to CHMh' can generate channel output signals rcb to rch by performing the same operation as the channel monitoring unit CHMa'.

[0095] In response to the third selection signal CHS having a "high" level, a "high" level, and a "high" level, the fourth selector SEL4 can generate the first odd row command / address RF1, the first even row command / address RS1, the second odd row command / address RF2, and the second even row command / address RS2 (which are channel output signals rca) as monitoring data md. The monitoring unit 40' can also generate the buffered channel clock signal ckba as monitoring data md.

[0096] Fig.12 is an operation timing diagram for describing the operation of the monitoring unit 40 ′ when the second selection signal RCS is at a “low” level and the third selection signal CHS is at a “high” level, a “high” level, and a “high” level.

[0097] refer to Fig.10 and Fig.12 , by reference Fig.11 The description of the first selector SEL1' and the second selector SEL2' will make it easy to understand the operation of the first selector SEL1' and the second selector SEL2'. In response to the second selection signal RCS having a "low" level, the third selector SEL3 can sequentially generate the odd column command / address CF and the even column command / address CS (which are column output signals ceoa) as the channel output signal rca. In response to the third selection signal CHS having a "high" level, a "high" level, and a "high" level, the fourth selector SEL4 can generate the channel output signal rca as the monitoring data md. The monitoring unit 40' can also generate the buffered channel clock signal ckba as the monitoring data md.

[0098] like Fig.11 and Fig.12 As shown above Fig.10 The monitoring unit 40' shown in can receive the corresponding channel data DQa, DQb... or DQh (or the corresponding buffered channel data dqba, dqbb... or dqbh) applied in DDR, which will be arranged at the center of the corresponding channel clock signal CKa, CKb... or CKh (or the corresponding buffered channel clock signal ckba, ckbb... or ckbh), and output the monitoring data md generated in DDR, which will be arranged at the edge of the corresponding channel clock signal CKa, CKb... or CKh (or the corresponding buffered channel clock signal ckba, ckbb... or ckbh).

[0099] References Fig.11 and Fig.12 The operation of outputting the channel clock signal CKa and the channel command / address CAa applied to the memory channel MCHa as the monitoring data md is described, but the corresponding channel clock signals CKb to CKh and the corresponding channel commands / addresses CAb to CAh applied to the corresponding memory channels MCHb to MCHh can also be output as the monitoring data md by setting the third selection signal CHS differently.

[0100] Above Figure 6 or Fig.10 The monitoring unit 40 or 40' shown in the figure may not include the first selector SEL1 and the second selector SEL2, or SEL1' and SEL2', and / or the third selector SEL3. When the monitoring unit 40 or 40' does not include the first selector SEL1 and the second selector SEL2 or SEL1' and SEL2', odd and even row commands / addresses RFA and RSA may be generated as channel output signals RCA, or odd and even column commands / addresses CFA and CSA may be generated as channel output signals RCA. When the monitoring unit 40 does not include the first to third selectors SEL1, SEL2 and SEL3, odd and even row and column commands / addresses RFA, RSA, CFA and CSA may be generated as channel output signals RCA.

[0101] In addition, the above Figure 6 or Fig.10 The monitoring unit 40 or 40' shown in the figure may not include the first to sixth triggers FF1 to FF6, or may not include the first trigger FF1, the third trigger FF3, the fourth trigger FF4, and the sixth trigger FF6. When the monitoring unit 40 or 40' does not include the first to sixth triggers FF1 to FF6, or does not include the first trigger FF1, the third trigger FF3, the fourth trigger FF4, and the sixth trigger FF6, the monitoring unit 40 or 40' may transmit the corresponding row command / address r0a to r5a, ..., r0h to r5h and the corresponding column command / address (c0a to c7a), ..., (c0h to c7h) (such as) through the first to fourth selectors (SEL1 to SEL4, or SEL1', SEL2', SEL3, and SEL4). FIG. 8A to FIG. 9B or Fig.11 and Fig.12That is, the monitoring unit 40 or 40' can receive the corresponding channel command / address CAa, CAb... or CAh (or the corresponding buffer channel command / address caba, cabb... or cabh) (which is applied to be arranged at the center of the corresponding channel clock signal CKa, CKb... or CKh (or the corresponding buffer channel clock signal ckba, ckbb... or ckbh)), and generate the monitoring data md output in SDR or DDR.

[0102] Despite the above Figure 6 or Fig.10 The monitoring unit 40 or 40' shown in the figure can be constructed to monitor all channel clock signals CKa to CKh and channel commands / addresses CAa to CAh applied to eight memory channels MCHa to MCHh included in multiple memory tube cores MD1 to MD4, but the present invention concept can be constructed to monitor all or part of the channel clock signals and channel commands / addresses of a specific channel. Fig.13 is a diagram showing a configuration of a monitoring unit 40″ according to an exemplary embodiment of the inventive concept. The monitoring unit 40″ may include channel monitoring units CHMa″ to CHMh″ and a storage unit 42. Each channel monitoring unit CHMa″ to CHMh″ may include an inverter I′ and seventh to ninth flip-flops FF7 to FF9.

[0103] refer to Fig.13 Each of the seventh to ninth flip-flops FF7 to FF9 can perform the same Figure 6 The same operation as the first trigger FF1 to the third trigger FF3 shown. For example, the channel monitoring unit CHMa" can receive the buffered channel data dqba and generate odd data dfa and even data dsa. The channel monitoring unit CHMa" can generate the even and odd data dsa and dfa as channel output data dfsa. The corresponding channel monitoring unit CHMb", CHMc"... or CHMh" can receive the corresponding buffered channel data dqbb, dqbc... or dqbh, and generate the corresponding odd and even data dfb and dsb, dfc and dsc... or dfh and dsh as corresponding channel output data dfsb, dfsc... or dfsh. The storage unit 42 can store the corresponding channel output data dfsa to dfsh in parallel in response to the corresponding buffered clock signals ckba to ckbh, and sequentially output the corresponding channel output data dfsa to dfsh as monitoring data md in response to the corresponding buffered clock signals ckba to ckbh.

[0104] Fig.14 is used to describe Figure 1 and Figure 2 1 is a timing diagram of an operation of a monitoring unit 40 ″ according to an exemplary embodiment of the inventive concept when a write latency WL of the HBM device 100 is 4 and a burst length BL is 4.

[0105] refer to Figure 7B , Fig.13 and Fig.14 , a write command WRITE (as a column command CCOM) and a column address can be applied according to the column command truth table. In response to the rising and falling edges of the corresponding channel clock signals CKa, CKb... or CKh during one clock cycle, odd column commands / addresses CF and even column commands / addresses CS can be sequentially applied as column commands / addresses C0 to C7. Channel data DQa to DQh can be applied after four clock cycles corresponding to the write delay WL. Each channel data DQa to DQh can be 128-bit data DQ0 to DQ127. In response to the rising and falling edges of the corresponding channel clock signals CKa, CKb... or CKh, four data D1 to D4 corresponding to the burst length BL can be sequentially input through one data terminal. Fig.14 An assumption is shown that each piece of 128-bit data DQ0 to DQ127 is input through a corresponding one of 128 data terminals, and the same four pieces of data D1 to D4 are sequentially input through each data terminal.

[0106] The channel monitoring unit CHMa" can receive the buffered channel data (dqb0 to dqb127), and generate the data D1 and D3 as odd data dfa, and generate the data D2 and D4 as even data dsa. The channel monitoring unit CHMa" can generate the odd data dfa and the even data dsa as corresponding channel output data dfsa. Each channel monitoring unit CHMb" to CHMh" can generate one of the corresponding channel output data dfsb to dfsh. The channel output data dfsa to dfsh can be stored in parallel in the storage unit 42. In response to the buffered channel clock signal ckba, the storage unit 42 can multiply the channel output data dfsa for the memory channel MCHa stored in the storage unit 42 by 4 and output it, that is, the storage unit 42 can sequentially output a total of 16 bits of parallel data. Although not shown, the corresponding channel output data dfsb, dfsc ... or dfsh for the corresponding memory channel MCHb, MCHc ... or MCHh stored in the storage unit 42 may be multiplied by 4 and output in response to the corresponding buffer channel clock signal ckbb, ckbc ... or ckbh, that is, the storage unit 42 may sequentially output a total of 16 bits of parallel data. In this case, the storage unit 42 may be a serial-to-parallel converter.

[0107] like Fig.14 As shown above Fig.13 The monitoring unit 40" shown in the figure can receive the corresponding channel data DQa, DQb... or DQh (or the corresponding buffered channel data dqba, dqbb... or dqbh) applied in DDR, which will be arranged at the center of the corresponding channel clock signal CKa, CKb... or CKh (or the corresponding buffered channel clock signal ckba, ckbb... or ckhb), and output the monitoring data md generated in SDR, which will be arranged at the edge of the corresponding channel clock signal CKa, CKb... or CKh (or the corresponding buffered channel clock signal ckba, ckbb... or ckbh).

[0108] In addition, the above Fig.13 The monitoring unit 40" shown in FIG. 4 may not include the seventh to ninth triggers FF7 to FF9. Fig.13 When the monitoring unit 40" shown in does not include the seventh to ninth triggers FF7 to FF9, the monitoring unit 40" can generate the corresponding channel data DQa, DQb... or DQh (or the corresponding buffered channel data dqba, dqbb... or dqbh) as monitoring data md through the storage unit 42. That is, the monitoring unit 40" can receive the corresponding channel data DQa, DQb... or DQh (or the corresponding buffered channel data dqba, dqbb... or dqbh) (which is applied to be arranged at the center of the corresponding channel clock signal CKa, CKb... or CKh (or the corresponding buffered channel clock signal ckba, ckbb... or ckbh)), and generate monitoring data md output in DDR.

[0109] Despite the above Fig.13 The monitoring unit 40" shown in FIG. 4 may be configured to monitor all channel data DQa to DQh applied to eight memory channels (MCHa to MCHh), but the inventive concept may be configured to monitor all or part of the channel data of a specific channel. In addition, the above Fig.13 The monitoring unit 40 ″ shown in FIG. 4 may not include the storage unit 42 . In this case, the monitoring unit 40 ″ may be configured to output only channel data of specific channels corresponding to at least the number of first DA terminals dab for monitoring.

[0110] Fig.15 41 may have a configuration in which a fifth selector SEL5 is added to the monitoring unit 41. Figure 6 The monitoring unit 40 shown, Fig.10 The monitoring unit 40' shown, and Fig.13The monitoring unit 40" is shown. Fig.15 In the example, md1 indicates that Figure 6 The monitoring unit 40 shown or Fig.10 The monitoring unit 40' shown in FIG. 1 outputs monitoring data, and md2 represents the monitoring data outputted from Fig.13 The monitoring unit 40" shown outputs monitoring data.

[0111] refer to Fig.15 , the fifth selector SEL5 may output the monitoring data md1 or the monitoring data md2 as the monitoring data md in response to the fourth selection signal RGS.

[0112] The monitoring unit 40, 40', 40" or 41 of the base die BD according to an exemplary embodiment of the inventive concept may output all or part of the applied channel clock signals CKa to CKh, channel commands / addresses CAa to CAh, and / or channel data DQa to DQh as real-time monitoring data md.

[0113] In system-level test mode or normal mode, by storing and Figure 7B The mode setting code applied together with the mode register setting command MODE REGISTER SET shown in the figure can set the above-mentioned first to fourth selection signals EOS, RCS, CHS and RGS and the DA enable signal DAEN, wherein the MODE REGISTER SET is applied through the first command / address bump in the mode setting register (not shown) included in the base die BD.

[0114] According to an exemplary embodiment of the present invention, in a system-level test mode or a normal mode, a channel clock signal, a channel command / address, or a channel data of an HBM device applied from a controller to a system device can be monitored externally in real time. For example, monitoring can include sending a channel clock signal, a channel command / address, and a channel data received from a controller to a specific i / o terminal (e.g., a direct access terminal) of a base die BD through a monitoring circuit of the base die BD of the memory device. Monitoring can include sending information (e.g., monitoring data) received at these i / o terminals to a host (e.g., a host that originally sent instructions to the controller) to check whether the information sent to the memory device accurately reflects the information originally sent from the host to the controller. For example, the host may include one or more comparison circuits to compare the monitoring data with the original data sent from the host to the controller.

[0115] Although the embodiments of the present invention have been described with reference to the accompanying drawings, it should be understood by those skilled in the art that various modifications may be made without departing from the scope of the present invention and without changing the basic features. Therefore, the above embodiments should be considered as merely illustrative and not for limiting purposes.

Claims

1. A memory device, comprising: Base tube die; as well as A plurality of memory dies stacked on the base die and electrically connected to the base die through a plurality of substrate through vias, The base tube core comprises: a plurality of first terminals configured to receive channel signals or channel data from outside the memory device during a first operation mode, a monitoring unit configured to generate monitoring data from at least a portion of the channel signals or channel data received during the first operating mode, a plurality of second terminals configured to receive a test signal or test data from outside the memory device during the second operation mode, and configured to receive the monitoring data from the monitoring unit during the first operation mode to generate the monitoring data to the outside of the memory device, Among them, in the first operating mode, the channel signal and the channel data are sent to the multiple memory tube cores through the multiple first terminals for accessing the multiple memory tube cores, and at least a part of the channel signal or the channel data is also sent through the monitoring unit and the multiple first output buffers to be output from the base tube core at the multiple second terminals.

2. The memory device of claim 1, wherein: The first operating mode is a system level test mode or a normal mode, and The second operation mode is a direct access mode, in which the test signals and test data are transmitted to the plurality of memory dies through the plurality of second terminals as direct access terminals for testing the plurality of memory dies.

3. The memory device of claim 2, wherein: The direct access terminals are used for direct access testing operations during the second operating mode and for monitoring operations during the first operating mode.

4. The memory device of claim 3, wherein the base die further comprises: a plurality of first input buffers configured to receive the channel signals or channel data from the plurality of first terminals during a first operation mode to generate the at least a portion of the received channel signals or channel data to the monitoring unit, a plurality of second input buffers configured to receive the test signals or test data from the plurality of second terminals during a second operation mode, and The plurality of first output buffers are configured to receive the monitoring data from the monitoring unit during a first operation mode to generate the monitoring data to the plurality of second terminals.

5. The memory device of claim 4, wherein: During a first operating mode, the at least a portion of the channel signals and channel data received at the plurality of first input buffers are sent to the plurality of memory dies simultaneously with being sent to the monitoring unit.

6. The memory device of claim 1, wherein: The test signal and the test data include test information, and the plurality of second terminals are all used to receive the test information during the second operation mode and are all used to receive the monitoring data during the first operation mode.

7. The memory device of claim 1, wherein: The memory device is configured to output channel data received from the plurality of memory dies through the plurality of second output buffers during a first operation mode, and to output test data received from the plurality of memory dies through the plurality of first output buffers during a second operation mode.

8. The memory device according to claim 2, wherein: Each of the plurality of memory dies includes at least one memory channel, and the plurality of substrate through vias connected to the plurality of signal terminals and the plurality of data terminals, and each of the plurality of memory dies is configured to receive a corresponding signal or corresponding data transmitted from the base die through the plurality of substrate through vias.

9. The memory device according to claim 1, wherein: The channel signal includes a channel clock signal and a channel command / address, and The monitoring unit is configured to receive the channel command / address and at least a portion of the channel data applied at a double data rate (DDR) in response to the channel clock signal, and generate the monitoring data at a single data rate (SDR) or DDR.

10. The memory device of claim 9, wherein: The monitoring unit is configured to receive the channel command / address in response to the channel clock signal, and generate at least a portion of a row command / address and a column command / address included in the channel command / address as the monitoring data.

11. The memory device according to claim 10, wherein: The monitoring unit includes a channel monitoring unit for each of the plurality of memory dies, and The channel monitoring unit includes a row monitoring unit and a column monitoring unit. The row monitoring unit is configured to receive the row command / address in response to the channel clock signal and generate at least a portion of the odd row command / address and the even row command / address included in the row command / address as a row output signal. The column monitoring unit is configured to receive the column command / address in response to the channel clock signal and generate at least a portion of the odd column command / address and the even column command / address included in the column command / address as a column output signal.

12. The memory device of claim 11, wherein: The row monitoring unit includes a first flip-flop, a second flip-flop, and a third flip-flop, the first flip-flop being configured to receive and output the row command / address in response to the channel clock signal, the second flip-flop being configured to generate an output signal of the first flip-flop as the odd row command / address in response to an inverted channel clock signal generated by inverting the channel clock signal, the third flip-flop being configured to generate the row command / address as the even row command / address in response to the inverted channel clock signal, and The column monitoring unit includes a fourth flip-flop, a fifth flip-flop, and a sixth flip-flop, the fourth flip-flop being configured to receive and output the column command / address in response to the channel clock signal, the fifth flip-flop being configured to generate an output signal of the fourth flip-flop as the odd column command / address in response to the inverted channel clock signal, and the sixth flip-flop being configured to generate the column command / address as the even column command / address in response to the inverted channel clock signal, and The odd row command / address includes a first odd row command / address and a second odd row command / address generated sequentially, and the even row command / address includes a first even row command / address and a second even row command / address generated sequentially.

13. The memory device of claim 12, wherein: The row monitoring unit further includes a first selector configured to generate the odd row command / address or the even row command / address as the row output signal in response to a first selection signal, and The column monitoring unit further includes a second selector configured to generate the odd column command / address or the even column command / address as the column output signal in response to the first selection signal.

14. The memory device of claim 13, wherein: The channel monitoring unit further includes a third selector configured to generate the row output signal or the column output signal as a channel output signal in response to a second selection signal, and The monitoring unit further includes a fourth selector configured to select and output one of the channel output signals output from the channel monitoring unit in response to a third selection signal.

15. The memory device of claim 11, wherein: The row monitoring unit comprises: a first flip-flop configured to generate the row command / address as the odd row command / address in response to the channel clock signal, and a second flip-flop configured to generate the row command / address as the even-numbered row command / address in response to an inverted channel clock signal generated by inverting the channel clock signal, and Wherein, the column monitoring unit comprises: a third flip-flop configured to generate the column command / address as the odd-numbered column command / address in response to the channel clock signal, and The fourth flip-flop is configured to generate the column command / address as the even column command / address in response to the inverted channel clock signal.

16. The memory device of claim 15, wherein: The row monitoring unit further includes a first selector configured to generate the odd row command / address as the row output signal in response to the channel clock signal, or to generate the even row command / address as the row output signal in response to the channel clock signal, and The column monitoring unit further includes a second selector configured to generate the odd column command / address as the column output signal in response to the channel clock signal, or to generate the even column command / address as the column output signal in response to the channel clock signal, and Among them, the odd row command / address includes a first odd row command / address and a second odd row command / address generated sequentially, the even row command / address includes a first even row command / address and a second even row command / address generated sequentially, the row output signal includes the first odd row command / address, the first even row command / address, the second odd row command / address and the second even row command / address generated sequentially, and the column output signal includes the odd column command / address and the even column command / address generated sequentially.

17. The memory device of claim 16, wherein: The channel monitoring unit further includes a third selector configured to generate the row output signal or the column output signal as a channel output signal in response to a second selection signal, and The monitoring unit further includes a fourth selector configured to select and output one of the channel output signals output from the channel monitoring unit in response to a third selection signal.

18. The memory device of claim 9, wherein: The monitoring unit includes a channel monitoring unit for each of the plurality of memory dies, and The channel monitoring unit includes a first trigger, a second trigger, a third trigger and a storage unit, the first trigger is configured to receive and output the channel data in response to the channel clock signal, the second trigger is configured to generate an output signal of the first trigger as odd data in response to an inverted channel clock signal generated by inverting the channel clock signal, the third trigger is configured to generate the channel data as even data in response to the inverted channel clock signal, and the storage unit is configured to store the odd data and the even data in parallel in response to the channel clock signal, and sequentially generate the odd data and the even data as monitoring data.

19. A memory system device, comprising: System equipment substrate; A memory device, comprising a base die and a group of memory dies stacked on the system device substrate, the base die being electrically connected to the group of memory dies via substrate through-holes; Controller; as well as an interposer mounted on the system device substrate, and the memory device and the controller mounted on the interposer, wherein the interposer electrically connects the memory device to the controller, wherein: The controller is configured to receive control signals and data signals as inputs to the memory system device and, based on the inputs, output a channel clock signal, a channel command / address, and channel data to the memory device; and The base die is constructed as follows: receiving the channel clock signal, channel command / address and channel data from the controller at a first set of input / output (i / o) terminals of the base die; sending the channel clock signal, channel commands / addresses, and channel data to the set of memory dies; and sending at least a portion of one or more of the channel clock signal, the channel command / address and the channel data to a second set of I / O terminals of the base die through a monitoring unit, The base die is further constructed such that: a second group of buffers connected to the second group of I / O terminals receives a test clock signal, a test command / address, and test data from outside the base die during a direct access test mode, and receives at least a portion of one or more of the channel clock signal, channel command / address, and channel data during a normal mode or a system level test mode.

20. The memory system device according to claim 19, wherein: The at least a portion of one or more of the channel clock signal, channel command / address and channel data is sent to monitor whether the control signal and data signal accurately correspond to the channel clock signal, channel command / address and channel data.

21. The memory system device according to claim 19, wherein: The base die also includes: a first set of buffers connected to the first set of I / O terminals and connected to receive the channel clock signal, channel command / address, and channel data from the first set of I / O terminals; and The second group of buffers is connected to the second group of I / O terminals and is connected to send the at least a portion of one or more of the channel clock signal, channel command / address, and channel data to the second group of I / O terminals.

22. The memory system device according to claim 21, wherein: The second set of buffers is also connected to receive test clock signals, test commands / addresses, and test data from outside the base die.

23. The memory system device according to claim 21, wherein: The monitoring unit is connected between the first group of buffers and the second group of buffers, and is constructed to: send signals output from the first group of buffers to the second group of buffers during a first operating mode of the memory device, and prevent signals output from the first group of buffers from being sent to the second group of buffers during a second operating mode of the memory device.

24. The memory system device according to claim 19, wherein: The number of terminals of the first group of i / o terminals is greater than the number of terminals of the second group of i / o terminals.

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