Method and system for controlling retention margin of semiconductor memory device

Abstract

Embodiments herein disclose a system for controlling a hold margin in a semiconductor memory device. The system includes a programmable RC network communicatively coupled to at least one delay logic circuit, a latch clock generator, and a latch circuit. A combination of a wire and a logic circuit placed across at least one of the columns and rows of the semiconductor memory device is used to cause a delay associated with a clock path. A combination of a wire routed across at least one of the columns and rows of the semiconductor memory device, at least one of the load cells, and at least one of the delay logic circuits is used to cause a delay associated with a data path. The system is configured to control a hold margin based on a delay associated with the data path and a delay associated with the clock path.

Description

Technical Field

[0001] The present application relates to semiconductor memory devices, and more particularly to methods and systems for controlling a hold-margion of semiconductor memory devices. Background Art

[0002] A system on a chip (SOC) includes a semiconductor memory device (e.g., on-chip memory, etc.). The on-chip memory typically occupies 10% to 40% of the area of ​​the SOC. The on-chip memory may be a static random access memory (SRAM), a read-only memory (ROM), and a register file. The on-chip memory includes two types of hardware circuits (e.g., a bit cell array circuit and a peripheral circuit). The bit cell array circuit includes an array of bit cells. Each bit cell stores 1 bit of data. The peripheral circuit includes logic gates for controlling read operations and write operations.

[0003] The retention margin of an on-chip memory indicates the delay between an internal clock signal and a data signal (e.g., an address signal, an enable signal, etc.). Figure 1 As shown, the hold margin corresponds to a data path delay (TD2) that is greater than the internal clock path delay (TD1). Typically, the data signal is delayed to satisfy the hold margin. Figure 1 An implementation of delays using logic gates in a data path is shown. Circuit 100 includes a clock generator 102, a set of delay logic 104a to 104c, logic 106, a latch clock generator 108, a latch 110, a decoder 112, a set of input / output (IO) circuits 114a-114c. Latch clock generator 108 is connected to latch 110, wherein latch 110 is connected to decoder 112. Clock generator 102, a set of delay logic 104a-104c, logic 106, and latch clock generator 108 are included in a control block 150.

[0004] Since logic gate delays vary across process, voltage, and temperature (PVT) corners, a very high number of delay logics 104a-104c is required to meet the retention margin across the PVT range. This results in limiting the performance of compilers associated with the SOC. In addition, the number of delay logics 104a-104c is placed based on the largest instance, so small instances will unnecessarily contain additional delays, which hinders the performance of the semiconductor memory device.

[0005] In addition, for semiconductor memory devices of different sizes, the amount of delay required to meet the retention margin is different. In addition, several delay logics 104a-104c are placed inside the control block 150, and the same control block is used across semiconductor memory devices of different sizes, so that the number of delay units cannot be changed based on the size of the semiconductor memory device, so that the delay required for the largest instance (i.e., the larger number of IO circuits used) is also used in the smaller instance (i.e., the smaller number of IO circuits used). This hinders the performance of the smaller instance.

[0006] It would therefore be desirable to address the above-mentioned shortcomings or other deficiencies or at least provide a useful alternative.

[0007] Purpose of the Invention

[0008] A primary object of the embodiments herein is to provide a method and system for controlling a retention margin of a semiconductor memory device.

[0009] It is another object of embodiments herein to induce a delay associated with a clock path using a combination of conductive lines and logic circuits placed across at least one of the columns and rows of a semiconductor memory device.

[0010] Another object of embodiments herein is to induce a delay associated with a data path using a combination of conductive lines placed across at least one of columns and rows of a semiconductor memory device, at least one load cell, and at least one delay logic circuit.

[0011] Another object of embodiments herein is to control a hold margin based on a delay associated with a data path and a delay associated with a clock path. Summary of the invention

[0012] Embodiments herein disclose a method for controlling a hold margin of a semiconductor memory device. The method includes using a combination of a conductor placed across at least one of the columns and rows of the semiconductor memory device and a logic circuit to cause a delay associated with a clock path. In addition, the method includes using a combination of a conductor placed across at least one of the columns and rows of the semiconductor memory device, at least one load unit, and at least one delay logic circuit to cause a delay associated with a data path. In addition, the method includes controlling a hold margin based on a delay associated with the data path and a delay associated with the clock path.

[0013] Embodiments herein disclose a system for controlling a hold margin in a semiconductor memory device. The system includes at least one delay logic circuit, a latch clock generator, a clock generator, and a programmable RC network. The clock generator generates a clock signal and a data path. The programmable RC network is communicatively coupled to the at least one delay logic circuit, the latch clock generator, and the latch circuit. A combination of a wire placed across at least one of the columns and rows of a semiconductor memory device and a logic circuit is used to cause a delay associated with the clock path. A combination of a wire placed across at least one of the columns and rows of a semiconductor memory device, at least one of the load units, and at least one of the delay units is used to cause a delay associated with the data path. The system is configured to control the hold margin based on a delay associated with the data path and a delay associated with the clock path.

[0014] When considered in conjunction with the following description and the accompanying drawings, these and other aspects of the embodiments herein will be better appreciated and understood. However, it should be understood that the following description, although pointing out preferred embodiments and many specific details thereof, is provided in an illustrative and non-limiting manner. Without departing from the gist of the embodiments herein, many changes and modifications may be made within the scope of the embodiments herein, and the embodiments herein include all such modifications. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The present invention is illustrated in the accompanying drawings, and throughout the drawings, the same reference numerals indicate corresponding parts in the various drawings. The embodiments herein will be better understood from the following description with reference to the accompanying drawings, in which:

[0016] Figure 1 is a circuit diagram illustrating a method of implementing a delay using logic gates according to the prior art;

[0017] Figure 2 is a circuit diagram illustrating RC network delays across columns for latch clock generation according to embodiments disclosed herein;

[0018] Figure 3 is a circuit diagram illustrating RC network delays across rows for latching clock generation according to embodiments disclosed herein;

[0019] Figure 4 is a circuit diagram illustrating RC network delays across rows and columns for latch clock generation according to embodiments disclosed herein;

[0020] Figure 5 is a circuit diagram illustrating RC network delays across rows and columns for different latch clock generation according to embodiments disclosed herein; and

[0021] Figure 6is a flowchart illustrating a method for controlling a retention margin of a semiconductor memory device according to an embodiment disclosed herein. DETAILED DESCRIPTION

[0022] The embodiments herein and their various features and advantageous details will be explained more fully with reference to the non-limiting embodiments illustrated in the accompanying drawings and described in detail in the following description. Descriptions of known components and processing techniques are omitted so as not to unnecessarily obscure the embodiments herein. Moreover, the various embodiments described herein are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments. Unless otherwise indicated, the term "or" as used herein refers to non-exclusive. The examples used herein are intended only to facilitate understanding of the manner in which the embodiments herein can be practiced, and further enable those skilled in the art to practice the embodiments herein. Therefore, these examples should not be interpreted as limiting the scope of the embodiments herein.

[0023] As traditional in the art, embodiments can be described and illustrated according to the blocks that perform the described one or more functions. These blocks, which may be referred to herein as units or modules, are implemented by analog or digital circuits such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hard-wired circuits, etc., and may be optionally driven by firmware and software. These circuits may, for example, be embodied in one or more semiconductor chips, or on substrate supports such as printed circuit boards. The circuits constituting the blocks may be implemented by dedicated hardware or by a processor (e.g., one or more programmed microprocessors and associated circuits) or by a combination of dedicated hardware that performs some functions of the blocks and processors that perform other functions of the blocks. Without departing from the scope of the present invention, each block of the embodiment may be physically separated into two or more interacting and discrete blocks. Similarly, without departing from the scope of the present invention, the blocks of the embodiment may be physically combined into more complex blocks.

[0024] The accompanying drawings are used to help to easily understand various technical features, and it should be understood that the embodiments presented herein are not limited by the accompanying drawings. Like this, the disclosure should be interpreted as extending to any changes, equivalents and substitutes other than those specifically proposed in the accompanying drawings. Although the terms first, second, etc. can be used to describe various elements in this article, these elements should not be limited by these terms. These terms are usually only used to distinguish one element from another element.

[0025] The terms first level and second level, high and low, and 1 and 0 as used in the following description can be used to describe various logic states known in the art. The specific voltage values ​​of the second and first levels are arbitrarily defined with respect to each circuit. In addition, the voltage values ​​of the second level and the first level can be defined differently for each signal such as a clock and a digital data signal. Although specific circuits have been described, it will be understood by those skilled in the art that not all disclosed circuits are required to practice the present invention. In addition, certain well-known circuits are not described to maintain attention to the present invention. Similarly, although in some locations, the description involves logic "0" and logic "1" or low and high, it is understood by those skilled in the art that the logic values ​​can be switched, wherein the rest of the circuit is adjusted accordingly without affecting the operation of the present invention.

[0026] Some parts of the following detailed description are presented in terms of processes, logic blocks, processing, and other symbolic representations of operations on data bits within semiconductor memory devices. These descriptions and representations are means used by technicians in the field of data processing to most effectively convey the essence of their work to other technicians in the field. In this application, processes, logic blocks, processing, etc. are considered to be self-consistent sequences of steps or instructions that lead to desired results. These steps are steps that require physical manipulation of physical quantities. Although not necessarily, these quantities are usually in the form of electrical or magnetic signals that can be stored, transmitted, combined, compared, and otherwise manipulated in a computer system.

[0027] Embodiments herein provide a system for controlling a hold margin in a semiconductor memory device. The system includes at least one delay logic circuit, a latch clock generator, a clock generator, and a programmable RC network. The clock generator generates a clock signal and a data path. The programmable RC network is communicatively coupled to at least one delay logic circuit, a latch clock generator, and a latch circuit. A combination of a wire and a logic circuit placed across at least one of the columns and rows of a semiconductor memory device is used to induce a delay associated with a clock path. A combination of at least one of a wire and a load unit placed across at least one of the columns and rows of a semiconductor memory device, and at least one of the delay logic circuits is used to induce a delay associated with a data path. The system is configured to control the hold margin based on a delay associated with the data path and a delay associated with the clock path.

[0028] In an embodiment, a delay associated with a clock path is induced using a combination of a wire placed across a column of a semiconductor memory device and a logic circuit. A delay associated with a data path is induced using a combination of at least one of a wire placed across a column of a semiconductor memory device and a load cell, and at least one of a delay logic circuit. The system is configured to control a hold margin based on the delay associated with the data path and the delay associated with the clock path.

[0029] In an embodiment, a delay associated with a clock path is induced using a combination of a wire and a logic circuit placed across a column of a semiconductor memory device. A delay associated with a data path is induced using a combination of at least one of a wire and a load unit placed across multiple columns of a semiconductor memory device and at least one of a delay logic circuit. The system is configured to control a hold margin based on the delay associated with the data path and the delay associated with the clock path.

[0030] In an embodiment, a delay associated with a clock path is induced using a combination of a wire placed across a row of a semiconductor memory device and a logic circuit. A delay associated with a data path is induced using a combination of at least one of a wire placed across a row of a semiconductor memory device and a load cell, and at least one of a delay logic circuit. The system is configured to control a hold margin based on the delay associated with the data path and the delay associated with the clock path.

[0031] In an embodiment, a delay associated with a clock path is induced using a combination of a wire and a logic circuit placed across rows of a semiconductor memory device. A delay associated with a data path is induced using a combination of at least one of a wire and a load unit placed across multiple rows of a semiconductor memory device and at least one of a delay logic circuit. The system is configured to control a hold margin based on the delay associated with the data path and the delay associated with the clock path.

[0032] In an embodiment, a delay associated with a clock path is induced using a combination of wires placed in a combination of rows and columns of a semiconductor memory device and a combination of logic circuits. A delay associated with a data path is induced using a combination of at least one of wires placed in a combination of rows and columns of a semiconductor memory device and a load cell, and at least one of delay logic circuits. The system is configured to control a hold margin based on the delay associated with the data path and the delay associated with the clock path.

[0033] In an embodiment, a delay associated with a clock path is induced using a combination of wires placed in a combination of rows and columns of a semiconductor memory device and a combination of logic circuits. A delay associated with a data path is induced using a combination of at least one of wires placed in a combination of multiple rows and multiple columns of a semiconductor memory device and a load cell, and at least one of delay logic circuits. The system is configured to control a hold margin based on the delay associated with the data path and the delay associated with the clock path.

[0034] In an embodiment, the system is configured to determine a required amount of delay associated with the data path for controlling the hold margin when the number of columns is minimized.

[0035] In an embodiment, the system is configured to determine a required amount of delay associated with the data path for controlling the hold margin when the number of columns is maximum.

[0036] In an embodiment, a system is configured to control a retention margin of a semiconductor memory device using a programmable RC network based at least on a difference between a desired delay amount associated with a data path when the number of columns is maximum and a desired delay amount associated with the data path when the number of columns is minimum.

[0037] In an embodiment, the system is configured to determine a required amount of delay associated with the data path to control the hold margin when the number of rows is minimized.

[0038] In an embodiment, the system is configured to determine a required amount of delay associated with the data path to control the hold margin when the number of rows is maximum.

[0039] In an embodiment, a system is configured to control a retention margin of a semiconductor memory device using a programmable RC network based at least on a difference between a desired delay amount associated with a data path when the number of rows is maximum and a desired delay amount associated with the data path when the number of rows is minimum.

[0040] In an embodiment, the hold margin is a hold margin based on parasitic delays.

[0041] In an embodiment, the retention margin may be referred to as an internal retention margin of the SRAM.

[0042] In an embodiment, the hold margin corresponds to a difference between a delay associated with the data path and a delay associated with the clock path.

[0043] In an embodiment, the delay associated with the data path is based on the operation of at least one delay logic circuit in conjunction with a programmable RC network.

[0044] In an embodiment, the system is configured to manage at least one holding margin across a PVT corner.

[0045] Unlike conventional circuits, the proposed system and method can be used to control parasitic delay-based retention margin in high-speed memories (e.g., SRAM, ROM, etc.). The proposed system and method can be used to improve the performance of high-speed memories. In an example, for a compiler (e.g., RA1HC compiler for 28nm, SS28LPP_RA1HC compiler, etc.), a performance gain of 2% to 6% has been achieved based on the size of the memory.

[0046] The proposed system and method can be used to reduce the logic gates in the control block of the semiconductor memory device as a smaller delay unit requirement in the semiconductor memory device. This leads to regional gain in the case where some macro areas are limited by the control block. In traditional circuits, the physical area occupied by the semiconductor memory device is more due to the control block requiring more area due to the higher amount of delay logic units, so that the high area leads to increased circuit design costs. However, the proposed method can be used to reduce system design costs because the hold margin is controlled based on the delay associated with the data path and the delay associated with the clock path, and the delay associated with the data path is implemented using wires placed across the columns and rows of the semiconductor memory device. In advanced technology semiconductor memory devices, the logic gate variation is higher than the RC delay variation, so that the method will be more effective in technology scaling. In the proposed circuit, the wires are placed across the columns and rows of the semiconductor memory device to reduce the delay unit variation in the semiconductor memory device.

[0047] The proposed method can be implemented in a compiler (e.g., 28nm SS28RA1HC memory compiler, 10nm RF2HS memory compiler, etc.), an SRAM compiler, a wireless communication device, a TV, an embedded system, an application processor, or any other digital SoC or integrated circuit (IC).

[0048] Referring now to the drawings, and more particularly to Figures 2 to 6 , wherein like reference numerals consistently denote corresponding features throughout the drawings, and a preferred embodiment is shown.

[0049] Figure 2 is a circuit diagram 200 illustrating RC network delays across columns for latching clock generation according to embodiments disclosed herein.

[0050] Generally, a semiconductor memory device (e.g., SRAM, ROM, register file, etc.) includes a memory cell array (not shown) having a plurality of memory cells (not shown) arranged in a matrix of rows and columns. A plurality of word lines (not shown) are arranged to correspond to the respective rows of the memory cells. A plurality of bit lines (not shown) are arranged to correspond to the respective columns of the memory cells.

[0051] Specifically, the memory cells are each placed at a corresponding intersection between a word line and a bit line pair. The memory cells are arranged in a matrix constituting a memory cell array for storing information.

[0052] refer to Figure 2 , the circuit diagram 200 includes a control block 150, a latch 110, a decoder 112, an input / output circuit (IO-0114a-114c) and a set of loads 116a-116n, wherein the control block 150 includes a clock generator 102, a delay logic 104, a logic 106 and a latch clock generator 108. Clock inputs and enable inputs (e.g., data inputs, address inputs, etc.) are provided to the clock generator 102. The clock generator 102 provides a node A, wherein the node A is a diverging point for a clock path (D1) and a data path (D2). The clock path (D1) includes logic 106 and a conductor routed across a column of a semiconductor memory device. The latch clock generator 108 is coupled to the latch 110, wherein the latch 110 is coupled to the decoder 112.

[0053] A delay associated with the clock path (D1) is caused using a combination of wires and logic 106 routed across columns of the semiconductor memory device. A data path (D2) is implemented using a combination of wires placed across columns of the semiconductor memory device, loads 116a-116n, and delay cells (i.e., delay logic 104) to fix the retention margin. A delay associated with the data path (D2) is caused using a combination of at least one of the wires and loads 116a-116n, and at least one of the delay cells placed across columns of the semiconductor memory device. The clock path (D1) and the data path (D2) converge at node B, so that the data path delay (TD2) is greater than the clock path delay (TD1).

[0054] Furthermore, the size of the programmable RC network is a function of the memory size (IO-0 to IO-n 114a-114c), and as the size of the memory increases / decreases, "n" increases / decreases, causing the delay provided by the RC network to scale with "n". The RC network delay varies less than the delay cell variation across PVT corners. This results in higher performance of the semiconductor memory device being achieved.

[0055] Furthermore, the latch clock can be identified based on the latch 110 on the silicon. By traversing the latch clock, the latch clock generator 108 can be identified and the input to the latch clock generator 108 can be detected if the input is routed across rows / columns.

[0056] Figure 33 is a circuit diagram 300 illustrating RC network delay across rows for latching clock generation according to an embodiment as disclosed herein. A semiconductor memory device includes a memory cell array (not shown) having a plurality of memory cells (not shown) arranged in a matrix of rows and columns. A plurality of word lines (not shown) are arranged to correspond to respective rows of memory cells. A plurality of bit lines (not shown) are arranged to correspond to respective columns of memory cells.

[0057] The circuit diagram 300 includes a control block 150, a latch 110, decoders 112a-112d, and a set of loads 116a-116n, wherein the control block 150 includes a clock generator 102, a delay logic 104, a logic 106, and a latch clock generator 108. A clock input and an enable input are provided to the clock generator 102. The latch clock generator 108 is connected to the latch 110. The latch 110 is connected to the decoder 112d.

[0058] The clock generator 102 provides a node A, where the node A is a branch point for a clock path (D1) and a data path (D2). The clock path (D1) includes logic 106 and a conductor placed across a row of a semiconductor memory device. The delay associated with the clock path (D1) is caused using a combination of the conductor and logic 106 routed across a row of a semiconductor memory device.

[0059] The data path (D2) is implemented using a combination of wires and loads 116a-116n placed across columns of the semiconductor memory device, and delay logic 104 to fix the hold margin. The delay associated with the data path (D2) is caused using a combination of at least one of the wires and loads 116a-116n placed across columns of the semiconductor memory device, and at least one of the delay units 104. The clock path (D1) and the data path (D2) converge at node B, so that the data path delay (TD2) is greater than the clock path delay (TD1) (i.e., hold margin = TD2-TD1>0).

[0060] Figure 4 is a circuit diagram 400 illustrating RC network delays across rows and columns for latch clock generation.

[0061] refer to Figure 4 , the semiconductor memory device includes a memory cell array (not shown) having a plurality of memory cells (not shown) arranged in a matrix of rows and columns. A plurality of word lines (not shown) are arranged to correspond to the respective rows of the memory cells. A plurality of bit lines (not shown) are arranged to correspond to the respective columns of the memory cells.

[0062] Circuit diagram 400 includes control block 150, latches 110a and 110b, decoders 112a-112e, IO circuits 114a-114c, and a set of loads 116a-116c, wherein control block 150 includes clock generator 102, delay logic 104, logic 106a and 106b, and latch clock generator 108. Clock input and enable input are provided to clock generator 102. Latch clock generator 108 is connected to latches 110a and 110b. Latch 110a is connected to decoder 112d. Latch 110b is connected to decoder 112e.

[0063] The clock input and the enable input are provided to the clock generator 102. The clock generator 102 provides a node A, where the node A is a branching point for the clock path (D1) and the data path (D2).

[0064] In the circuit diagram 400, there are two holding margins (eg, HM1 and HM2), where HM1 = D2_HM1 - D1_HM1, and HM2 = D2_HM2 - D1_HM2. The shunt point for both HM1 and HM2 is the same (ie, node A).

[0065] The use of a combination of conductive lines and logic 106a and 106b placed across the columns and rows of the semiconductor memory device introduces a delay associated with the clock path (D1).

[0066] The delay associated with the data path (D1) is caused using a combination of at least one of the wires and loads 116a-116f and at least one of the delay cells 104 placed across the columns and rows of the semiconductor memory device.

[0067] In addition, the convergence point (i.e., target point) for HM1 is node B_HM1, and the convergence point (i.e., target point) for HM2 is node B_HM2. The data paths (D2_HM1 and D2_HM2) are implemented using a combination of wires and loads 116a-116f placed across rows and columns of the semiconductor memory device and delay logic 104 to fix the holding margin.

[0068] Figure 5 is a circuit diagram 500 illustrating RC network delays across rows and columns for different latch clock generation according to embodiments disclosed herein.

[0069] refer to Figure 5 , the semiconductor memory device includes a memory cell array (not shown) having a plurality of memory cells (not shown) arranged in a matrix of rows and columns. A plurality of word lines (not shown) are arranged to correspond to the respective rows of the memory cells. A plurality of bit lines (not shown) are arranged to correspond to the respective columns of the memory cells.

[0070] The circuit diagram 500 includes a control block 150, a latch 110, a set of decoders 112a-112e, IO circuits 114a-114c, and a set of loads 116a-116f, wherein the control block 150 includes a clock generator 102, delay logic 104a and 104b, logic 106a and 106b, and latch clock generators 108a and 108b. The latch clock generator 108b is connected to the latch 110. The latch 110 is connected to the decoder 112e. The clock input and enable input are provided to the clock generator 102.

[0071] In the circuit diagram 500, there are two holding margins (i.e., HM1 and HM2), where HM1 = D2_HM1-D1_HM1, and HM2 = D2_HM2-D1_HM2. The shunt point for HM1 is node A_HM1, and the shunt point for HM2 is the same node A_HM2. The convergence point for HM1 is node B_HM1, and the convergence point for HM2 is node B_HM2.

[0072] In this design, different latch clock generators 108a and 108b are used for the two hold margins.

[0073] The delay associated with the clock paths (D1_HM1 and D1_HM2) is caused by the combination of wires and logic 106a and 106b routed across the columns and rows of the semiconductor memory device. The data path (i.e., D2_HM1) is implemented using a combination of wires and loads 116a-116c placed across the rows of the semiconductor memory device, and delay logic 104a, while the data path (i.e., D2_HM2) is implemented using a combination of wires and loads 116d-116f, and delay logic 104b extended across the columns of the semiconductor memory device.

[0074] In an embodiment, there are two hold margins (HM1 and HM2). HM1 = D2_HM1-D1_HM1. HM2 = D2_HM2-D1_HM2. The shunt point for HM1 is node A_HM1, and the shunt point for HM2 is the same node A_HM2, while the convergence point for HM1 is node B_HM1, and the convergence point for HM2 is node B_HM2. In this scheme, the two hold margins use different latch clock generators. Data path D2_HM1 is implemented using a combination of wires and load cells, delay logic that extend across rows, while data path D2_HM2 is implemented using a combination of wires and load cells, delay logic that extend across columns.

[0075] Figure 6600 is a flowchart illustrating a method for controlling a retention margin of a semiconductor memory device according to an embodiment disclosed herein. At 602, the method includes causing a delay associated with a clock path (D1) using a combination of a wire placed across at least one of a column and a row of a semiconductor memory device and logic 106. At 604, the method includes causing a delay associated with a data path (D2) using a combination of a wire placed across at least one of a column and a row of a semiconductor memory device and at least one load unit 116, at least one delay logic 104. At 606, the method includes controlling a retention margin based on a delay associated with the data path (D2) and a delay associated with the clock path (D1).

[0076] The proposed method may be used to determine the required amount of delay associated with the delay logic 104 in the data path (D2) to control the hold margin when the number of columns is minimized.

[0077] The proposed method can be used to determine the required amount of delay in the data path (D2) to control the hold margin when the number of columns is maximum.

[0078] The proposed method can be used to control the retention margin of a semiconductor memory device using a programmable RC network based at least on the difference between the required delay amount associated with a data path (D2) when the number of columns is maximum and the required delay amount associated with the data path (D2) when the number of columns is minimum.

[0079] The proposed method may be used to determine the required amount of delay associated with the delay logic 104 in the data path (D2) to control the hold margin when the number of rows is minimized.

[0080] In an embodiment, the method may be used to determine the required amount of delay in the data path (D2) when the number of rows is maximum to control the hold margin.

[0081] In an embodiment, the method may be used to control a retention margin of a semiconductor memory device using a programmable RC network based at least on a difference between a desired delay amount associated with a data path (D2) when the number of rows is maximum and a desired delay amount associated with the data path (D2) when the number of rows is minimum.

[0082] The various activities, actions, blocks, steps, etc. in method 600 can be performed in the order presented, in a different order, or simultaneously. In addition, in some embodiments, some activities, actions, blocks, steps, etc. can be omitted, added, modified, skipped, etc. without departing from the scope of the present invention.

[0083] The embodiments disclosed herein may be implemented by at least one software program running on at least one hardware device and performing network management functions to control elements. Figures 2 to 6 The elements shown in the drawings include blocks, elements, activities, actions, steps, which may be at least one of a hardware device, or a combination of a hardware device and a software module.

[0084] The foregoing description of specific embodiments will fully reveal the general nature of the embodiments herein so that others can easily modify and / or adapt such specific embodiments for various applications by applying current knowledge without departing from the general concepts, and therefore, these adaptations and modifications should and are intended to be understood as being within the meaning and scope of the equivalents of the disclosed embodiments. It should be understood that the wording or terminology used herein is for descriptive purposes rather than for limiting purposes. Therefore, although the embodiments herein have been described in accordance with preferred embodiments, those skilled in the art will recognize that the embodiments herein can be practiced with modifications within the spirit and scope of the embodiments described herein.

Claims

1. A method for controlling a retention margin of a semiconductor memory device, the method comprising: Using a combination of conductive lines and logic circuits placed across at least one of the columns and rows of the semiconductor memory device to cause a delay associated with the clock path; causing a delay associated with a data path using a combination of conductive lines placed across at least one of a column and a row of a semiconductor memory device, at least one load cell, and at least one delay logic circuit; as well as A hold margin is controlled based on a delay associated with a data path and a delay associated with a clock path, wherein the hold margin is a hold margin based on parasitic delays.

2. The method according to claim 1, wherein: The delay associated with the data path is based on the operation of at least one delay logic circuit in conjunction with a programmable resistor-capacitor RC network.

3. The method according to claim 1, wherein: The hold margin corresponds to the difference between the delay associated with the data path and the delay associated with the clock path.

4. The method according to claim 1, wherein: The method further includes managing hold margin across process, voltage, and temperature PVT corners.

5. The method according to claim 1, wherein: When the number of columns is minimized, a desired amount of delay associated with a delay logic circuit in the data path for controlling a hold margin is determined.

6. The method according to claim 5, wherein: When the number of columns is maximum, a required delay amount associated with a data path for controlling a retention margin is determined, wherein a difference between at least the required delay amount associated with the data path when the number of columns is maximum and the required delay amount associated with the data path when the number of columns is minimum is used to control the retention margin of a semiconductor memory device using a programmable resistor-capacitor RC network.

7. A system for controlling a retention margin in a semiconductor memory device, the system comprising: at least one delay logic circuit; Latch clock generator; a clock generator, wherein the clock generator generates a clock signal and provides nodes associated with the data path; and a programmable resistor-capacitor RC network, wherein the programmable resistor-capacitor RC network is communicatively coupled to the at least one delay logic circuit, the latch clock generator, and the latch circuit; and wherein a delay associated with a clock path is induced using a combination of conductive lines and logic circuits placed across at least one of the columns and rows of the semiconductor memory device, wherein the delay associated with the data path is induced using a combination of conductive lines placed across at least one of columns and rows of the semiconductor memory device, at least one load cell, and at least one delay logic circuit; and The system is configured to control the hold margin based on a delay associated with a data path and a delay associated with a clock path.

8. The system according to claim 7, wherein: The hold margin corresponds to the difference between the delay associated with the data path and the delay associated with the clock path.

9. The system according to claim 7, wherein: The hold margin is the hold margin based on parasitic delays.

10. The system according to claim 7, wherein: The delay associated with the data path is based on the operation of at least one delay logic circuit in conjunction with a programmable resistor-capacitor RC network.

11. The system according to claim 7, wherein: The system is configured to manage hold margins across process, voltage, and temperature PVT corners.

12. The system according to claim 7, wherein: The system is configured to determine a desired amount of delay associated with a delay logic circuit in a data path for controlling a hold margin when the number of columns is minimized.

13. The system according to claim 12, wherein: The system is configured to determine a required amount of delay in a data path for controlling a retention margin when the number of columns is maximum, wherein a difference between at least the required amount of delay associated with the data path when the number of columns is maximum and the required amount of delay associated with the data path when the number of columns is minimum is used to control the retention margin of the semiconductor memory device using a programmable resistor-capacitor RC network.

Images