High-precision texture filtering

Abstract

The present application relates to high-precision texture filtering. A texture filtering unit is described, the texture filtering unit comprising: an input terminal arranged to receive at least two texture values ​​and a plurality of filter coefficients per clock cycle, the plurality of filter coefficients relating to a plurality of different texture filtering methods; hardware logic arranged to convert the input texture values ​​into fixed-point representation; a coefficient merging logic block arranged to generate a single composite filter coefficient for each input texture value from the plurality of filter coefficients; a multiplier for each input texture value, wherein each multiplier is arranged to multiply one of the input texture values ​​by its corresponding single composite filter coefficient; an adding unit arranged to add together the outputs from each of the multipliers; hardware logic arranged to convert the outputs from the adding unit back into a floating-point format; and an output terminal arranged to output the converted outputs from the adding unit.

Description

Technical Field

[0001] This application relates to high-precision texture filtering. background

[0002] In 3D computer graphics, much of the information contained within a scene is encoded as surface properties of 3D geometry. Texture mapping, which is an efficient technique for encoding this information into a bitmap, is therefore an integral part of the process of rendering an image. It is often not possible to read directly from a texture, as the projection of 3D geometry often requires some form of resampling, and therefore, as part of rendering a scene, a graphics processing unit (GPU) performs texture filtering. This may be, for example, because the center of a pixel (in the rendered scene) is not aligned with the center of a texel in the texture (where a texture comprises an array of texels, such that a texel in the texture is analogous to a pixel in an image), and in different cases a pixel may be larger or smaller than a texel.

[0003] There are many different methods for texture filtering, including volumetric filtering, anisotropic filtering, and trilinear filtering, and in various examples, these methods can be applied in various combinations. Filtering can be a computationally expensive operation, and any errors in filtering (such as rounding errors) can cause visual artifacts in the rendered scene.

[0004] The embodiments described below are provided by way of example only and are not limiting of implementations that address any or all of the disadvantages of known methods of implementing texture filtering in hardware.

[0005] Overview

[0006] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

[0007] A texture filtering unit is described, comprising: an input terminal arranged to receive at least two texture values ​​and a plurality of filter coefficients per clock cycle, the plurality of filter coefficients being associated with a plurality of different texture filtering methods; hardware logic arranged to convert the input texture values ​​into a fixed point format representation; a coefficient merging logic block arranged to generate a single composite filter coefficient for each input texture value based on the plurality of filter coefficients; a multiplier for each input texture value, wherein each multiplier is arranged to multiply one of the input texture values ​​by its corresponding single composite filter coefficient; an adding unit arranged to add together the outputs from each of the multipliers; hardware logic arranged to convert the outputs from the adding unit back into a floating point format; and an output terminal arranged to output the converted outputs from the adding unit.

[0008] A first aspect provides a texture filtering unit implemented in hardware logic, the texture filtering unit comprising: a plurality of input terminals arranged to receive at least two texture values ​​and a plurality of filter coefficients per clock cycle, the plurality of filter coefficients comprising coefficients associated with a plurality of different texture filtering methods; format conversion logic arranged to convert the input texture values ​​from a floating point format to fixed point significands and exponents; a coefficient merging logic block arranged to generate a single composite filter coefficient for each input texture value based on the plurality of filter coefficients; a multiplier for each input texture value, wherein each multiplier is arranged to multiply the significand of one of the input texture values ​​by its corresponding single composite filter coefficient; an adding unit arranged to add together the outputs from each of the multipliers; hardware logic arranged to convert the output from the adding unit from a fixed point format to a floating point format; and an output terminal arranged to output the converted output from the adding unit.

[0009] A second aspect provides a method for performing texture filtering in hardware logic, the method comprising: in a texture filtering unit, receiving at least two texture values ​​and multiple filter coefficients per clock cycle, the multiple filter coefficients including coefficients associated with multiple different texture filtering methods; converting the input texture values ​​from a floating point format into fixed-point significant numbers and exponents; generating a single composite filter coefficient for each input texture value based on the multiple filter coefficients; in each of a plurality of multipliers, multiplying the significant number of one of the input texture values ​​by its corresponding single composite filter coefficient, wherein the multiple multipliers include a multiplier for each input texture value received in the clock cycle; adding the outputs from each of the multipliers together and converting the result from the fixed-point format into a floating point format; and outputting the result of the conversion.

[0010] The texture filtering unit described herein may be embodied in hardware on an integrated circuit. A method of manufacturing the texture filtering unit at an integrated circuit manufacturing system may be provided. An integrated circuit definition data set may be provided, which when processed in the integrated circuit manufacturing system configures the system to manufacture the texture filtering unit. A non-transitory computer readable storage medium may be provided, having stored thereon a computer readable description of the integrated circuit, which when processed causes a layout processing system to generate a circuit layout description for use in the integrated circuit manufacturing system to manufacture the texture filtering unit.

[0011] An integrated circuit manufacturing system can be provided, comprising: a non-transitory computer-readable storage medium having stored thereon a computer-readable integrated circuit description describing a texture filtering unit; a layout processing system configured to process the integrated circuit description to generate a circuit layout description of an integrated circuit embodying the texture filtering unit; and an integrated circuit generation system configured to manufacture the texture filtering unit based on the circuit layout description.

[0012] Computer program code for performing any of the methods described herein may be provided.A non-transitory computer-readable storage medium having computer-readable instructions stored thereon may be provided, which when executed at a computer system causes the computer system to perform any of the methods described herein.

[0013] As will be apparent to the skilled person, the above features may be combined as appropriate and with any aspects of the examples described herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Examples will now be described in detail with reference to the accompanying drawings, in which:

[0015] Figure 1 is a schematic diagram of an example graphics processing unit (GPU) pipeline;

[0016] Figure 2 is a schematic diagram of a first example texture filtering unit;

[0017] Figure 3 is a schematic diagram of a second example texture filtering unit;

[0018] Figure 4 is a schematic diagram of a third example texture filtering unit;

[0019] Figure 5 is a schematic diagram of an example coefficient merging logic block;

[0020] Figure 6 A computer system is shown in which a texture filtering unit as described herein is implemented; and

[0021] Figure 7 An integrated circuit manufacturing system for producing an integrated circuit embodying a texture filtering unit as described herein is shown.

[0022] The accompanying drawings illustrate different examples. The skilled person will recognize that the element boundaries (e.g., boxes, groups of boxes, or other shapes) shown in the figures represent an example of boundaries. In some examples, it is possible that an element can be designed as multiple elements, or multiple elements can be designed as one element. Where appropriate, common reference numerals are used to indicate similar features throughout the accompanying drawings. Detailed Description

[0023] The following description is presented by way of example to enable those skilled in the art to make and use the invention. The present invention is not limited to the embodiments described herein, and various modifications to the disclosed embodiments will be apparent to those skilled in the art.

[0024] The embodiments will now be described by way of example only.

[0025] Texture filtering is implemented in dedicated hardware within the GPU, and as mentioned above, this is a computationally expensive operation, and so this hardware can be quite large. Texture values ​​can be stored in any digital format (where each value typically corresponds to a texel center), but these are typically floating point values ​​(e.g., a half-precision binary floating point format that may be referred to as F16), and in current hardware, the floating point modules used to perform filtering include intermediate rounding steps, which means that the final output (i.e., the filtered value) is not completely precise, and this can lead to visual artifacts in the rendered scene.

[0026] A texture filtering unit is described herein that can be implemented within a GPU and includes only a single multiplication stage for each input texture value. To achieve this, hardware logic within the texture filtering unit generates a single composite filter coefficient for each input texture value. The texture filtering unit described herein converts the input texture values ​​from a floating point form (e.g., F16 form) to a type of fixed point representation (e.g., including a fixed point significand and an exponent) so that they can be accurately represented at all stages of filtering and there are no intermediate rounding steps. Therefore, the output filtered values ​​are completely accurate. In addition to providing completely accurate output values, the hardware described herein further provides high throughput (e.g., two texture values ​​per clock cycle), requires very little control logic, and can be implemented as hardware of similar size to current, less accurate hardware, and can further have reduced power consumption (e.g., the hardware area of ​​the texture filtering unit described herein is smaller than that of current hardware implementations).

[0027] Figure 1 1 is a schematic diagram of an example graphics processing unit (GPU) pipeline 100, which may be implemented in hardware within a GPU and includes a texture filtering unit 102. Figure 1 As shown, pipeline 100 includes a geometry processing stage 104 and a rasterization stage 106. Data generated by geometry processing stage 104 may be passed directly to rasterization stage 106, and / or some data may be written to memory (e.g., parameter memory, Figure 1 ), and then read from memory by the rasterization stage 106.

[0028] The geometry processing stage 104 includes a vertex shader 108 and a tessellation unit 110. In various examples, it may also include a tiling unit ( Figure 1 There may be one or more optional hull shaders ( hull_shaders ) between the vertex shader 108 and the tessellation unit (or tessellation unit) 110. Figure 1 The geometry processing stage 104 may also include Figure 1 Other components not shown, such as memory and / or other components.

[0029] Vertex shader 108 is responsible for performing per-vertex calculations. Unlike vertex shaders, hardware tessellation unit 110 (and any optional hull shader) operates per-patch rather than per-vertex. Tessellation unit 110 outputs primitives.

[0030] The rasterization stage 106 renders some or all of the primitives generated by the geometry processing stage 104. The rasterization stage 106 includes a texture filter unit 102, a pixel shader 112, and may include Figure 1 The structure and operation of the texture filtering unit 102 will be described in detail below.

[0031] Figure 2 is a schematic diagram of a first example texture filtering unit 200, which may be implemented as Figure 1 The texture filtering unit 102 in the pipeline 100 is as follows. Figure 2As shown, texture filtering unit 200 includes several inputs, including a plurality of filter coefficients 202 and two texture value inputs: input A0 204 and input A1 206. In this example, texture filtering unit 200 may receive two texture values ​​per clock cycle (one via input A0 and another via input A1); however, in other examples, texture filtering unit may be configured to receive more than two texture values ​​in a single clock cycle and may have additional inputs ( Figure 2 As described above, the received texture value is in floating point format (eg, F16).

[0032] The texture filtering unit 200 also includes a coefficient merging logic block 208, a format conversion logic 210, two multipliers 212 (or more generally, one multiplier per texture value input, so that in the case where there are more than two input terminals, there are more than two multipliers), a left shifter 214, an addition unit 216, and conversion logic 218, wherein the format conversion logic 210 is arranged to convert each of the input texture values ​​from a floating point format to a type of fixed point representation including a fixed point significand and an exponent, the left shifter 214 is arranged to shift (e.g., left shift) the output of each multiplier (e.g., by an exponent value so that the inputs are correctly aligned with respect to each other before entering the addition unit), and the conversion logic 218 is arranged to convert the output from the addition unit back to a floating point format before being output via an output terminal 220.

[0033] In various examples, the texture filtering unit 200 is arranged to perform any weighted sum of a set of floating point texture value inputs, and in the examples described herein this is described as being used to perform any combination of volumetric filtering, anisotropic filtering and trilinear filtering; however, in other examples, the texture filtering unit 200 is arranged to perform any combination of two or more filtering methods of a different set or any other operation implemented as a weighted sum of a set of floating point texture value inputs. Thus, the coefficients 202 input to the texture filtering unit 200 (and in particular to the coefficient merging logic block 208) include at least one coefficient for each filtering method that the texture filtering unit 200 can implement, such as vfrac, afrac and tfrac (where vfrac is a coefficient for volumetric filtering, afrac is a coefficient for anisotropic filtering, and tfrac is a coefficient for trilinear filtering), and / or 2 n -vfrac and 2 m-tfrac (where n and m are the bit widths of vfrac and tfrac, respectively), and / or additional coefficients for any of the filtering methods. In various examples, the values ​​of the coefficients may change every clock cycle, or may change less frequently, or may be constant (e.g., vfrac may change every clock cycle, afrac may change less frequently, and tfrac may be constant). In various examples, the coefficients may be unsigned fixed-point values ​​with no integer bits and 8 or 16 fractional bits (e.g., U0.8 or U0.16); however, any coefficient size (e.g., in terms of the number of bits) may be used. In the case where only an appropriate subset of the filtering methods are used, the coefficients of those methods that are not used may be set to default values ​​(e.g., where anisotropic filtering is not used, the coefficient afrac may be set to 1), or a separate enable signal 203 may be provided in addition.

[0034] In the example of providing enable signals 203, these signals may have values ​​specifying whether each filtering method (or mode) is enabled and any necessary parameters for the filtering method. For example, three enable signals may be provided, as detailed below:

[0035]

[0036] The texture filtering unit 200 is arranged to perform filtering using any combination of one or more of a set of filtering methods, and the coefficient merging logic block 208 includes hardware logic arranged to combine the coefficients for each of the filtering methods together to generate (and then output) a single composite filter coefficient for each input texture value. Figure 2 In the example shown, where two texture values ​​are received per clock cycle, the coefficient merging logic block 208 outputs two coefficients coeff_0 and coeff_1 per clock cycle, and these coefficients are input to the A0 coefficient multiplier and the A1 coefficient multiplier 212, respectively. In various examples, these merged coefficients are unsigned fixed-point numbers with zero or one integer bit and 32 fractional bits. In various examples, the coefficient merging logic block 208 may include multiple multiplexers, logical negation elements (e.g., XOR) and adders and only two multipliers (as described in detail below). In other examples, more than two multipliers may be provided within the coefficient merging logic block 208.

[0037] As described above, the texture values ​​received via the input terminals 204, 206 are in a floating point format (e.g., F16), and these texture values ​​are input into the format conversion logic 210, which is arranged to convert each of the input texture values ​​from a floating point format to a type of fixed point representation, namely by generating a fixed point significand and exponent from the input texture value. The input texture value comprises a sign bit s, an exponent e, and a mantissa m. The exponent e comprises an exponent E exponent bits (where E=5 for F16), and the mantissa m comprises M mantissa (or fraction) bits (where M=10 for F16). Each of these format conversion logics 210 converts the input texture value into a fixed point representation by splitting the input texture value into two outputs:

[0038] a i_sig =(-1) s (1.m)

[0039] a i_exp =2 e-15

[0040] Where i = [0, 1], and for the first input texture value, i = 0, and for the second input texture value, i = 1. The first output from each of the format conversion logic 210 is input to the A0 coefficient and A1 coefficient multipliers 212, respectively, with one first output (i.e., a1 ) for each of the input texture values. 0_sig and a 1_sig ). For F16 input, these first outputs are signed fixed point numbers with two integer bits and 10 fractional bits. The second output from each of the format conversion logic 210 is input to the first and second left shifters 214, respectively, with one second output for each of the input texture values ​​(i.e., a 0_exp and a 1_exp ).

[0041] Each of the multipliers 212 receives one input from the format conversion logic 210 (comprising a portion of the input texture value represented in fixed point) and one input from the coefficient merging logic block 208 (comprising the composite filter coefficient for the particular input texture value). Each multiplier 212 multiplies its two inputs together to generate an output value add i :

[0042] add i =a i_sig *coeff_i

[0043] Where i=[0,1], and for the first input texture value (and hence the first multiplier), i=0, and for the second input texture value (and hence the second multiplier), i=1.

[0044] The output from the multiplier 212 is shifted by the value a in the corresponding left shifter 214 before the two outputs from the left shifter 214 are added together in the adding unit 216. i_exp , for F16 input, the output from multiplier 212 is a signed fixed point number with two integer bits and 42 fraction bits. For F16 input, the result of the addition in the addition unit may be on the order of 77 bits in width.

[0045] As described above, a single compound coefficient is generated for each input texture value in the coefficient merging logic block 208, and therefore each multiplication operation performed by either of the two multipliers 212 involves a new texture value and a newly generated compound coefficient for that texture value, although in some cases two or more of the compound coefficients may have the same value when generated separately.

[0046] If the texture filtering operation involves only two texture values ​​input on the same clock cycle, then the result of the addition operation in the addition unit 216 is the final result, which is output (via the output terminal 220) after being converted back to floating point format in the conversion logic 218; however, as described below, unless only volumetric filtering or only trilinear filtering is enabled (e.g., by enabling signal 203 or by setting the coefficients used for the other filtering method to their default values, such as 1), more than two texture values ​​will be involved in generating the output result. However, in all cases, the final result generated by the addition unit 216 is fully accurate, and only a single rounding operation is performed when the final result is converted from fixed point format back to floating point format in the conversion logic 218.

[0047] In examples where the texture filtering operation involves more than two texture values, the texture values ​​are input over multiple clock cycles (e.g., N clock cycles). For example, the filtering operation may use up to 64 texture value inputs over up to 32 clock cycles (assuming no stalling). In examples where more than two texture values ​​are used to generate an output result (e.g., where N>1), the addition unit 216 may be a fixed-point 3-adder (i.e., configured to add three fixed-point inputs together) that adds together the result from the previous clock cycle (which may be referred to as an intermediate result and may be stored in a register) and the two newly received inputs. In such an example, the result of the Nth addition operation is output as the final result (via output 220) after it has been converted back to floating point format in the conversion logic 218.

[0048] The size of the 3 adders is determined at design time based on the size of the coefficients and texture inputs and the resulting required accuracy of the hardware. A wider 3 adder (in terms of bit width) is physically larger (e.g., in terms of area) and slower, and thus the time it takes for a wide 3 adder to perform an addition may exceed the time available in a single clock cycle. Therefore, in various examples, the addition unit 216 may include a 3:2 compressor followed by a carry-save adder, rather than a 3 adder.

[0049] The number of texture values ​​involved in any filtering operation may be determined, for example, based on the value of the enable signal 203 as follows:

[0050] Number of texture values ​​= (vol_en+1)*(ani_rt+1)*(tri_en+1).

[0051] For example, if all three filtering methods are used, such that vol_en=tri_en=1 and ani_rt={1, 3, . . . , 15}, the total number of texture values ​​involved is between 8 and 64.

[0052] For example, if 2N texture values ​​are involved, the addition performed by the addition unit 216 is as follows:

[0053] Result 1 =add 0_1 +add 1_1

[0054] Result 2 =result 1 +add 0_2 +add 1_2

[0055] Result 3 =result 2 +add 0_3 +add 1_3

[0056] …

[0057] Result N =result N-1 +add 0_N +add 1_N

[0058] Among them, add i_t is the output from the i-th multiplier, which is input to the adding unit 216 for the t-th addition operation (i.e., generating result t ). In this example, result 1 -resultN-1 is the intermediate result, and result N is the final result.

[0059] In the above examples where more than two texture values ​​are used in the texture filtering operation (and therefore N>1), it is assumed that all texture values ​​used in the texture filtering operation are input on consecutive clock cycles. In such an example, the fixed-point 3 adder adds the two newly received inputs to the result of the immediately previous addition operation (in the addition unit 216). However, in other examples, the input stream of multiple texture values ​​can be interleaved so that the fixed-point 3 adder adds the two newly received inputs to the result of the immediately previous addition operation for the input stream, which addition operation may not necessarily be the immediately previous addition operation performed by the addition unit. This interleaving operation can be enabled using an additional enable signal 203:

[0060] Enable signal Possible values meaning staggered 0、1 Interleaving is disabled or enabled respectively

[0061] For example, if two input streams of texture values ​​(stream A and stream B) are interleaved, and each filtering operation involves 2N texture values, the addition unit 216 performs the following additions:

[0062] Result 1A =add 0_1A +add 1_1A

[0063] Result 1B =add 0_1b +add 1_1B

[0064] Result 2A =result 1A +add 0_2A +ddd 1_2A

[0065] Result 2B =result 1B +add 0_2B +add 1_2B

[0066] Result 3A =result 2A +add 0_3A +add 1_3A

[0067] Result 3B =result 2B +add 0_3B +add 1_3B

[0068] Result NA =result (N-1)A +add 0_NA +add 1_NA

[0069] Result NB =result (N-1)B +add 0_NB +add 1_NB

[0070] Among them, add i_tA is the output from the i-th multiplier, which is input to the addition unit 216 for the t-th addition operation on stream A (i.e., generating result tA ), and add i_tB is the output from the i-th multiplier, which is input to the addition unit 216 for the t-th addition operation on stream B (i.e., generating result tB ). In this example, result 1A -result (N-1)A and result 1B -result (N-1)B is the intermediate result, and result NA and result NB is the final result.

[0071] Interleaving of input streams of texture values ​​may be used where, for example, multiple texture values ​​(e.g., R values ​​and G values) are accessed from memory simultaneously, e.g., because they are stored contiguously, but need to be filtered separately (e.g., where color filtering is performed separately for each color). This improves efficiency (e.g., in terms of speed and power because it avoids having to store texture values ​​(e.g., G values) of one stream in a separate register until texture values ​​(e.g., R values) of all other streams are filtered).

[0072] While the above examples show the interleaving of two input streams, in other examples, additional control logic and registers may be provided to enable the filtering unit to interleave more than two input streams (eg, 3 or 4 input streams).

[0073] Figure 3 is a schematic diagram of a second example texture filtering unit 300, which may be implemented as Figure 1 The texture filter unit 102 in the pipeline 100. The texture filter unit 300 and Figure 2 The texture filter unit is the same as shown in and described above, with the addition of mode and interleave counter logic element 302. Figure 3As shown, the mode and interleave counter logic element 302 receives the enable signal 203, where, as described above, these enable signals may include values ​​specifying whether each filtering method (or mode) is enabled and any necessary parameters for the filtering method. In the example where more than two texture values ​​are used in the texture filtering operation (and therefore N>1), the mode and interleave counter logic element 302 controls which addition results are output by the addition unit 216, converted back to floating point by the conversion logic 218 and output (via the output terminal 220) through the input to the addition unit 216, and which addition results are only intermediate results that need to be further accumulated to generate the final result. The control logic may include a counter that counts down from N or counts up to N, and reaches 0 or N, respectively, triggering the output of the final result of the addition unit 216. In addition, or alternatively, the mode and interleave counter logic element 302 controls any interleave operation of the addition unit 216 through the input to the addition unit 216 (as described above). For example, depending on the value of the stagger control signal input to the adding unit 216 from the mode and stagger counter logic element 302, two new inputs to the adding unit 216 may be added to different ones of the plurality of stored intermediate results (eg, one for each input stream).

[0074] Figure 4 is a schematic diagram of a third example texture filtering unit 400, which may be implemented as Figure 1 The texture filtering unit 102 in the pipeline 100 is Figure 3 4 is a variation of the texture filter unit 300 shown and described above. The figure shows a register stage 401 within the texture filter unit 400, and the logic between the two register stages operates in a single clock cycle. The clock input 410 controls the timing of the logic operations and when data is read into and out of the register stage 401. The denormalization (denorm) flush and significand optional denormalization block 402 performs at least a portion of the conversion of the input texture value from a floating point format to a fixed point format (equivalent to Figure 2 and Figure 3 If the output from the adder 216 is negative, then the Figure 4 Optional XOR (negation) logic block 404 is shown. In this case, the output is negated and the sign bit is changed. The combination of fixed point normaliser logic block 406 and rounding, exponent increment and exception output multiplexer 408 performs the conversion of the output back to floating point format (equivalent to Figure 2 and Figure 3 218 in the conversion logic). Figure 4Many other signals are also shown, such as flags (e.g., VALID_UP, which indicates whether inputs A0 and A1 contain valid data; and VALID_DOWN, which indicates whether a sequence that takes more than one clock signal to execute has completed and therefore indicates whether the output y is the result of a texture filtering sequence) and enable signals (e.g., ENABLE_DOWN, which indicates whether the next component in the sequence has enough register space to accept the next valid output or whether the previous register stage must be stalled).

[0075] Figure 5 is a schematic diagram of a more detailed example coefficient merging logic block 500. The coefficient merging logic block 500 may be implemented as Figure 2-Figure 4 The coefficients in any one of the merging logic blocks 208. Figure 5 As shown, the coefficient merging logic block 500 includes four multiplexers 501-504 and two multipliers 506-507. There are also many adding elements 508-510 and a logic negation unit (e.g., XOR) 512. The coefficient merging logic block 500 receives three coefficients: vfrac, tfrac, and afrac (as described above) and various control signals: ani_rt (as described above), control_mul_a_0, control_mul_0_b_0, control_mul_0_b_1, control_mul_1_b_0, control_mul_1_b_1, control_coeff_1 as inputs, wherein these control signals can be derived, for example, from the above-mentioned enable signals so that the coefficients are correctly merged to combine different filtering modes as required by the mode enable signal. The coefficient merging logic block 500 generates two outputs, coeff_0 and coeff_1 (as described above).

[0076] The first multiplexer 501 receives two inputs, afrac and afrac_last (which may be, for example, the second anisotropic filter coefficients) and two control signals ani_rt and control_mul_a_0, and generates an output mul_0_a as follows:

[0077]

[0078] The second multiplexer 502 receives an input tfrac and two control signals control_mul_0_b_0 and control_mul_0_b_1, and generates the following output mul_0_b:

[0079]

[0080] in, is the logical inversion of the bits in tfrac (e.g., so that 01101101 becomes 10010010).

[0081] The third multiplexer 503 receives one input mul_0_a (which is the output from the first multiplexer 501) and two control signals control_mul_0_b_0 and control_mul_0_b_1, and generates the following output mul_0_b_inc:

[0082]

[0083] The signal mul_0_b_inc is actually an increment bit with the same selection logic as mul_0_b, which effectively adds The value is changed to 1-tfrac without the need for subtraction. The fourth multiplexer 504 receives two inputs tfrac and vfrac, and two control signals control_mul_1_b_0 and control_mul_1_b_1, and generates the following output mul_1_b:

[0084]

[0085] The first multiplier 506 receives two inputs mul_0_a (as output by the first multiplexer 501) and mul_0_b (as output by the second multiplexer 502) and multiplies the two inputs together. The result is then added (in the adding element 508) to the output from the third multiplexer 503, such that:

[0086] mul_1_a=mul_0_a*mul_0_b+mul_0_b_inc.

[0087] The second multiplier 507 receives two inputs mul_1_a (as output by the first multiplier 506) and mul_1_b (as output by the fourth multiplexer 504) and multiplies the two inputs together such that:

[0088] mul_2=mul_1_a*mul_1_b.

[0089] Then, two output coefficients coeff_0 and coeff_1 are generated using two further adding elements 509, 510. The first of these adding units 509 receives two inputs, mul_1_a (as output by another adding unit 508) and mul_2 (as output by the second multiplier 507), and generates coeff_0 as follows:

[0090]

[0091] The second of these adding units 510 receives the same two inputs and a control signal control_coeff_1 (which may be generated as control_coeff_1 = not(vol_en) AND ani_rt[0]), and generates coeff_1 as follows:

[0092] coeff_1=(mul_2+(control_coeff_1?mul_1_a: 0).

[0093] In other examples, the following can be modified by implementing any one or more of the following Figure 5 The coefficient merging logic block 500 is shown:

[0094] - can be achieved by placing Replaced with 1-tfrac to save multiplexer;

[0095] - Any logical negation (i.e. XOR block) can be exchanged for an arithmetic negation;

[0096] - Replace the XOR block 512 with a NOT block;

[0097] - Combine filter mode coefficients (e.g., afrac and tfrac) in different orders.

[0098] like Figure 5 As shown, only two multiplications (and thus two multipliers 506, 507) are used to generate the two coefficients, and this provides an efficient hardware implementation (eg, in terms of size and / or power).

[0099] In the above example, the composite filter coefficients generated by the coefficient merging logic block are not rounded. In order to reduce the area of ​​the texture filtering unit at the expense of reduced accuracy, the composite filter coefficients may be rounded to reduce their bit width.

[0100] Although all of the examples described herein show two texture values ​​being input per clock cycle, the texture filtering unit described herein may be expanded by including additional texture value inputs and corresponding format conversion logic 210, multiplier 212, and left shifter 214 to enable input (and subsequent processing) of more than two values ​​per clock cycle.

[0101] In another variation, the texture filter unit may include a bilinear filter stage. In such an example, two texture values ​​may be input to the bilinear filter stage, and two values ​​output from the stage may be output to two multipliers. Alternatively, the coefficient merge block may be modified to include bilinear filter coefficients.

[0102] Although the above examples involve input texture values ​​in F16 format, i.e., such that E=5 and M=10, the above hardware and methods can also be used for texture values ​​in different formats, such as F32 or full precision floating point format (where E=8 and M=23). By using F32 inputs, the output from the multiplier is significantly wider (e.g., a 279-bit signed number), and the width of the output from the addition unit 216 can be on the order of 300 bits.

[0103] In variations of the examples described herein, accuracy can be traded off against area / delay by reducing the internal bit width at any stage.

[0104] The techniques described above in the context of texture filtering within a GPU may also be used in other applications that include floating point operations, including the estimation of multiple sums of products (SOPs) followed by an accumulation stage (e.g., any weighted sum of floating point input values). In such examples, the texture filtering unit described above may alternatively be referred to as a computation unit, and the filter coefficients may be replaced by SOP coefficients instead.

[0105] Another example describes a graphics processing unit comprising a computing unit implemented in hardware logic, the computing unit comprising: multiple input terminals arranged to receive at least two input values ​​and multiple SOP coefficients per clock cycle, the multiple SOP coefficients including coefficients associated with multiple different SOPs; hardware logic arranged to convert the input values ​​from a floating point format to a fixed point format; a coefficient merging logic block arranged to generate a single complex coefficient for each input value from the multiple SOP coefficients; a multiplier for each input value, wherein each multiplier is arranged to multiply one of the input values ​​by its corresponding single complex coefficient; an adding unit arranged to add together the outputs from each of the multipliers; hardware logic arranged to convert the output from the adding unit from a fixed point format to a floating point format; and an output terminal arranged to output the converted output from the adding unit.

[0106] Figure 6 A computer system 600 is shown in which the graphics processing system described herein may be implemented. The computer system includes a CPU 602, a GPU 604, a memory 606, and other devices 614 such as a display 616, a speaker 618, and a camera 620. A GPU pipeline 100 including a texture filtering unit as described above is implemented within the GPU 604. The components of the computer system may communicate with each other via a communication bus 622.

[0107] Figure 1-Figure 5is shown as comprising a plurality of functional blocks. This is merely illustrative, and is not intended to define a strict division between the different logical elements of these entities. Each functional block may be provided in any suitable manner. It should be understood that the intermediate values ​​described herein as being formed by the texture filtering unit (or more generally, the coefficient merging logic blocks within the texture filtering unit) need not be physically generated by hardware logic at any point, and may simply represent logical values ​​that conveniently describe the processing performed by the texture filtering unit between its input and output terminals.

[0108] The texture filtering unit described herein may be embodied in hardware on an integrated circuit. The texture filtering unit described herein may be configured to perform any of the methods described herein. Generally, any of the functions, methods, techniques, or components described above can be implemented in software, firmware, hardware (e.g., fixed logic circuits), or any combination thereof. The terms "module," "function," "component," "element," "unit," "block," and "logic" may be used herein to generally represent software, firmware, hardware, or any combination thereof. In the case of a software implementation, a module, function, component, element, unit, block, or logic represents a program code that performs a specific task when executed on a processor. The algorithms and methods described herein may be performed by one or more processors that execute a code that causes the processor(s) to perform the algorithm / method. Examples of computer-readable storage media include random access memory (RAM), read-only memory (ROM), optical disks, flash memory, hard disk storage, and other memory devices that can use magnetic, optical, or other technologies to store instructions or other data and can be accessed by a machine.

[0109] As used herein, the terms computer program code and computer readable instructions refer to any type of executable code for a processor, including code expressed in machine language, interpreted language, or scripting language. Executable code includes binary code, machine code, bytecode, code that defines an integrated circuit (such as a hardware description language or netlist), and code expressed in programming language code such as C, Java, or OpenCL. Executable code can be, for example, any type of software, firmware, script, module, or library that, when properly executed, processed, interpreted, compiled, executed in a virtual machine or other software environment, causes a processor of a computer system that supports the executable code to perform the tasks specified by the code.

[0110] Processor, computer or computer system can be any type of equipment, machine or special circuit or their collection or part with processing power so that it can execute instruction.Processor can be any type of general processor or special processor, such as CPU, GPU, system on chip, state machine, media processor, application specific integrated circuit (ASIC), programmable logic array, field programmable gate array (FPGA), physical processing unit (PPU), radio processing unit (RPU), digital signal processor (DSP), general processor (for example, general GPU), microprocessor, any processing unit designed to accelerate task outside CPU etc.Computer or computer system can include one or more processors.Those skilled in the art will recognize that such processing power is incorporated into many different equipments, and therefore term " computer " includes set-top box, media player, digital radio, PC, server, mobile phone, personal digital assistant and many other equipments.

[0111] It is also intended to encompass software that defines the configuration of hardware as described herein, such as HDL (Hardware Description Language) software, such as for designing integrated circuits or for configuring programmable chips to perform desired functions. That is, a computer-readable storage medium may be provided having computer-readable program code encoded thereon in the form of an integrated circuit definition data set, which, when processed (i.e., run) in an integrated circuit manufacturing system, configures the system to manufacture a texture filtering unit configured to perform any of the methods described herein, or to manufacture a texture filtering unit comprising any of the apparatus described herein. The integrated circuit definition data set may, for example, be an integrated circuit description.

[0112] Thus, a method of manufacturing a texture filter unit as described herein at an integrated circuit manufacturing system may be provided. Furthermore, an integrated circuit definition data set may be provided which, when processed in an integrated circuit manufacturing system, causes a method of manufacturing a texture filter unit to be performed.

[0113] The integrated circuit definition data set may be in the form of computer code, for example, as a netlist, code for configuring a programmable chip, as a hardware description language defining the integrated circuit at any level (including as register transfer level (RTL) code), as a high-level circuit representation such as Verilog or VHDL, and as a low-level circuit representation such as OASIS (RTM) and GDSII. The higher-level representation (such as RTL) that logically defines the integrated circuit may be processed at a computer system that is configured to generate a manufacturing definition of the integrated circuit in the context of a software environment, including definitions of circuit elements and rules for combining such elements, so as to generate a manufacturing definition of the integrated circuit so defined by the representation. As is typically the case where software is executed at a computer system to define a machine, one or more intermediate user steps (e.g., providing commands, variables, etc.) may be required in order for a computer system configured to generate a manufacturing definition of an integrated circuit to execute code that defines the integrated circuit, thereby generating a manufacturing definition of the integrated circuit.

[0114] Now refer to Figure 7 An example of processing an integrated circuit definition data set at an integrated circuit manufacturing system to configure the system to manufacture a texture filtering unit is described.

[0115] Figure 7 An example of an integrated circuit (IC) manufacturing system 702 configured to manufacture a texture filtering unit as described in any of the examples herein (or a GPU including a texture filtering unit as described in any of the examples herein) is shown. Specifically, the IC manufacturing system 702 includes a layout processing system 704 and an integrated circuit generation system 706. The IC manufacturing system 702 is configured to receive an IC definition data set (e.g., defining a texture filtering unit as described in any of the examples herein), process the IC definition data set, and generate an IC (e.g., which embodies a texture filtering unit as described in any of the examples herein) based on the IC definition data set. The processing of the IC definition data set configures the IC manufacturing system 702 to manufacture an integrated circuit embodying a texture filtering unit as described in any of the examples herein.

[0116] The layout processing system 704 is configured to receive and process an IC definition data set to determine a circuit layout. Methods for determining a circuit layout based on an IC definition data set are known in the art and may, for example, involve synthesizing RTL code to determine a gate-level representation of a circuit to be generated, for example, in terms of logic components (e.g., NAND, NOR, AND, OR, MUX, and flip-flop components). The circuit layout may be determined based on the gate-level representation of the circuit by determining location information for the logic components. This may be done automatically or with user intervention to optimize the circuit layout. When the layout processing system 704 has determined the circuit layout, it may output a circuit layout definition to the IC generation system 706. For example, the circuit layout definition may be a circuit layout description.

[0117] As is known in the art, the IC generation system 706 generates the IC according to the circuit layout definition. For example, the IC generation system 706 may implement a semiconductor device manufacturing process to generate the IC, which may involve a multi-step sequence of photolithography and chemical processing steps during which electronic circuits are gradually created on a wafer made of semiconductor material. The circuit layout definition may be in the form of a mask that may be used in a photolithography process to generate the IC according to the circuit definition. Optionally, the circuit layout definition provided to the IC generation system 706 may be in the form of a computer readable code that the IC generation system 706 may use to form an appropriate mask for use in generating the IC.

[0118] The different processes performed by the IC manufacturing system 702 can all be implemented at one location, for example, by one party. Alternatively, the IC manufacturing system 702 can be a distributed system so that some of the processes can be performed at different locations and can be performed by different parties. For example, some of the following stages can be performed at different locations and / or by different parties: (i) synthesizing RTL code representing an IC definition data set to form a gate-level representation of a circuit to be generated; (ii) generating a circuit layout based on the gate-level representation; (iii) forming a mask based on the circuit layout; and (iv) manufacturing the integrated circuit using the mask.

[0119] In other examples, processing of an integrated circuit definition data set at an integrated circuit manufacturing system may configure the system to manufacture a texture filtering unit without processing the IC definition data set to determine a circuit layout. For example, an integrated circuit definition data set may define a configuration of a reconfigurable processor (e.g., an FPGA), and processing of the data set may configure the IC manufacturing system to generate a reconfigurable processor having the defined configuration (e.g., by loading the configuration data into the FPGA).

[0120] In some embodiments, the integrated circuit manufacturing definition data set, when processed in the integrated circuit manufacturing system, can cause the integrated circuit manufacturing system to generate the device as described herein. Figure 7 Configuration by an integrated circuit manufacturing definition data set in the manner described may enable the manufacture of a device as described herein.

[0121] In some examples, the integrated circuit definition data set may include software that runs on or in combination with hardware defined at the data set. Figure 7 In the example shown, the IC generation system may also be configured by the integrated circuit definition data set to load firmware onto the integrated circuit when manufacturing the integrated circuit according to the program code defined at the integrated circuit definition data set, or to otherwise provide program code to the integrated circuit for use with the integrated circuit.

[0122] Those skilled in the art will recognize that storage devices for storing program instructions can be distributed in a network. For example, a remote computer can store examples of processes described as software. A local or terminal computer can access the remote computer and download a portion or all of the software to run the program. Alternatively, a local computer can download fragments of the software on demand, or execute some software instructions at a local terminal and execute some software instructions at a remote computer (or computer network). Those skilled in the art will also recognize that all or part of the software instructions can be executed by a dedicated circuit (e.g., DSP, programmable logic array, etc.) by utilizing conventional techniques known to those skilled in the art.

[0123] The methods described herein may be performed by a computer configured with software in a machine-readable form stored on a tangible storage medium, such as in the form of a computer program including computer-readable program code for configuring a computer to perform the components of the method, or in the form of a computer program including computer program code suitable for performing all the steps of any method described herein when the program is run on a computer, and wherein the computer program may be embodied on a computer-readable storage medium. Examples of tangible (or non-transitory) storage media include disks, thumb drives, memory cards, etc., and do not include propagating signals. The software may be suitable for execution on a parallel processor or a serial processor, so that the method steps may be executed in any appropriate order or simultaneously.

[0124] The hardware components described herein may be generated by a non-transitory computer-readable storage medium having computer-readable program code encoded thereon.

[0125] The memory storing the machine executable data used in implementing the disclosed aspects may be a non-transitory medium. The non-transitory medium may be volatile or non-volatile. Examples of volatile non-transitory media include semiconductor-based memories, such as SRAM or DRAM. Examples of technologies that can be used to implement non-volatile memory include optical and magnetic memory technologies, flash memory, phase change memory, resistive RAM.

[0126] A specific reference to "logic" refers to a structure that performs one or more functions. Examples of logic include circuits that are arranged to perform these functions (one / more functions). For example, such circuits may include transistors and / or other hardware elements available in the manufacturing process. As an example, such transistors and / or other elements may be used to form circuits or structures that implement and / or contain memories (such as registers, flip-flops or latches), logic operators (such as Boolean operations), mathematical operators (such as adders, multipliers or shifters) and interconnections. Such elements may be provided as custom circuits or standard cell libraries, macros or at other abstract levels. Such elements may be interconnected in a specific arrangement. Logic may include fixed-function circuits, and the circuits may be programmed to perform one or more functions; such programming may be provided by firmware or software updates or control mechanisms. Logic identified as performing a function may also include logic that implements constituent functions or subprocesses. In an example, hardware logic has a circuit that implements fixed-function operations, or multiple operations, state machines or processes.

[0127] When compared with known implementations, the implementation of the concepts set forth in this application in devices, apparatuses, modules and / or systems (and in the methods implemented herein) can cause performance improvements. Performance improvements can include one or more of increased computing performance, reduced delays, increased throughput and / or reduced power consumption. During the manufacture of such devices, devices, modules and systems (e.g., in integrated circuits), performance improvements can be compromised with physical implementations to improve manufacturing methods. For example, performance improvements can be weighed for layout area to match the performance of known implementations, but using less silicon. This can be accomplished, for example, by reusing functional blocks in a serialized manner or sharing functional blocks between units of devices, devices, modules and / or systems. On the contrary, the concepts set forth in this application that produce improvements (such as reduced silicon area) in the physical implementation of devices, devices, modules and systems can be weighed for improved performance. This can be accomplished, for example, by manufacturing multiple instances of modules within a predetermined area budget.

[0128] As will be apparent to the skilled artisan, any range or device value given herein may be expanded or altered without losing the effect sought.

[0129] It will be understood that the benefits and advantages described above may relate to one embodiment or may relate to several embodiments. The embodiments are not limited to those that solve any or all of the stated problems or those that have any or all of the stated benefits and advantages.

[0130] Any reference to "an" item refers to one or more of those items. The term "comprising" is used herein to mean including the identified method blocks or elements, but such blocks or elements do not comprise an exclusive list, and an apparatus may contain additional blocks or elements, and a method may contain additional operations or elements. Furthermore, blocks, elements, and operations themselves are not implicitly closed.

[0131] The steps of the method described herein can be performed in any appropriate order or performed simultaneously when appropriate. The arrows between the frames in the accompanying drawings illustrate an example order of method steps, but are not intended to exclude the parallel execution of other orders or multiple steps. In addition, each block can be deleted from any method without departing from the spirit and scope of the subject matter described herein. The aspect of any example described above can be combined with any aspect of other examples described to form other examples without losing the effect sought. The elements of the accompanying drawings are shown as being connected by arrows, and it will be appreciated that these arrows only illustrate an example communication flow (comprising data and control messages) between the elements. The flow between the elements can be in either direction or in two directions.

[0132] Applicants hereby independently disclose each individual feature described herein and any combination of two or more such features, to the extent that such feature or combination can be implemented based on the specification as a whole according to the common general knowledge of a person skilled in the art, regardless of whether such feature or combination of features solves any problem disclosed herein. In view of the above description, it will be apparent to a person skilled in the art that various modifications may be made within the scope of the invention.

[0133] Aspects of the present disclosure may be implemented in one or more embodiments below.

[0134] 1) A texture filtering unit implemented in hardware logic, the texture filtering unit comprising:

[0135] a plurality of inputs arranged to receive at least two texture values ​​per clock cycle and a plurality of filter coefficients, the plurality of filter coefficients comprising coefficients associated with a plurality of different texture filtering methods;

[0136] format conversion logic arranged to convert input texture values ​​from a floating point format to a fixed point significand and exponent;

[0137] a coefficient merging logic block arranged to generate a single composite filter coefficient for each input texture value from the plurality of filter coefficients;

[0138] a plurality of multipliers, the multipliers comprising one multiplier for each input texture value, wherein each of the multipliers is arranged to multiply the significand of one of the input texture values ​​by its corresponding single complex filter coefficient;

[0139] an adding unit arranged to add together the output from each of the multipliers;

[0140] hardware logic arranged to convert an output from the adding unit from a fixed point format to a floating point format; and

[0141] An output terminal is arranged to output the converted output from the adding unit.

[0142] 2) The texture filtering unit according to 1), wherein each input texture value comprises a sign bit, a plurality of exponent bits and a plurality of mantissa bits, and the texture filtering unit further comprises a left shift logic block for each input texture value,

[0143] and wherein the format conversion logic is configured to divide each input texture value into a fixed-point significand and an exponent, wherein the fixed-point significand of each input texture value is input to a corresponding multiplier and a second partial exponent of each input texture value is input to a corresponding left shift logic block,

[0144] wherein the fixed-point significand of each input texture value comprises the sign bit and the mantissa bit, and the exponent of each input texture value comprises the exponent bit,

[0145] And wherein each left shift logic block is arranged to left shift the output from the multiplier by an amount equal to the input exponent of the texture value and output the left shifted output from the multiplier to the adding unit.

[0146] 3) The texture filtering unit according to 1), wherein the texture filtering unit is configured to perform a filtering operation involving texture values ​​input within N clock cycles, where N>1, and wherein the adding unit is arranged to:

[0147] In a first clock cycle of the N clock cycles, adding together outputs from each of the multipliers;

[0148] in each of the second clock cycle to the Nth clock cycle of the N clock cycles, adding together the output from each of the multipliers and the result of addition from the immediately previous clock cycle of the N clock cycles; and

[0149] The result of addition in the Nth clock cycle of the N clock cycles is output.

[0150] 4) The texture filtering unit according to 1), wherein the texture filtering unit is configured to perform a filtering operation on each of a plurality of streams of texture values, the filtering operation involving texture values ​​input within N clock cycles, where N>1, and wherein the adding unit is arranged to perform the following operation on each of the streams of texture values:

[0151] In a first clock cycle of the N clock cycles for the stream of texture values, adding together an output from each of the multipliers;

[0152] in each of a second clock cycle to an Nth clock cycle of the N clock cycles for the stream of texture values, adding together an output from each of the multipliers and a result of addition from an immediately previous clock cycle of the N clock cycles for the stream of texture values; and

[0153] A result of the addition in the Nth clock cycle of the N clock cycles for the stream of the texture value is output.

[0154] 5) The texture filtering unit according to 4), wherein the multiple streams of texture values ​​are interleaved so that texture values ​​are input from different streams of texture values ​​in adjacent clock cycles.

[0155] 6) The texture filtering unit according to 3), further comprising a mode and interleave counter logic block, wherein the mode and interleave counter logic block is arranged to control the operation of the adding unit.

[0156] 7) The texture filtering unit according to 6), wherein the mode and interleave counter logic block comprises a counter arranged to count the N clock cycles and trigger output of the result of the adding unit in the Nth clock cycle of the N clock cycles.

[0157] 8) The texture filtering unit according to 1), wherein the input receives i texture values ​​per clock cycle, the texture filtering unit comprises i multipliers, and the coefficient merging logic block comprises another i multipliers.

[0158] 9) A graphics processing unit comprising the texture filtering unit described in any one of 1) to 8).

[0159] 10) A method for performing texture filtering in hardware logic, the method comprising:

[0160] In a texture filtering unit, receiving at least two texture values ​​per clock cycle and a plurality of filter coefficients, the plurality of filter coefficients including coefficients associated with a plurality of different texture filtering methods;

[0161] Convert input texture values ​​from floating point format to fixed point significands and exponents;

[0162] generating a single composite filter coefficient for each input texture value based on the plurality of filter coefficients;

[0163] multiplying the fixed point significand of one of the input texture values ​​by its corresponding single complex filter coefficient in each of a plurality of multipliers, wherein the plurality of multipliers includes one multiplier for each input texture value received in a clock cycle;

[0164] adding together the output from each of the plurality of multipliers and converting the result from a fixed point format to a floating point format; and

[0165] Output the converted result.

[0166] 11) The method according to 10), wherein each input texture value comprises a sign bit, a plurality of exponent bits and a plurality of mantissa bits,

[0167] Wherein, converting the input texture value from a floating point format to a fixed point significand and an exponent comprises: dividing each input texture value into a fixed point significand and an exponent, wherein the fixed point significand of each input texture value is input to a corresponding multiplier, and the exponent of each input texture value is input to a corresponding left shift logic block,

[0168] wherein the fixed point significand of each input texture value comprises the sign bit and the mantissa bits, and the exponent of each input texture value comprises the exponent bits, and wherein adding together the output from each of the plurality of multipliers comprises:

[0169] For each of the plurality of multipliers, an output from the multiplier is left shifted by an amount equal to the input exponent of the texture value, and the left shifted outputs of each of the plurality of multipliers are added together.

[0170] 12) The method of 10), wherein the method performs a filtering operation involving texture values ​​input within N clock cycles, where N>1, and wherein adding together the outputs from each of the plurality of multipliers comprises:

[0171] In a first clock cycle of the N clock cycles, adding together outputs from each of the plurality of multipliers;

[0172] in each of a second clock cycle to an Nth clock cycle of the N clock cycles, adding together an output from each of the plurality of multipliers and a result of addition from an immediately previous clock cycle of the N clock cycles; and

[0173] The result of addition in the Nth clock cycle of the N clock cycles is output.

[0174] 13) The method of 10), wherein the method performs a filtering operation involving texture values ​​input within N clock cycles for each of a plurality of streams of texture values, where N>1, and wherein adding together the output from each of the plurality of multipliers comprises:

[0175] In a first clock cycle of the N clock cycles for the stream of texture values, adding together an output from each of the plurality of multipliers;

[0176] in each of a second clock cycle to an Nth clock cycle of the N clock cycles for the stream of texture values, adding together an output from each of the plurality of multipliers and a result of addition from an immediately previous clock cycle of the N clock cycles for the stream of texture values; and

[0177] A result of the addition in the Nth clock cycle of the N clock cycles for the stream of the texture value is output.

[0178] 14) The method according to 13), wherein the multiple streams of texture values ​​are interleaved so that texture values ​​are input from different streams of texture values ​​in adjacent clock cycles.

[0179] 15) The method according to 12) further comprises:

[0180] The N clock cycles are counted, and output of a result of addition in the Nth clock cycle of the N clock cycles is triggered.

[0181] 16) A graphics processing unit configured to execute the method described in any one of 10)-15).

[0182] 17) The graphics processing unit of 16), wherein the graphics processing unit is embodied in hardware on an integrated circuit.

[0183] 18) The texture filtering unit according to any one of 1) to 8), wherein the texture filtering unit is embodied in hardware on an integrated circuit.

[0184] 19) A computer-readable storage medium having a computer-readable code encoded thereon, the computer-readable storage medium being configured such that when the code is executed, the method described in any one of 10)-15) is performed.

[0185] 20) An integrated circuit manufacturing system, comprising:

[0186] A computer-readable storage medium having a computer-readable description of an integrated circuit stored thereon, the computer-readable description of the integrated circuit describing a graphics processing unit as described in 16) or a texture filtering unit as described in any one of 1) to 8);

[0187] a layout processing system configured to process the computer-readable description of the integrated circuit to generate a circuit layout description of the integrated circuit embodying the graphics processing unit or the texture filtering unit; and

[0188] An integrated circuit production system is configured to manufacture the graphics processing unit or the texture filtering unit according to the circuit layout description.

Claims

1. A texture filtering unit implemented in hardware logic, the texture filtering unit comprising: a plurality of inputs arranged to receive at least two texture values ​​per clock cycle and a plurality of filter coefficients, the plurality of filter coefficients comprising coefficients associated with a plurality of different texture filtering methods; format conversion logic arranged to convert input texture values ​​from a floating point format to a fixed point significand and exponent; a coefficient merging logic block arranged to generate a single composite filter coefficient for each input texture value from the plurality of filter coefficients including coefficients associated with the plurality of different texture filtering methods; a plurality of multipliers, the multipliers comprising one multiplier for each input texture value, wherein each of the multipliers is arranged to multiply the significand of one of the input texture values ​​by its corresponding single complex filter coefficient; an adding unit arranged to add together the output from each of the multipliers; hardware logic arranged to convert an output from the adding unit from a fixed point format to a floating point format; and An output terminal is arranged to output the converted output from the adding unit.

2. The texture filtering unit according to claim 1, wherein: Each input texture value includes a sign bit, a plurality of exponent bits, and a plurality of mantissa bits, and the texture filtering unit further includes a left shift logic block for each input texture value, and wherein the format conversion logic is configured to divide each input texture value into a fixed-point significand and an exponent, wherein the fixed-point significand of each input texture value is input to a corresponding multiplier and a second partial exponent of each input texture value is input to a corresponding left shift logic block, wherein the fixed-point significand of each input texture value comprises the sign bit and the mantissa bit, and the exponent of each input texture value comprises the exponent bit, And wherein each left shift logic block is arranged to left shift the output from the multiplier by an amount equal to the input exponent of the texture value and output the left shifted output from the multiplier to the adding unit.

3. The texture filtering unit according to claim 1, wherein: The texture filtering unit is configured to perform a filtering operation involving texture values ​​input within N clock cycles, where N>1, and wherein the adding unit is arranged to: In a first clock cycle of the N clock cycles, adding together outputs from each of the multipliers; in each of the second clock cycle to the Nth clock cycle of the N clock cycles, adding together the output from each of the multipliers and the result of addition from the immediately previous clock cycle of the N clock cycles; and The result of addition in the Nth clock cycle of the N clock cycles is output.

4. The texture filtering unit according to claim 1, wherein: The texture filtering unit is configured to perform a filtering operation on each of a plurality of streams of texture values, the filtering operation involving texture values ​​input within N clock cycles, where N>1, and wherein the adding unit is arranged to perform the following operation on each of the streams of texture values: In a first clock cycle of the N clock cycles for the stream of texture values, adding together an output from each of the multipliers; in each of a second clock cycle to an Nth clock cycle of the N clock cycles for the stream of texture values, adding together an output from each of the multipliers and a result of addition from an immediately previous clock cycle of the N clock cycles for the stream of texture values; and A result of the addition in the Nth clock cycle of the N clock cycles for the stream of the texture value is output.

5. The texture filtering unit according to claim 4, wherein: The multiple streams of texture values ​​are interleaved such that texture values ​​are input from different streams of texture values ​​in adjacent clock cycles.

6. The texture filtering unit of claim 3, further comprising a mode and interleave counter logic block, the mode and interleave counter logic block being arranged to control the operation of the adding unit, wherein The mode and stagger counter logic block comprises a counter arranged to count the N clock cycles and trigger an output of a result of the adding unit in the Nth clock cycle of the N clock cycles.

7. The texture filtering unit according to claim 1, wherein: The input receives i texture values ​​per clock cycle, the texture filtering unit includes i multipliers, and the coefficient merging logic block includes another i multipliers.

8. The texture filtering unit according to claim 1, wherein: The texture filtering unit is arranged to perform texture filtering using a combination of two or more of a volumetric texture filtering method, an anisotropic texture filtering method and a trilinear texture filtering method.

9. A graphics processing unit, comprising the texture filtering unit according to any one of claims 1 to 8.

10. A method for performing texture filtering in hardware logic, the method comprising: In a texture filtering unit, receiving at least two texture values ​​per clock cycle and a plurality of filter coefficients, the plurality of filter coefficients including coefficients associated with a plurality of different texture filtering methods; Convert input texture values ​​from floating point format to fixed point significands and exponents; generating a single composite filter coefficient for each input texture value based on the plurality of filter coefficients including coefficients associated with the plurality of different texture filtering methods; multiplying the fixed point significand of one of the input texture values ​​by its corresponding single complex filter coefficient in each of a plurality of multipliers, wherein the plurality of multipliers includes one multiplier for each input texture value received in a clock cycle; adding together the output from each of the plurality of multipliers and converting the result from a fixed point format to a floating point format; and Output the converted result.

11. The method according to claim 10, wherein: Each input texture value includes a sign bit, multiple exponent bits, and multiple mantissa bits. Wherein, converting the input texture value from a floating point format to a fixed point significand and an exponent comprises: dividing each input texture value into a fixed point significand and an exponent, wherein the fixed point significand of each input texture value is input to a corresponding multiplier, and the exponent of each input texture value is input to a corresponding left shift logic block, wherein the fixed point significand of each input texture value comprises the sign bit and the mantissa bits, and the exponent of each input texture value comprises the exponent bits, and wherein adding together the output from each of the plurality of multipliers comprises: For each of the plurality of multipliers, an output from the multiplier is left shifted by an amount equal to the input exponent of the texture value, and the left shifted outputs of each of the plurality of multipliers are added together.

12. The method according to claim 10, wherein: The method performs a filtering operation involving texture values ​​input over N clock cycles, where N>1, and wherein adding together the output from each of the plurality of multipliers comprises: In a first clock cycle of the N clock cycles, adding together outputs from each of the plurality of multipliers; in each of a second clock cycle to an Nth clock cycle of the N clock cycles, adding together an output from each of the plurality of multipliers and a result of addition from an immediately previous clock cycle of the N clock cycles; and The result of addition in the Nth clock cycle of the N clock cycles is output.

13. The method according to claim 10, wherein: The method performs a filtering operation involving texture values ​​input within N clock cycles for each of a plurality of streams of texture values, where N>1, and wherein adding together the output from each of the plurality of multipliers comprises: In a first clock cycle of the N clock cycles for the stream of texture values, adding together an output from each of the plurality of multipliers; in each of a second clock cycle to an Nth clock cycle of the N clock cycles for the stream of texture values, adding together an output from each of the plurality of multipliers and a result of addition from an immediately previous clock cycle of the N clock cycles for the stream of texture values; and A result of the addition in the Nth clock cycle of the N clock cycles for the stream of the texture value is output.

14. The method according to claim 13, wherein: The multiple streams of texture values ​​are interleaved such that texture values ​​are input from different streams of texture values ​​in adjacent clock cycles.

15. The method according to claim 12, further comprising: The N clock cycles are counted, and output of a result of addition in the Nth clock cycle of the N clock cycles is triggered.

16. A graphics processing unit configured to perform the method of any one of claims 10-15.

17. The graphics processing unit according to claim 16, wherein: The graphics processing unit is embodied in hardware on an integrated circuit.

18. The texture filtering unit according to any one of claims 1 to 8, wherein: The texture filtering unit is embodied in hardware on an integrated circuit.

19. A computer-readable storage medium having computer-readable code encoded thereon, the computer-readable storage medium being configured such that when the code is executed, the method of any one of claims 10-15 is performed.

20. An integrated circuit manufacturing system, comprising: A computer readable storage medium having stored thereon a computer readable description of an integrated circuit, the computer readable description of the integrated circuit describing the graphics processing unit of claim 16 or the texture filtering unit of any one of claims 1-8; a layout processing system configured to process the computer-readable description of the integrated circuit to generate a circuit layout description of the integrated circuit embodying the graphics processing unit or the texture filtering unit; as well as An integrated circuit production system is configured to manufacture the graphics processing unit or the texture filtering unit according to the circuit layout description.

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