Signal Path Linearizer

Abstract

The present application discloses a signal path linearizer. A signal path linearizer (500) is used to compensate (including pre-compensate) signal path nonlinearity for PAM4 SerDes communication. The linearizer can be configured with a first differential GM stage (510) and a second differential GM stage (520), the first differential GM stage (510) is used to provide DC gain, and the second differential GM stage (520) is used to introduce a defined nonlinear adjustment in DC gain by adding to the DC gain of the first differential GM stage or subtracting from the DC gain of the first differential GM stage. The differential GM stage can be configured to generate a compensated PAM4 signal using a combined DC gain, wherein the combined DC gain provides a nonlinear broadband gain adjustment to compensate for nonlinearity in the PAM4 signal path. The compensation range can be increased by selective degradation (516, 526), ​​and the compensation region can be moved by selectively introducing (one or more) input offsets (528P1, 528P2).

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] Priority is claimed under 37 CFR 1.78 and 35 USC 119(e) to U.S. Provisional Application No. 62 / 654,753 (Docket TI-77323PS), filed on April 9, 2018, the entire contents of which are incorporated herein by reference. Background Art

[0003] The PAM4SerDes communication link is based on PAM4 signal encoding, with four signal levels encoding the 2 bits mapped to one symbol, for example based on Gray encoding: 10 / 11 / 01 / 00 or 3201. The PAM4 signal levels are separated by three PAM4 eyes: top, middle and bottom.

[0004] The three PAM4 eyes are not vertically symmetrical (eye height and width) because with four signal / voltage levels, transitions need to occur between non-adjacent signal levels, which takes longer than transitions between adjacent signal levels. As a result, the top and bottom eyes are narrower relative to the middle eye.

[0005] Signal path nonlinearity causes significant degradation of the PAM4 signal, as reflected in the eye symmetry (eye height / width) and vertical alignment (skew). For an example system that connects a transmitter TX and a receiver RX via a PAM4SerDes communication link, signal path nonlinearity in the TX, RX, and communication link (including the TX-side and RX-side signal interfaces) causes the PAM4 signal (see Figure 3A ) degradation, as reflected in degraded vertical eye symmetry and vertical eye alignment. Summary of the invention

[0006] This summary is a general introduction to the disclosure provided by the detailed description and drawings, summarizing aspects and features of the disclosure. It is not a complete overview of the disclosure and should not be interpreted as identifying key elements or features of the disclosed invention, or otherwise characterizing or defining the scope of the invention.

[0007] The disclosure describes apparatus and methods for signal path linearization of PAM4 signals, such as those that may be used in PAM4 serial communication based systems, including PAM4 SerDes (serializer / deserializer) communication links.

[0008] According to aspects of the present disclosure, a method for linearizing a PAM4 signal path includes: (a) receiving a PAM4 signal on a PAM4 signal path; (b) providing a first DC (direct current) gain to the PAM4 signal using a first differential gm stage configured to provide a DC (direct current) gain; (c) providing a second DC gain using a second differential gm stage, the second differential gm stage being configured to introduce a defined nonlinear adjustment in the DC gain by adding to or subtracting from the DC gain of the first differential gm stage. The method may include generating a compensated PAM4 signal using a combined DC gain from the first and second differential gm stages, the combined DC gain from the first and second differential gm stages providing a nonlinear broadband gain adjustment to compensate for nonlinearities in the PAM4 signal path.

[0009] According to other aspects of the present disclosure, a PAM4 signal path linearizer may be configured with at least a first and a second differential GM stage coupled in cascade between an input port and an output port. The first differential GM stage is coupled to the differential input port and is configured to provide a DC (direct current) gain. The second differential GM stage is coupled to the output of the first differential GM stage and is configured to introduce a defined nonlinear adjustment in the DC gain by adding to or subtracting from the DC gain of the first differential GM stage. At least the first and second differential GM stages may be configured to generate a compensated PAM4 signal using a combined DC gain from the first and second differential GM stages, wherein the combined DC gain from the first and second differential GM stages provides a nonlinear broadband gain adjustment to compensate for nonlinearities in the PAM4 signal path. The compensation range may be increased by selective degeneration, and the compensation region may be moved by selectively introducing (one or more) input offsets.

[0010] According to other aspects of the present disclosure, a PAM4 communication system includes a PAM4SerDes (serializer / deserializer) communication link (PAM4 link), a transmitter (TX) that interfaces to a first end of the PAM4 link, and a receiver (RX) that interfaces to a second end of the PAM4 link, wherein the TX, RX, and PAM4 link include a PAM4 signal path. The PAM4 communication system includes at least a first and a second differential gm stage coupled in cascade between an input port and an output port, the first differential gm stage coupled to the differential input port and configured to provide a DC (direct current) gain, the second differential gm stage coupled to the output of the first differential gm stage, and configured to introduce a defined nonlinear adjustment in the DC gain by adding to or subtracting from the DC gain of the first differential gm stage. At least the first and second differential gm stages are configured to generate a compensated PAM4 signal at a differential output port, wherein the combined DC gain from the first and second differential gm stages provides a nonlinear broadband gain adjustment to compensate for nonlinearities in the PAM4 signal path. At least the first and second differential gm stages may be configured to introduce a nonlinear DC gain adjustment to approximate the inverse of the PAM4 signal path nonlinearity to compensate for the nonlinearity at the signal bandwidth of the PAM4 signal.

[0011] Other aspects and features of the invention claimed in this patent document will be apparent to those skilled in the art from the following disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1A and 1B An example communication system 10 is shown having a transmitter 11 and a receiver 13, 13A and an example PAM4Ser Des communication link 15, and including an example repeater 30 including an example signal path linearizer 40 according to the present disclosure, wherein Figure 1B Example graphs are provided illustrating the effect of introducing a signal path linearizer into a signal path in accordance with the present disclosure.

[0013] Figure 2A and 2B An example PAM4 repeater 30 according to the present disclosure is shown, which includes a CTLE 32 and a linear driver 34, and includes an example signal path linearizer 40 having N cascaded differential gm stages (DIFF1 41, DIFF2 42...DIFFN 40N), each of the N cascaded differential gm stages being configured to provide nonlinear gain compensation within the signal band to compensate for large signal bandwidth reduction from signal path nonlinearities (nonlinearities at the signal bandwidth), for example, to compress the middle eye and / or expand the bottom and top eyes (and reduce skew).

[0014] Figures 3A-3Dis an example PAM4 eye diagram according to the present disclosure, which illustrates the effects of signal path nonlinearity and signal path linearization based on introducing selective gain compensation for signal path nonlinearity, for example, to reduce the AC gain difference between the top / bottom eyes 20T, 20B and the middle eye 20M.

[0015] Figure 4A , 5A 6A shows a design example of signal path linearization according to the present disclosure to provide wideband compensation of signal path nonlinearity based on cascaded differential GM stages, which are configured to provide selective nonlinear gain compensation within the signal band by reducing the AC gain difference between PAM4 signal levels (between PAM4 top / bottom and middle eyes), for example, by compressing the middle eye and / or expanding the top and / or bottom eyes, introducing piecewise nonlinear DC gain adjustment to compensate for nonlinearity at the signal bandwidth (large signal bandwidth reduction).

[0016] Figure 4A An example schematic diagram is illustrated with cascaded differential gm stages DIFF1 410 and DIFF2 420 configured to reduce gain in the mid-eye region, wherein Figure 4B Provide an equivalent piecewise functional circuit representation of [DIFF1-DIFF2], and where Figure 4C An example DIFF1 / DIFF2 piecewise transfer function is illustrated, including a piecewise reduction in current gain (DIFF2) to compress the middle eye 402M, and wherein Figure 4D An example diagram illustrating the effect of non-linear gain compensation provided by DIFF1 / DIFF2 in the middle eye region 402M is provided.

[0017] Figure 5A An example schematic diagram is illustrated with cascaded differential gm stages DIFF1 510 and DIFF2 520 configured to introduce a piecewise nonlinear (offset-shift) DC gain adjustment to increase gain in the bottom eye region, wherein Figure 5B Provide an equivalent piecewise functional circuit representation of [DIFF1+(DIFF2+Vos)], and where Figure 5C An example DIFF1 / DIFF2 piecewise transfer function is illustrated, including a piecewise increase in the (offset-shift) current gain [DIFF2+Vos] to extend the bottom eye, and where Figure 5D An example graph illustrating the effect of non-linear gain compensation provided by DIFF1 / DIFF2 in the bottom eye region 502B is provided.

[0018] Fig. 6AAn example schematic diagram is illustrated with cascaded differential gm stages DIFF1 610, DIFF2 620, and DIFF3 630 configured to introduce a piecewise nonlinear (offset-shift) DC gain adjustment to increase gain in the regions of the top and bottom eyes, wherein Figure 6B An equivalent piecewise functional circuit representation of offset-shift nonlinear gain compensation for the top eye [DIFF1+(DIFF2+Vos)] and the bottom eye [DIFF1+(DIFF3-Vos)] is provided, and wherein Figure 6C An example DIFF1 / DIFF2 / DIFF3 piecewise transfer function is shown, including a piecewise increase in current gain to extend the top and bottom eyes (602T and 602B), and wherein Fig.6D Example graphs are provided illustrating the (offset-shift) nonlinear gain compensation provided by DIFF1 / DIFF2 / DIFF3 in the top and bottom eye regions (602T and 602B). DETAILED DESCRIPTION

[0019] The present specification and accompanying drawings constitute a disclosure of a signal path linearizer for compensating for signal path nonlinearities, based on cascading differential gm stages to introduce nonlinear DC gain adjustment (segmentation), approximating the inverse of signal path nonlinearities to provide compensation for nonlinearities at the signal bandwidth (large signal bandwidth reduction) by reducing the AC gain difference between PAM4 signal levels (between PAM4 top / bottom and mid-eye), and illustrating various technical features and advantages.

[0020] This disclosure uses the following terms. "Signal path linearizer" and "signal path linearization," in the context of a PAM4 serial communication link, means compensating (including pre-compensating) for nonlinearities in the entire signal path (e.g., transmit (TX) and receive (RX) mediated by a PAM4 SerDes (serializer deserializer) communication link).

[0021] Briefly summarized, in an example embodiment, a signal path linearizer for PAM4 SerDes communication is used to compensate (including pre-compensate) signal path nonlinearities. The signal path linearizer may include at least a first and a second differential gm stage coupled in cascade, the second gm stage being configured to introduce a defined adjustment in the combined DC gain by adding to or subtracting from the DC gain of the first gm stage. The compensation range may be increased by selective degradation, and the compensation region may be moved by selectively introducing (one or more) input offsets. The first and second differential gm stages may be configured to introduce a combined DC gain to provide a nonlinear broadband gain adjustment to compensate for PAM4 signal path nonlinearities, for example, by introducing a nonlinear DC gain adjustment to approximate the inverse of the signal path nonlinearity at the signal bandwidth, reducing the AC gain difference between PAM4 signal levels (between the PAM4 top / bottom and mid-eye). In effect, the signal path linearizer introduces a piecewise nonlinear DC gain adjustment to selectively distort the DC gain to provide broadband linearization to compensate for the large signal bandwidth reduction caused by the nonlinearity at the signal bandwidth.

[0022] Figure 1A and Figure 1B An example communication system 10 is illustrated. In this illustrative example, a transmitter TX IC 11 (such as an application specific integrated circuit or ASIC), and a receiver RX IC 13, 13A and an example PAM4 SerDes com link 15. The SerDes communication link includes a TX end 15TX and a receive end 15RX.

[0023] The communication system 10 illustratively includes a repeater 30. The SerDes communication link may include a repeater at the TX end 15TX and / or the RX end 15RX, for example, to extend the link range beyond normal TX-to-RX capabilities. Alternatively, the repeater function may be integrated with the RX 13 as a single RX IC 13A having a front-end linearizer interface to the RX signal path circuitry.

[0024] As illustrated, the repeater 30 includes an analog CTLE (Continuous Time Linear Equalizer) 32 and a linear (eg, Finite Impulse Response (FIR)) driver 34 that drives the linearized PAM4 data signal to the RX 13 .

[0025] The repeater 30 includes an example signal path linearizer 40 according to the present disclosure. The signal path linearizer can be configured to provide compensation (including pre-compensation) for signal path nonlinearity through the signal chain, TX-to-RX (including TX and RX SerDes interfaces in TX and RX) of the PAM4 SerDes communication link 15.

[0026] Figure 1B Example graphs are provided that illustrate the effect of introducing a signal path linearizer into the signal path to improve PAM4 signaling linearity according to the present disclosure. For an example TX-to-RX PAM4 SerDes system, the PAM4 signal linearity of the system without signal path linearization is illustrated at 10A, and the PAM4 signal linearity of the system with a signal path linearizer in the signal path (e.g., at 40A) is illustrated. Figure 1A The example repeater 30 of FIG. 1 includes a signal path linearizer for PAM4 signal linearity of a system. According to the disclosure, the signal path linearizer compensates for signal path nonlinearity that produces nonlinearity at signal bandwidth 10A (large signal bandwidth reduction) by introducing a nonlinear DC gain adjustment that approximates the inverse of signal path nonlinearity 40A.

[0027] Figure 2A and 2B An example PAM4 repeater 30 is illustrated. Figure 2A , the repeater 30 includes a CTLE 32 and a linear driver 34. According to the present disclosure, the repeater 30 includes a signal path linearizer 40 in the signal path.

[0028] The PAM4 repeater 30 receives the PAM4 data signal through the PAM4 serial interface RXnP / RXnN and retransmits the PAM4 data signal through the PAM4 serial interface TXnP / TXnN. According to the present disclosure, the example repeater 40 performs CTLE linearization and signal path linearization to compensate (including pre-compensation) for nonlinearities in the signal path.

[0029] Also refer to Figure 2B , an example signal path linearizer 40 includes N (N≥2) cascaded differential gm stages (DIFF1 41, DIFF2 42, ... DIFFN 40N). Each differential gm stage is configured to introduce a nonlinear DC gain adjustment (segmented), approximating the inverse of the signal path nonlinearity to compensate for the nonlinearity at the signal bandwidth (large signal bandwidth reduction), including selectively using the degradation in the tail of the differential gm stage (compensation range), and the offset at the input of the differential gm stage (compensation region).

[0030] According to the present disclosure, the combined effect of the nonlinear DC gain adjustment provided by the cascaded DIFF1-DIFFN gm stages, and the (optional) offset adjustment is to compensate for signal path nonlinearity by reducing the AC gain difference between PAM4 signals. For example, the signal path linearizer can be configured to compress the middle eye and / or expand the bottom eye and top eye (approximately the inverse of the signal path nonlinearity) to compensate for the nonlinearity at the signal bandwidth (large signal bandwidth reduction).

[0031] Figures 3A-3D is an example PAM4 eye diagram with top, middle and bottom eyes 20T, 20M and 20B separating the PAM signaling levels 201, 200, 210, 211 corresponding to the Gray coded mapping 01, 00, 10, 11 (3201). Figure 3A An example PAM signal 200 is illustrated without signal path linearization, illustrating the effects of signal path nonlinearity: the eye height and alignment (skew) of the middle eye relative to the top and bottom eyes 20T and 20B is asymmetric.

[0032] Figure 3B-3D Three successive levels of signal path linearization according to the present disclosure are illustrated, which are based on introducing selective gain compensation to reduce the AC gain difference between the top / bottom eyes 20T, 20B and the middle eye 20M. Figure 3D , through the third level of gain compensation, the vertical symmetry and alignment of the PAM4 signal 200 are significantly improved.

[0033] Figure 4A , 5A , 6A illustrate design examples for signal path linearization according to the present disclosure to provide wideband compensation for signal path nonlinearity. These design examples illustrate configurations of signal path linearizers (400, 500, 600) based on cascaded differential gm stages configured to provide selective nonlinear gain compensation within the signal band by reducing the AC gain difference between PAM4 signal levels (between PAM4 top / bottom and middle eyes), for example, by compressing the middle eye and / or expanding the top and / or bottom eyes, introducing piecewise nonlinear DC gain adjustment to compensate for nonlinearity at the signal bandwidth (large signal bandwidth reduction). Nonlinear gain compensation can be used to approximate the inverse of signal path nonlinearity. The compensation range can be increased by selective degradation, and the compensation region can be moved by selectively introducing (one or more) input offsets.

[0034] These design examples illustrate the use of selectively configured differential gm stages to introduce piecewise nonlinear DC gain adjustment to linearize the AC gain at the signal bandwidth. In practice, the differential gm stage is configured to provide selective DC gain distortion so that the IIP3 curve at the signal bandwidth is linearized. For example, an IIP3 curve for an optical application may show compression primarily at the bottom eye, so that the piecewise differential gm stage design may be configured to introduce an offset-shifted increased gain to extend the bottom eye ( Figures 5A-5D As another example, the IIP3 curves for other applications may show compression at both the top and bottom eyes, so that the piecewise differential gm stage design may be configured to introduce an offset-shifted increased gain to extend the top and bottom eyes ( Figures 6A-6D ).

[0035] Figure 4A An example design schematic of a signal path linearizer 400 is illustrated having cascaded differential gm stages DIFF1 410 and DIFF2 420 configured to introduce a nonlinear DC gain adjustment (segmentation) to reduce the gain in the region of the mid-eye to compensate for the large signal bandwidth reduction caused by signal path nonlinearity at the signal bandwidth.

[0036] DIFF1 410 includes a differential NPN pair 411 / 412 that receives differential inputs VINP / VINN and provides current gain. DIF1 410 includes a collector resistor 413 and emitter tail current sources 414A / 414B. DIFF1 provides a differential output voltage VOUTP / VOUTN from the collectors of NPN 411 and NPN 412.

[0037] DIFF1 410 is cascade coupled to DIFF2 420. DIFF2 420 includes a differential NPN pair 421 / 422 coupled to receive differential inputs VINP / VINN. The DIFF2 differential NPN pair collectors are connected 423 to outputs VOUTN / VOUTP, and the emitters are coupled to emitter tail current sources 424. For the illustrative example, the collector of the VINP controlled NPN 421 is connected to VOUTN from the collector of the DIFF1 NPN 412, and the collector of the VINN controlled NPN 422 is connected to VOUTP from the collector of the DIFF1 NPN 411, such that the DIFF2 current gain is subtracted from the DIFF1 current gain (see Figure 4B / 4C).

[0038] Depending on the design requirements, DIFF1 410 and DIFF2 420 may include emitter degeneration to extend the linear operating range. For the illustrative example signal path linearizer design 400, DIFF1 410 includes resistor degeneration 416, while DIFF2 420 does not include emitter degeneration, as shown in FIG. Figure 4C This is reflected in the example transfer function illustrated in .

[0039] Figure 4B An equivalent piecewise functional circuit representation of the signal path linearizer 400 is provided: [DIFF1-DIFF2]=IOUT.

[0040] Figure 4CAn example DIFF1 / DIFF2 piecewise transfer function is illustrated. Within the middle eye region 402M, DIFF1 and DIFF2 introduce a piecewise nonlinear DC gain adjustment, where DIFF2 reduces the gain of DIFF1, represented by a reduction in current gain IOUT within the middle eye region 402M. Note that the linear range of DIFF1 is extended by degradation.

[0041] Figure 4D An example graph is provided that illustrates the nonlinear gain compensation provided by DIFF1 and DIFF2 in the middle eye region 402M to compress the middle eye. DIFF1 / DIFF2 provides nonlinear adjustment to the DC current gain of the small signal (middle eye) compared to the large signal gain (top / bottom eye) to compensate for the reduction in large signal bandwidth due to nonlinearity at the signal bandwidth. This segmented (DIFF1 / DIFF2) nonlinear DC gain adjustment effectively reduces the gain of the middle eye at DC, thereby linearizing the gain at the signal bandwidth of the middle and upper / lower eyes.

[0042] Figure 5A An example design schematic with cascaded differential gm stages DIFF1 510 and DIFF2 520 configured to introduce a piecewise nonlinear DC gain adjustment to increase the gain in the (offset-shift) region of the bottom eye is illustrated.

[0043] DIFF1 510 includes a differential NPN pair 511 / 512 that receives differential inputs VINP / VINN and provides current gain. DIFF1 includes a collector resistor 513 and emitter tail current sources 514A / 514B. DIFF1 provides a differential output voltage VOUTP / VOUTN from the collectors of NPN 511 and NPN 512.

[0044] DIFF1 510 is cascade coupled to DIFF2 520. DIFF2 520 includes a differential NPN pair 521 / 522 coupled to receive VINP / VINN. The DIFF2 differential NPN pair collectors are connected 523 to outputs VOUTN / VOUTP, and the emitters are coupled to emitter tail current source 524. For the illustrative example, the collector of the VINP controlled NPN 521 is connected to VOUTP from the collector of the DIFF1 NPN 511, and the collector of the VINN controlled NPN 522 is connected to VOUTN from the collector of the DIFF1 NPN 512, such that the DIFF2 current gain is added to the DIFF1 current gain (see Figure 5B / 5C).

[0045] Depending on the design requirements, DIFF1 510 and DIFF2 520 may include emitter degeneration to extend the linear operating range. For the illustrative example signal path linearizer design 500 , DIFF1 510 includes resistor degeneration 516 , and DIFF2 520 includes resistor degeneration 526 .

[0046] For the example signal path linearizer design 500, DIFF2 includes a positive side offset circuit 528P1 / 528P2 at the VINP input 521P to the NPN 521. The DIFF2 offset can be used to move the compensation region down to the bottom eye region (see Figure 5C / 5D, 502B).

[0047] Figure 5B An equivalent piecewise functional circuit representation of the signal path linearizer 400 is provided: [DIFF1+(DIFF2+Vos)]=IOUT.

[0048] Figure 5C An example DIFF1 / DIFF2 piecewise transfer function is illustrated. The DIFF1 linear region is extended by degradation, and the DIFF2 linear region is offset-shifted to the bottom eye region 502B. Within the bottom eye region 502B, DIFF1 and DIFF2 are piecewise linear, where DIFF2 increases the current gain of DIFF1, represented by an increase in the current gain IOUT within the bottom eye region 502B, providing a piecewise increase in the offset-shifted DC current gain [DIFF2+Vos] to extend the bottom eye.

[0049] Figure 5D An example graph is provided illustrating the nonlinear gain compensation provided by DIFF1 / DIFF2 in the bottom eye region 502B to extend the bottom eye compared to pure linear gain. DIFF1 / DIFF2 provides nonlinear adjustment to the DC current gain of the bottom eye to compensate for the reduction in large signal bandwidth due to nonlinearity at the signal bandwidth. This segmented (DIFF1 / DIFF2) nonlinear DC gain adjustment effectively increases the gain of the bottom eye compared to the middle eye at DC to linearize the gain at the signal bandwidth of the bottom and middle eyes.

[0050] Fig. 6A An example schematic diagram is illustrated with cascaded differential gm stages DIFF1 610, DIFF2 620, and DIFF3 630 configured to introduce piecewise nonlinear DC gain adjustment to increase gain in the offset-shift region of the top and bottom eyes.

[0051] DIFF1 610 includes a differential NPN pair 611 / 612 that receives differential inputs VINP / VINN and provides current gain. DIFF1 includes a collector resistor 613 and emitter tail current sources 614A / 614B. DIFF1 provides a differential output voltage VOUTP / VOUTN from the collectors of NPN 611 controlled by VINP and NPN 612 controlled by VINN.

[0052] DIFF1 610 is cascade coupled to DIFF2 620 and DIFF3 630 .

[0053] DIFF2 620 includes a differential NPN pair 621 / 622 coupled to receive VINP / VINN. The DIFF2 differential NPN pair collectors are connected 623 to the output VOUTN / VOUTP, and the emitters are coupled to an emitter tail current source 624. For the illustrative example, the collector of the VINP-controlled NPN 621 is connected to VOUTP from the collector of the DIFF1 NPN 611, and the collector of the VINN-controlled NPN 622 is connected to VOUTN from the collector of the DIFF1 NPN 612, so DIFF2 is added to DIFF1 (with an offset shift described below).

[0054] DIFF3 630 includes a differential NPN pair 631 / 632 coupled to receive VINP / VINN. The DIFF2 differential NPN pair collectors are connected 633 to the output VOUTN / VOUTP, and the emitters are coupled to the emitter tail current source 624. For the illustrative example, the collector of the VINP controlled NPN 631 is connected to VOUTP from the collector of the DIFF1 NPN 611, and the collector of the VINN controlled NPN 622 is connected to VOUTN from the collector of the DIFF1 NPN 612, so the DIFF3 current gain is added to the DIFF1 current gain (see Figure 5B / 5C) (with the offset movement described below).

[0055] Depending on design requirements, DIFF1 610 , DIFF2 620 , and DIFF3 630 may include emitter degeneration to extend the linear operating range. For the illustrative example signal path linearizer design 600 , DIFF1 610 includes resistor degeneration 616 , DIFF2 620 includes resistor degeneration 626 , and DIFF3 630 includes resistor degeneration 636 .

[0056] For the example signal path linearizer design 600, DIFF2 620 includes a positive side input offset to move the compensation region down to the bottom eye region, and DIFF3 includes a negative side input offset to move the compensation region up to the top eye region (see Figure 6C / 6D, 602B / 602T). DIFF2 620 includes offset circuits 628P1 / 628P2 at VINP input 621P to NPN 621. DIFF3 630 includes offset circuits 638N1 / 638N2 at VINN input 632N to NPN 632. Figure 6C The effect of using an offset is further described.

[0057] Figure 6B An equivalent piecewise functional circuit representation of the signal path linearizer design 400 is provided: [DIFF1+(DIFF2+Vos)+(DIFF3-Vos)]=IOUT. That is, for the top eye ( Figure 6C / 6D, 602T), nonlinear gain compensation is provided by [DIFF1+(DIFF2+Vos)], and for the bottom eye ( Figure 6C / 6D, 602B), nonlinear gain compensation is provided by [DIFF1+(DIFF3-Vos)].

[0058] Figure 6C An example DIFF1 / DIFF2 / DIFF3 piecewise transfer function is illustrated. The DIFF1 linear region is extended by degradation. The DIFF2 compensation region is shifted downward - moved to region 602B of the bottom eye. The DIFF3 compensation region is shifted - moved to region 602T of the top eye. Within the bottom eye region 602B, DIFF1 and DIFF2 are piecewise linear, where DIFF2 increases the gain of DIFF1, represented by an increase in current gain IOUT within the bottom eye region 602B. Similarly, within the top eye region 602T, DIFF1 and DIFF3 are piecewise linear, where DIFF3 increases the gain of DIFF1, represented by an increase in current gain IOUT within the top eye region 602B.

[0059] Fig.6DExample graphs illustrating nonlinear gain compensation provided by cascaded signal path linearizers DIFF1 / DIFF2 / DIFF3 are provided. In the bottom eye region, DIFF1 and DIFF2 combine to provide a piecewise nonlinear DC gain increase in the bottom eye region, thereby extending the bottom eye. In the top eye region, DIFF1 and DIFF3 combine to provide a piecewise nonlinear gain increase in the bottom eye region, thereby extending the bottom eye. DIFF1 / DIFF2 provide a nonlinear adjustment to the DC current gain of the bottom eye, and DIFF1 / DIFF3 provide a nonlinear adjustment to the DC current gain of the top eye to compensate for the reduction in large signal bandwidth due to nonlinearity at the signal bandwidth. This piecewise (DIFF1 / DIFF2 / DIFF3) nonlinear DC gain adjustment effectively increases the gain of the top and bottom eyes compared to the middle eye at DC to linearize the gain at the signal bandwidth of the bottom and middle eyes.

[0060] The disclosure provided in this specification and the accompanying drawings sets forth example designs and applications that illustrate aspects and features of the present invention and does not limit the scope of the present invention as defined by the claims. Known circuits, connections, functions, and operations are not described in detail to avoid obscuring the principles and features of the disclosed example designs and applications. The present disclosure may be used by a person of ordinary skill as a basis for modification, substitution, and alternative, including adaptation to other applications.

Claims

1. A circuit for a system having a transmitter (TX) and a receiver (RX) interfaced via a PAM4 SerDes communication link (PAM4 serializer / deserializer communication link (PAM4 link), and a PAM4 signal path, the circuit comprising: A signal path linearizer included in the PAM4 signal path, the signal path linearizer comprising: a differential input port and a differential output port, the differential input port being configured to couple to the PAM4 link to receive a PAM4 signal, and at least a first differential gm stage and a second differential gm stage, the first differential gm stage and the second differential gm stage being cascade coupled between the differential input port and the differential output port: Each gm stage includes a differential transistor pair coupled between a differential output voltage node and a common node, and At least the second differential gm stage selectively includes a degeneration element coupled between the differential transistor pair and the common node; The first differential gm stage is coupled to the differential input port and is configured to provide a DC gain, i.e., a direct current gain; The second differential gm stage is coupled to an output of the first differential gm stage and is configured to introduce a non-linear DC gain adjustment by adding to or subtracting from a DC gain of the first differential gm stage.

2. The circuit according to claim 1, wherein: The at least first and second differential gm stages are configured to generate a compensated PAM4 signal at the differential output port, wherein a combined DC gain from the first and second differential gm stages provides a non-linear broadband gain adjustment to compensate for non-linearities in the PAM4 signal path.

3. The circuit of claim 1, wherein: The at least first differential gm stage and the second differential gm stage are configured to introduce the nonlinear DC gain adjustment to approximate the inverse of the PAM4 signal path nonlinearity to compensate for the nonlinearity at a signal bandwidth of the PAM4 signal.

4. The circuit of claim 1 , wherein each of the at least first and second differential gm stages comprises a differential transistor pair coupled between a differential output voltage node and a common node, and: At least one of the first differential gm stage and the second differential gm stage includes an input offset element coupled to an input of at least one transistor of the corresponding differential transistor pair.

5. The circuit of claim 1, wherein: The non-linear DC gain adjustment includes at least one of: compressing the PAM4 middle eye, or expanding at least one of the PAM4 top eye and the bottom eye.

6. The circuit of claim 1, wherein: The non-linear DC gain adjustment includes pre-compensation for non-linearities in the PAM4 signal path.

7. The circuit of claim 1, wherein: The PAM4 signal path includes a repeater, wherein the signal path linearizer is integrated in the repeater.

8. A system circuit for data communication via a PAM4 communication link, comprising: PAM4 SerDes communication link is PAM4 serializer / deserializer communication link is PAM4 link; a transmitter, TX, connected to a first end of the PAM4 link; and A receiver, namely RX, which is connected to the second end of the PAM4 link; The TX, the RX, and the PAM4 link include a PAM4 signal path; A signal path linearizer included in the PAM4 signal path, the signal path linearizer comprising: a differential input port and a differential output port, the differential input port being configured to couple to the PAM4 link to receive a PAM4 signal, and at least a first differential gm stage and a second differential gm stage cascade-coupled between the differential input port and the differential output port: Each differential gm stage includes a differential transistor pair coupled between a differential output voltage node and a common node, and At least the second differential gm stage selectively includes a degeneration element coupled between the differential transistor pair and the common node; The first differential gm stage is coupled to the differential input port and is configured to provide a DC gain, i.e., a direct current gain, and the second differential gm stage coupled to an output of the first differential gm stage and configured to introduce a non-linear DC gain adjustment by adding to or subtracting from a DC gain of the first differential gm stage, The at least first and second differential gm stages are configured to generate a compensated PAM4 signal at the differential output port, wherein a combined DC gain from the first and second differential gm stages provides a non-linear broadband gain adjustment to compensate for non-linearities in the PAM4 signal path.

9. The system circuit according to claim 8, wherein: The at least first differential gm stage and the second differential gm stage are configured to introduce the nonlinear DC gain adjustment to approximate the inverse of the PAM4 signal path nonlinearity to compensate for the nonlinearity at a signal bandwidth of the PAM4 signal.

10. The system circuit of claim 8, wherein each of the at least first differential gm stage and the second differential gm stage comprises a differential transistor pair coupled between a differential output voltage node and a common node, and: At least one of the first differential gm stage and the second differential gm stage includes an input offset element coupled to an input of at least one transistor of the corresponding differential transistor pair.

11. The system circuit according to claim 8, wherein: The non-linear DC gain adjustment includes at least one of: compressing the PAM4 middle eye, or expanding at least one of the PAM4 top eye and the bottom eye.

12. The system circuit according to claim 8, wherein: The non-linear DC gain adjustment includes pre-compensation for non-linearities in the PAM4 signal path.

13. The system circuit according to claim 8, wherein: The PAM4 signal path includes a repeater, wherein the signal path linearizer is integrated in the repeater.

14. A method for a system having a transmitter (TX) and a receiver (RX) interfaced via a PAM4 SerDes communication link (PAM4 serializer / deserializer communication link (PAM4 link), and a PAM4 signal path, the method comprising: receiving a PAM 4 signal through the PAM4 signal path; Providing a first DC gain to the PAM4 signal using a first differential gm stage, the first differential gm stage being configured to provide a DC gain, the first differential gm stage comprising a differential transistor pair coupled between a differential output voltage node and a common node; providing a second DC gain using a second differential gm stage, the second differential gm stage configured to introduce a nonlinear DC gain adjustment by adding to or subtracting from the DC gain of the first differential gm stage, the second differential gm stage comprising a differential transistor pair coupled between a differential output voltage node and a common node; as well as For at least the second differential gm stage, a degeneration element is selectively included coupled between a corresponding differential transistor pair and the common node.

15. The method according to claim 14, further comprising: A compensated PAM4 signal is generated using a combined DC gain from the first differential gm stage and the second differential gm stage, wherein the combined DC gain from the first differential gm stage and the second differential gm stage provides a non-linear wideband gain adjustment to compensate for non-linearity in the PAM4 signal path.

16. The method of claim 15, wherein: The first DC gain and the second DC gain introduce a nonlinear DC gain adjustment to approximate the inverse of the nonlinearity of the PAM4 signal path to compensate for the nonlinearity at the signal bandwidth of the PAM4 signal.

17. The method according to claim 15, further comprising: For at least the second differential gm stage, an input offset is selectively provided to shift the compensation region.

18. The method of claim 15, wherein: The non-linear DC gain adjustment includes at least one of: compressing the PAM4 middle eye, or expanding at least one of the PAM4 top eye and the bottom eye.

19. The method of claim 14, wherein: The non-linear DC gain adjustment includes pre-compensation for non-linearities in the PAM4 signal path.

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