For the gate of a transistor

Abstract

Substrates, components, and techniques for a device are disclosed, where the device includes: a gate, where the gate includes a first gate side and a second gate side opposite the first gate side; a gate dielectric on the gate, where the gate dielectric includes a first gate dielectric side and a second gate dielectric side opposite the first gate dielectric side; a first dielectric, where the first dielectric is adjacent to the first gate side, the first gate dielectric side, the second gate side, and the second gate dielectric side; a channel, where the gate dielectric is between the channel and the gate; a source coupled to the channel; and a drain coupled to the channel, where the first dielectric is adjacent to the source and the drain. In an example, the first dielectric and the gate dielectric help insulate the gate from the channel, the source, and the drain.

Description

Technical Field

[0001] The present disclosure generally relates to the field of transistors, and more particularly, to gates for transistors. Background Art

[0002] Most, if not all, logic devices require some type of memory cell, such as random access memory (RAM). Dynamic random access memory (DRAM) is a type of random access memory that stores each bit of data in a separate capacitor. The capacitor can be charged or discharged, and these two states are used to represent the two values of a bit (i.e., 1 and 0). DRAM is widely used in digital electronic devices that require low-cost and high-capacitance memory. One of the largest applications of DRAM is the main memory or RAM in modern computers and electronic devices. DRAM is typically coupled to a transistor. However, the transistor leaks a small amount of current and may cause the capacitor of the DRAM to discharge and gradually weaken. Brief Description of the Drawings

[0003] Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. For the sake of convenience of this description, like reference numerals denote like structural elements. Embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings.

[0004] Figure 1 is a simplified block diagram of an embodiment showing a part of an electronic device according to an embodiment of the present disclosure;

[0005] Figure 2 is a simplified block diagram of an embodiment showing a part of an electronic device according to an embodiment of the present disclosure;

[0006] Figure 3 is a simplified block diagram of an embodiment showing a part of an electronic device according to an embodiment of the present disclosure;

[0007] Figure 4 is a simplified block diagram of an embodiment showing a part of an electronic device according to an embodiment of the present disclosure;

[0008] Figure 5 is a simplified block diagram of an embodiment showing a part of an electronic device according to an embodiment of the present disclosure;

[0009] Figure 6 is a simplified block diagram of an embodiment showing a part of an electronic device according to an embodiment of the present disclosure;

[0010] Figure 7A is a simplified block diagram of an embodiment showing a part of an electronic device according to an embodiment of the present disclosure;

[0011] Figure 7B is a simplified block diagram of an embodiment showing a part of an electronic device according to an embodiment of the present disclosure;

[0012] Figure 7C is a simplified block diagram of an embodiment showing a part of an electronic device according to an embodiment of the present disclosure;

[0013] Figure 7D is a simplified block diagram of an embodiment showing a part of an electronic device according to an embodiment of the present disclosure;

[0014] Figure 7E is a simplified block diagram of an embodiment showing a part of an electronic device according to an embodiment of the present disclosure;

[0015] Figure 7F is a simplified block diagram of an embodiment showing a part of an electronic device according to an embodiment of the present disclosure;

[0016] Figure 7G is a simplified block diagram of an embodiment showing a part of an electronic device according to an embodiment of the present disclosure;

[0017] Figure 7H is a simplified block diagram of an embodiment showing a part of an electronic device according to an embodiment of the present disclosure;

[0018] Figure 7I is a simplified block diagram of an embodiment showing a part of an electronic device according to an embodiment of the present disclosure;

[0019] Figure 8 is a simplified block diagram of an embodiment showing a part of an electronic device according to an embodiment of the present disclosure;

[0020] Figure 9 is a simplified block diagram of an embodiment showing a part of an electronic device according to an embodiment of the present disclosure;

[0021] Figure 10 is an interpolator that implements one or more of the embodiments disclosed herein; and

[0022] Figure 11 is a computing device constructed according to the embodiments disclosed herein.

[0023] The figures in the drawings are not necessarily drawn to scale, as their dimensions can be changed considerably without departing from the scope of the present disclosure. Detailed Description

[0024] The following detailed description sets forth exemplary embodiments of devices, methods, and systems related to the gates of transistors. For convenience, features such as structures, functions, and / or characteristics are described with reference to one embodiment, for example; any suitable one or more of the described features may be utilized to implement various embodiments.

[0025] In the following description, common terms used by those skilled in the art will be used to describe aspects of the exemplary embodiments to convey the substance of their work to other skilled artisans in the field. However, it will be apparent to those skilled in the art that the embodiments disclosed herein may be practiced using only some of the described aspects. For purposes of explanation, specific quantities, materials, and configurations are set forth in order to provide a thorough understanding of the exemplary embodiments. However, it will be apparent to those skilled in the art that the embodiments disclosed herein may be practiced without specific details. In other instances, well-known features are omitted or simplified so as not to render the exemplary embodiments difficult to understand.

[0026] Disclosed herein are substrates, components, and techniques for implementing devices that include one or more transistors. The transistors may include being configured to allow lower leakage when the gate is biased to a cutoff condition and to conduct only one type of charge (i.e., electrons). In a specific example, the transistor may include a gate, a dielectric above the gate, a channel above the dielectric, a source, and a drain, wherein the channel couples the source and the drain. A first dielectric (e.g., nitride) may be positioned along the sides of the gate and beneath the source and the drain. The first dielectric and the gate dielectric may help insulate the gate from the channel, the source, and the drain and allow the transistor to exhibit a lower amount of leakage. For example, a larger bandgap from the oxide layer in the transistor results in less leakage. A bottom gate of the transistor may be produced using a self-alignment process. The self-alignment process allows for a reduction in gate length variation during the manufacture of the transistor. This can allow for reliable control of subthreshold leakage and good electrostatics, as well as short-channel effects, to help enhance performance at scaled dimensions.

[0027] As used herein, the terms "above," "beneath," "below," "between," and "on" refer to the relative position of a layer of material or a component with respect to other layers or components. For example, a layer disposed above or below another layer may be in direct contact with the other layer or may have one or more intervening layers. Additionally, a layer disposed between two layers may be in direct contact with the two layers or may have one or more intervening layers. In contrast, a first layer "on" a second layer is in direct contact with the second layer. Similarly, unless otherwise expressly stated, a feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.

[0028] Embodiments of the present disclosure may be formed or implemented on a substrate such as a non-semiconductor substrate or a semiconductor substrate. In one embodiment, the non-semiconductor substrate may be silicon dioxide, an interlayer dielectric composed of silicon dioxide, silicon nitride, titanium oxide, and other transition metal oxides. Although several examples of materials that can form the non-semiconductor substrate are described herein, any material that can serve as a basis on which non-semiconductor devices can be built falls within the spirit and scope of the embodiments disclosed herein.

[0029] In another embodiment, the semiconductor substrate may be a crystalline substrate formed using bulk silicon or a silicon-on-insulator substructure. In other embodiments, the semiconductor substrate may be formed using alternative materials, which may or may not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-V or group IV materials. In other examples, the substrate may be a flexible substrate, including 2D materials such as graphene and molybdenum disulfide, organic materials such as pentacene, transparent oxides such as indium gallium zinc oxide polycrystalline / amorphous (low-temperature deposition) III-V semiconductors and germanium / silicon, and other non-silicon flexible substrates. Although several examples of materials that can form the substrate are described herein, any material that can serve as a basis on which semiconductor devices can be built falls within the spirit and scope of the embodiments disclosed herein.

[0030] In the following detailed description, reference is made to the accompanying drawings, which form a part of the detailed description, and in which like reference numerals always denote like parts, and in which embodiments that may be practiced are illustrated by way of example. The drawings show straight lines and parallel features; however, those skilled in the art will recognize that the scope of the present disclosure does not require straight lines and parallel features and allows for deviations. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be taken in a limiting sense.

[0031] Various operations may be described sequentially as a number of discrete actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations must be order-dependent. Specifically, these operations may not be performed in the order expressed. The described operations may be performed in an order different from the described embodiments. In additional embodiments, various additional operations may be performed and / or the described operations may be omitted. For the purposes of the present disclosure, the phrase “A and / or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and / or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0032] The description uses the phrase "in an embodiment", which can refer to one or more of the same or different embodiments. In addition, the terms "comprising", "including", "having", etc. used with respect to the embodiments of the present disclosure are synonymous. As used herein, "package" and "IC package" are synonymous. As used herein, the terms "chip" and "die" may be used interchangeably.

[0033] Figure 1 FIG. 4 is a simplified block diagram of an electronic device 100 including one or more transistors and an array according to an embodiment of the present disclosure. The electronic device 100 can be any electronic device including a memory (e.g., a computer, a smart phone, a laptop computer, a desktop computer, an Internet of Things (IoT) device, a vehicle electronic device, a handheld electronic device, a personal digital assistant, a wearable device, a home electronic device, etc.). The electronic device 100 can include one or more electronic components 102a - 102d. Each electronic component 102a - 102d can include one or more transistors 104 and / or one or more transistor arrays 106. Each transistor array 106 can be a systematic arrangement of multiple transistors 104 (e.g., arranged in rows and columns).

[0034] The transistor 104 can be configured to provide lower leakage and include a bottom gate formed using a self - alignment process. The self - alignment process allows for a reduction in gate length variation during the fabrication of the transistor. This enables reliable control of sub - threshold leakage and good electrostatics, as well as short - channel effects, to help enhance performance at scaled dimensions. Reliably controlling sub - threshold leakage allows the transistor 104 to have lower leakage compared to some current transistors. Using a bottom gate can result in a fin - like gate and enables a back - end - of - line (BEOL) self - aligned gate device for an oxide semiconductor channel.

[0035] The transistor 104 can be a transistor or an electronic switch that can be in an "on" or "off" state, and the term "transistor" includes metal-oxide semiconductor (MOS), complementary MOS (CMOS), n-channel MOS (NMOS), p-channel MOS (PMOS), MOS field-effect transistor (MOSFET), bipolar junction transistor (BJT), field-effect transistor (FET), finFET, junction-gate FET (JFET), insulated-gate FET (IGFET), n-channel field-effect transistor (NFET), insulated-gate bipolar transistor, or other similar transistors that can be configured to perform the functions, features, and operations disclosed herein. In an example, the transistor 104 can be a back-end transistor. A back-end transistor is a thin-film transistor above a metal layer. Back-end transistors enable functional scaling of devices by allowing the stacking of memory and logic devices in the back-end. However, some back-end transistors suffer from high contact resistance and relatively large amounts of leakage. This can render some back-end transistors useless due to low drive current and thus degrade the performance of the memory or logic system.

[0036] The transistor 104 can be coupled to a capacitive element. The capacitive element can be a memory element such as embedded dynamic random access memory (eDRAM). In another example, the transistor 104 can be coupled to a resistive element such as resistive random access memory (RRAM). In yet another example, the transistor 104 can be coupled to some other type of memory or element. eDRAM can be integrated on the same die or multi-chip module (MCM) of an application-specific integrated circuit (ASIC) or microprocessor. Embedding memory on an ASIC or microprocessor allows for a relatively wider bus and high operating speeds. Also, since the density of DRAM is much higher compared to SRAM, a larger amount of memory can be installed on a smaller chip.

[0037] One problem with traditional transistors is that during the manufacturing process, the channel length can vary between different transistors. This variation can make it difficult to reliably control the subthreshold leakage current in the transistor and can also cause the transistor to fall outside of the specification requirements. The term "leakage" refers to the small amount of current that all transistors conduct even when they are turned off. If a transistor is coupled to a capacitive element, the leakage causes a gradual loss of energy from the capacitive element as the current slowly discharges the capacitive element. Currently, leakage is one of the main factors limiting the performance improvement of computer processors. Transistor 104 can be configured to address these problems (and other problems). For example, due to the inherent properties of the materials in transistor 104, transistor 104 can be configured to allow relatively low leakage. For example, a larger bandgap from the oxide layer in transistor 104 enables less leakage. In traditional silicon transistors, there are majority and minority carriers (i.e., holes and electrons), which means that traditional silicon transistors can have leakage in either gate bias direction. Transistor 104 can be configured to have the ability to conduct only one type of charge (i.e., electrons) when the gate is biased to the cutoff condition and to allow a lower leakage current. In a specific example, transistor 104 can include a gate, a gate dielectric above the gate, a channel above the dielectric, a source, and a drain, where the channel couples the source and the drain. A first dielectric can be positioned along the sides of the gate and under the source and the drain. The first dielectric and the gate dielectric can help insulate the gate from the channel, the source, and the drain and allow transistor 104 to exhibit a lower amount of leakage.

[0038] Turning Figure 2 , Figure 2 FIG. shows an embodiment of transistor 104. Transistor 104 can include an oxide layer 108, a gate 110, a first dielectric 112, a second dielectric 160, a gate dielectric 114, a channel 116, a passivation layer 118, a third dielectric 120, a source 122, and a drain 124. The source 122 and the drain 124 can be coupled to each other using the channel 116. In the example, the second dielectric 160 is the same material as the oxide 108. The first dielectric 112 can help insulate the gate 110 and the gate dielectric 114 from the oxide 108 and the second dielectric 160 and can help ensure that the leakage in transistor 104 is low. The gate 110 can be configured as a gate or a word line. The source 122 can be configured as a source. The drain 124 can be configured as a drain or a bit line. The first dielectric 112 can abut the sides of the gate 110 (e.g., the first gate side of the gate 110 and the second gate side of the gate 110) and the sides of the gate dielectric 114 (e.g., the first gate dielectric side of the gate dielectric 114 and the second gate dielectric side of the gate dielectric 114) to help prevent the gate 110 from shorting.

[0039] In the case of an NMOS transistor, when a positive voltage greater than the threshold voltage of the NMOS transistor is applied, the channel 116 will allow current to flow from the source 122 to the drain 124. In the case of a PMOS transistor, when a negative voltage greater than the threshold voltage of the PMOS transistor is applied, the channel 116 will allow current to flow. In both the NMOS transistor and the PMOS transistor, when the voltage is below the threshold voltage, the transistor will turn off and no current will flow. The larger bandgap in the transistor 104 and the ability to conduct only one type of charge help ensure low leakage in the transistor 104.

[0040] The oxide 108 can be a non-semiconductor substrate and can be composed of silicon dioxide, an interlayer dielectric composed of silicon dioxide, titanium oxide, other transition metal oxides, or other materials with a large bandgap that can act as a non-conductive layer. The gate 110 can be composed of different metals with various work functions ranging from approximately 5.6 eV to approximately 3.8 eV. More specifically, the gate 110 can be composed of a layer or bilayer of tungsten, cobalt, titanium nitride, tantalum nitride, titanium, aluminum, indium tin oxide, tantalum, ruthenium, hafnium, and other similar materials. The first dielectric 112 can be composed of silicon nitride, silicon dioxide, silicon oxynitride, carbon-doped silicon dioxide, carbon-doped silicon nitride, or some other material that can insulate the gate 110 and the gate dielectric 114 from the oxide 108 and the second dielectric 160 and help reduce leakage in the transistor 104. The second dielectric 160 can be a non-semiconductor substrate and can be composed of silicon dioxide, an interlayer dielectric composed of silicon dioxide, silicon nitride, silicon oxynitride, titanium oxide, other transition metal oxides, or other materials with a large bandgap that can act as a non-conductive layer. In an example, the second dielectric 160 is the same material as the oxide 108. In other examples, the second dielectric 160 can be the same material as the material of adjacent layers on the chip or die. The gate dielectric 114 can be a dielectric and can be a high-k dielectric material and is composed of one or more layers of silicon dioxide, silicon dioxide, ternary metal oxides, and / or high-k dielectric materials. The high-k dielectric materials can include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. More specifically, the high-k dielectric materials can include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process can be performed on the gate dielectric 114 to improve its quality when using high-k materials.

[0041] The channel 116 can be formed of indium gallium zinc oxide, zinc oxide, zinc oxide nitride, gallium oxide, tin oxide, copper oxide, indium zinc oxide, indium oxide, or some other semiconductor metal oxide, or other semiconductor materials. The passivation layer 118 can be formed of a low-k dielectric, carbon-doped silicon dioxide, titanium oxide, hafnium oxide, or some other material acting as a passivation layer. The third dielectric 120 can be formed of a material having etch properties different from those of the materials in the first dielectric 112 and the second dielectric 160 and can include silicon nitride, silicon dioxide, silicon oxynitride, carbon-doped silicon dioxide, carbon-doped silicon nitride, or some other material other than the materials in the first dielectric 112 and the second dielectric 160. The source 122 can be formed of different metals having various work functions in the range from about 5.6 eV to about 3.8 eV. More specifically, the source 122 can be formed of a layer or bilayer of tungsten, cobalt, titanium nitride, tantalum nitride, titanium, aluminum, indium tin oxide, tantalum, ruthenium, hafnium, and other similar materials. The drain 124 can be formed of different metals having various work functions in the range from about 5.6 eV to about 3.8 eV. More specifically, the drain 124 can be formed of a layer or bilayer of tungsten, cobalt, titanium nitride, tantalum nitride, titanium, aluminum, indium tin oxide, tantalum, ruthenium, hafnium, and other similar materials.

[0042] Turning Figure 3 , Figure 3 An embodiment of the transistor 104 is shown. The transistor 104 can be over one or more interlayer dielectrics (ILDs) 126. The ILD 126 layer can be formed using dielectric materials known to be suitable for integrated circuit structures (such as low-k dielectric materials). Examples of dielectric materials that can be used in the ILD 126 include, but are not limited to, silicon dioxide, carbon-doped oxides, silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass, and organosilicates such as silsesquioxane, siloxane, or organosilicate glass. The ILD 126 can include pores or air gaps to further reduce its dielectric constant. The nitride 128 can be from a previous metal layer and can be on the ILD 126 and under the gate 110 and the first dielectric 112.

[0043] Turning Figure 4 , Figure 4An embodiment of transistor 104 is shown. In a specific implementation, transistor 104 may be coupled to capacitor element 130 using connector 132. Capacitor element 130 may be a memory element such as RAM, eDRAM. In other examples, capacitor element 130 may not be a capacitor element, but may be a phase change material or a resistive element such as a resistive memory element (e.g., RRAM). In another example, capacitor element 130 may be a magnetoresistive RAM (MRAM), phase change memory, or some other type of memory element. Connector 132 may be configured as a metal connection for transistor 104 and may be a metal connection from capacitor element 130 to drain 124. Connector 132 may be part of an extended connection of metal 2 or metal 3, an extended connection of metal 4 or metal 5 (as Figure 6 shown), or some other metal layer or extended connection.

[0044] Transistor 104 may be configured to allow access to capacitor element 130 and to charge capacitor element 130 and change its resistance. For example, transistor 104 may be configured to program capacitor element 130, charge or discharge capacitor element 130, deselect or not interfere with capacitor element 130, read capacitor element 130, etc. In one implementation, capacitor element 130 may acquire charge by applying a bias and causing current to flow through transistor 104 and capacitor element 130. When transistor 104 is turned off, the channel resistance increases significantly, and due to the inherent material properties of transistor 104, leakage of capacitor element 130 can be reduced compared to traditional transistors.

[0045] In a specific example, transistor 104 may be a low-off-state leakage write transistor, such as an amorphous oxide semiconductor. Capacitor element 130 may be a small charge storage metal-insulator-metal (MIM) capacitor. The ability to use a smaller MIM capacitor is due to the lower leakage provided by transistor 104. As a result, different integration schemes for fabricating metal-oxide thin-film transistors with scaled dimensions can be used to implement a monolithic, BEOL, embedded one-transistor-one-capacitor (1T-1C) DRAM, which allows for increased density relative to current transistors.

[0046] Turning Figure 5 to Figure 5An embodiment of transistor 104 is shown. Transistor 104 may be on a silicon-based component such as a logic circuit. For example, transistor 104 may be on logic element 134. Logic element 134 may be on or above substrate 136. Substrate 136 may be a silicon-based substrate. Logic element 134 may include transistors, logic (e.g., adders, registers, etc.), microprocessor circuitry for processing data, and other circuitry. In an example, logic element 134 may communicate through transistor 104 with capacitor element 130 and cause data (or charge) to be stored in one or more capacitor elements 130.

[0047] Scaling of logic devices is typically achieved by reducing the size of the logic devices. One approach is based on increasing the number of logic elements per unit area. To increase the number of logic elements per unit area, the die density needs to be increased, and additional logic devices need to be fabricated above the silicon. To increase the die density in an integrated circuit (IC) package of a given footprint, one or more transistors 104 may be stacked on top of each other such that instead of fabricating transistor 104 on substrate 136, transistor 104 may be fabricated above substrate 136.

[0048] Turning Figure 6 , Figure 6 An example of an IC package including an embodiment of transistor 104 is shown. The IC package may be on substrate 136 and may include one or more logic elements 134, a first metal layer 140, a second metal layer 142, a third metal layer 144, a fourth metal layer 146, a fifth metal layer 148, a sixth metal layer 150, a seventh metal layer 152, and an eighth metal layer 154. As Figure 5 shown, transistor 104 may be in or on the fifth metal layer 148, and capacitor element 130 may be in or on the sixth metal layer 150. It should be noted that there may be more or fewer metal layers than Figure 5 shown. Also, one or more transistors 104 may be in or on one or more metal layers different from the illustrated fifth metal layer 148, and one or more capacitor elements 130 may be in or on one or more metal layers different from the illustrated sixth metal layer 150.

[0049] If the base substrate 136 is a semiconductor substrate, alternative materials can be used to form the semiconductor substrate (and any additional silicon-based layers), which may or may not be combined with silicon. This includes, but is not limited to, silicon, silicon germanium, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-V or group IV materials. In other examples, the substrate of any layer can be a flexible substrate, which includes 2D materials such as graphene and molybdenum disulfide, organic materials such as pentacene, transparent oxides such as indium gallium zinc oxide polycrystalline / amorphous (low-temperature deposition) group III-V semiconductors and germanium / silicon, and other non-silicon flexible substrates.

[0050] In an example, the plurality of electrical components can include one or more transistors 104 and / or one or more arrays 106 of transistors 104. Additionally, a plurality of transistors such as MOSFETs or just MOS transistors can include one or more transistors 104 and can be fabricated on the base substrate 136. In various embodiments, the MOS transistor can be a planar transistor, a non-planar transistor, or a combination of both. Non-planar transistors include FinFET transistors such as double-gate transistors or triple-gate transistors, and wrap-around or fully-enclosed gate transistors such as nanoribbon and nanowire transistors. Although the embodiments described herein may illustrate planar transistors, it should be noted that non-planar transistors can also be used to implement various embodiments.

[0051] Each MOS transistor includes a gate stack formed by at least two layers (a gate dielectric layer and a gate electrode layer). The gate dielectric layer can include one layer or a stack of layers. One or more layers can include silicon oxide, silicon dioxide, and / or high-k dielectric materials. High-k dielectric materials can include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that can be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and zinc niobate. In some embodiments, an annealing process can be performed on the gate dielectric layer to improve its quality when using high-k materials.

[0052] The gate electrode layer is formed on the gate dielectric layer and can be composed of at least one P-type work function metal or N-type work function metal, depending on whether the transistor is a PMOS or NMOS transistor. In some embodiments, the gate electrode layer can be composed of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Other metal layers can be included for other purposes, such as a barrier layer.

[0053] For a PMOS transistor, the metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides such as ruthenium oxide. The P-type metal layer will enable the formation of a PMOS gate electrode having a work function between approximately 4.9 eV and approximately 5.2 eV. For an NMOS transistor, the metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. The N-type metal layer will enable the formation of an NMOS gate electrode having a work function between approximately 3.9 eV and approximately 4.2 eV.

[0054] In some embodiments, when observing a cross-section of the transistor along the source-channel-drain direction, the gate electrode can be formed of a U-shaped structure that includes a bottom portion generally parallel to the substrate surface and two sidewall portions generally perpendicular to the top surface of the substrate. In another embodiment, at least one of the metal layers forming the gate electrode can simply be a planar layer generally parallel to the top surface of the substrate and not include sidewall portions generally perpendicular to the top surface of the substrate. In other embodiments, the gate electrode can be formed of a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode can be formed of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0055] In some embodiments, a pair of sidewall spacers that sandwich the gate stack can be formed on opposite sides of the gate stack. The sidewall spacers can be formed of materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. The process for forming the sidewall spacers generally includes deposition and etching process steps. In an alternative embodiment, multiple spacer pairs can be used. For example, two pairs, three pairs, or four pairs of sidewall spacers can be formed on opposite sides of the gate stack.

[0056] Source and drain regions may be formed within the base substrate 136, adjacent to the gate stack of each MOS transistor. Source and drain regions are typically formed using an implantation / diffusion process or an etch / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion implanted into the substrate to form the source and drain regions. After the ion implantation process, an annealing process is typically carried out which activates the dopants and causes them to further diffuse into the substrate. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. Then an epitaxial deposition process may be performed to fill the recesses with the material used to fabricate the source and drain regions. In some embodiments, a silicon alloy such as silicon germanium or silicon carbide may be used to fabricate the source and drain regions. In some embodiments, the epitaxially deposited silicon alloy may be in-situ doped with a dopant such as boron, arsenic, or phosphorus. In other embodiments, one or more alternative semiconductor materials such as germanium or III-V materials or alloys may be used to form the source and drain regions. And in still other embodiments, one or more layers of metal and / or metal alloy may be used to form the source and drain regions.

[0057] One or more ILDs may be deposited over the MOS transistors. The ILD layer may be formed using dielectric materials known to be suitable for integrated circuit structures (e.g., low-k dielectric materials). Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide, carbon-doped oxides, silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass, and organosilicates such as silsesquioxane, siloxane, or organosilicate glass. The ILD layer may include pores or air gaps to further reduce its dielectric constant.

[0058] Turning Figure 7A , Figure 7A FIG. shows a simplified block diagram of an early stage in the formation of transistor 104 in accordance with an embodiment of the present disclosure. As Figure 7A shown, gate 110 may be deposited over oxide 108. Gate 110 may be deposited using spin-on deposition from a slurry, sputtering, chemical vapor deposition (CVD), thermal vacuum deposition (TVD), atomic layer deposition (ALD), or any combination, or some other form of deposition that may deposit gate 110 over oxide 108. Oxide 108 may have a thickness of from about one (1) nanometer to about forty (40) nanometers. Gate 110 may also have a thickness of from about 1 nanometer to about 40 nanometers. Gate 110 may be etched, polished, planarized, and / or patterned.

[0059] Turning Figure 7B , Figure 7BShows a simplified block diagram of an early stage in the formation of transistor 104 according to an embodiment of the present disclosure. In an example, a gate dielectric 114 may be deposited on a gate 110. The gate dielectric 114 may be deposited using spin-on deposition from a slurry, sputtering, CVD, TVD, ALD, or any combination, or some other form of deposition that may deposit the gate dielectric 114 on the oxide 110. The gate dielectric 114 may have a thickness of from about 1 nanometer to about twenty (20) nanometers. The gate dielectric 114 may be etched, polished, planarized, and / or patterned.

[0060] Turning Figure 7C , Figure 7C Shows a simplified block diagram of an early stage in the formation of transistor 104 according to an embodiment of the present disclosure. In an example, a channel 116 may be deposited on the gate dielectric 114. The channel 116 may be deposited using spin-on deposition from a slurry, sputtering, CVD, TVD, ALD, or any combination, or some other form of deposition that may deposit the channel 116 on the gate dielectric 114. The channel 116 may have a thickness of from about three (3) nanometers to about 40 nanometers. The channel 116 may be etched, polished, planarized, and / or patterned.

[0061] Turning Figure 7D , Figure 7D Shows a simplified block diagram of an early stage in the formation of transistor 104 according to an embodiment of the present disclosure. In an example, a passivation layer 118 may be deposited on the channel 116. The passivation layer 118 may be deposited using spin-on deposition from a slurry, sputtering, CVD, TVD, ALD, or any combination, or some other form of deposition that may deposit the passivation layer 118 on the channel 116. The passivation layer 118 may have a thickness of from about 1 nanometer to about 40 nanometers. The passivation layer 118 may be etched, polished, planarized, and / or patterned.

[0062] Turning Figure 7E , Figure 7E Shows a simplified block diagram of a stage in the formation of transistor 104 according to an embodiment of the present disclosure. In an example, a third dielectric 120 may be deposited on the passivation layer 118. The third dielectric 120 may be deposited using spin-on deposition from a slurry, sputtering, CVD, TVD, ALD, or any combination, or some other form of deposition that may deposit the third dielectric 120 on the passivation layer 118. The third dielectric 120 may have a thickness of from about 1 nanometer to about 40 nanometers. The third dielectric 120 may be etched, polished, planarized, and / or patterned.

[0063] Turning Figure 7F , Figure 7FA simplified block diagram of a stage in forming transistor 104 according to an embodiment of the present disclosure is shown. As Figure 7F shown, gate 110, gate dielectric 114, channel 116, passivation layer 188, and third dielectric 120 can be etched. The etching can extend down to oxide 108.

[0064] Turning Figure 7G , Figure 7G A simplified block diagram of a stage in forming transistor 104 according to an embodiment of the present disclosure is shown. In an example, first dielectric 112 can be deposited over oxide layer 108, gate 110, gate dielectric 114, channel 116, passivation layer 188, and third dielectric 120. First dielectric 112 can be deposited using spin-on deposition from a slurry, sputtering, CVD, TVD, ALD, or any combination, or some other form of deposition that can deposit first dielectric 112 over oxide 108, gate 110, gate dielectric 114, channel 116, passivation layer 188, and third dielectric 120. First dielectric 112 can be about 1 nanometer to about 40 nanometers in thickness. First dielectric 112 can be etched, polished, planarized, and / or patterned.

[0065] Turning Figure 7H , Figure 7H A simplified block diagram of a stage in forming transistor 104 according to an embodiment of the present disclosure is shown. In an example, second dielectric 160 can be deposited over first dielectric 112. Second dielectric 160 can be deposited using spin-on deposition from a slurry, sputtering, CVD, TVD, ALD, or any combination, or some other form of deposition that can deposit second dielectric 160 over first dielectric 112. Second dielectric 160 can have a thickness of about 1 nanometer to about 40 nanometers. Second dielectric 160 can be etched, polished, planarized, and / or patterned.

[0066] Turning Figure 7I , Figure 7I A simplified block diagram of a stage in forming transistor 104 according to an embodiment of the present disclosure is shown. As Figure 7I shown, first dielectric 112 and second dielectric 160 can be etched to the same level as gate dielectric 114 to create source cavity 156 and drain cavity 158. Third dielectric 120 can act as an etch stop and help prevent channel 116 and passivation layer 118 from being etched.

[0067] Turning Figure 8 , Figure 8 A simplified block diagram of a stage in forming transistor 104 according to an embodiment of the present disclosure is shown. Figure 8 is Figure 7HTop view, which shows oxide 108, first dielectric 112, and third dielectric 120. Gate 110, gate dielectric 114, channel 116, passivation layer 188, and third dielectric 120 are under third dielectric 120.

[0068] Turning Figure 9 , Figure 9 shows a simplified block diagram of a stage in forming transistor 104 in accordance with an embodiment of the present disclosure. Figure 9 is after depositing source 122 into source cavity 156 and depositing drain 124 into drain cavity 158 Figure 7I Top view. For example, spin-on deposition from a slurry, sputtering, CVD, TVD, ALD, or any combination, or some other form of deposition that can deposit source in source cavity 156 and deposit drain 124 in drain cavity 158 can be used to deposit source 122 and drain 124. Source 122 and drain 124 can have a thickness of from about 1 nanometer to about 40 nanometers.

[0069] Turning Figure 10 , Figure 10 shows an interposer 1000 that can include one or more embodiments disclosed herein or interact therewith. Interposer 1000 is an intermediate substrate for bridging a first substrate 1002 to a second substrate 1004. The first substrate 1002 can be, for example, an integrated circuit die. The second substrate 1004 can be, for example, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of interposer 1000 is to extend connections to wider pitches or reroute connections to different connections. For example, interposer 1000 can couple an integrated circuit die to a ball grid array (BGA) 1006, and ball grid array 1006 can then be coupled to second substrate 1004. In some embodiments, the first and second substrates 1002 / 1004 are attached to opposite sides of interposer 1000. In other embodiments, the first and second substrates 1002 / 1004 are attached to the same side of interposer 1000. And in still other embodiments, three or more substrates are interconnected using interposer 1000.

[0070] Interposer 1000 can be formed of epoxy resin, glass fiber-reinforced epoxy resin, ceramic material, or a polymeric material such as polyimide. In other embodiments, the interposer can be formed of alternating rigid or flexible materials, which can include the same materials described above for semiconductor substrates, such as silicon, germanium, and other Group III-V and Group IV materials.

[0071] The interposer may include metal interconnects 1008 and vias 1010, and the vias 1010 include, but are not limited to, through-silicon vias (TSVs) 1012. The interposer 1000 may also include embedded devices 1014, which include passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices, such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices, may also be formed on the interposer 1000. According to various embodiments, the devices or processes disclosed herein may be used in the manufacture of the interposer 1000.

[0072] Turning Figure 11 , Figure 11 FIG. 11 shows a computing device 1100 according to various embodiments. The computing device 1100 may include a number of components. In one embodiment, these components are attached to one or more motherboards. In alternative embodiments, some or all of these components are fabricated onto a single system-on-chip (SoC) die. The components in the computing device 1100 include, but are not limited to, an integrated circuit die 1102 and at least one communication logic unit 1108. In some implementations, the communication logic unit 1108 is fabricated within the integrated circuit die 1102, while in other implementations, the communication logic unit 1108 is fabricated in a separate integrated circuit chip, which may be bonded to a substrate or motherboard that shares or is electrically coupled to the integrated circuit die 1102. The integrated circuit die 1102 may include a CPU 1104 and on-die memory 1106, which is often used as cache memory and may be provided by technologies such as embedded DRAM (eDRAM) or spin-transfer torque memory (STTM or STT-MRAM).

[0073] The computing device 1100 may include other components that may or may not be physically and electrically coupled to a motherboard or fabricated within an SoC die. These other components include, but are not limited to, volatile memory 1110 (e.g., DRAM), non-volatile memory 1112 (e.g., ROM or flash memory), graphics processing unit 1114 (GPU), digital signal processor 1116, cryptographic processor 1142 (a dedicated processor that executes cryptographic algorithms in hardware), chipset 1120, antenna 1122, display or touchscreen display 1124, touchscreen controller 1126, battery 1128 or other power source, power amplifier (not shown), voltage regulator (not shown), global positioning system (GPS) device 1128, compass 1130, motion processor or sensor 1132 (which may include an accelerometer, gyroscope, and compass), speaker 1134, camera 1136, user input device 1138 (e.g., keyboard, mouse, stylus, and touchpad), and mass storage device 1140 (e.g., hard disk drive, compact disk (CD), digital versatile disk (DVD), etc.).

[0074] The communication logic unit 1108 is capable of implementing wireless communication for transmitting data to and from the computing device 1100. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transfer data by using modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not. The communication logic unit 1108 may implement any of several wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G, and later. The computing device 1100 may include multiple communication logic units 1108. For example, a first communication logic unit 1108 may be dedicated to short-range wireless communication such as Wi-Fi and Bluetooth, and a second communication logic unit 1108 may be dedicated to long-range wireless communication such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others.

[0075] The processor 1104 of the computing device 1100 may communicate with one or more devices formed in accordance with various embodiments. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform that electronic data into other electronic data that may be stored in registers and / or memory.

[0076] The communication logic unit 1108 may also include one or more devices that communicate with various embodiments in the embodiments disclosed herein, such as transistors or metal interconnects. In other embodiments, another component housed within the computing device 1100 may include one or more devices formed in accordance with the embodiments disclosed herein, such as transistors or metal interconnects.

[0077] In various embodiments, the computing device 1100 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smart phone, a tablet computer, a personal digital assistant (PDA), a super mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In other embodiments, the computing device 1100 may be any other electronic device that processes data.

[0078] The above description of the illustrated embodiments, including what is described in the abstract, is not intended to be exhaustive or to limit the scope of the disclosure to the precise forms disclosed. Although specific embodiments and examples of the embodiments disclosed herein are described herein for illustrative purposes, those skilled in the relevant art will recognize that various equivalent modifications are possible within the scope of the disclosure.

[0079] Other notes and examples

[0080] Example 1 is a device that includes: a gate, where the gate includes a first gate side and a second gate side opposite the first gate side; a gate dielectric on the gate, where the gate dielectric includes a first gate dielectric side and a second gate dielectric side opposite the first gate dielectric side; a first dielectric, where the first dielectric abuts the first gate side, the first gate dielectric side, the second gate side, and the second gate dielectric side; a channel, where the gate dielectric is between the channel and the gate; a source coupled to the channel; and a drain coupled to the channel, where the first dielectric abuts the source and the drain.

[0081] In Example 2, the subject matter of Example 1 may optionally include a second dielectric between a portion of the first dielectric and a portion of the source.

[0082] In Example 3, the subject matter of any one of Examples 1 and 2 may optionally include: wherein the first dielectric and the gate dielectric insulate the gate from the channel, source, and drain.

[0083] In Example 4, the subject matter of any one of Examples 1-3 may optionally include a passivation layer between the source and the drain.

[0084] In Example 5, the subject matter of any one of Examples 1-4 may optionally include a third dielectric on the passivation layer.

[0085] In Example 6, the subject matter of any one of Examples 1-5 may optionally include: wherein the device is on an interlayer gate dielectric.

[0086] In Example 7, the subject matter of any one of Examples 1-6 may optionally include: wherein the device is coupled to a capacitive element.

[0087] In Example 8, the subject matter of any one of Examples 1-7 may optionally include: wherein the capacitive element is an embedded dynamic random access memory.

[0088] In Example 9, a method includes: depositing a gate on an oxide, depositing a gate dielectric on the gate, depositing a first dielectric on both sides of the gate and the gate dielectric, and depositing a channel on the gate dielectric and the first dielectric.

[0089] In Example 10, the subject matter of Example 9 may optionally include: depositing a second dielectric on a portion of the first dielectric and depositing a source and a drain on the second dielectric and the first dielectric, wherein the channel couples the source and the drain.

[0090] In Example 11, the subject matter of any one of Examples 9 and 10 may optionally include: depositing a passivation layer between the source and the drain.

[0091] In Example 12, the subject matter of any one of Examples 9-11 may optionally include: wherein the drain is coupled to a capacitive element.

[0092] In Example 13, the subject matter of any one of Examples 9-12 may optionally include: wherein the drain is coupled to an embedded dynamic random access memory.

[0093] In Example 14, the subject matter of any one of Examples 9-13 may optionally include: wherein the oxide layer is above the logic element.

[0094] Example 15 is a computing device that includes a processor mounted on a substrate, a communication logic unit within the processor, a memory within the processor, a graphics processing unit within the computing device, an antenna within the computing device, a display on the computing device, a battery within the computing device, a power amplifier within the processor, and a voltage regulator within the processor. The memory may be coupled to a back-end transistor, and the back-end transistor may include: a gate, where the gate includes a first gate side and a second gate side opposite the first gate side; a gate dielectric on the gate, where the gate dielectric includes a first gate dielectric side and a second gate dielectric side opposite the first gate dielectric side; a first dielectric, where the first dielectric abuts the first gate side, the first gate dielectric side, the second gate side, and the second gate dielectric side; a channel, where the gate dielectric is between the channel and the gate; a source coupled to the channel; and a drain coupled to the channel, where the first dielectric abuts the source and the drain.

[0095] In Example 16, the subject matter of Example 15 may optionally include: where the back-end transistor further includes a second dielectric between a portion of the first dielectric and a portion of the source.

[0096] In Example 17, the subject matter of any one of Examples 15 and 16 may optionally include: where the first dielectric and the gate dielectric insulate the gate from the channel, the source, and the drain.

[0097] In Example 18, the subject matter of any one of Examples 15-17 may optionally include: a passivation layer between the source and the drain.

[0098] In Example 19, the subject matter of any one of Examples 15-18 may optionally include: where the memory element is an embedded dynamic random access memory.

[0099] In Example 20, the subject matter of any one of Examples 15-19 may optionally include: where the back-end transistor is on an interlayer gate dielectric.

[0100] Example 21 is an integrated circuit (IC) component that includes a substrate, a device layer including one or more first transistors on the substrate, an interconnect stack on the device layer for routing electrical signals to the first transistors, and a second transistor embedded in the interconnect stack. The second transistor can include: a gate, where the gate includes a first gate side and a second gate side opposite the first gate side; a gate dielectric on the gate, where the gate dielectric includes a first gate dielectric side and a second gate dielectric side opposite the first gate dielectric side; a first dielectric, where the first dielectric abuts the first gate side, the first gate dielectric side, the second gate side, and the second gate dielectric side; a channel, where the gate dielectric is between the channel and the gate; a source coupled to the channel; and a drain coupled to the channel, where the first dielectric abuts the source and the drain.

[0101] In Example 22, the subject matter of Example 21 can optionally include: a second dielectric between a portion of the first dielectric and a portion of the source.

[0102] In Example 23, the subject matter of Example 21 and any one of Examples 22 - 23 can optionally include: where the first dielectric and the gate dielectric insulate the gate from the channel, the source, and the drain.

[0103] In Example 24, the subject matter of any one of Examples 21 - 23 can optionally include: a passivation layer between the source and the drain.

[0104] In Example 25, the subject matter of any one of Examples 22 - 24 can optionally include: where the interconnect stack is coupled to a capacitive element.

Claims

1. A device, comprising: a gate, wherein the gate includes a first gate side and a second gate side opposite the first gate side; a gate dielectric on the gate, wherein the gate dielectric includes a first gate dielectric side and a second gate dielectric side opposite the first gate dielectric side; a first dielectric, wherein the first dielectric abuts the first gate side, the first gate dielectric side, the second gate side, and the second gate dielectric side; a channel, wherein the gate dielectric is between the channel and the gate; a source coupled to the channel; a drain coupled to the channel, wherein the first dielectric abuts the source and the drain; and a second dielectric between a portion of the first dielectric and the source.

2. The device according to claim 1, wherein the first dielectric and the gate dielectric insulate the gate from the channel, the source, and the drain.

3. The device according to claim 1, further comprising: a passivation layer between the source and the drain.

4. The device according to claim 3, further comprising: a third dielectric on the passivation layer.

5. The device according to any one of claims 1-4, wherein the device is on an interlayer dielectric.

6. The device according to any one of claims 1-4, wherein the device is coupled to a capacitive element.

7. The device according to claim 6, wherein the capacitive element is an embedded dynamic random access memory.

8. A method, comprising: depositing a gate on an oxide; depositing a gate dielectric on the gate; depositing a first dielectric along both sides of the gate and the gate dielectric; depositing a channel on the gate dielectric and the first dielectric; depositing a second dielectric on a portion of the first dielectric; and depositing a source and a drain on the second dielectric and the first dielectric, wherein the channel couples the source and the drain.

9. The method according to claim 8, further comprising: depositing a passivation layer between the source and the drain.

10. The method according to claim 8, wherein the drain is coupled to a capacitive element.

11. The method according to claim 8, wherein the drain is coupled to an embedded dynamic random access memory.

12. The method according to any one of claims 8-11, wherein the oxide layer is above a logic element.

13. A computing device, comprising: a processor mounted on a substrate; a communication logic unit within the processor; a memory within the processor; a graphics processing unit within the computing device; an antenna within the computing device; a display on the computing device; a battery within the computing device; a power amplifier within the processor; and a voltage regulator within the processor; wherein the memory is coupled to a back-end transistor, and the back-end transistor includes: a gate, wherein the gate includes a first gate side and a second gate side opposite the first gate side; The gate dielectric on the gate, wherein the gate dielectric includes a first gate dielectric side and a second gate dielectric side opposite the first gate dielectric side; A first dielectric, wherein the first dielectric is adjacent to the first gate side, the first gate dielectric side, the second gate side, and the second gate dielectric side; A channel, wherein the gate dielectric is between the channel and the gate; A source coupled to the channel; A drain coupled to the channel, wherein the first dielectric is adjacent to the source and the drain; and A second dielectric between a portion of the first dielectric and the source.

14. The computing device according to claim 13, wherein, The first dielectric and the gate dielectric insulate the gate from the channel, the source, and the drain.

15. The computing device according to any one of claims 13-14, wherein, The back-end transistor further includes: A passivation layer between the source and the drain.

16. The computing device according to any one of claims 13-14, wherein, The memory element is an embedded dynamic random access memory.

17. The computing device according to any one of claims 13-14, wherein, The back-end transistor is on an interlayer dielectric.

18. An integrated circuit (IC) component, comprising: A substrate; A device layer on the substrate including one or more first transistors; An interconnect stack on the device layer for routing electrical signals to the first transistors; and A second transistor embedded in the interconnect stack, wherein the second transistor includes: A gate, wherein the gate includes a first gate side and a second gate side opposite the first gate side; The gate dielectric on the gate, wherein the gate dielectric includes a first gate dielectric side and a second gate dielectric side opposite the first gate dielectric side; A first dielectric, wherein the first dielectric is adjacent to the first gate side, the first gate dielectric side, the second gate side, and the second gate dielectric side; A channel, wherein the gate dielectric is between the channel and the gate; A source coupled to the channel; and A drain coupled to the channel, wherein the first dielectric is adjacent to the source and the drain; and A second dielectric between a portion of the first dielectric and the source.

19. The integrated circuit (IC) component according to claim 18, wherein, The first dielectric and the gate dielectric insulate the gate from the channel, the source, and the drain.

20. The integrated circuit (IC) component according to any one of claims 18-19, wherein, The second transistor further includes: A passivation layer between the source and the drain.

21. The integrated circuit (IC) component according to any one of claims 18-19, wherein, The second transistor is coupled to a capacitive element.

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